wd33c93.c revision 1.15
1 /* $NetBSD: wd33c93.c,v 1.15 2007/05/21 18:56:32 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.15 2007/05/21 18:56:32 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *dev) 188 { 189 struct scsipi_adapter *adapt = &dev->sc_adapter; 190 struct scsipi_channel *chan = &dev->sc_channel; 191 192 adapt->adapt_dev = &dev->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &dev->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = dev->sc_id; 207 208 callout_init(&dev->sc_watchdog); 209 210 /* 211 * Add reference to adapter so that we drop the reference after 212 * config_found() to make sure the adatper is disabled. 213 */ 214 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 215 printf("%s: unable to enable controller\n", 216 dev->sc_dev.dv_xname); 217 return; 218 } 219 220 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 221 wd33c93_init(dev); 222 223 printf(": %s (%d.%d MHz clock, %s, SCSI ID %d)\n", 224 wd33c93_chip_names[dev->sc_chip], 225 dev->sc_clkfreq / 10, dev->sc_clkfreq % 10, 226 (dev->sc_dmamode == SBIC_CTL_DMA) ? "DMA" : 227 (dev->sc_dmamode == SBIC_CTL_DBA_DMA) ? "DBA" : 228 (dev->sc_dmamode == SBIC_CTL_BURST_DMA) ? "BURST DMA" : "PIO", 229 dev->sc_channel.chan_id); 230 if (dev->sc_chip == SBIC_CHIP_WD33C93B) { 231 printf("%s: microcode revision 0x%02x", 232 dev->sc_dev.dv_xname, dev->sc_rev); 233 if (dev->sc_minsyncperiod < 50) 234 printf(", Fast SCSI"); 235 printf("\n"); 236 } 237 238 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 239 scsiprint); 240 scsipi_adapter_delref(&dev->sc_adapter); 241 } 242 243 /* 244 * Initialize driver-private structures 245 */ 246 void 247 wd33c93_init(struct wd33c93_softc *dev) 248 { 249 u_int i; 250 251 if (!wd33c93_pool_initialized) { 252 /* All instances share the same pool */ 253 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 254 "wd33c93_acb", NULL, IPL_BIO); 255 ++wd33c93_pool_initialized; 256 } 257 258 if (dev->sc_state == 0) { 259 TAILQ_INIT(&dev->ready_list); 260 261 dev->sc_nexus = NULL; 262 dev->sc_disc = 0; 263 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 264 265 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 266 } else 267 panic("wd33c93: reinitializing driver!"); 268 269 dev->sc_flags = 0; 270 dev->sc_state = SBIC_IDLE; 271 wd33c93_reset(dev); 272 273 for (i = 0; i < 8; i++) { 274 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 275 /* 276 * sc_flags = 0xTTRRSS 277 * 278 * TT = Bitmask to disable Tagged Queues 279 * RR = Bitmask to disable disconnect/reselect 280 * SS = Bitmask to diable Sync negotiation 281 */ 282 ti->flags = T_NEED_RESET; 283 if (dev->sc_cfflags & (1<<(i+8))) 284 ti->flags |= T_NOSYNC; 285 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 286 ti->flags |= T_NODISC; 287 ti->period = dev->sc_minsyncperiod; 288 ti->offset = 0; 289 } 290 } 291 292 void 293 wd33c93_reset(struct wd33c93_softc *dev) 294 { 295 u_int my_id, s, div, i; 296 u_char csr, reg; 297 298 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 299 WAIT_CIP(dev); 300 301 s = splbio(); 302 303 if (dev->sc_reset != NULL) 304 (*dev->sc_reset)(dev); 305 306 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 307 308 /* Enable advanced features and really(!) advanced features */ 309 #if 1 310 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 311 #endif 312 313 SET_SBIC_myid(dev, my_id); 314 315 /* Reset the chip */ 316 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 317 DELAY(25); 318 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 319 320 /* Set up various chip parameters */ 321 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 322 323 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 324 GET_SBIC_cdb1(dev, dev->sc_rev); /* valid with RAF on wd33c93b */ 325 326 switch (csr) { 327 case SBIC_CSR_RESET: 328 dev->sc_chip = SBIC_CHIP_WD33C93; 329 break; 330 case SBIC_CSR_RESET_AM: 331 SET_SBIC_queue_tag(dev, 0x55); 332 GET_SBIC_queue_tag(dev, reg); 333 dev->sc_chip = (reg == 0x55) ? 334 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 335 SET_SBIC_queue_tag(dev, 0x0); 336 break; 337 default: 338 dev->sc_chip = SBIC_CHIP_UNKNOWN; 339 } 340 341 /* 342 * Choose a suitable clock divisor and work out the resulting 343 * sync transfer periods in 4ns units. 344 */ 345 if (dev->sc_clkfreq < 110) { 346 my_id |= SBIC_ID_FS_8_10; 347 div = 2; 348 } else if (dev->sc_clkfreq < 160) { 349 my_id |= SBIC_ID_FS_12_15; 350 div = 3; 351 } else if (dev->sc_clkfreq < 210) { 352 my_id |= SBIC_ID_FS_16_20; 353 div = 4; 354 } else 355 panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq); 356 357 for (i = 0; i < 7; i++) 358 dev->sc_syncperiods[i] = 359 (i + 2) * div * 1250 / dev->sc_clkfreq; 360 dev->sc_minsyncperiod = dev->sc_syncperiods[0]; 361 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 362 dev->sc_syncperiods[0], dev->sc_syncperiods[1], 363 dev->sc_syncperiods[2], dev->sc_syncperiods[3], 364 dev->sc_syncperiods[4], dev->sc_syncperiods[5], 365 dev->sc_syncperiods[6])); 366 367 if (dev->sc_clkfreq >= 160 && dev->sc_chip == SBIC_CHIP_WD33C93B) { 368 for (i = 0; i < 3; i++) 369 dev->sc_fsyncperiods[i] = 370 (i + 2) * 2 * 1250 / dev->sc_clkfreq; 371 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 372 dev->sc_fsyncperiods[0], dev->sc_fsyncperiods[1], 373 dev->sc_fsyncperiods[2])); 374 dev->sc_minsyncperiod = dev->sc_fsyncperiods[0]; 375 } 376 377 /* Max Sync Offset */ 378 if (dev->sc_chip == SBIC_CHIP_WD33C93A || 379 dev->sc_chip == SBIC_CHIP_WD33C93B) 380 dev->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET; 381 else 382 dev->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET; 383 384 /* 385 * don't allow Selection (SBIC_RID_ES) 386 * until we can handle target mode!! 387 */ 388 SET_SBIC_rselid(dev, SBIC_RID_ER); 389 390 /* Asynchronous for now */ 391 SET_SBIC_syn(dev, 0); 392 393 dev->sc_flags = 0; 394 dev->sc_state = SBIC_IDLE; 395 396 splx(s); 397 } 398 399 void 400 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 401 { 402 struct scsipi_xfer *xs = acb->xs; 403 404 KASSERT(xs); 405 406 if (xs->xs_control & XS_CTL_SILENT) 407 return; 408 409 scsipi_printaddr(xs->xs_periph); 410 printf("SCSI Error\n"); 411 } 412 413 /* 414 * Determine an appropriate value for the synchronous transfer register 415 * given the period and offset values in *ti. 416 */ 417 u_char 418 wd33c93_stp2syn(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 419 { 420 unsigned i; 421 422 /* see if we can handle fast scsi (100-200ns) first */ 423 if (ti->period < 50 && dev->sc_minsyncperiod < 50) { 424 for (i = 0; i < 3; i++) 425 if (dev->sc_fsyncperiods[i] >= ti->period) 426 return (SBIC_SYN(ti->offset, i + 2, 1)); 427 } 428 429 for (i = 0; i < 7; i++) { 430 if (dev->sc_syncperiods[i] >= ti->period) { 431 if (i == 6) 432 return (SBIC_SYN(0, 0, 0)); 433 else 434 return (SBIC_SYN(ti->offset, i + 2, 0)); 435 } 436 } 437 438 /* XXX - can't handle it; do async */ 439 return (SBIC_SYN(0, 0, 0)); 440 } 441 442 /* 443 * Setup sync mode for given target 444 */ 445 void 446 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 447 { 448 u_char syncreg; 449 450 if (ti->flags & T_SYNCMODE) 451 syncreg = wd33c93_stp2syn(dev, ti); 452 else 453 syncreg = SBIC_SYN(0, 0, 0); 454 455 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 456 SET_SBIC_syn(dev, syncreg); 457 } 458 459 /* 460 * Check if current operation can be done using DMA 461 * 462 * returns 1 if DMA OK, 0 for polled I/O transfer 463 */ 464 int 465 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 466 { 467 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 468 return (0); 469 return(1); 470 } 471 472 /* 473 * Setup for DMA transfer 474 */ 475 void 476 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 477 { 478 struct wd33c93_acb *acb = dev->sc_nexus; 479 int s; 480 481 dev->sc_daddr = acb->daddr; 482 dev->sc_dleft = acb->dleft; 483 484 s = splbio(); 485 /* Indicate that we're in DMA mode */ 486 if (dev->sc_dleft) { 487 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 488 datain, &dev->sc_dleft); 489 } 490 splx(s); 491 return; 492 } 493 494 495 /* 496 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 497 */ 498 void 499 wd33c93_dma_stop(struct wd33c93_softc *dev) 500 { 501 size_t count; 502 int asr; 503 504 /* Wait until WD chip is idle */ 505 do { 506 GET_SBIC_asr(dev, asr); /* XXX */ 507 if (asr & SBIC_ASR_DBR) { 508 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 509 break; 510 } 511 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 512 513 /* Only need to save pointers if DMA was active */ 514 if (dev->sc_flags & SBICF_INDMA) { 515 int s = splbio(); 516 517 /* Shut down DMA and flush FIFO's */ 518 dev->sc_dmastop(dev); 519 520 /* Fetch the residual count */ 521 SBIC_TC_GET(dev, count); 522 523 /* Work out how many bytes were actually transferred */ 524 count = dev->sc_tcnt - count; 525 526 if (dev->sc_dleft < count) 527 printf("xfer too large: dleft=%zu resid=%zu\n", 528 dev->sc_dleft, count); 529 530 /* Fixup partial xfers */ 531 dev->sc_daddr = (char*)dev->sc_daddr + count; 532 dev->sc_dleft -= count; 533 dev->sc_tcnt = 0; 534 dev->sc_flags &= ~SBICF_INDMA; 535 splx(s); 536 SBIC_DEBUG(DMA, ("dma_stop\n")); 537 } 538 /* 539 * Ensure the WD chip is back in polled I/O mode, with nothing to 540 * transfer. 541 */ 542 SBIC_TC_PUT(dev, 0); 543 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 544 } 545 546 547 /* 548 * Handle new request from scsipi layer 549 */ 550 void 551 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 552 { 553 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 554 struct scsipi_xfer *xs; 555 struct scsipi_periph *periph; 556 struct wd33c93_acb *acb; 557 int flags, s; 558 559 SBIC_DEBUG(MISC, ("wd33c93_scsi_request: req 0x%x\n", (int)req)); 560 561 switch (req) { 562 case ADAPTER_REQ_RUN_XFER: 563 xs = arg; 564 periph = xs->xs_periph; 565 flags = xs->xs_control; 566 567 if (flags & XS_CTL_DATA_UIO) 568 panic("wd33c93: scsi data uio requested"); 569 570 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 571 panic("wd33c93_scsicmd: busy"); 572 573 s = splbio(); 574 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 575 splx(s); 576 577 if (acb == NULL) { 578 scsipi_printaddr(periph); 579 printf("cannot allocate acb\n"); 580 xs->error = XS_RESOURCE_SHORTAGE; 581 scsipi_done(xs); 582 return; 583 } 584 585 acb->flags = ACB_ACTIVE; 586 acb->xs = xs; 587 acb->clen = xs->cmdlen; 588 acb->daddr = xs->data; 589 acb->dleft = xs->datalen; 590 acb->timeout = xs->timeout; 591 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 592 593 if (flags & XS_CTL_POLL) { 594 /* 595 * Complete currently active command(s) before 596 * issuing an immediate command 597 */ 598 while (dev->sc_nexus) 599 wd33c93_poll(dev, dev->sc_nexus); 600 } 601 602 s = splbio(); 603 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 604 acb->flags |= ACB_READY; 605 606 /* If nothing is active, try to start it now. */ 607 if (dev->sc_state == SBIC_IDLE) 608 wd33c93_sched(dev); 609 splx(s); 610 611 if ((flags & XS_CTL_POLL) == 0) 612 return; 613 614 if (wd33c93_poll(dev, acb)) { 615 wd33c93_timeout(acb); 616 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 617 wd33c93_timeout(acb); 618 } 619 return; 620 621 case ADAPTER_REQ_GROW_RESOURCES: 622 /* XXX Not supported. */ 623 return; 624 625 case ADAPTER_REQ_SET_XFER_MODE: 626 { 627 struct wd33c93_tinfo *ti; 628 struct scsipi_xfer_mode *xm = arg; 629 630 ti = &dev->sc_tinfo[xm->xm_target]; 631 ti->flags &= ~T_WANTSYNC; 632 633 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 634 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 635 ti->flags |= T_TAG; 636 else 637 ti->flags &= ~T_TAG; 638 639 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 640 "target %d: scsipi requested %s\n", xm->xm_target, 641 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 642 643 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 644 (ti->flags & T_NOSYNC) == 0) 645 ti->flags |= T_WANTSYNC; 646 /* 647 * If we're not going to negotiate, send the notification 648 * now, since it won't happen later. 649 */ 650 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 651 wd33c93_update_xfer_mode(dev, xm->xm_target); 652 else 653 ti->flags |= T_NEGOTIATE; 654 return; 655 } 656 657 } 658 } 659 660 /* 661 * attempt to start the next available command 662 */ 663 void 664 wd33c93_sched(struct wd33c93_softc *dev) 665 { 666 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 667 struct wd33c93_acb *acb; 668 struct wd33c93_tinfo *ti; 669 struct wd33c93_linfo *li; 670 int lun, tag, flags; 671 672 if (dev->sc_state != SBIC_IDLE) 673 return; 674 675 KASSERT(dev->sc_nexus == NULL); 676 677 /* Loop through the ready list looking for work to do... */ 678 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 679 periph = acb->xs->xs_periph; 680 lun = periph->periph_lun; 681 ti = &dev->sc_tinfo[periph->periph_target]; 682 li = TINFO_LUN(ti, lun); 683 684 KASSERT(acb->flags & ACB_READY); 685 686 /* Select type of tag for this command */ 687 if ((ti->flags & T_NODISC) != 0) 688 tag = 0; 689 else if ((ti->flags & T_TAG) == 0) 690 tag = 0; 691 else if ((acb->flags & ACB_SENSE) != 0) 692 tag = 0; 693 else if (acb->xs->xs_control & XS_CTL_POLL) 694 tag = 0; /* No tags for polled commands */ 695 else 696 tag = acb->xs->xs_tag_type; 697 698 if (li == NULL) { 699 /* Initialize LUN info and add to list. */ 700 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 701 if (li == NULL) 702 continue; 703 memset(li, 0, sizeof(*li)); 704 li->lun = lun; 705 if (lun < SBIC_NLUN) 706 ti->lun[lun] = li; 707 } 708 li->last_used = time_second; 709 710 /* 711 * We've found a potential command, but is the target/lun busy? 712 */ 713 714 if (tag == 0 && li->untagged == NULL) 715 li->untagged = acb; /* Issue untagged */ 716 717 if (li->untagged != NULL) { 718 tag = 0; 719 if ((li->state != L_STATE_BUSY) && li->used == 0) { 720 /* Issue this untagged command now */ 721 acb = li->untagged; 722 periph = acb->xs->xs_periph; 723 } else /* Not ready yet */ 724 continue; 725 } 726 727 acb->tag_type = tag; 728 if (tag != 0) { 729 if (li->queued[acb->xs->xs_tag_id]) 730 printf("queueing to active tag\n"); 731 li->queued[acb->xs->xs_tag_id] = acb; 732 acb->tag_id = acb->xs->xs_tag_id; 733 li->used++; 734 break; 735 } 736 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 737 li->state = L_STATE_BUSY; 738 break; 739 } 740 if (li->untagged == NULL && tag != 0) { 741 break; 742 } else 743 printf("%d:%d busy\n", periph->periph_target, 744 periph->periph_lun); 745 } 746 747 if (acb == NULL) { 748 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 749 return; /* did not find an available command */ 750 } 751 752 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 753 periph->periph_lun)); 754 755 TAILQ_REMOVE(&dev->ready_list, acb, chain); 756 acb->flags &= ~ACB_READY; 757 758 flags = acb->xs->xs_control; 759 if (flags & XS_CTL_RESET) 760 wd33c93_reset(dev); 761 762 /* XXX - Implicitly call scsidone on select timeout */ 763 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 764 acb->dleft = dev->sc_dleft; 765 wd33c93_scsidone(dev, acb, dev->sc_status); 766 return; 767 } 768 769 return; 770 } 771 772 void 773 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 774 { 775 struct scsipi_xfer *xs = acb->xs; 776 struct wd33c93_tinfo *ti; 777 struct wd33c93_linfo *li; 778 int s; 779 780 #ifdef DIAGNOSTIC 781 KASSERT(dev->target == xs->xs_periph->periph_target); 782 KASSERT(dev->lun == xs->xs_periph->periph_lun); 783 if (acb == NULL || xs == NULL) { 784 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 785 dev->target, dev->lun); 786 } 787 KASSERT(acb->flags != ACB_FREE); 788 #endif 789 790 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 791 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 792 dev->target, dev->lun, status)); 793 callout_stop(&xs->xs_callout); 794 795 xs->status = status & SCSI_STATUS_MASK; 796 xs->resid = acb->dleft; 797 798 if (xs->error == XS_NOERROR) { 799 switch (xs->status) { 800 case SCSI_CHECK: 801 case SCSI_TERMINATED: 802 /* XXX Need to read sense - return busy for now */ 803 /*FALLTHROUGH*/ 804 case SCSI_QUEUE_FULL: 805 case SCSI_BUSY: 806 xs->error = XS_BUSY; 807 break; 808 } 809 } 810 811 ti = &dev->sc_tinfo[dev->target]; 812 li = TINFO_LUN(ti, dev->lun); 813 ti->cmds++; 814 if (xs->error == XS_SELTIMEOUT) { 815 /* Selection timeout -- discard this LUN if empty */ 816 if (li->untagged == NULL && li->used == 0) { 817 if (dev->lun < SBIC_NLUN) 818 ti->lun[dev->lun] = NULL; 819 free(li, M_DEVBUF); 820 } 821 } 822 823 wd33c93_dequeue(dev, acb); 824 if (dev->sc_nexus == acb) { 825 dev->sc_state = SBIC_IDLE; 826 dev->sc_nexus = NULL; 827 dev->sc_flags = 0; 828 829 if (!TAILQ_EMPTY(&dev->ready_list)) 830 wd33c93_sched(dev); 831 } 832 833 /* place control block back on free list. */ 834 s = splbio(); 835 acb->flags = ACB_FREE; 836 pool_put(&wd33c93_pool, (void *)acb); 837 splx(s); 838 839 scsipi_done(xs); 840 } 841 842 void 843 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 844 { 845 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 846 struct wd33c93_linfo *li; 847 int lun = acb->xs->xs_periph->periph_lun; 848 849 li = TINFO_LUN(ti, lun); 850 #ifdef DIAGNOSTIC 851 if (li == NULL || li->lun != lun) 852 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 853 lun, acb); 854 #endif 855 if (li->untagged == acb) { 856 li->state = L_STATE_IDLE; 857 li->untagged = NULL; 858 } 859 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 860 #ifdef DIAGNOSTIC 861 if (li->queued[acb->tag_id] != NULL && 862 (li->queued[acb->tag_id] != acb)) 863 panic("wd33c93_dequeue: slot %d for lun %d has %p " 864 "instead of acb %p\n", acb->tag_id, 865 lun, li->queued[acb->tag_id], acb); 866 #endif 867 li->queued[acb->tag_id] = NULL; 868 li->used--; 869 } 870 } 871 872 873 int 874 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 875 { 876 u_char val; 877 878 if (timeo == 0) 879 timeo = 1000000; /* some large value.. */ 880 GET_SBIC_asr(dev, val); 881 while ((val & until) == 0) { 882 if (timeo-- == 0) { 883 int csr; 884 GET_SBIC_csr(dev, csr); 885 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 886 line, val, csr); 887 #if defined(DDB) && defined(DEBUG) 888 Debugger(); 889 #endif 890 return(val); /* Maybe I should abort */ 891 break; 892 } 893 DELAY(1); 894 GET_SBIC_asr(dev, val); 895 } 896 return(val); 897 } 898 899 int 900 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 901 const char *where) 902 { 903 u_char csr, asr; 904 905 GET_SBIC_asr(dev, asr); 906 GET_SBIC_csr(dev, csr); 907 908 scsipi_printaddr(acb->xs->xs_periph); 909 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 910 911 acb->timeout = SBIC_ABORT_TIMEOUT; 912 acb->flags |= ACB_ABORT; 913 914 /* 915 * Clean up chip itself 916 */ 917 if (dev->sc_nexus == acb) { 918 /* Reschedule timeout. */ 919 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 920 wd33c93_timeout, acb); 921 922 while (asr & SBIC_ASR_DBR) { 923 /* 924 * wd33c93 is jammed w/data. need to clear it 925 * But we don't know what direction it needs to go 926 */ 927 GET_SBIC_data(dev, asr); 928 printf("abort %s: clearing data buffer 0x%02x\n", 929 where, asr); 930 GET_SBIC_asr(dev, asr); 931 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 932 SET_SBIC_data(dev, asr); 933 GET_SBIC_asr(dev, asr); 934 } 935 936 scsipi_printaddr(acb->xs->xs_periph); 937 printf("sending ABORT command\n"); 938 939 WAIT_CIP(dev); 940 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 941 WAIT_CIP(dev); 942 943 GET_SBIC_asr(dev, asr); 944 945 scsipi_printaddr(acb->xs->xs_periph); 946 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 947 /* 948 * ok, get more drastic.. 949 */ 950 printf("Resetting bus\n"); 951 wd33c93_reset(dev); 952 } else { 953 printf("sending DISCONNECT to target\n"); 954 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 955 WAIT_CIP(dev); 956 957 do { 958 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 959 GET_SBIC_asr(dev, asr); 960 GET_SBIC_csr(dev, csr); 961 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 962 csr, asr)); 963 } while ((csr != SBIC_CSR_DISC) && 964 (csr != SBIC_CSR_DISC_1) && 965 (csr != SBIC_CSR_CMD_INVALID)); 966 } 967 dev->sc_state = SBIC_ERROR; 968 dev->sc_flags = 0; 969 } 970 return SBIC_STATE_ERROR; 971 } 972 973 974 /* 975 * select the bus, return when selected or error. 976 * 977 * Returns the current CSR following selection and optionally MSG out phase. 978 * i.e. the returned CSR *should* indicate CMD phase... 979 * If the return value is 0, some error happened. 980 */ 981 u_char 982 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 983 { 984 struct scsipi_xfer *xs = acb->xs; 985 struct wd33c93_tinfo *ti; 986 u_char target, lun, asr, csr, id; 987 988 KASSERT(dev->sc_state == SBIC_IDLE); 989 990 target = xs->xs_periph->periph_target; 991 lun = xs->xs_periph->periph_lun; 992 ti = &dev->sc_tinfo[target]; 993 994 dev->sc_state = SBIC_SELECTING; 995 dev->target = target; 996 dev->lun = lun; 997 998 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 999 1000 if ((xs->xs_control & XS_CTL_POLL) == 0) 1001 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 1002 wd33c93_timeout, acb); 1003 1004 /* 1005 * issue select 1006 */ 1007 SBIC_TC_PUT(dev, 0); 1008 SET_SBIC_selid(dev, target); 1009 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1010 1011 GET_SBIC_asr(dev, asr); 1012 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1013 /* This means we got ourselves reselected upon */ 1014 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1015 return 0; 1016 } 1017 1018 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 1019 WAIT_CIP(dev); 1020 1021 /* 1022 * wait for select (merged from separate function may need 1023 * cleanup) 1024 */ 1025 do { 1026 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1027 if (asr & SBIC_ASR_LCI) { 1028 QPRINTF(("late LCI: asr %02x\n", asr)); 1029 return 0; 1030 } 1031 1032 /* Clear interrupt */ 1033 GET_SBIC_csr (dev, csr); 1034 1035 /* Reselected from under our feet? */ 1036 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1037 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1038 /* 1039 * We need to handle this now so we don't lock up later 1040 */ 1041 wd33c93_nextstate(dev, acb, csr, asr); 1042 return 0; 1043 } 1044 1045 /* Whoops! */ 1046 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1047 panic("wd33c93_selectbus: target issued select!"); 1048 return 0; 1049 } 1050 1051 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1052 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1053 csr != SBIC_CSR_SEL_TIMEO); 1054 1055 /* Anyone at home? */ 1056 if (csr == SBIC_CSR_SEL_TIMEO) { 1057 xs->error = XS_SELTIMEOUT; 1058 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1059 return 0; 1060 } 1061 1062 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1063 1064 /* Assume we're now selected */ 1065 GET_SBIC_selid(dev, id); 1066 if (id != target) { 1067 /* Something went wrong - wrong target was select */ 1068 printf("wd33c93_selectbus: wrong target selected;" 1069 " WANTED %d GOT %d", target, id); 1070 return 0; /* XXX: Need to call nexstate to handle? */ 1071 } 1072 1073 dev->sc_flags |= SBICF_SELECTED; 1074 dev->sc_state = SBIC_CONNECTED; 1075 1076 /* setup correct sync mode for this target */ 1077 wd33c93_setsync(dev, ti); 1078 1079 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1080 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1081 else 1082 SET_SBIC_rselid (dev, SBIC_RID_ER); 1083 1084 /* 1085 * We only really need to do anything when the target goes to MSG out 1086 * If the device ignored ATN, it's probably old and brain-dead, 1087 * but we'll try to support it anyhow. 1088 * If it doesn't support message out, it definately doesn't 1089 * support synchronous transfers, so no point in even asking... 1090 */ 1091 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1092 if (ti->flags & T_NEGOTIATE) { 1093 /* Inititae a SDTR message */ 1094 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1095 if (ti->flags & T_WANTSYNC) { 1096 ti->period = dev->sc_minsyncperiod; 1097 ti->offset = dev->sc_maxoffset; 1098 } else { 1099 ti->period = 0; 1100 ti->offset = 0; 1101 } 1102 /* Send Sync negotiation message */ 1103 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1104 dev->sc_omsg[1] = MSG_EXTENDED; 1105 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1106 dev->sc_omsg[3] = MSG_EXT_SDTR; 1107 if (ti->flags & T_WANTSYNC) { 1108 dev->sc_omsg[4] = dev->sc_minsyncperiod; 1109 dev->sc_omsg[5] = dev->sc_maxoffset; 1110 } else { 1111 dev->sc_omsg[4] = 0; 1112 dev->sc_omsg[5] = 0; 1113 } 1114 wd33c93_xfout(dev, 6, dev->sc_omsg); 1115 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1116 dev->sc_flags |= SBICF_SYNCNEGO; 1117 } else { 1118 if (dev->sc_nexus->tag_type != 0) { 1119 /* Use TAGS */ 1120 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1121 dev->target, dev->lun, 1122 dev->sc_nexus->tag_id)); 1123 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1124 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1125 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1126 wd33c93_xfout(dev, 3, dev->sc_omsg); 1127 dev->sc_msgout |= SEND_TAG; 1128 } else { 1129 int no_disc; 1130 1131 /* Setup LUN nexus and disconnect privilege */ 1132 no_disc = xs->xs_control & XS_CTL_POLL || 1133 ti->flags & T_NODISC; 1134 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1135 } 1136 } 1137 /* 1138 * There's one interrupt still to come: 1139 * the change to CMD phase... 1140 */ 1141 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1142 GET_SBIC_csr(dev, csr); 1143 } 1144 1145 return csr; 1146 } 1147 1148 /* 1149 * Information Transfer *to* a SCSI Target. 1150 * 1151 * Note: Don't expect there to be an interrupt immediately after all 1152 * the data is transferred out. The WD spec sheet says that the Transfer- 1153 * Info command for non-MSG_IN phases only completes when the target 1154 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1155 * 1156 * This can have a nasty effect on commands which take a relatively long 1157 * time to complete, for example a START/STOP unit command may remain in 1158 * CMD phase until the disk has spun up. Only then will the target change 1159 * to STATUS phase. This is really only a problem for immediate commands 1160 * since we don't allow disconnection for them (yet). 1161 */ 1162 int 1163 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1164 { 1165 int wait = wd33c93_data_wait; 1166 u_char asr, *buf = bp; 1167 1168 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1169 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1170 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1171 1172 /* 1173 * sigh.. WD-PROTO strikes again.. sending the command in one go 1174 * causes the chip to lock up if talking to certain (misbehaving?) 1175 * targets. Anyway, this procedure should work for all targets, but 1176 * it's slightly slower due to the overhead 1177 */ 1178 1179 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1180 SBIC_TC_PUT (dev, (unsigned)len); 1181 1182 WAIT_CIP (dev); 1183 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1184 1185 /* 1186 * Loop for each byte transferred 1187 */ 1188 do { 1189 GET_SBIC_asr (dev, asr); 1190 1191 if (asr & SBIC_ASR_DBR) { 1192 if (len) { 1193 SET_SBIC_data (dev, *buf); 1194 buf++; 1195 len--; 1196 } else { 1197 SET_SBIC_data (dev, 0); 1198 } 1199 wait = wd33c93_data_wait; 1200 } 1201 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1202 1203 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1204 1205 /* 1206 * Normally, an interrupt will be pending when this routing returns. 1207 */ 1208 return(len); 1209 } 1210 1211 /* 1212 * Information Transfer *from* a Scsi Target 1213 * returns # bytes left to read 1214 */ 1215 int 1216 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1217 { 1218 int wait = wd33c93_data_wait; 1219 u_char *buf = bp; 1220 u_char asr; 1221 #ifdef DEBUG 1222 u_char *obp = bp; 1223 #endif 1224 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1225 SBIC_TC_PUT (dev, (unsigned)len); 1226 1227 WAIT_CIP (dev); 1228 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1229 1230 /* 1231 * Loop for each byte transferred 1232 */ 1233 do { 1234 GET_SBIC_asr (dev, asr); 1235 1236 if (asr & SBIC_ASR_DBR) { 1237 if (len) { 1238 GET_SBIC_data (dev, *buf); 1239 buf++; 1240 len--; 1241 } else { 1242 u_char foo; 1243 GET_SBIC_data (dev, foo); 1244 } 1245 wait = wd33c93_data_wait; 1246 } 1247 1248 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1249 1250 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1251 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1252 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1253 1254 SBIC_TC_PUT (dev, 0); 1255 1256 /* 1257 * this leaves with one csr to be read 1258 */ 1259 return len; 1260 } 1261 1262 1263 /* 1264 * Finish SCSI xfer command: After the completion interrupt from 1265 * a read/write operation, sequence through the final phases in 1266 * programmed i/o. 1267 */ 1268 void 1269 wd33c93_xferdone(struct wd33c93_softc *dev) 1270 { 1271 u_char phase, csr; 1272 int s; 1273 1274 QPRINTF(("{")); 1275 s = splbio(); 1276 1277 /* 1278 * have the wd33c93 complete on its own 1279 */ 1280 SBIC_TC_PUT(dev, 0); 1281 SET_SBIC_cmd_phase(dev, 0x46); 1282 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1283 1284 do { 1285 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1286 GET_SBIC_csr (dev, csr); 1287 QPRINTF(("%02x:", csr)); 1288 } while ((csr != SBIC_CSR_DISC) && 1289 (csr != SBIC_CSR_DISC_1) && 1290 (csr != SBIC_CSR_S_XFERRED)); 1291 1292 dev->sc_flags &= ~SBICF_SELECTED; 1293 dev->sc_state = SBIC_DISCONNECT; 1294 1295 GET_SBIC_cmd_phase (dev, phase); 1296 QPRINTF(("}%02x", phase)); 1297 1298 if (phase == 0x60) 1299 GET_SBIC_tlun(dev, dev->sc_status); 1300 else 1301 wd33c93_error(dev, dev->sc_nexus); 1302 1303 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1304 splx(s); 1305 } 1306 1307 1308 int 1309 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1310 { 1311 struct scsipi_xfer *xs = acb->xs; 1312 int i, dmaok; 1313 u_char csr, asr; 1314 1315 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1316 1317 dev->sc_nexus = acb; 1318 1319 dev->target = xs->xs_periph->periph_target; 1320 dev->lun = xs->xs_periph->periph_lun; 1321 1322 dev->sc_status = STATUS_UNKNOWN; 1323 dev->sc_daddr = acb->daddr; 1324 dev->sc_dleft = acb->dleft; 1325 1326 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1327 dev->sc_flags = 0; 1328 1329 dmaok = wd33c93_dmaok(dev, xs); 1330 1331 if (dmaok == 0) 1332 dev->sc_flags |= SBICF_NODMA; 1333 1334 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1335 dev->target, dev->sc_tcnt, dmaok)); 1336 1337 /* select the SCSI bus (it's an error if bus isn't free) */ 1338 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1339 return(0); /* Not done: needs to be rescheduled */ 1340 1341 /* 1342 * Lets cycle a while then let the interrupt handler take over. 1343 */ 1344 GET_SBIC_asr(dev, asr); 1345 do { 1346 QPRINTF(("go[0x%x] ", csr)); 1347 1348 /* Handle the new phase */ 1349 i = wd33c93_nextstate(dev, acb, csr, asr); 1350 WAIT_CIP(dev); /* XXX */ 1351 if (dev->sc_state == SBIC_CONNECTED) { 1352 1353 GET_SBIC_asr(dev, asr); 1354 1355 if (asr & SBIC_ASR_LCI) 1356 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1357 1358 if (asr & SBIC_ASR_INT) 1359 GET_SBIC_csr(dev, csr); 1360 } 1361 1362 } while (dev->sc_state == SBIC_CONNECTED && 1363 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1364 1365 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1366 1367 if (i == SBIC_STATE_DONE) { 1368 if (dev->sc_status == STATUS_UNKNOWN) { 1369 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1370 return 1; /* Did we really finish that fast? */ 1371 } 1372 } 1373 return 0; 1374 } 1375 1376 1377 int 1378 wd33c93_intr(struct wd33c93_softc *dev) 1379 { 1380 u_char asr, csr; 1381 int i; 1382 1383 /* 1384 * pending interrupt? 1385 */ 1386 GET_SBIC_asr (dev, asr); 1387 if ((asr & SBIC_ASR_INT) == 0) 1388 return(0); 1389 1390 GET_SBIC_csr(dev, csr); 1391 1392 do { 1393 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1394 1395 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1396 WAIT_CIP(dev); /* XXX */ 1397 if (dev->sc_state == SBIC_CONNECTED) { 1398 GET_SBIC_asr(dev, asr); 1399 1400 if (asr & SBIC_ASR_LCI) 1401 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1402 asr, csr); 1403 1404 if (asr & SBIC_ASR_INT) 1405 GET_SBIC_csr(dev, csr); 1406 } 1407 } while (dev->sc_state == SBIC_CONNECTED && 1408 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1409 1410 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1411 1412 return(1); 1413 } 1414 1415 /* 1416 * Complete current command using polled I/O. Used when interrupt driven 1417 * I/O is not allowed (ie. during boot and shutdown) 1418 * 1419 * Polled I/O is very processor intensive 1420 */ 1421 int 1422 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1423 { 1424 u_char asr, csr=0; 1425 int i, count; 1426 struct scsipi_xfer *xs = acb->xs; 1427 1428 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1429 for (count=acb->timeout; count;) { 1430 GET_SBIC_asr (dev, asr); 1431 if (asr & SBIC_ASR_LCI) 1432 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1433 asr, csr); 1434 if (asr & SBIC_ASR_INT) { 1435 GET_SBIC_csr(dev, csr); 1436 dev->sc_flags |= SBICF_NODMA; 1437 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1438 WAIT_CIP(dev); /* XXX */ 1439 } else { 1440 DELAY(1000); 1441 count--; 1442 } 1443 1444 if ((xs->xs_status & XS_STS_DONE) != 0) 1445 return (0); 1446 1447 if (dev->sc_state == SBIC_IDLE) { 1448 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1449 wd33c93_sched(dev); 1450 } 1451 } 1452 return (1); 1453 } 1454 1455 static inline int 1456 __verify_msg_format(u_char *p, int len) 1457 { 1458 1459 if (len == 1 && MSG_IS1BYTE(p[0])) 1460 return 1; 1461 if (len == 2 && MSG_IS2BYTE(p[0])) 1462 return 1; 1463 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1464 len == p[1] + 2) 1465 return 1; 1466 return 0; 1467 } 1468 1469 /* 1470 * Handle message_in phase 1471 */ 1472 int 1473 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1474 { 1475 int len; 1476 u_char asr, csr, *msg; 1477 1478 GET_SBIC_asr(dev, asr); 1479 1480 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1481 1482 GET_SBIC_selid (dev, csr); 1483 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1484 1485 SBIC_TC_PUT(dev, 0); 1486 1487 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1488 1489 msg = dev->sc_imsg; 1490 len = 0; 1491 1492 do { 1493 /* Fetch the next byte of the message */ 1494 RECV_BYTE(dev, *msg++); 1495 len++; 1496 1497 /* 1498 * get the command completion interrupt, or we 1499 * can't send a new command (LCI) 1500 */ 1501 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1502 GET_SBIC_csr(dev, csr); 1503 1504 if (__verify_msg_format(dev->sc_imsg, len)) 1505 break; /* Complete message recieved */ 1506 1507 /* 1508 * Clear ACK, and wait for the interrupt 1509 * for the next byte or phase change 1510 */ 1511 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1512 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1513 1514 GET_SBIC_csr(dev, csr); 1515 } while (len < SBIC_MAX_MSGLEN); 1516 1517 if (__verify_msg_format(dev->sc_imsg, len)) 1518 wd33c93_msgin(dev, dev->sc_imsg, len); 1519 1520 /* 1521 * Clear ACK, and wait for the interrupt 1522 * for the phase change 1523 */ 1524 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1525 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1526 1527 /* Should still have one CSR to read */ 1528 return SBIC_STATE_RUNNING; 1529 } 1530 1531 1532 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1533 { 1534 struct wd33c93_acb *acb = dev->sc_nexus; 1535 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1536 struct wd33c93_linfo *li; 1537 u_char asr; 1538 1539 switch (dev->sc_state) { 1540 case SBIC_CONNECTED: 1541 switch (msgaddr[0]) { 1542 case MSG_MESSAGE_REJECT: 1543 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1544 "last msgout=%x\n", dev->sc_msgout)); 1545 switch (dev->sc_msgout) { 1546 case SEND_TAG: 1547 printf("%s: tagged queuing rejected: " 1548 "target %d\n", 1549 dev->sc_dev.dv_xname, dev->target); 1550 ti->flags &= ~T_TAG; 1551 li = TINFO_LUN(ti, dev->lun); 1552 if (acb->tag_type && 1553 li->queued[acb->tag_id] != NULL) { 1554 li->queued[acb->tag_id] = NULL; 1555 li->used--; 1556 } 1557 acb->tag_type = acb->tag_id = 0; 1558 li->untagged = acb; 1559 li->state = L_STATE_BUSY; 1560 break; 1561 1562 case SEND_SDTR: 1563 printf("%s: sync transfer rejected: target %d\n", 1564 dev->sc_dev.dv_xname, dev->target); 1565 1566 dev->sc_flags &= ~SBICF_SYNCNEGO; 1567 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1568 wd33c93_update_xfer_mode(dev, 1569 acb->xs->xs_periph->periph_target); 1570 wd33c93_setsync(dev, ti); 1571 1572 case SEND_INIT_DET_ERR: 1573 goto abort; 1574 1575 default: 1576 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1577 break; 1578 } 1579 dev->sc_msgout = 0; 1580 break; 1581 1582 case MSG_HEAD_OF_Q_TAG: 1583 case MSG_ORDERED_Q_TAG: 1584 case MSG_SIMPLE_Q_TAG: 1585 printf("-- Out of phase TAG;" 1586 "Nexus=%d:%d Tag=%02x/%02x\n", 1587 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1588 break; 1589 1590 case MSG_DISCONNECT: 1591 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1592 /* 1593 * Mark the fact that all bytes have moved. The 1594 * target may not bother to do a SAVE POINTERS 1595 * at this stage. This flag will set the residual 1596 * count to zero on MSG COMPLETE. 1597 */ 1598 if (dev->sc_dleft == 0) 1599 acb->flags |= ACB_COMPLETE; 1600 1601 if (acb->xs->xs_control & XS_CTL_POLL) 1602 /* Don't allow disconnect in immediate mode */ 1603 goto reject; 1604 else { /* Allow disconnect */ 1605 dev->sc_flags &= ~SBICF_SELECTED; 1606 dev->sc_state = SBIC_DISCONNECT; 1607 } 1608 if ((acb->xs->xs_periph->periph_quirks & 1609 PQUIRK_AUTOSAVE) == 0) 1610 break; 1611 /*FALLTHROUGH*/ 1612 1613 case MSG_SAVEDATAPOINTER: 1614 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1615 acb->daddr = dev->sc_daddr; 1616 acb->dleft = dev->sc_dleft; 1617 break; 1618 1619 case MSG_RESTOREPOINTERS: 1620 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1621 dev->sc_daddr = acb->daddr; 1622 dev->sc_dleft = acb->dleft; 1623 break; 1624 1625 case MSG_CMDCOMPLETE: 1626 /* 1627 * !! KLUDGE ALERT !! quite a few drives don't seem to 1628 * really like the current way of sending the 1629 * sync-handshake together with the ident-message, and 1630 * they react by sending command-complete and 1631 * disconnecting right after returning the valid sync 1632 * handshake. So, all I can do is reselect the drive, 1633 * and hope it won't disconnect again. I don't think 1634 * this is valid behavior, but I can't help fixing a 1635 * problem that apparently exists. 1636 * 1637 * Note: we should not get here on `normal' command 1638 * completion, as that condition is handled by the 1639 * high-level sel&xfer resume command used to walk 1640 * thru status/cc-phase. 1641 */ 1642 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1643 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1644 " acting weird.." 1645 " waiting for disconnect...\n", 1646 msgaddr[0], dev->target)); 1647 1648 /* Check to see if wd33c93 is handling this */ 1649 GET_SBIC_asr(dev, asr); 1650 if (asr & SBIC_ASR_BSY) 1651 break; 1652 1653 /* XXX: Assume it works and set status to 00 */ 1654 dev->sc_status = 0; 1655 dev->sc_state = SBIC_CMDCOMPLETE; 1656 break; 1657 1658 case MSG_EXTENDED: 1659 switch(msgaddr[2]) { 1660 case MSG_EXT_SDTR: /* Sync negotiation */ 1661 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1662 "period %d, offset %d", 1663 msgaddr[3], msgaddr[4])); 1664 if (msgaddr[1] != 3) 1665 goto reject; 1666 1667 ti->period = 1668 MAX(msgaddr[3], dev->sc_minsyncperiod); 1669 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1670 1671 /* 1672 * <SGI, IBM DORS-32160, WA6A> will do nothing 1673 * but attempt sync negotiation until it gets 1674 * what it wants. To avoid an infinite loop set 1675 * off by the identify request, oblige them. 1676 */ 1677 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0 && 1678 msgaddr[3] != 0) 1679 ti->flags |= T_WANTSYNC; 1680 1681 if (!(ti->flags & T_WANTSYNC)) 1682 ti->period = ti->offset = 0; 1683 1684 ti->flags &= ~T_NEGOTIATE; 1685 1686 if (ti->offset == 0) 1687 ti->flags &= ~T_SYNCMODE; /* Async */ 1688 else 1689 ti->flags |= T_SYNCMODE; /* Sync */ 1690 1691 /* target initiated negotiation */ 1692 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1693 wd33c93_sched_msgout(dev, SEND_SDTR); 1694 dev->sc_flags &= ~SBICF_SYNCNEGO; 1695 1696 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1697 dev->target, ti->offset, 1698 ti->period)); 1699 wd33c93_update_xfer_mode(dev, 1700 acb->xs->xs_periph->periph_target); 1701 wd33c93_setsync(dev, ti); 1702 break; 1703 1704 case MSG_EXT_WDTR: 1705 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1706 goto reject; 1707 1708 default: 1709 scsipi_printaddr(acb->xs->xs_periph); 1710 printf("unrecognized MESSAGE EXTENDED;" 1711 " sending REJECT\n"); 1712 goto reject; 1713 } 1714 break; 1715 1716 default: 1717 scsipi_printaddr(acb->xs->xs_periph); 1718 printf("unrecognized MESSAGE; sending REJECT\n"); 1719 1720 reject: 1721 /* We don't support whatever this message is... */ 1722 wd33c93_sched_msgout(dev, SEND_REJECT); 1723 break; 1724 } 1725 break; 1726 1727 case SBIC_IDENTIFIED: 1728 /* 1729 * IDENTIFY message was received and queue tag is expected now 1730 */ 1731 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1732 printf("%s: TAG reselect without IDENTIFY;" 1733 " MSG %x; sending DEVICE RESET\n", 1734 dev->sc_dev.dv_xname, msgaddr[0]); 1735 goto reset; 1736 } 1737 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1738 if (dev->sc_nexus) 1739 printf("*TAG Recv with active nexus!!\n"); 1740 wd33c93_reselect(dev, dev->target, dev->lun, 1741 msgaddr[0], msgaddr[1]); 1742 break; 1743 1744 case SBIC_RESELECTED: 1745 /* 1746 * IDENTIFY message with target 1747 */ 1748 if (MSG_ISIDENTIFY(msgaddr[0])) { 1749 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1750 dev->sc_msgify = msgaddr[0]; 1751 } else { 1752 printf("%s: reselect without IDENTIFY;" 1753 " MSG %x;" 1754 " sending DEVICE RESET\n", 1755 dev->sc_dev.dv_xname, msgaddr[0]); 1756 goto reset; 1757 } 1758 break; 1759 1760 default: 1761 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1762 dev->sc_state); 1763 reset: 1764 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1765 break; 1766 abort: 1767 wd33c93_sched_msgout(dev, SEND_ABORT); 1768 break; 1769 } 1770 } 1771 1772 void 1773 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1774 { 1775 u_char asr; 1776 1777 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1778 dev->sc_msgpriq |= msg; 1779 1780 /* Schedule MSGOUT Phase to send message */ 1781 1782 WAIT_CIP(dev); 1783 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1784 WAIT_CIP(dev); 1785 GET_SBIC_asr(dev, asr); 1786 if (asr & SBIC_ASR_LCI) { 1787 printf("MSGOUT Failed!\n"); 1788 } 1789 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1790 WAIT_CIP(dev); 1791 } 1792 1793 /* 1794 * Send the highest priority, scheduled message 1795 */ 1796 void 1797 wd33c93_msgout(struct wd33c93_softc *dev) 1798 { 1799 struct wd33c93_tinfo *ti; 1800 struct wd33c93_acb *acb = dev->sc_nexus; 1801 1802 if (acb == NULL) 1803 panic("MSGOUT with no nexus"); 1804 1805 if (dev->sc_omsglen == 0) { 1806 /* Pick up highest priority message */ 1807 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1808 dev->sc_msgoutq |= dev->sc_msgout; 1809 dev->sc_msgpriq &= ~dev->sc_msgout; 1810 dev->sc_omsglen = 1; /* "Default" message len */ 1811 switch (dev->sc_msgout) { 1812 case SEND_SDTR: 1813 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1814 dev->sc_omsg[0] = MSG_EXTENDED; 1815 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1816 dev->sc_omsg[2] = MSG_EXT_SDTR; 1817 if (ti->flags & T_WANTSYNC) { 1818 dev->sc_omsg[3] = ti->period; 1819 dev->sc_omsg[4] = ti->offset; 1820 } else { 1821 dev->sc_omsg[3] = 0; 1822 dev->sc_omsg[4] = 0; 1823 } 1824 dev->sc_omsglen = 5; 1825 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1826 if (ti->flags & T_WANTSYNC) 1827 ti->flags |= T_SYNCMODE; 1828 else 1829 ti->flags &= ~T_SYNCMODE; 1830 wd33c93_setsync(dev, ti); 1831 } 1832 break; 1833 case SEND_IDENTIFY: 1834 if (dev->sc_state != SBIC_CONNECTED) { 1835 printf("%s at line %d: no nexus\n", 1836 dev->sc_dev.dv_xname, __LINE__); 1837 } 1838 dev->sc_omsg[0] = 1839 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1840 break; 1841 case SEND_TAG: 1842 if (dev->sc_state != SBIC_CONNECTED) { 1843 printf("%s at line %d: no nexus\n", 1844 dev->sc_dev.dv_xname, __LINE__); 1845 } 1846 dev->sc_omsg[0] = acb->tag_type; 1847 dev->sc_omsg[1] = acb->tag_id; 1848 dev->sc_omsglen = 2; 1849 break; 1850 case SEND_DEV_RESET: 1851 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1852 ti = &dev->sc_tinfo[dev->target]; 1853 ti->flags &= ~T_SYNCMODE; 1854 wd33c93_update_xfer_mode(dev, dev->target); 1855 if ((ti->flags & T_NOSYNC) == 0) 1856 /* We can re-start sync negotiation */ 1857 ti->flags |= T_NEGOTIATE; 1858 break; 1859 case SEND_PARITY_ERROR: 1860 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1861 break; 1862 case SEND_ABORT: 1863 dev->sc_flags |= SBICF_ABORTING; 1864 dev->sc_omsg[0] = MSG_ABORT; 1865 break; 1866 case SEND_INIT_DET_ERR: 1867 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1868 break; 1869 case SEND_REJECT: 1870 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1871 break; 1872 default: 1873 /* Wasn't expecting MSGOUT Phase */ 1874 dev->sc_omsg[0] = MSG_NOOP; 1875 break; 1876 } 1877 } 1878 1879 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1880 } 1881 1882 1883 /* 1884 * wd33c93_nextstate() 1885 * return: 1886 * SBIC_STATE_DONE == done 1887 * SBIC_STATE_RUNNING == working 1888 * SBIC_STATE_DISCONNECT == disconnected 1889 * SBIC_STATE_ERROR == error 1890 */ 1891 int 1892 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1893 { 1894 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1895 1896 switch (csr) { 1897 1898 case SBIC_CSR_XFERRED | CMD_PHASE: 1899 case SBIC_CSR_MIS | CMD_PHASE: 1900 case SBIC_CSR_MIS_1 | CMD_PHASE: 1901 case SBIC_CSR_MIS_2 | CMD_PHASE: 1902 1903 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1904 goto abort; 1905 break; 1906 1907 case SBIC_CSR_XFERRED | STATUS_PHASE: 1908 case SBIC_CSR_MIS | STATUS_PHASE: 1909 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1910 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1911 1912 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1913 1914 /* 1915 * this should be the normal i/o completion case. 1916 * get the status & cmd complete msg then let the 1917 * device driver look at what happened. 1918 */ 1919 wd33c93_xferdone(dev); 1920 1921 wd33c93_dma_stop(dev); 1922 1923 /* Fixup byte count to be passed to higher layer */ 1924 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1925 dev->sc_dleft; 1926 1927 /* 1928 * Indicate to the upper layers that the command is done 1929 */ 1930 wd33c93_scsidone(dev, acb, dev->sc_status); 1931 1932 return SBIC_STATE_DONE; 1933 1934 1935 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1936 case SBIC_CSR_MIS | DATA_IN_PHASE: 1937 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1938 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1939 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1940 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1941 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1942 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1943 /* 1944 * Verify that we expected to transfer data... 1945 */ 1946 if (acb->dleft <= 0) { 1947 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1948 acb->dleft, asr, csr); 1949 goto abort; 1950 } 1951 1952 /* 1953 * Should we transfer using PIO or DMA ? 1954 */ 1955 if (acb->xs->xs_control & XS_CTL_POLL || 1956 dev->sc_flags & SBICF_NODMA) { 1957 /* Perfrom transfer using PIO */ 1958 int resid; 1959 1960 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1961 dev->sc_daddr, dev->sc_dleft)); 1962 1963 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1964 /* data in */ 1965 resid = wd33c93_xfin(dev, dev->sc_dleft, 1966 dev->sc_daddr); 1967 else /* data out */ 1968 resid = wd33c93_xfout(dev, dev->sc_dleft, 1969 dev->sc_daddr); 1970 1971 dev->sc_daddr = (char*)dev->sc_daddr + 1972 (acb->dleft - resid); 1973 dev->sc_dleft = resid; 1974 } else { 1975 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1976 1977 /* Perform transfer using DMA */ 1978 wd33c93_dma_setup(dev, datain); 1979 1980 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1981 dev->sc_dmamode); 1982 1983 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1984 dev->sc_daddr, dev->sc_dleft)); 1985 1986 /* Setup byte count for transfer */ 1987 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1988 1989 /* Start the transfer */ 1990 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1991 1992 /* Start the DMA chip going */ 1993 dev->sc_tcnt = dev->sc_dmago(dev); 1994 1995 /* Indicate that we're in DMA mode */ 1996 dev->sc_flags |= SBICF_INDMA; 1997 } 1998 break; 1999 2000 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2001 case SBIC_CSR_MIS | MESG_IN_PHASE: 2002 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2003 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2004 2005 wd33c93_dma_stop(dev); 2006 2007 /* Handle a single message in... */ 2008 return wd33c93_msgin_phase(dev, 0); 2009 2010 case SBIC_CSR_MSGIN_W_ACK: 2011 2012 /* 2013 * We should never see this since it's handled in 2014 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 2015 */ 2016 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2017 2018 printf("Acking unknown msgin CSR:%02x",csr); 2019 break; 2020 2021 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2022 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2023 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2024 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2025 2026 /* 2027 * Message out phase. ATN signal has been asserted 2028 */ 2029 wd33c93_dma_stop(dev); 2030 wd33c93_msgout(dev); 2031 return SBIC_STATE_RUNNING; 2032 2033 case SBIC_CSR_DISC: 2034 case SBIC_CSR_DISC_1: 2035 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2036 dev->target)); 2037 wd33c93_dma_stop(dev); 2038 2039 dev->sc_nexus = NULL; 2040 dev->sc_state = SBIC_IDLE; 2041 dev->sc_flags = 0; 2042 2043 ++dev->sc_tinfo[dev->target].dconns; 2044 ++dev->sc_disc; 2045 2046 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2047 return SBIC_STATE_DISCONNECT; 2048 2049 /* Try to schedule another target */ 2050 wd33c93_sched(dev); 2051 2052 return SBIC_STATE_DISCONNECT; 2053 2054 case SBIC_CSR_RSLT_NI: 2055 case SBIC_CSR_RSLT_IFY: 2056 { 2057 /* 2058 * A reselection. 2059 * Note that since we don't enable Advanced Features (assuming 2060 * the WD chip is at least the 'A' revision), we're only ever 2061 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2062 * hell of it, we'll handle it anyway, for all the extra code 2063 * it needs... 2064 */ 2065 u_char newtarget, newlun; 2066 2067 if (dev->sc_flags & SBICF_INDMA) { 2068 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2069 wd33c93_dma_stop(dev); 2070 } 2071 2072 dev->sc_state = SBIC_RESELECTED; 2073 GET_SBIC_rselid(dev, newtarget); 2074 2075 /* check SBIC_RID_SIV? */ 2076 newtarget &= SBIC_RID_MASK; 2077 2078 if (csr == SBIC_CSR_RSLT_IFY) { 2079 /* Read Identify msg to avoid lockup */ 2080 GET_SBIC_data(dev, newlun); 2081 WAIT_CIP(dev); 2082 newlun &= SBIC_TLUN_MASK; 2083 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 2084 } else { 2085 /* 2086 * Need to read Identify message the hard way, assuming 2087 * the target even sends us one... 2088 */ 2089 for (newlun = 255; newlun; --newlun) { 2090 GET_SBIC_asr(dev, asr); 2091 if (asr & SBIC_ASR_INT) 2092 break; 2093 DELAY(10); 2094 } 2095 2096 /* If we didn't get an interrupt, somethink's up */ 2097 if ((asr & SBIC_ASR_INT) == 0) { 2098 printf("%s: Reselect without identify? asr %x\n", 2099 dev->sc_dev.dv_xname, asr); 2100 newlun = 0; /* XXXX */ 2101 } else { 2102 /* 2103 * We got an interrupt, verify that it's a 2104 * change to message in phase, and if so 2105 * read the message. 2106 */ 2107 GET_SBIC_csr(dev,csr); 2108 2109 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2110 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2111 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2112 /* 2113 * Yup, gone to message in. 2114 * Fetch the target LUN 2115 */ 2116 dev->sc_msgify = 0; 2117 wd33c93_msgin_phase(dev, 1); 2118 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2119 } else { 2120 /* 2121 * Whoops! Target didn't go to msg_in 2122 * phase!! 2123 */ 2124 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2125 newlun = 0; /* XXXSCW */ 2126 } 2127 } 2128 } 2129 2130 /* Ok, we have the identity of the reselecting target. */ 2131 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2132 newtarget, newlun)); 2133 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2134 dev->sc_disc--; 2135 2136 if (csr == SBIC_CSR_RSLT_IFY) 2137 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2138 break; 2139 } 2140 2141 default: 2142 abort: 2143 /* Something unexpected happend -- deal with it. */ 2144 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2145 2146 #ifdef DDB 2147 Debugger(); 2148 #endif 2149 2150 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2151 if (acb->xs) 2152 wd33c93_error(dev, acb); 2153 wd33c93_abort(dev, acb, "next"); 2154 2155 if (dev->sc_flags & SBICF_INDMA) { 2156 wd33c93_dma_stop(dev); 2157 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2158 } 2159 return SBIC_STATE_ERROR; 2160 } 2161 return SBIC_STATE_RUNNING; 2162 } 2163 2164 2165 void 2166 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2167 { 2168 2169 struct wd33c93_tinfo *ti; 2170 struct wd33c93_linfo *li; 2171 struct wd33c93_acb *acb; 2172 2173 if (dev->sc_nexus) { 2174 /* 2175 * Whoops! We've been reselected with a 2176 * command in progress! 2177 * The best we can do is to put the current 2178 * command back on the ready list and hope 2179 * for the best. 2180 */ 2181 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2182 dev->sc_dev.dv_xname)); 2183 ti = &dev->sc_tinfo[dev->target]; 2184 li = TINFO_LUN(ti, dev->lun); 2185 li->state = L_STATE_IDLE; 2186 2187 wd33c93_dequeue(dev, dev->sc_nexus); 2188 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2189 dev->sc_nexus->flags |= ACB_READY; 2190 2191 dev->sc_nexus = NULL; 2192 } 2193 2194 /* Setup state for new nexus */ 2195 acb = NULL; 2196 dev->sc_flags = SBICF_SELECTED; 2197 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2198 2199 ti = &dev->sc_tinfo[target]; 2200 li = TINFO_LUN(ti, lun); 2201 2202 if (li != NULL) { 2203 if (li->untagged != NULL && li->state) 2204 acb = li->untagged; 2205 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2206 /* Wait for tag to come by during MESG_IN Phase */ 2207 dev->target = target; /* setup I_T_L nexus */ 2208 dev->lun = lun; 2209 dev->sc_state = SBIC_IDENTIFIED; 2210 return; 2211 } else if (tag_type) 2212 acb = li->queued[tag_id]; 2213 } 2214 2215 if (acb == NULL) { 2216 printf("%s: reselect from target %d lun %d tag %x:%x " 2217 "with no nexus; sending ABORT\n", 2218 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2219 goto abort; 2220 } 2221 2222 dev->target = target; 2223 dev->lun = lun; 2224 dev->sc_nexus = acb; 2225 dev->sc_state = SBIC_CONNECTED; 2226 2227 if (!wd33c93_dmaok(dev, acb->xs)) 2228 dev->sc_flags |= SBICF_NODMA; 2229 2230 /* Do an implicit RESTORE POINTERS. */ 2231 dev->sc_daddr = acb->daddr; 2232 dev->sc_dleft = acb->dleft; 2233 2234 /* Set sync modes for new target */ 2235 wd33c93_setsync(dev, ti); 2236 2237 if (acb->flags & ACB_RESET) 2238 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2239 else if (acb->flags & ACB_ABORT) 2240 wd33c93_sched_msgout(dev, SEND_ABORT); 2241 return; 2242 2243 abort: 2244 wd33c93_sched_msgout(dev, SEND_ABORT); 2245 return; 2246 2247 } 2248 2249 void 2250 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2251 { 2252 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2253 struct scsipi_xfer_mode xm; 2254 2255 xm.xm_target = target; 2256 xm.xm_mode = 0; 2257 xm.xm_period = 0; 2258 xm.xm_offset = 0; 2259 2260 if (ti->flags & T_SYNCMODE) { 2261 xm.xm_mode |= PERIPH_CAP_SYNC; 2262 xm.xm_period = ti->period; 2263 xm.xm_offset = ti->offset; 2264 } 2265 2266 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2267 xm.xm_mode |= PERIPH_CAP_TQING; 2268 2269 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2270 xm.xm_target, 2271 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2272 2273 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2274 } 2275 2276 void 2277 wd33c93_timeout(void *arg) 2278 { 2279 struct wd33c93_acb *acb = arg; 2280 struct scsipi_xfer *xs = acb->xs; 2281 struct scsipi_periph *periph = xs->xs_periph; 2282 struct wd33c93_softc *dev = 2283 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2284 int s, asr; 2285 2286 s = splbio(); 2287 2288 GET_SBIC_asr(dev, asr); 2289 2290 scsipi_printaddr(periph); 2291 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2292 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2293 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2294 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2295 dev->sc_msgpriq, dev->sc_msgout); 2296 2297 if (asr & SBIC_ASR_INT) { 2298 /* We need to service a missed IRQ */ 2299 wd33c93_intr(dev); 2300 } else { 2301 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2302 } 2303 splx(s); 2304 } 2305 2306 2307 void 2308 wd33c93_watchdog(void *arg) 2309 { 2310 struct wd33c93_softc *dev = arg; 2311 struct wd33c93_tinfo *ti; 2312 struct wd33c93_linfo *li; 2313 int t, s, l; 2314 /* scrub LUN's that have not been used in the last 10min. */ 2315 time_t old = time_second - (10 * 60); 2316 2317 for (t = 0; t < SBIC_NTARG; t++) { 2318 ti = &dev->sc_tinfo[t]; 2319 for (l = 0; l < SBIC_NLUN; l++) { 2320 s = splbio(); 2321 li = TINFO_LUN(ti, l); 2322 if (li && li->last_used < old && 2323 li->untagged == NULL && li->used == 0) { 2324 ti->lun[li->lun] = NULL; 2325 free(li, M_DEVBUF); 2326 } 2327 splx(s); 2328 } 2329 } 2330 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2331 } 2332 2333 2334 #ifdef DEBUG 2335 void 2336 wd33c93_hexdump(u_char *buf, int len) 2337 { 2338 printf("{%d}:", len); 2339 while (len--) 2340 printf(" %02x", *buf++); 2341 printf("\n"); 2342 } 2343 2344 2345 void 2346 wd33c93_print_csr(u_char csr) 2347 { 2348 switch (SCSI_PHASE(csr)) { 2349 case CMD_PHASE: 2350 printf("CMD_PHASE\n"); 2351 break; 2352 2353 case STATUS_PHASE: 2354 printf("STATUS_PHASE\n"); 2355 break; 2356 2357 case DATA_IN_PHASE: 2358 printf("DATAIN_PHASE\n"); 2359 break; 2360 2361 case DATA_OUT_PHASE: 2362 printf("DATAOUT_PHASE\n"); 2363 break; 2364 2365 case MESG_IN_PHASE: 2366 printf("MESG_IN_PHASE\n"); 2367 break; 2368 2369 case MESG_OUT_PHASE: 2370 printf("MESG_OUT_PHASE\n"); 2371 break; 2372 2373 default: 2374 switch (csr) { 2375 case SBIC_CSR_DISC_1: 2376 printf("DISC_1\n"); 2377 break; 2378 2379 case SBIC_CSR_RSLT_NI: 2380 printf("RESELECT_NO_IFY\n"); 2381 break; 2382 2383 case SBIC_CSR_RSLT_IFY: 2384 printf("RESELECT_IFY\n"); 2385 break; 2386 2387 case SBIC_CSR_SLT: 2388 printf("SELECT\n"); 2389 break; 2390 2391 case SBIC_CSR_SLT_ATN: 2392 printf("SELECT, ATN\n"); 2393 break; 2394 2395 case SBIC_CSR_UNK_GROUP: 2396 printf("UNK_GROUP\n"); 2397 break; 2398 2399 default: 2400 printf("UNKNOWN csr=%02x\n", csr); 2401 } 2402 } 2403 } 2404 #endif 2405
Indexes created Wed Sep 24 15:09:51 GMT 2025