wd33c93.c revision 1.23
1 /* $NetBSD: wd33c93.c,v 1.23 2009/02/12 06:20:58 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.23 2009/02/12 06:20:58 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <sys/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *sc) 188 { 189 struct scsipi_adapter *adapt = &sc->sc_adapter; 190 struct scsipi_channel *chan = &sc->sc_channel; 191 192 adapt->adapt_dev = sc->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &sc->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = sc->sc_id; 207 208 callout_init(&sc->sc_watchdog, 0); 209 210 /* 211 * Add reference to adapter so that we drop the reference after 212 * config_found() to make sure the adatper is disabled. 213 */ 214 if (scsipi_adapter_addref(&sc->sc_adapter) != 0) { 215 aprint_error_dev(sc->sc_dev, "unable to enable controller\n"); 216 return; 217 } 218 219 sc->sc_cfflags = device_cfdata(sc->sc_dev)->cf_flags; 220 wd33c93_init(sc); 221 222 aprint_normal(": %s (%d.%d MHz clock, %s, SCSI ID %d)\n", 223 wd33c93_chip_names[sc->sc_chip], 224 sc->sc_clkfreq / 10, sc->sc_clkfreq % 10, 225 (sc->sc_dmamode == SBIC_CTL_DMA) ? "DMA" : 226 (sc->sc_dmamode == SBIC_CTL_DBA_DMA) ? "DBA" : 227 (sc->sc_dmamode == SBIC_CTL_BURST_DMA) ? "BURST DMA" : "PIO", 228 sc->sc_channel.chan_id); 229 if (sc->sc_chip == SBIC_CHIP_WD33C93B) { 230 aprint_normal_dev(sc->sc_dev, "microcode revision 0x%02x", 231 sc->sc_rev); 232 if (sc->sc_minsyncperiod < 50) 233 aprint_normal(", Fast SCSI"); 234 aprint_normal("\n"); 235 } 236 237 sc->sc_child = config_found(sc->sc_dev, &sc->sc_channel, 238 scsiprint); 239 scsipi_adapter_delref(&sc->sc_adapter); 240 } 241 242 /* 243 * Initialize driver-private structures 244 */ 245 void 246 wd33c93_init(struct wd33c93_softc *sc) 247 { 248 u_int i; 249 250 if (!wd33c93_pool_initialized) { 251 /* All instances share the same pool */ 252 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 253 "wd33c93_acb", NULL, IPL_BIO); 254 ++wd33c93_pool_initialized; 255 } 256 257 if (sc->sc_state == 0) { 258 TAILQ_INIT(&sc->ready_list); 259 260 sc->sc_nexus = NULL; 261 sc->sc_disc = 0; 262 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 263 264 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc); 265 } else 266 panic("wd33c93: reinitializing driver!"); 267 268 sc->sc_flags = 0; 269 sc->sc_state = SBIC_IDLE; 270 wd33c93_reset(sc); 271 272 for (i = 0; i < 8; i++) { 273 struct wd33c93_tinfo *ti = &sc->sc_tinfo[i]; 274 /* 275 * cf_flags = 0xTTSSRR 276 * 277 * TT = Bitmask to disable Tagged Queues 278 * SS = Bitmask to disable Sync negotiation 279 * RR = Bitmask to disable disconnect/reselect 280 */ 281 ti->flags = T_NEED_RESET; 282 if (CFFLAGS_NOSYNC(sc->sc_cfflags, i)) 283 ti->flags |= T_NOSYNC; 284 if (CFFLAGS_NODISC(sc->sc_cfflags, i) || wd33c93_nodisc) 285 ti->flags |= T_NODISC; 286 ti->period = sc->sc_minsyncperiod; 287 ti->offset = 0; 288 } 289 } 290 291 void 292 wd33c93_reset(struct wd33c93_softc *sc) 293 { 294 u_int my_id, s, div, i; 295 u_char csr, reg; 296 297 SET_SBIC_cmd(sc, SBIC_CMD_ABORT); 298 WAIT_CIP(sc); 299 300 s = splbio(); 301 302 if (sc->sc_reset != NULL) 303 (*sc->sc_reset)(sc); 304 305 my_id = sc->sc_channel.chan_id & SBIC_ID_MASK; 306 307 /* Enable advanced features and really(!) advanced features */ 308 #if 1 309 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 310 #endif 311 312 SET_SBIC_myid(sc, my_id); 313 314 /* Reset the chip */ 315 SET_SBIC_cmd(sc, SBIC_CMD_RESET); 316 DELAY(25); 317 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 318 319 /* Set up various chip parameters */ 320 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 321 322 GET_SBIC_csr(sc, csr); /* clears interrupt also */ 323 GET_SBIC_cdb1(sc, sc->sc_rev); /* valid with RAF on wd33c93b */ 324 325 switch (csr) { 326 case SBIC_CSR_RESET: 327 sc->sc_chip = SBIC_CHIP_WD33C93; 328 break; 329 case SBIC_CSR_RESET_AM: 330 SET_SBIC_queue_tag(sc, 0x55); 331 GET_SBIC_queue_tag(sc, reg); 332 sc->sc_chip = (reg == 0x55) ? 333 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 334 SET_SBIC_queue_tag(sc, 0x0); 335 break; 336 default: 337 sc->sc_chip = SBIC_CHIP_UNKNOWN; 338 } 339 340 /* 341 * Choose a suitable clock divisor and work out the resulting 342 * sync transfer periods in 4ns units. 343 */ 344 if (sc->sc_clkfreq < 110) { 345 my_id |= SBIC_ID_FS_8_10; 346 div = 2; 347 } else if (sc->sc_clkfreq < 160) { 348 my_id |= SBIC_ID_FS_12_15; 349 div = 3; 350 } else if (sc->sc_clkfreq < 210) { 351 my_id |= SBIC_ID_FS_16_20; 352 div = 4; 353 } else 354 panic("wd33c93: invalid clock speed %d", sc->sc_clkfreq); 355 356 for (i = 0; i < 7; i++) 357 sc->sc_syncperiods[i] = 358 (i + 2) * div * 1250 / sc->sc_clkfreq; 359 sc->sc_minsyncperiod = sc->sc_syncperiods[0]; 360 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 361 sc->sc_syncperiods[0], sc->sc_syncperiods[1], 362 sc->sc_syncperiods[2], sc->sc_syncperiods[3], 363 sc->sc_syncperiods[4], sc->sc_syncperiods[5], 364 sc->sc_syncperiods[6])); 365 366 if (sc->sc_clkfreq >= 160 && sc->sc_chip == SBIC_CHIP_WD33C93B) { 367 for (i = 0; i < 3; i++) 368 sc->sc_fsyncperiods[i] = 369 (i + 2) * 2 * 1250 / sc->sc_clkfreq; 370 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 371 sc->sc_fsyncperiods[0], sc->sc_fsyncperiods[1], 372 sc->sc_fsyncperiods[2])); 373 sc->sc_minsyncperiod = sc->sc_fsyncperiods[0]; 374 } 375 376 /* Max Sync Offset */ 377 if (sc->sc_chip == SBIC_CHIP_WD33C93A || 378 sc->sc_chip == SBIC_CHIP_WD33C93B) 379 sc->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET; 380 else 381 sc->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET; 382 383 /* 384 * don't allow Selection (SBIC_RID_ES) 385 * until we can handle target mode!! 386 */ 387 SET_SBIC_rselid(sc, SBIC_RID_ER); 388 389 /* Asynchronous for now */ 390 SET_SBIC_syn(sc, 0); 391 392 sc->sc_flags = 0; 393 sc->sc_state = SBIC_IDLE; 394 395 splx(s); 396 } 397 398 void 399 wd33c93_error(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 400 { 401 struct scsipi_xfer *xs = acb->xs; 402 403 KASSERT(xs); 404 405 if (xs->xs_control & XS_CTL_SILENT) 406 return; 407 408 scsipi_printaddr(xs->xs_periph); 409 printf("SCSI Error\n"); 410 } 411 412 /* 413 * Determine an appropriate value for the synchronous transfer register 414 * given the period and offset values in *ti. 415 */ 416 u_char 417 wd33c93_stp2syn(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti) 418 { 419 unsigned i; 420 421 /* see if we can handle fast scsi (100-200ns) first */ 422 if (ti->period < 50 && sc->sc_minsyncperiod < 50) { 423 for (i = 0; i < 3; i++) 424 if (sc->sc_fsyncperiods[i] >= ti->period) 425 return (SBIC_SYN(ti->offset, i + 2, 1)); 426 } 427 428 for (i = 0; i < 7; i++) { 429 if (sc->sc_syncperiods[i] >= ti->period) { 430 if (i == 6) 431 return (SBIC_SYN(0, 0, 0)); 432 else 433 return (SBIC_SYN(ti->offset, i + 2, 0)); 434 } 435 } 436 437 /* XXX - can't handle it; do async */ 438 return (SBIC_SYN(0, 0, 0)); 439 } 440 441 /* 442 * Setup sync mode for given target 443 */ 444 void 445 wd33c93_setsync(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti) 446 { 447 u_char syncreg; 448 449 if (ti->flags & T_SYNCMODE) 450 syncreg = wd33c93_stp2syn(sc, ti); 451 else 452 syncreg = SBIC_SYN(0, 0, 0); 453 454 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 455 SET_SBIC_syn(sc, syncreg); 456 } 457 458 /* 459 * Check if current operation can be done using DMA 460 * 461 * returns 1 if DMA OK, 0 for polled I/O transfer 462 */ 463 int 464 wd33c93_dmaok(struct wd33c93_softc *sc, struct scsipi_xfer *xs) 465 { 466 if (wd33c93_nodma || sc->sc_dmamode == SBIC_CTL_NO_DMA || 467 (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 468 return (0); 469 return(1); 470 } 471 472 /* 473 * Setup for DMA transfer 474 */ 475 void 476 wd33c93_dma_setup(struct wd33c93_softc *sc, int datain) 477 { 478 struct wd33c93_acb *acb = sc->sc_nexus; 479 int s; 480 481 sc->sc_daddr = acb->daddr; 482 sc->sc_dleft = acb->dleft; 483 484 s = splbio(); 485 /* Indicate that we're in DMA mode */ 486 if (sc->sc_dleft) { 487 sc->sc_dmasetup(sc, &sc->sc_daddr, &sc->sc_dleft, 488 datain, &sc->sc_dleft); 489 } 490 splx(s); 491 return; 492 } 493 494 495 /* 496 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 497 */ 498 void 499 wd33c93_dma_stop(struct wd33c93_softc *sc) 500 { 501 size_t count; 502 int asr; 503 504 /* Wait until WD chip is idle */ 505 do { 506 GET_SBIC_asr(sc, asr); /* XXX */ 507 if (asr & SBIC_ASR_DBR) { 508 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 509 break; 510 } 511 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 512 513 /* Only need to save pointers if DMA was active */ 514 if (sc->sc_flags & SBICF_INDMA) { 515 int s = splbio(); 516 517 /* Shut down DMA and flush FIFO's */ 518 sc->sc_dmastop(sc); 519 520 /* Fetch the residual count */ 521 SBIC_TC_GET(sc, count); 522 523 /* Work out how many bytes were actually transferred */ 524 count = sc->sc_tcnt - count; 525 526 if (sc->sc_dleft < count) 527 printf("xfer too large: dleft=%zu resid=%zu\n", 528 sc->sc_dleft, count); 529 530 /* Fixup partial xfers */ 531 sc->sc_daddr = (char *)sc->sc_daddr + count; 532 sc->sc_dleft -= count; 533 sc->sc_tcnt = 0; 534 sc->sc_flags &= ~SBICF_INDMA; 535 splx(s); 536 SBIC_DEBUG(DMA, ("dma_stop\n")); 537 } 538 /* 539 * Ensure the WD chip is back in polled I/O mode, with nothing to 540 * transfer. 541 */ 542 SBIC_TC_PUT(sc, 0); 543 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 544 } 545 546 547 /* 548 * Handle new request from scsipi layer 549 */ 550 void 551 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 552 { 553 struct wd33c93_softc *sc = 554 device_private(chan->chan_adapter->adapt_dev); 555 struct scsipi_xfer *xs; 556 struct scsipi_periph *periph; 557 struct wd33c93_acb *acb; 558 int flags, s; 559 560 SBIC_DEBUG(MISC, ("wd33c93_scsi_request: req 0x%x\n", (int)req)); 561 562 switch (req) { 563 case ADAPTER_REQ_RUN_XFER: 564 xs = arg; 565 periph = xs->xs_periph; 566 flags = xs->xs_control; 567 568 if (flags & XS_CTL_DATA_UIO) 569 panic("wd33c93: scsi data uio requested"); 570 571 if (sc->sc_nexus && (flags & XS_CTL_POLL)) 572 panic("wd33c93_scsicmd: busy"); 573 574 s = splbio(); 575 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 576 splx(s); 577 578 if (acb == NULL) { 579 scsipi_printaddr(periph); 580 printf("cannot allocate acb\n"); 581 xs->error = XS_RESOURCE_SHORTAGE; 582 scsipi_done(xs); 583 return; 584 } 585 586 acb->flags = ACB_ACTIVE; 587 acb->xs = xs; 588 acb->clen = xs->cmdlen; 589 acb->daddr = xs->data; 590 acb->dleft = xs->datalen; 591 acb->timeout = xs->timeout; 592 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 593 594 if (flags & XS_CTL_POLL) { 595 /* 596 * Complete currently active command(s) before 597 * issuing an immediate command 598 */ 599 while (sc->sc_nexus) 600 wd33c93_poll(sc, sc->sc_nexus); 601 } 602 603 s = splbio(); 604 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 605 acb->flags |= ACB_READY; 606 607 /* If nothing is active, try to start it now. */ 608 if (sc->sc_state == SBIC_IDLE) 609 wd33c93_sched(sc); 610 splx(s); 611 612 if ((flags & XS_CTL_POLL) == 0) 613 return; 614 615 if (wd33c93_poll(sc, acb)) { 616 wd33c93_timeout(acb); 617 if (wd33c93_poll(sc, acb)) /* 2nd retry for ABORT */ 618 wd33c93_timeout(acb); 619 } 620 return; 621 622 case ADAPTER_REQ_GROW_RESOURCES: 623 /* XXX Not supported. */ 624 return; 625 626 case ADAPTER_REQ_SET_XFER_MODE: 627 { 628 struct wd33c93_tinfo *ti; 629 struct scsipi_xfer_mode *xm = arg; 630 631 ti = &sc->sc_tinfo[xm->xm_target]; 632 ti->flags &= ~T_WANTSYNC; 633 634 if ((CFFLAGS_NOTAGS(sc->sc_cfflags, xm->xm_target) == 0) && 635 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 636 ti->flags |= T_TAG; 637 else 638 ti->flags &= ~T_TAG; 639 640 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 641 "target %d: scsipi requested %s\n", xm->xm_target, 642 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 643 644 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 645 (ti->flags & T_NOSYNC) == 0) 646 ti->flags |= T_WANTSYNC; 647 /* 648 * If we're not going to negotiate, send the notification 649 * now, since it won't happen later. 650 */ 651 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 652 wd33c93_update_xfer_mode(sc, xm->xm_target); 653 else 654 ti->flags |= T_NEGOTIATE; 655 return; 656 } 657 658 } 659 } 660 661 /* 662 * attempt to start the next available command 663 */ 664 void 665 wd33c93_sched(struct wd33c93_softc *sc) 666 { 667 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 668 struct wd33c93_acb *acb; 669 struct wd33c93_tinfo *ti; 670 struct wd33c93_linfo *li; 671 int lun, tag, flags; 672 673 if (sc->sc_state != SBIC_IDLE) 674 return; 675 676 KASSERT(sc->sc_nexus == NULL); 677 678 /* Loop through the ready list looking for work to do... */ 679 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 680 periph = acb->xs->xs_periph; 681 lun = periph->periph_lun; 682 ti = &sc->sc_tinfo[periph->periph_target]; 683 li = TINFO_LUN(ti, lun); 684 685 KASSERT(acb->flags & ACB_READY); 686 687 /* Select type of tag for this command */ 688 if ((ti->flags & T_NODISC) != 0) 689 tag = 0; 690 else if ((ti->flags & T_TAG) == 0) 691 tag = 0; 692 else if ((acb->flags & ACB_SENSE) != 0) 693 tag = 0; 694 else if (acb->xs->xs_control & XS_CTL_POLL) 695 tag = 0; /* No tags for polled commands */ 696 else 697 tag = acb->xs->xs_tag_type; 698 699 if (li == NULL) { 700 /* Initialize LUN info and add to list. */ 701 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 702 if (li == NULL) 703 continue; 704 memset(li, 0, sizeof(*li)); 705 li->lun = lun; 706 if (lun < SBIC_NLUN) 707 ti->lun[lun] = li; 708 } 709 li->last_used = time_second; 710 711 /* 712 * We've found a potential command, but is the target/lun busy? 713 */ 714 715 if (tag == 0 && li->untagged == NULL) 716 li->untagged = acb; /* Issue untagged */ 717 718 if (li->untagged != NULL) { 719 tag = 0; 720 if ((li->state != L_STATE_BUSY) && li->used == 0) { 721 /* Issue this untagged command now */ 722 acb = li->untagged; 723 periph = acb->xs->xs_periph; 724 } else /* Not ready yet */ 725 continue; 726 } 727 728 acb->tag_type = tag; 729 if (tag != 0) { 730 if (li->queued[acb->xs->xs_tag_id]) 731 printf("queueing to active tag\n"); 732 li->queued[acb->xs->xs_tag_id] = acb; 733 acb->tag_id = acb->xs->xs_tag_id; 734 li->used++; 735 break; 736 } 737 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 738 li->state = L_STATE_BUSY; 739 break; 740 } 741 if (li->untagged == NULL && tag != 0) { 742 break; 743 } else 744 printf("%d:%d busy\n", periph->periph_target, 745 periph->periph_lun); 746 } 747 748 if (acb == NULL) { 749 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 750 return; /* did not find an available command */ 751 } 752 753 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 754 periph->periph_lun)); 755 756 TAILQ_REMOVE(&sc->ready_list, acb, chain); 757 acb->flags &= ~ACB_READY; 758 759 flags = acb->xs->xs_control; 760 if (flags & XS_CTL_RESET) 761 wd33c93_reset(sc); 762 763 /* XXX - Implicitly call scsidone on select timeout */ 764 if (wd33c93_go(sc, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 765 acb->dleft = sc->sc_dleft; 766 wd33c93_scsidone(sc, acb, sc->sc_status); 767 return; 768 } 769 770 return; 771 } 772 773 void 774 wd33c93_scsidone(struct wd33c93_softc *sc, struct wd33c93_acb *acb, int status) 775 { 776 struct scsipi_xfer *xs = acb->xs; 777 struct wd33c93_tinfo *ti; 778 struct wd33c93_linfo *li; 779 int s; 780 781 #ifdef DIAGNOSTIC 782 KASSERT(sc->target == xs->xs_periph->periph_target); 783 KASSERT(sc->lun == xs->xs_periph->periph_lun); 784 if (acb == NULL || xs == NULL) { 785 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 786 sc->target, sc->lun); 787 } 788 KASSERT(acb->flags != ACB_FREE); 789 #endif 790 791 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 792 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 793 sc->target, sc->lun, status)); 794 callout_stop(&xs->xs_callout); 795 796 xs->status = status & SCSI_STATUS_MASK; 797 xs->resid = acb->dleft; 798 799 if (xs->error == XS_NOERROR) { 800 switch (xs->status) { 801 case SCSI_CHECK: 802 case SCSI_TERMINATED: 803 /* XXX Need to read sense - return busy for now */ 804 /*FALLTHROUGH*/ 805 case SCSI_QUEUE_FULL: 806 case SCSI_BUSY: 807 xs->error = XS_BUSY; 808 break; 809 } 810 } 811 812 ti = &sc->sc_tinfo[sc->target]; 813 li = TINFO_LUN(ti, sc->lun); 814 ti->cmds++; 815 if (xs->error == XS_SELTIMEOUT) { 816 /* Selection timeout -- discard this LUN if empty */ 817 if (li->untagged == NULL && li->used == 0) { 818 if (sc->lun < SBIC_NLUN) 819 ti->lun[sc->lun] = NULL; 820 free(li, M_DEVBUF); 821 } 822 } 823 824 wd33c93_dequeue(sc, acb); 825 if (sc->sc_nexus == acb) { 826 sc->sc_state = SBIC_IDLE; 827 sc->sc_nexus = NULL; 828 sc->sc_flags = 0; 829 830 if (!TAILQ_EMPTY(&sc->ready_list)) 831 wd33c93_sched(sc); 832 } 833 834 /* place control block back on free list. */ 835 s = splbio(); 836 acb->flags = ACB_FREE; 837 pool_put(&wd33c93_pool, acb); 838 splx(s); 839 840 scsipi_done(xs); 841 } 842 843 void 844 wd33c93_dequeue(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 845 { 846 struct wd33c93_tinfo *ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 847 struct wd33c93_linfo *li; 848 int lun = acb->xs->xs_periph->periph_lun; 849 850 li = TINFO_LUN(ti, lun); 851 #ifdef DIAGNOSTIC 852 if (li == NULL || li->lun != lun) 853 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 854 lun, acb); 855 #endif 856 if (li->untagged == acb) { 857 li->state = L_STATE_IDLE; 858 li->untagged = NULL; 859 } 860 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 861 #ifdef DIAGNOSTIC 862 if (li->queued[acb->tag_id] != NULL && 863 (li->queued[acb->tag_id] != acb)) 864 panic("wd33c93_dequeue: slot %d for lun %d has %p " 865 "instead of acb %p\n", acb->tag_id, 866 lun, li->queued[acb->tag_id], acb); 867 #endif 868 li->queued[acb->tag_id] = NULL; 869 li->used--; 870 } 871 } 872 873 874 int 875 wd33c93_wait(struct wd33c93_softc *sc, u_char until, int timeo, int line) 876 { 877 u_char val; 878 879 if (timeo == 0) 880 timeo = 1000000; /* some large value.. */ 881 GET_SBIC_asr(sc, val); 882 while ((val & until) == 0) { 883 if (timeo-- == 0) { 884 int csr; 885 GET_SBIC_csr(sc, csr); 886 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 887 line, val, csr); 888 #if defined(DDB) && defined(DEBUG) 889 Debugger(); 890 #endif 891 return(val); /* Maybe I should abort */ 892 break; 893 } 894 DELAY(1); 895 GET_SBIC_asr(sc, val); 896 } 897 return(val); 898 } 899 900 int 901 wd33c93_abort(struct wd33c93_softc *sc, struct wd33c93_acb *acb, 902 const char *where) 903 { 904 u_char csr, asr; 905 906 GET_SBIC_asr(sc, asr); 907 GET_SBIC_csr(sc, csr); 908 909 scsipi_printaddr(acb->xs->xs_periph); 910 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 911 912 acb->timeout = SBIC_ABORT_TIMEOUT; 913 acb->flags |= ACB_ABORT; 914 915 /* 916 * Clean up chip itself 917 */ 918 if (sc->sc_nexus == acb) { 919 /* Reschedule timeout. */ 920 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 921 wd33c93_timeout, acb); 922 923 while (asr & SBIC_ASR_DBR) { 924 /* 925 * wd33c93 is jammed w/data. need to clear it 926 * But we don't know what direction it needs to go 927 */ 928 GET_SBIC_data(sc, asr); 929 printf("abort %s: clearing data buffer 0x%02x\n", 930 where, asr); 931 GET_SBIC_asr(sc, asr); 932 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 933 SET_SBIC_data(sc, asr); 934 GET_SBIC_asr(sc, asr); 935 } 936 937 scsipi_printaddr(acb->xs->xs_periph); 938 printf("sending ABORT command\n"); 939 940 WAIT_CIP(sc); 941 SET_SBIC_cmd(sc, SBIC_CMD_ABORT); 942 WAIT_CIP(sc); 943 944 GET_SBIC_asr(sc, asr); 945 946 scsipi_printaddr(acb->xs->xs_periph); 947 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 948 /* 949 * ok, get more drastic.. 950 */ 951 printf("Resetting bus\n"); 952 wd33c93_reset(sc); 953 } else { 954 printf("sending DISCONNECT to target\n"); 955 SET_SBIC_cmd(sc, SBIC_CMD_DISC); 956 WAIT_CIP(sc); 957 958 do { 959 SBIC_WAIT (sc, SBIC_ASR_INT, 0); 960 GET_SBIC_asr(sc, asr); 961 GET_SBIC_csr(sc, csr); 962 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 963 csr, asr)); 964 } while ((csr != SBIC_CSR_DISC) && 965 (csr != SBIC_CSR_DISC_1) && 966 (csr != SBIC_CSR_CMD_INVALID)); 967 } 968 sc->sc_state = SBIC_ERROR; 969 sc->sc_flags = 0; 970 } 971 return SBIC_STATE_ERROR; 972 } 973 974 975 /* 976 * select the bus, return when selected or error. 977 * 978 * Returns the current CSR following selection and optionally MSG out phase. 979 * i.e. the returned CSR *should* indicate CMD phase... 980 * If the return value is 0, some error happened. 981 */ 982 u_char 983 wd33c93_selectbus(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 984 { 985 struct scsipi_xfer *xs = acb->xs; 986 struct wd33c93_tinfo *ti; 987 u_char target, lun, asr, csr, id; 988 989 KASSERT(sc->sc_state == SBIC_IDLE); 990 991 target = xs->xs_periph->periph_target; 992 lun = xs->xs_periph->periph_lun; 993 ti = &sc->sc_tinfo[target]; 994 995 sc->sc_state = SBIC_SELECTING; 996 sc->target = target; 997 sc->lun = lun; 998 999 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 1000 1001 if ((xs->xs_control & XS_CTL_POLL) == 0) 1002 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 1003 wd33c93_timeout, acb); 1004 1005 /* 1006 * issue select 1007 */ 1008 SBIC_TC_PUT(sc, 0); 1009 SET_SBIC_selid(sc, target); 1010 SET_SBIC_timeo(sc, SBIC_TIMEOUT(250, sc->sc_clkfreq)); 1011 1012 GET_SBIC_asr(sc, asr); 1013 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1014 /* This means we got ourselves reselected upon */ 1015 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1016 return 0; 1017 } 1018 1019 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN); 1020 WAIT_CIP(sc); 1021 1022 /* 1023 * wait for select (merged from separate function may need 1024 * cleanup) 1025 */ 1026 do { 1027 asr = SBIC_WAIT(sc, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1028 if (asr & SBIC_ASR_LCI) { 1029 QPRINTF(("late LCI: asr %02x\n", asr)); 1030 return 0; 1031 } 1032 1033 /* Clear interrupt */ 1034 GET_SBIC_csr (sc, csr); 1035 1036 /* Reselected from under our feet? */ 1037 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1038 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1039 /* 1040 * We need to handle this now so we don't lock up later 1041 */ 1042 wd33c93_nextstate(sc, acb, csr, asr); 1043 return 0; 1044 } 1045 1046 /* Whoops! */ 1047 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1048 panic("wd33c93_selectbus: target issued select!"); 1049 return 0; 1050 } 1051 1052 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1053 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1054 csr != SBIC_CSR_SEL_TIMEO); 1055 1056 /* Anyone at home? */ 1057 if (csr == SBIC_CSR_SEL_TIMEO) { 1058 xs->error = XS_SELTIMEOUT; 1059 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1060 return 0; 1061 } 1062 1063 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1064 1065 /* Assume we're now selected */ 1066 GET_SBIC_selid(sc, id); 1067 if (id != target) { 1068 /* Something went wrong - wrong target was select */ 1069 printf("wd33c93_selectbus: wrong target selected;" 1070 " WANTED %d GOT %d", target, id); 1071 return 0; /* XXX: Need to call nexstate to handle? */ 1072 } 1073 1074 sc->sc_flags |= SBICF_SELECTED; 1075 sc->sc_state = SBIC_CONNECTED; 1076 1077 /* setup correct sync mode for this target */ 1078 wd33c93_setsync(sc, ti); 1079 1080 if (ti->flags & T_NODISC && sc->sc_disc == 0) 1081 SET_SBIC_rselid (sc, 0); /* Not expecting a reselect */ 1082 else 1083 SET_SBIC_rselid (sc, SBIC_RID_ER); 1084 1085 /* 1086 * We only really need to do anything when the target goes to MSG out 1087 * If the device ignored ATN, it's probably old and brain-dead, 1088 * but we'll try to support it anyhow. 1089 * If it doesn't support message out, it definately doesn't 1090 * support synchronous transfers, so no point in even asking... 1091 */ 1092 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1093 if (ti->flags & T_NEGOTIATE) { 1094 /* Inititae a SDTR message */ 1095 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1096 if (ti->flags & T_WANTSYNC) { 1097 ti->period = sc->sc_minsyncperiod; 1098 ti->offset = sc->sc_maxoffset; 1099 } else { 1100 ti->period = 0; 1101 ti->offset = 0; 1102 } 1103 /* Send Sync negotiation message */ 1104 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1105 sc->sc_omsg[1] = MSG_EXTENDED; 1106 sc->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1107 sc->sc_omsg[3] = MSG_EXT_SDTR; 1108 if (ti->flags & T_WANTSYNC) { 1109 sc->sc_omsg[4] = sc->sc_minsyncperiod; 1110 sc->sc_omsg[5] = sc->sc_maxoffset; 1111 } else { 1112 sc->sc_omsg[4] = 0; 1113 sc->sc_omsg[5] = 0; 1114 } 1115 wd33c93_xfout(sc, 6, sc->sc_omsg); 1116 sc->sc_msgout |= SEND_SDTR; /* may be rejected */ 1117 sc->sc_flags |= SBICF_SYNCNEGO; 1118 } else { 1119 if (sc->sc_nexus->tag_type != 0) { 1120 /* Use TAGS */ 1121 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1122 sc->target, sc->lun, 1123 sc->sc_nexus->tag_id)); 1124 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1125 sc->sc_omsg[1] = sc->sc_nexus->tag_type; 1126 sc->sc_omsg[2] = sc->sc_nexus->tag_id; 1127 wd33c93_xfout(sc, 3, sc->sc_omsg); 1128 sc->sc_msgout |= SEND_TAG; 1129 } else { 1130 int no_disc; 1131 1132 /* Setup LUN nexus and disconnect privilege */ 1133 no_disc = xs->xs_control & XS_CTL_POLL || 1134 ti->flags & T_NODISC; 1135 SEND_BYTE(sc, MSG_IDENTIFY(lun, !no_disc)); 1136 } 1137 } 1138 /* 1139 * There's one interrupt still to come: 1140 * the change to CMD phase... 1141 */ 1142 SBIC_WAIT(sc, SBIC_ASR_INT , 0); 1143 GET_SBIC_csr(sc, csr); 1144 } 1145 1146 return csr; 1147 } 1148 1149 /* 1150 * Information Transfer *to* a SCSI Target. 1151 * 1152 * Note: Don't expect there to be an interrupt immediately after all 1153 * the data is transferred out. The WD spec sheet says that the Transfer- 1154 * Info command for non-MSG_IN phases only completes when the target 1155 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1156 * 1157 * This can have a nasty effect on commands which take a relatively long 1158 * time to complete, for example a START/STOP unit command may remain in 1159 * CMD phase until the disk has spun up. Only then will the target change 1160 * to STATUS phase. This is really only a problem for immediate commands 1161 * since we don't allow disconnection for them (yet). 1162 */ 1163 int 1164 wd33c93_xfout(struct wd33c93_softc *sc, int len, void *bp) 1165 { 1166 int wait = wd33c93_data_wait; 1167 u_char asr, *buf = bp; 1168 1169 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1170 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1171 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1172 1173 /* 1174 * sigh.. WD-PROTO strikes again.. sending the command in one go 1175 * causes the chip to lock up if talking to certain (misbehaving?) 1176 * targets. Anyway, this procedure should work for all targets, but 1177 * it's slightly slower due to the overhead 1178 */ 1179 1180 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1181 SBIC_TC_PUT (sc, (unsigned)len); 1182 1183 WAIT_CIP (sc); 1184 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO); 1185 1186 /* 1187 * Loop for each byte transferred 1188 */ 1189 do { 1190 GET_SBIC_asr (sc, asr); 1191 1192 if (asr & SBIC_ASR_DBR) { 1193 if (len) { 1194 SET_SBIC_data (sc, *buf); 1195 buf++; 1196 len--; 1197 } else { 1198 SET_SBIC_data (sc, 0); 1199 } 1200 wait = wd33c93_data_wait; 1201 } 1202 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1203 1204 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1205 1206 /* 1207 * Normally, an interrupt will be pending when this routing returns. 1208 */ 1209 return(len); 1210 } 1211 1212 /* 1213 * Information Transfer *from* a Scsi Target 1214 * returns # bytes left to read 1215 */ 1216 int 1217 wd33c93_xfin(struct wd33c93_softc *sc, int len, void *bp) 1218 { 1219 int wait = wd33c93_data_wait; 1220 u_char *buf = bp; 1221 u_char asr; 1222 #ifdef DEBUG 1223 u_char *obp = bp; 1224 #endif 1225 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1226 SBIC_TC_PUT (sc, (unsigned)len); 1227 1228 WAIT_CIP (sc); 1229 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO); 1230 1231 /* 1232 * Loop for each byte transferred 1233 */ 1234 do { 1235 GET_SBIC_asr (sc, asr); 1236 1237 if (asr & SBIC_ASR_DBR) { 1238 if (len) { 1239 GET_SBIC_data (sc, *buf); 1240 buf++; 1241 len--; 1242 } else { 1243 u_char foo; 1244 GET_SBIC_data (sc, foo); 1245 } 1246 wait = wd33c93_data_wait; 1247 } 1248 1249 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1250 1251 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1252 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1253 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1254 1255 SBIC_TC_PUT (sc, 0); 1256 1257 /* 1258 * this leaves with one csr to be read 1259 */ 1260 return len; 1261 } 1262 1263 1264 /* 1265 * Finish SCSI xfer command: After the completion interrupt from 1266 * a read/write operation, sequence through the final phases in 1267 * programmed i/o. 1268 */ 1269 void 1270 wd33c93_xferdone(struct wd33c93_softc *sc) 1271 { 1272 u_char phase, csr; 1273 int s; 1274 1275 QPRINTF(("{")); 1276 s = splbio(); 1277 1278 /* 1279 * have the wd33c93 complete on its own 1280 */ 1281 SBIC_TC_PUT(sc, 0); 1282 SET_SBIC_cmd_phase(sc, 0x46); 1283 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN_XFER); 1284 1285 do { 1286 SBIC_WAIT (sc, SBIC_ASR_INT, 0); 1287 GET_SBIC_csr (sc, csr); 1288 QPRINTF(("%02x:", csr)); 1289 } while ((csr != SBIC_CSR_DISC) && 1290 (csr != SBIC_CSR_DISC_1) && 1291 (csr != SBIC_CSR_S_XFERRED)); 1292 1293 sc->sc_flags &= ~SBICF_SELECTED; 1294 sc->sc_state = SBIC_DISCONNECT; 1295 1296 GET_SBIC_cmd_phase (sc, phase); 1297 QPRINTF(("}%02x", phase)); 1298 1299 if (phase == 0x60) 1300 GET_SBIC_tlun(sc, sc->sc_status); 1301 else 1302 wd33c93_error(sc, sc->sc_nexus); 1303 1304 QPRINTF(("=STS:%02x=\n", sc->sc_status)); 1305 splx(s); 1306 } 1307 1308 1309 int 1310 wd33c93_go(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 1311 { 1312 struct scsipi_xfer *xs = acb->xs; 1313 int i, dmaok; 1314 u_char csr, asr; 1315 1316 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", sc->target, sc->lun)); 1317 1318 sc->sc_nexus = acb; 1319 1320 sc->target = xs->xs_periph->periph_target; 1321 sc->lun = xs->xs_periph->periph_lun; 1322 1323 sc->sc_status = STATUS_UNKNOWN; 1324 sc->sc_daddr = acb->daddr; 1325 sc->sc_dleft = acb->dleft; 1326 1327 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1328 sc->sc_flags = 0; 1329 1330 dmaok = wd33c93_dmaok(sc, xs); 1331 1332 if (dmaok == 0) 1333 sc->sc_flags |= SBICF_NODMA; 1334 1335 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1336 sc->target, sc->sc_tcnt, dmaok)); 1337 1338 /* select the SCSI bus (it's an error if bus isn't free) */ 1339 if ((csr = wd33c93_selectbus(sc, acb)) == 0) 1340 return(0); /* Not done: needs to be rescheduled */ 1341 1342 /* 1343 * Lets cycle a while then let the interrupt handler take over. 1344 */ 1345 GET_SBIC_asr(sc, asr); 1346 do { 1347 QPRINTF(("go[0x%x] ", csr)); 1348 1349 /* Handle the new phase */ 1350 i = wd33c93_nextstate(sc, acb, csr, asr); 1351 WAIT_CIP(sc); /* XXX */ 1352 if (sc->sc_state == SBIC_CONNECTED) { 1353 1354 GET_SBIC_asr(sc, asr); 1355 1356 if (asr & SBIC_ASR_LCI) 1357 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1358 1359 if (asr & SBIC_ASR_INT) 1360 GET_SBIC_csr(sc, csr); 1361 } 1362 1363 } while (sc->sc_state == SBIC_CONNECTED && 1364 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1365 1366 QPRINTF(("> done i=%d stat=%02x\n", i, sc->sc_status)); 1367 1368 if (i == SBIC_STATE_DONE) { 1369 if (sc->sc_status == STATUS_UNKNOWN) { 1370 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1371 return 1; /* Did we really finish that fast? */ 1372 } 1373 } 1374 return 0; 1375 } 1376 1377 1378 int 1379 wd33c93_intr(struct wd33c93_softc *sc) 1380 { 1381 u_char asr, csr; 1382 int i; 1383 1384 /* 1385 * pending interrupt? 1386 */ 1387 GET_SBIC_asr (sc, asr); 1388 if ((asr & SBIC_ASR_INT) == 0) 1389 return(0); 1390 1391 GET_SBIC_csr(sc, csr); 1392 1393 do { 1394 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1395 1396 i = wd33c93_nextstate(sc, sc->sc_nexus, csr, asr); 1397 WAIT_CIP(sc); /* XXX */ 1398 if (sc->sc_state == SBIC_CONNECTED) { 1399 GET_SBIC_asr(sc, asr); 1400 1401 if (asr & SBIC_ASR_LCI) 1402 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1403 asr, csr); 1404 1405 if (asr & SBIC_ASR_INT) 1406 GET_SBIC_csr(sc, csr); 1407 } 1408 } while (sc->sc_state == SBIC_CONNECTED && 1409 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1410 1411 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1412 1413 return(1); 1414 } 1415 1416 /* 1417 * Complete current command using polled I/O. Used when interrupt driven 1418 * I/O is not allowed (ie. during boot and shutdown) 1419 * 1420 * Polled I/O is very processor intensive 1421 */ 1422 int 1423 wd33c93_poll(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 1424 { 1425 u_char asr, csr=0; 1426 int i, count; 1427 struct scsipi_xfer *xs = acb->xs; 1428 1429 SBIC_WAIT(sc, SBIC_ASR_INT, wd33c93_cmd_wait); 1430 for (count=acb->timeout; count;) { 1431 GET_SBIC_asr (sc, asr); 1432 if (asr & SBIC_ASR_LCI) 1433 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1434 asr, csr); 1435 if (asr & SBIC_ASR_INT) { 1436 GET_SBIC_csr(sc, csr); 1437 sc->sc_flags |= SBICF_NODMA; 1438 i = wd33c93_nextstate(sc, sc->sc_nexus, csr, asr); 1439 WAIT_CIP(sc); /* XXX */ 1440 } else { 1441 DELAY(1000); 1442 count--; 1443 } 1444 1445 if ((xs->xs_status & XS_STS_DONE) != 0) 1446 return (0); 1447 1448 if (sc->sc_state == SBIC_IDLE) { 1449 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1450 wd33c93_sched(sc); 1451 } 1452 } 1453 return (1); 1454 } 1455 1456 static inline int 1457 __verify_msg_format(u_char *p, int len) 1458 { 1459 1460 if (len == 1 && MSG_IS1BYTE(p[0])) 1461 return 1; 1462 if (len == 2 && MSG_IS2BYTE(p[0])) 1463 return 1; 1464 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1465 len == p[1] + 2) 1466 return 1; 1467 return 0; 1468 } 1469 1470 /* 1471 * Handle message_in phase 1472 */ 1473 int 1474 wd33c93_msgin_phase(struct wd33c93_softc *sc, int reselect) 1475 { 1476 int len; 1477 u_char asr, csr, *msg; 1478 1479 GET_SBIC_asr(sc, asr); 1480 1481 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1482 1483 GET_SBIC_selid (sc, csr); 1484 SET_SBIC_selid (sc, csr | SBIC_SID_FROM_SCSI); 1485 1486 SBIC_TC_PUT(sc, 0); 1487 1488 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1489 1490 msg = sc->sc_imsg; 1491 len = 0; 1492 1493 do { 1494 /* Fetch the next byte of the message */ 1495 RECV_BYTE(sc, *msg++); 1496 len++; 1497 1498 /* 1499 * get the command completion interrupt, or we 1500 * can't send a new command (LCI) 1501 */ 1502 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1503 GET_SBIC_csr(sc, csr); 1504 1505 if (__verify_msg_format(sc->sc_imsg, len)) 1506 break; /* Complete message recieved */ 1507 1508 /* 1509 * Clear ACK, and wait for the interrupt 1510 * for the next byte or phase change 1511 */ 1512 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1513 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1514 1515 GET_SBIC_csr(sc, csr); 1516 } while (len < SBIC_MAX_MSGLEN); 1517 1518 if (__verify_msg_format(sc->sc_imsg, len)) 1519 wd33c93_msgin(sc, sc->sc_imsg, len); 1520 1521 /* 1522 * Clear ACK, and wait for the interrupt 1523 * for the phase change 1524 */ 1525 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1526 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1527 1528 /* Should still have one CSR to read */ 1529 return SBIC_STATE_RUNNING; 1530 } 1531 1532 1533 void wd33c93_msgin(struct wd33c93_softc *sc, u_char *msgaddr, int msglen) 1534 { 1535 struct wd33c93_acb *acb = sc->sc_nexus; 1536 struct wd33c93_tinfo *ti = &sc->sc_tinfo[sc->target]; 1537 struct wd33c93_linfo *li; 1538 u_char asr; 1539 1540 switch (sc->sc_state) { 1541 case SBIC_CONNECTED: 1542 switch (msgaddr[0]) { 1543 case MSG_MESSAGE_REJECT: 1544 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1545 "last msgout=%x\n", sc->sc_msgout)); 1546 switch (sc->sc_msgout) { 1547 case SEND_TAG: 1548 printf("%s: tagged queuing rejected: " 1549 "target %d\n", 1550 device_xname(sc->sc_dev), sc->target); 1551 ti->flags &= ~T_TAG; 1552 li = TINFO_LUN(ti, sc->lun); 1553 if (acb->tag_type && 1554 li->queued[acb->tag_id] != NULL) { 1555 li->queued[acb->tag_id] = NULL; 1556 li->used--; 1557 } 1558 acb->tag_type = acb->tag_id = 0; 1559 li->untagged = acb; 1560 li->state = L_STATE_BUSY; 1561 break; 1562 1563 case SEND_SDTR: 1564 printf("%s: sync transfer rejected: target %d\n", 1565 device_xname(sc->sc_dev), sc->target); 1566 1567 sc->sc_flags &= ~SBICF_SYNCNEGO; 1568 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1569 wd33c93_update_xfer_mode(sc, 1570 acb->xs->xs_periph->periph_target); 1571 wd33c93_setsync(sc, ti); 1572 1573 case SEND_INIT_DET_ERR: 1574 goto abort; 1575 1576 default: 1577 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1578 break; 1579 } 1580 sc->sc_msgout = 0; 1581 break; 1582 1583 case MSG_HEAD_OF_Q_TAG: 1584 case MSG_ORDERED_Q_TAG: 1585 case MSG_SIMPLE_Q_TAG: 1586 printf("-- Out of phase TAG;" 1587 "Nexus=%d:%d Tag=%02x/%02x\n", 1588 sc->target, sc->lun, msgaddr[0], msgaddr[1]); 1589 break; 1590 1591 case MSG_DISCONNECT: 1592 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1593 /* 1594 * Mark the fact that all bytes have moved. The 1595 * target may not bother to do a SAVE POINTERS 1596 * at this stage. This flag will set the residual 1597 * count to zero on MSG COMPLETE. 1598 */ 1599 if (sc->sc_dleft == 0) 1600 acb->flags |= ACB_COMPLETE; 1601 1602 if (acb->xs->xs_control & XS_CTL_POLL) 1603 /* Don't allow disconnect in immediate mode */ 1604 goto reject; 1605 else { /* Allow disconnect */ 1606 sc->sc_flags &= ~SBICF_SELECTED; 1607 sc->sc_state = SBIC_DISCONNECT; 1608 } 1609 if ((acb->xs->xs_periph->periph_quirks & 1610 PQUIRK_AUTOSAVE) == 0) 1611 break; 1612 /*FALLTHROUGH*/ 1613 1614 case MSG_SAVEDATAPOINTER: 1615 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1616 acb->daddr = sc->sc_daddr; 1617 acb->dleft = sc->sc_dleft; 1618 break; 1619 1620 case MSG_RESTOREPOINTERS: 1621 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1622 sc->sc_daddr = acb->daddr; 1623 sc->sc_dleft = acb->dleft; 1624 break; 1625 1626 case MSG_CMDCOMPLETE: 1627 /* 1628 * !! KLUDGE ALERT !! quite a few drives don't seem to 1629 * really like the current way of sending the 1630 * sync-handshake together with the ident-message, and 1631 * they react by sending command-complete and 1632 * disconnecting right after returning the valid sync 1633 * handshake. So, all I can do is reselect the drive, 1634 * and hope it won't disconnect again. I don't think 1635 * this is valid behavior, but I can't help fixing a 1636 * problem that apparently exists. 1637 * 1638 * Note: we should not get here on `normal' command 1639 * completion, as that condition is handled by the 1640 * high-level sel&xfer resume command used to walk 1641 * thru status/cc-phase. 1642 */ 1643 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1644 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1645 " acting weird.." 1646 " waiting for disconnect...\n", 1647 msgaddr[0], sc->target)); 1648 1649 /* Check to see if wd33c93 is handling this */ 1650 GET_SBIC_asr(sc, asr); 1651 if (asr & SBIC_ASR_BSY) 1652 break; 1653 1654 /* XXX: Assume it works and set status to 00 */ 1655 sc->sc_status = 0; 1656 sc->sc_state = SBIC_CMDCOMPLETE; 1657 break; 1658 1659 case MSG_EXTENDED: 1660 switch(msgaddr[2]) { 1661 case MSG_EXT_SDTR: /* Sync negotiation */ 1662 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1663 "period %d, offset %d", 1664 msgaddr[3], msgaddr[4])); 1665 if (msgaddr[1] != 3) 1666 goto reject; 1667 1668 ti->period = 1669 MAX(msgaddr[3], sc->sc_minsyncperiod); 1670 ti->offset = MIN(msgaddr[4], sc->sc_maxoffset); 1671 1672 /* 1673 * <SGI, IBM DORS-32160, WA6A> will do nothing 1674 * but attempt sync negotiation until it gets 1675 * what it wants. To avoid an infinite loop set 1676 * off by the identify request, oblige them. 1677 */ 1678 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0 && 1679 msgaddr[3] != 0) 1680 ti->flags |= T_WANTSYNC; 1681 1682 if (!(ti->flags & T_WANTSYNC)) 1683 ti->period = ti->offset = 0; 1684 1685 ti->flags &= ~T_NEGOTIATE; 1686 1687 if (ti->offset == 0) 1688 ti->flags &= ~T_SYNCMODE; /* Async */ 1689 else 1690 ti->flags |= T_SYNCMODE; /* Sync */ 1691 1692 /* target initiated negotiation */ 1693 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0) 1694 wd33c93_sched_msgout(sc, SEND_SDTR); 1695 sc->sc_flags &= ~SBICF_SYNCNEGO; 1696 1697 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1698 sc->target, ti->offset, 1699 ti->period)); 1700 wd33c93_update_xfer_mode(sc, 1701 acb->xs->xs_periph->periph_target); 1702 wd33c93_setsync(sc, ti); 1703 break; 1704 1705 case MSG_EXT_WDTR: 1706 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1707 goto reject; 1708 1709 default: 1710 scsipi_printaddr(acb->xs->xs_periph); 1711 printf("unrecognized MESSAGE EXTENDED;" 1712 " sending REJECT\n"); 1713 goto reject; 1714 } 1715 break; 1716 1717 default: 1718 scsipi_printaddr(acb->xs->xs_periph); 1719 printf("unrecognized MESSAGE; sending REJECT\n"); 1720 1721 reject: 1722 /* We don't support whatever this message is... */ 1723 wd33c93_sched_msgout(sc, SEND_REJECT); 1724 break; 1725 } 1726 break; 1727 1728 case SBIC_IDENTIFIED: 1729 /* 1730 * IDENTIFY message was received and queue tag is expected now 1731 */ 1732 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (sc->sc_msgify==0)) { 1733 printf("%s: TAG reselect without IDENTIFY;" 1734 " MSG %x; sending DEVICE RESET\n", 1735 device_xname(sc->sc_dev), msgaddr[0]); 1736 goto reset; 1737 } 1738 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1739 if (sc->sc_nexus) 1740 printf("*TAG Recv with active nexus!!\n"); 1741 wd33c93_reselect(sc, sc->target, sc->lun, 1742 msgaddr[0], msgaddr[1]); 1743 break; 1744 1745 case SBIC_RESELECTED: 1746 /* 1747 * IDENTIFY message with target 1748 */ 1749 if (MSG_ISIDENTIFY(msgaddr[0])) { 1750 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1751 sc->sc_msgify = msgaddr[0]; 1752 } else { 1753 printf("%s: reselect without IDENTIFY;" 1754 " MSG %x;" 1755 " sending DEVICE RESET\n", 1756 device_xname(sc->sc_dev), msgaddr[0]); 1757 goto reset; 1758 } 1759 break; 1760 1761 default: 1762 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1763 sc->sc_state); 1764 reset: 1765 wd33c93_sched_msgout(sc, SEND_DEV_RESET); 1766 break; 1767 abort: 1768 wd33c93_sched_msgout(sc, SEND_ABORT); 1769 break; 1770 } 1771 } 1772 1773 void 1774 wd33c93_sched_msgout(struct wd33c93_softc *sc, u_short msg) 1775 { 1776 u_char asr; 1777 1778 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1779 sc->sc_msgpriq |= msg; 1780 1781 /* Schedule MSGOUT Phase to send message */ 1782 1783 WAIT_CIP(sc); 1784 SET_SBIC_cmd(sc, SBIC_CMD_SET_ATN); 1785 WAIT_CIP(sc); 1786 GET_SBIC_asr(sc, asr); 1787 if (asr & SBIC_ASR_LCI) { 1788 printf("MSGOUT Failed!\n"); 1789 } 1790 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1791 WAIT_CIP(sc); 1792 } 1793 1794 /* 1795 * Send the highest priority, scheduled message 1796 */ 1797 void 1798 wd33c93_msgout(struct wd33c93_softc *sc) 1799 { 1800 struct wd33c93_tinfo *ti; 1801 struct wd33c93_acb *acb = sc->sc_nexus; 1802 1803 if (acb == NULL) 1804 panic("MSGOUT with no nexus"); 1805 1806 if (sc->sc_omsglen == 0) { 1807 /* Pick up highest priority message */ 1808 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1809 sc->sc_msgoutq |= sc->sc_msgout; 1810 sc->sc_msgpriq &= ~sc->sc_msgout; 1811 sc->sc_omsglen = 1; /* "Default" message len */ 1812 switch (sc->sc_msgout) { 1813 case SEND_SDTR: 1814 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1815 sc->sc_omsg[0] = MSG_EXTENDED; 1816 sc->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1817 sc->sc_omsg[2] = MSG_EXT_SDTR; 1818 if (ti->flags & T_WANTSYNC) { 1819 sc->sc_omsg[3] = ti->period; 1820 sc->sc_omsg[4] = ti->offset; 1821 } else { 1822 sc->sc_omsg[3] = 0; 1823 sc->sc_omsg[4] = 0; 1824 } 1825 sc->sc_omsglen = 5; 1826 if ((sc->sc_flags & SBICF_SYNCNEGO) == 0) { 1827 if (ti->flags & T_WANTSYNC) 1828 ti->flags |= T_SYNCMODE; 1829 else 1830 ti->flags &= ~T_SYNCMODE; 1831 wd33c93_setsync(sc, ti); 1832 } 1833 break; 1834 case SEND_IDENTIFY: 1835 if (sc->sc_state != SBIC_CONNECTED) { 1836 printf("%s at line %d: no nexus\n", 1837 device_xname(sc->sc_dev), __LINE__); 1838 } 1839 sc->sc_omsg[0] = 1840 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1841 break; 1842 case SEND_TAG: 1843 if (sc->sc_state != SBIC_CONNECTED) { 1844 printf("%s at line %d: no nexus\n", 1845 device_xname(sc->sc_dev), __LINE__); 1846 } 1847 sc->sc_omsg[0] = acb->tag_type; 1848 sc->sc_omsg[1] = acb->tag_id; 1849 sc->sc_omsglen = 2; 1850 break; 1851 case SEND_DEV_RESET: 1852 sc->sc_omsg[0] = MSG_BUS_DEV_RESET; 1853 ti = &sc->sc_tinfo[sc->target]; 1854 ti->flags &= ~T_SYNCMODE; 1855 wd33c93_update_xfer_mode(sc, sc->target); 1856 if ((ti->flags & T_NOSYNC) == 0) 1857 /* We can re-start sync negotiation */ 1858 ti->flags |= T_NEGOTIATE; 1859 break; 1860 case SEND_PARITY_ERROR: 1861 sc->sc_omsg[0] = MSG_PARITY_ERROR; 1862 break; 1863 case SEND_ABORT: 1864 sc->sc_flags |= SBICF_ABORTING; 1865 sc->sc_omsg[0] = MSG_ABORT; 1866 break; 1867 case SEND_INIT_DET_ERR: 1868 sc->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1869 break; 1870 case SEND_REJECT: 1871 sc->sc_omsg[0] = MSG_MESSAGE_REJECT; 1872 break; 1873 default: 1874 /* Wasn't expecting MSGOUT Phase */ 1875 sc->sc_omsg[0] = MSG_NOOP; 1876 break; 1877 } 1878 } 1879 1880 wd33c93_xfout(sc, sc->sc_omsglen, sc->sc_omsg); 1881 } 1882 1883 1884 /* 1885 * wd33c93_nextstate() 1886 * return: 1887 * SBIC_STATE_DONE == done 1888 * SBIC_STATE_RUNNING == working 1889 * SBIC_STATE_DISCONNECT == disconnected 1890 * SBIC_STATE_ERROR == error 1891 */ 1892 int 1893 wd33c93_nextstate(struct wd33c93_softc *sc, struct wd33c93_acb *acb, u_char csr, u_char asr) 1894 { 1895 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1896 1897 switch (csr) { 1898 1899 case SBIC_CSR_XFERRED | CMD_PHASE: 1900 case SBIC_CSR_MIS | CMD_PHASE: 1901 case SBIC_CSR_MIS_1 | CMD_PHASE: 1902 case SBIC_CSR_MIS_2 | CMD_PHASE: 1903 1904 if (wd33c93_xfout(sc, acb->clen, &acb->cmd)) 1905 goto abort; 1906 break; 1907 1908 case SBIC_CSR_XFERRED | STATUS_PHASE: 1909 case SBIC_CSR_MIS | STATUS_PHASE: 1910 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1911 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1912 1913 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1914 1915 /* 1916 * this should be the normal i/o completion case. 1917 * get the status & cmd complete msg then let the 1918 * device driver look at what happened. 1919 */ 1920 wd33c93_xferdone(sc); 1921 1922 wd33c93_dma_stop(sc); 1923 1924 /* Fixup byte count to be passed to higher layer */ 1925 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1926 sc->sc_dleft; 1927 1928 /* 1929 * Indicate to the upper layers that the command is done 1930 */ 1931 wd33c93_scsidone(sc, acb, sc->sc_status); 1932 1933 return SBIC_STATE_DONE; 1934 1935 1936 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1937 case SBIC_CSR_MIS | DATA_IN_PHASE: 1938 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1939 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1940 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1941 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1942 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1943 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1944 /* 1945 * Verify that we expected to transfer data... 1946 */ 1947 if (acb->dleft <= 0) { 1948 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1949 acb->dleft, asr, csr); 1950 goto abort; 1951 } 1952 1953 /* 1954 * Should we transfer using PIO or DMA ? 1955 */ 1956 if (acb->xs->xs_control & XS_CTL_POLL || 1957 sc->sc_flags & SBICF_NODMA) { 1958 /* Perfrom transfer using PIO */ 1959 int resid; 1960 1961 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", sc->target, 1962 sc->sc_daddr, sc->sc_dleft)); 1963 1964 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1965 /* data in */ 1966 resid = wd33c93_xfin(sc, sc->sc_dleft, 1967 sc->sc_daddr); 1968 else /* data out */ 1969 resid = wd33c93_xfout(sc, sc->sc_dleft, 1970 sc->sc_daddr); 1971 1972 sc->sc_daddr = (char *)sc->sc_daddr + 1973 (acb->dleft - resid); 1974 sc->sc_dleft = resid; 1975 } else { 1976 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1977 1978 /* Perform transfer using DMA */ 1979 wd33c93_dma_setup(sc, datain); 1980 1981 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI | 1982 sc->sc_dmamode); 1983 1984 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", sc->target, 1985 sc->sc_daddr, sc->sc_dleft)); 1986 1987 /* Setup byte count for transfer */ 1988 SBIC_TC_PUT(sc, (unsigned)sc->sc_dleft); 1989 1990 /* Start the transfer */ 1991 SET_SBIC_cmd(sc, SBIC_CMD_XFER_INFO); 1992 1993 /* Start the DMA chip going */ 1994 sc->sc_tcnt = sc->sc_dmago(sc); 1995 1996 /* Indicate that we're in DMA mode */ 1997 sc->sc_flags |= SBICF_INDMA; 1998 } 1999 break; 2000 2001 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2002 case SBIC_CSR_MIS | MESG_IN_PHASE: 2003 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2004 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2005 2006 wd33c93_dma_stop(sc); 2007 2008 /* Handle a single message in... */ 2009 return wd33c93_msgin_phase(sc, 0); 2010 2011 case SBIC_CSR_MSGIN_W_ACK: 2012 2013 /* 2014 * We should never see this since it's handled in 2015 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 2016 */ 2017 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 2018 2019 printf("Acking unknown msgin CSR:%02x",csr); 2020 break; 2021 2022 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2023 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2024 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2025 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2026 2027 /* 2028 * Message out phase. ATN signal has been asserted 2029 */ 2030 wd33c93_dma_stop(sc); 2031 wd33c93_msgout(sc); 2032 return SBIC_STATE_RUNNING; 2033 2034 case SBIC_CSR_DISC: 2035 case SBIC_CSR_DISC_1: 2036 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2037 sc->target)); 2038 wd33c93_dma_stop(sc); 2039 2040 sc->sc_nexus = NULL; 2041 sc->sc_state = SBIC_IDLE; 2042 sc->sc_flags = 0; 2043 2044 ++sc->sc_tinfo[sc->target].dconns; 2045 ++sc->sc_disc; 2046 2047 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2048 return SBIC_STATE_DISCONNECT; 2049 2050 /* Try to schedule another target */ 2051 wd33c93_sched(sc); 2052 2053 return SBIC_STATE_DISCONNECT; 2054 2055 case SBIC_CSR_RSLT_NI: 2056 case SBIC_CSR_RSLT_IFY: 2057 { 2058 /* 2059 * A reselection. 2060 * Note that since we don't enable Advanced Features (assuming 2061 * the WD chip is at least the 'A' revision), we're only ever 2062 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2063 * hell of it, we'll handle it anyway, for all the extra code 2064 * it needs... 2065 */ 2066 u_char newtarget, newlun; 2067 2068 if (sc->sc_flags & SBICF_INDMA) { 2069 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2070 wd33c93_dma_stop(sc); 2071 } 2072 2073 sc->sc_state = SBIC_RESELECTED; 2074 GET_SBIC_rselid(sc, newtarget); 2075 2076 /* check SBIC_RID_SIV? */ 2077 newtarget &= SBIC_RID_MASK; 2078 2079 if (csr == SBIC_CSR_RSLT_IFY) { 2080 /* Read Identify msg to avoid lockup */ 2081 GET_SBIC_data(sc, newlun); 2082 WAIT_CIP(sc); 2083 newlun &= SBIC_TLUN_MASK; 2084 sc->sc_msgify = MSG_IDENTIFY(newlun, 0); 2085 } else { 2086 /* 2087 * Need to read Identify message the hard way, assuming 2088 * the target even sends us one... 2089 */ 2090 for (newlun = 255; newlun; --newlun) { 2091 GET_SBIC_asr(sc, asr); 2092 if (asr & SBIC_ASR_INT) 2093 break; 2094 DELAY(10); 2095 } 2096 2097 /* If we didn't get an interrupt, somethink's up */ 2098 if ((asr & SBIC_ASR_INT) == 0) { 2099 printf("%s: Reselect without identify? asr %x\n", 2100 device_xname(sc->sc_dev), asr); 2101 newlun = 0; /* XXXX */ 2102 } else { 2103 /* 2104 * We got an interrupt, verify that it's a 2105 * change to message in phase, and if so 2106 * read the message. 2107 */ 2108 GET_SBIC_csr(sc,csr); 2109 2110 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2111 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2112 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2113 /* 2114 * Yup, gone to message in. 2115 * Fetch the target LUN 2116 */ 2117 sc->sc_msgify = 0; 2118 wd33c93_msgin_phase(sc, 1); 2119 newlun = sc->sc_msgify & SBIC_TLUN_MASK; 2120 } else { 2121 /* 2122 * Whoops! Target didn't go to msg_in 2123 * phase!! 2124 */ 2125 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2126 newlun = 0; /* XXXSCW */ 2127 } 2128 } 2129 } 2130 2131 /* Ok, we have the identity of the reselecting target. */ 2132 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2133 newtarget, newlun)); 2134 wd33c93_reselect(sc, newtarget, newlun, 0, 0); 2135 sc->sc_disc--; 2136 2137 if (csr == SBIC_CSR_RSLT_IFY) 2138 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 2139 break; 2140 } 2141 2142 default: 2143 abort: 2144 /* Something unexpected happend -- deal with it. */ 2145 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2146 2147 #ifdef DDB 2148 Debugger(); 2149 #endif 2150 2151 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 2152 if (acb->xs) 2153 wd33c93_error(sc, acb); 2154 wd33c93_abort(sc, acb, "next"); 2155 2156 if (sc->sc_flags & SBICF_INDMA) { 2157 wd33c93_dma_stop(sc); 2158 wd33c93_scsidone(sc, acb, STATUS_UNKNOWN); 2159 } 2160 return SBIC_STATE_ERROR; 2161 } 2162 return SBIC_STATE_RUNNING; 2163 } 2164 2165 2166 void 2167 wd33c93_reselect(struct wd33c93_softc *sc, int target, int lun, int tag_type, int tag_id) 2168 { 2169 2170 struct wd33c93_tinfo *ti; 2171 struct wd33c93_linfo *li; 2172 struct wd33c93_acb *acb; 2173 2174 if (sc->sc_nexus) { 2175 /* 2176 * Whoops! We've been reselected with a 2177 * command in progress! 2178 * The best we can do is to put the current 2179 * command back on the ready list and hope 2180 * for the best. 2181 */ 2182 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2183 device_xname(sc->sc_dev))); 2184 ti = &sc->sc_tinfo[sc->target]; 2185 li = TINFO_LUN(ti, sc->lun); 2186 li->state = L_STATE_IDLE; 2187 2188 wd33c93_dequeue(sc, sc->sc_nexus); 2189 TAILQ_INSERT_HEAD(&sc->ready_list, sc->sc_nexus, chain); 2190 sc->sc_nexus->flags |= ACB_READY; 2191 2192 sc->sc_nexus = NULL; 2193 } 2194 2195 /* Setup state for new nexus */ 2196 acb = NULL; 2197 sc->sc_flags = SBICF_SELECTED; 2198 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2199 2200 ti = &sc->sc_tinfo[target]; 2201 li = TINFO_LUN(ti, lun); 2202 2203 if (li != NULL) { 2204 if (li->untagged != NULL && li->state) 2205 acb = li->untagged; 2206 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2207 /* Wait for tag to come by during MESG_IN Phase */ 2208 sc->target = target; /* setup I_T_L nexus */ 2209 sc->lun = lun; 2210 sc->sc_state = SBIC_IDENTIFIED; 2211 return; 2212 } else if (tag_type) 2213 acb = li->queued[tag_id]; 2214 } 2215 2216 if (acb == NULL) { 2217 printf("%s: reselect from target %d lun %d tag %x:%x " 2218 "with no nexus; sending ABORT\n", 2219 device_xname(sc->sc_dev), target, lun, tag_type, tag_id); 2220 goto abort; 2221 } 2222 2223 sc->target = target; 2224 sc->lun = lun; 2225 sc->sc_nexus = acb; 2226 sc->sc_state = SBIC_CONNECTED; 2227 2228 if (!wd33c93_dmaok(sc, acb->xs)) 2229 sc->sc_flags |= SBICF_NODMA; 2230 2231 /* Do an implicit RESTORE POINTERS. */ 2232 sc->sc_daddr = acb->daddr; 2233 sc->sc_dleft = acb->dleft; 2234 2235 /* Set sync modes for new target */ 2236 wd33c93_setsync(sc, ti); 2237 2238 if (acb->flags & ACB_RESET) 2239 wd33c93_sched_msgout(sc, SEND_DEV_RESET); 2240 else if (acb->flags & ACB_ABORT) 2241 wd33c93_sched_msgout(sc, SEND_ABORT); 2242 return; 2243 2244 abort: 2245 wd33c93_sched_msgout(sc, SEND_ABORT); 2246 return; 2247 2248 } 2249 2250 void 2251 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2252 { 2253 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2254 struct scsipi_xfer_mode xm; 2255 2256 xm.xm_target = target; 2257 xm.xm_mode = 0; 2258 xm.xm_period = 0; 2259 xm.xm_offset = 0; 2260 2261 if (ti->flags & T_SYNCMODE) { 2262 xm.xm_mode |= PERIPH_CAP_SYNC; 2263 xm.xm_period = ti->period; 2264 xm.xm_offset = ti->offset; 2265 } 2266 2267 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2268 xm.xm_mode |= PERIPH_CAP_TQING; 2269 2270 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2271 xm.xm_target, 2272 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2273 2274 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2275 } 2276 2277 void 2278 wd33c93_timeout(void *arg) 2279 { 2280 struct wd33c93_acb *acb = arg; 2281 struct scsipi_xfer *xs = acb->xs; 2282 struct scsipi_periph *periph = xs->xs_periph; 2283 struct wd33c93_softc *sc = 2284 device_private(periph->periph_channel->chan_adapter->adapt_dev); 2285 int s, asr; 2286 2287 s = splbio(); 2288 2289 GET_SBIC_asr(sc, asr); 2290 2291 scsipi_printaddr(periph); 2292 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2293 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2294 device_xname(sc->sc_dev), asr, acb, acb->flags, acb->dleft, 2295 sc->sc_state, sc->sc_nexus, (long)sc->sc_dleft, 2296 sc->sc_msgpriq, sc->sc_msgout); 2297 2298 if (asr & SBIC_ASR_INT) { 2299 /* We need to service a missed IRQ */ 2300 wd33c93_intr(sc); 2301 } else { 2302 (void) wd33c93_abort(sc, sc->sc_nexus, "timeout"); 2303 } 2304 splx(s); 2305 } 2306 2307 2308 void 2309 wd33c93_watchdog(void *arg) 2310 { 2311 struct wd33c93_softc *sc = arg; 2312 struct wd33c93_tinfo *ti; 2313 struct wd33c93_linfo *li; 2314 int t, s, l; 2315 /* scrub LUN's that have not been used in the last 10min. */ 2316 time_t old = time_second - (10 * 60); 2317 2318 for (t = 0; t < SBIC_NTARG; t++) { 2319 ti = &sc->sc_tinfo[t]; 2320 for (l = 0; l < SBIC_NLUN; l++) { 2321 s = splbio(); 2322 li = TINFO_LUN(ti, l); 2323 if (li && li->last_used < old && 2324 li->untagged == NULL && li->used == 0) { 2325 ti->lun[li->lun] = NULL; 2326 free(li, M_DEVBUF); 2327 } 2328 splx(s); 2329 } 2330 } 2331 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc); 2332 } 2333 2334 2335 #ifdef DEBUG 2336 void 2337 wd33c93_hexdump(u_char *buf, int len) 2338 { 2339 printf("{%d}:", len); 2340 while (len--) 2341 printf(" %02x", *buf++); 2342 printf("\n"); 2343 } 2344 2345 2346 void 2347 wd33c93_print_csr(u_char csr) 2348 { 2349 switch (SCSI_PHASE(csr)) { 2350 case CMD_PHASE: 2351 printf("CMD_PHASE\n"); 2352 break; 2353 2354 case STATUS_PHASE: 2355 printf("STATUS_PHASE\n"); 2356 break; 2357 2358 case DATA_IN_PHASE: 2359 printf("DATAIN_PHASE\n"); 2360 break; 2361 2362 case DATA_OUT_PHASE: 2363 printf("DATAOUT_PHASE\n"); 2364 break; 2365 2366 case MESG_IN_PHASE: 2367 printf("MESG_IN_PHASE\n"); 2368 break; 2369 2370 case MESG_OUT_PHASE: 2371 printf("MESG_OUT_PHASE\n"); 2372 break; 2373 2374 default: 2375 switch (csr) { 2376 case SBIC_CSR_DISC_1: 2377 printf("DISC_1\n"); 2378 break; 2379 2380 case SBIC_CSR_RSLT_NI: 2381 printf("RESELECT_NO_IFY\n"); 2382 break; 2383 2384 case SBIC_CSR_RSLT_IFY: 2385 printf("RESELECT_IFY\n"); 2386 break; 2387 2388 case SBIC_CSR_SLT: 2389 printf("SELECT\n"); 2390 break; 2391 2392 case SBIC_CSR_SLT_ATN: 2393 printf("SELECT, ATN\n"); 2394 break; 2395 2396 case SBIC_CSR_UNK_GROUP: 2397 printf("UNK_GROUP\n"); 2398 break; 2399 2400 default: 2401 printf("UNKNOWN csr=%02x\n", csr); 2402 } 2403 } 2404 } 2405 #endif 2406
Indexes created Thu Sep 25 16:09:42 GMT 2025