wd33c93.c revision 1.7
1 /* $NetBSD: wd33c93.c,v 1.7 2006/09/05 17:31:31 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.7 2006/09/05 17:31:31 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 int wd33c93_div2stp (struct wd33c93_softc *, int); 148 int wd33c93_stp2div (struct wd33c93_softc *, int); 149 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 150 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 151 152 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 153 static int wd33c93_pool_initialized = 0; 154 155 /* 156 * Timeouts 157 */ 158 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 159 int wd33c93_data_wait = SBIC_DATA_WAIT; 160 int wd33c93_init_wait = SBIC_INIT_WAIT; 161 162 int wd33c93_nodma = 0; /* Use polled IO transfers */ 163 int wd33c93_nodisc = 0; /* Allow command queues */ 164 int wd33c93_notags = 0; /* No Tags */ 165 166 /* 167 * Some useful stuff for debugging purposes 168 */ 169 #ifdef DEBUG 170 171 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 172 173 int wd33c93_debug = 0; /* Debug flags */ 174 175 void wd33c93_print_csr (u_char); 176 void wd33c93_hexdump (u_char *, int); 177 178 #else 179 #define QPRINTF(a) /* */ 180 #endif 181 182 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 183 184 /* 185 * Attach instance of driver and probe for sub devices 186 */ 187 void 188 wd33c93_attach(struct wd33c93_softc *dev) 189 { 190 struct scsipi_adapter *adapt = &dev->sc_adapter; 191 struct scsipi_channel *chan = &dev->sc_channel; 192 193 adapt->adapt_dev = &dev->sc_dev; 194 adapt->adapt_nchannels = 1; 195 adapt->adapt_openings = 256; 196 adapt->adapt_max_periph = 256; /* Max tags per device */ 197 adapt->adapt_ioctl = NULL; 198 /* adapt_request initialized by MD interface */ 199 /* adapt_minphys initialized by MD interface */ 200 201 memset(chan, 0, sizeof(*chan)); 202 chan->chan_adapter = &dev->sc_adapter; 203 chan->chan_bustype = &scsi_bustype; 204 chan->chan_channel = 0; 205 chan->chan_ntargets = SBIC_NTARG; 206 chan->chan_nluns = SBIC_NLUN; 207 chan->chan_id = dev->sc_id; 208 209 callout_init(&dev->sc_watchdog); 210 211 dev->sc_minsync = 200/4; /* Min SCSI sync rate in 4ns units */ 212 dev->sc_maxoffset = SBIC_SYN_MAX_OFFSET; /* Max Sync Offset */ 213 214 /* 215 * Add reference to adapter so that we drop the reference after 216 * config_found() to make sure the adatper is disabled. 217 */ 218 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 219 printf("%s: unable to enable controller\n", 220 dev->sc_dev.dv_xname); 221 return; 222 } 223 224 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 225 wd33c93_init(dev); 226 227 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 228 scsiprint); 229 scsipi_adapter_delref(&dev->sc_adapter); 230 } 231 232 /* 233 * Initialize driver-private structures 234 */ 235 void 236 wd33c93_init(struct wd33c93_softc *dev) 237 { 238 u_int i; 239 240 if (!wd33c93_pool_initialized) { 241 /* All instances share the same pool */ 242 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 243 "wd33c93_acb", NULL); 244 ++wd33c93_pool_initialized; 245 } 246 247 if (dev->sc_state == 0) { 248 TAILQ_INIT(&dev->ready_list); 249 250 dev->sc_nexus = NULL; 251 dev->sc_disc = 0; 252 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 253 254 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 255 } else 256 panic("wd33c93: reinitializing driver!"); 257 258 dev->sc_flags = 0; 259 dev->sc_state = SBIC_IDLE; 260 wd33c93_reset(dev); 261 262 for (i = 0; i < 8; i++) { 263 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 264 /* 265 * sc_flags = 0xTTRRSS 266 * 267 * TT = Bitmask to disable Tagged Queues 268 * RR = Bitmask to disable disconnect/reselect 269 * SS = Bitmask to diable Sync negotiation 270 */ 271 ti->flags = T_NEED_RESET; 272 if (dev->sc_minsync == 0 || (dev->sc_cfflags & (1<<(i+8)))) 273 ti->flags |= T_NOSYNC; 274 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 275 ti->flags |= T_NODISC; 276 ti->period = dev->sc_minsync; 277 ti->offset = 0; 278 } 279 } 280 281 void 282 wd33c93_reset(struct wd33c93_softc *dev) 283 { 284 u_int my_id, s; 285 u_char csr, reg; 286 287 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 288 WAIT_CIP(dev); 289 290 s = splbio(); 291 292 if (dev->sc_reset != NULL) 293 (*dev->sc_reset)(dev); 294 295 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 296 if (dev->sc_clkfreq < 110) 297 my_id |= SBIC_ID_FS_8_10; 298 else if (dev->sc_clkfreq < 160) 299 my_id |= SBIC_ID_FS_12_15; 300 else if (dev->sc_clkfreq < 210) 301 my_id |= SBIC_ID_FS_16_20; 302 303 /* Enable advanced features */ 304 #if 1 305 my_id |= SBIC_ID_EAF; /* XXX - MD Layer */ 306 #endif 307 308 SET_SBIC_myid(dev, my_id); 309 310 /* Reset the chip */ 311 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 312 DELAY(25); 313 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 314 315 /* Set up various chip parameters */ 316 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 317 318 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 319 GET_SBIC_cdb1(dev, dev->sc_rev); 320 321 switch (csr) { 322 case SBIC_CSR_RESET: 323 dev->sc_chip = SBIC_CHIP_WD33C93; 324 break; 325 case SBIC_CSR_RESET_AM: 326 SET_SBIC_queue_tag(dev, 0x55); 327 GET_SBIC_queue_tag(dev, reg); 328 dev->sc_chip = (reg == 0x55) ? 329 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 330 SET_SBIC_queue_tag(dev, 0x0); 331 break; 332 default: 333 dev->sc_chip = SBIC_CHIP_UNKNOWN; 334 } 335 336 /* 337 * don't allow Selection (SBIC_RID_ES) 338 * until we can handle target mode!! 339 */ 340 SET_SBIC_rselid(dev, SBIC_RID_ER); 341 342 /* Asynchronous for now */ 343 SET_SBIC_syn(dev, 0); 344 345 dev->sc_flags = 0; 346 dev->sc_state = SBIC_IDLE; 347 348 splx(s); 349 350 printf(": %s SCSI, rev=%d, target %d\n", 351 wd33c93_chip_names[dev->sc_chip], dev->sc_rev, 352 dev->sc_channel.chan_id); 353 } 354 355 void 356 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 357 { 358 struct scsipi_xfer *xs = acb->xs; 359 360 KASSERT(xs); 361 362 if (xs->xs_control & XS_CTL_SILENT) 363 return; 364 365 scsipi_printaddr(xs->xs_periph); 366 printf("SCSI Error\n"); 367 } 368 369 /* 370 * Setup sync mode for given target 371 */ 372 void 373 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 374 { 375 u_char offset, period; 376 377 if (ti->flags & T_SYNCMODE) { 378 offset = ti->offset; 379 period = wd33c93_stp2div(dev, ti->period); 380 } else { 381 offset = 0; 382 period = 0; 383 } 384 385 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", 386 SBIC_SYN(offset, period))); 387 SET_SBIC_syn(dev, SBIC_SYN(offset, period)); 388 } 389 390 /* 391 * Check if current operation can be done using DMA 392 * 393 * returns 1 if DMA OK, 0 for polled I/O transfer 394 */ 395 int 396 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 397 { 398 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 399 return (0); 400 return(1); 401 } 402 403 /* 404 * Setup for DMA transfer 405 */ 406 void 407 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 408 { 409 struct wd33c93_acb *acb = dev->sc_nexus; 410 int s; 411 412 dev->sc_daddr = acb->daddr; 413 dev->sc_dleft = acb->dleft; 414 415 s = splbio(); 416 /* Indicate that we're in DMA mode */ 417 if (dev->sc_dleft) { 418 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 419 datain, &dev->sc_dleft); 420 } 421 splx(s); 422 return; 423 } 424 425 426 /* 427 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 428 */ 429 void 430 wd33c93_dma_stop(struct wd33c93_softc *dev) 431 { 432 size_t count; 433 int asr; 434 435 /* Wait until WD chip is idle */ 436 do { 437 GET_SBIC_asr(dev, asr); /* XXX */ 438 if (asr & SBIC_ASR_DBR) { 439 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 440 break; 441 } 442 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 443 444 /* Only need to save pointers if DMA was active */ 445 if (dev->sc_flags & SBICF_INDMA) { 446 int s = splbio(); 447 448 /* Shut down DMA and flush FIFO's */ 449 dev->sc_dmastop(dev); 450 451 /* Fetch the residual count */ 452 SBIC_TC_GET(dev, count); 453 454 /* Work out how many bytes were actually transferred */ 455 count = dev->sc_tcnt - count; 456 457 if (dev->sc_dleft < count) 458 printf("xfer too large: dleft=%zu resid=%zu\n", 459 dev->sc_dleft, count); 460 461 /* Fixup partial xfers */ 462 dev->sc_daddr += count; 463 dev->sc_dleft -= count; 464 dev->sc_tcnt = 0; 465 dev->sc_flags &= ~SBICF_INDMA; 466 splx(s); 467 SBIC_DEBUG(DMA, ("dma_stop\n")); 468 } 469 /* 470 * Ensure the WD chip is back in polled I/O mode, with nothing to 471 * transfer. 472 */ 473 SBIC_TC_PUT(dev, 0); 474 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 475 } 476 477 478 /* 479 * Handle new request from scsipi layer 480 */ 481 void 482 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 483 { 484 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 485 struct scsipi_xfer *xs; 486 struct scsipi_periph *periph; 487 struct wd33c93_acb *acb; 488 int flags, s; 489 490 switch (req) { 491 case ADAPTER_REQ_RUN_XFER: 492 xs = arg; 493 periph = xs->xs_periph; 494 flags = xs->xs_control; 495 496 if (flags & XS_CTL_DATA_UIO) 497 panic("wd33c93: scsi data uio requested"); 498 499 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 500 panic("wd33c93_scsicmd: busy"); 501 502 s = splbio(); 503 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 504 splx(s); 505 506 if (acb == NULL) { 507 scsipi_printaddr(periph); 508 printf("cannot allocate acb\n"); 509 xs->error = XS_RESOURCE_SHORTAGE; 510 scsipi_done(xs); 511 return; 512 } 513 514 acb->flags = ACB_ACTIVE; 515 acb->xs = xs; 516 acb->clen = xs->cmdlen; 517 acb->daddr = xs->data; 518 acb->dleft = xs->datalen; 519 acb->timeout = xs->timeout; 520 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 521 522 if (flags & XS_CTL_POLL) { 523 /* 524 * Complete currently active command(s) before 525 * issuing an immediate command 526 */ 527 while (dev->sc_nexus) 528 wd33c93_poll(dev, dev->sc_nexus); 529 } 530 531 s = splbio(); 532 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 533 acb->flags |= ACB_READY; 534 535 /* If nothing is active, try to start it now. */ 536 if (dev->sc_state == SBIC_IDLE) 537 wd33c93_sched(dev); 538 splx(s); 539 540 if ((flags & XS_CTL_POLL) == 0) 541 return; 542 543 if (wd33c93_poll(dev, acb)) { 544 wd33c93_timeout(acb); 545 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 546 wd33c93_timeout(acb); 547 } 548 return; 549 550 case ADAPTER_REQ_GROW_RESOURCES: 551 /* XXX Not supported. */ 552 return; 553 554 case ADAPTER_REQ_SET_XFER_MODE: 555 { 556 struct wd33c93_tinfo *ti; 557 struct scsipi_xfer_mode *xm = arg; 558 559 ti = &dev->sc_tinfo[xm->xm_target]; 560 ti->flags &= ~(T_NEGOTIATE|T_SYNCMODE); 561 ti->period = 0; 562 ti->offset = 0; 563 564 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 565 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 566 ti->flags |= T_TAG; 567 else 568 ti->flags &= ~T_TAG; 569 570 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 571 (ti->flags & T_NOSYNC) == 0 && dev->sc_minsync != 0) { 572 SBIC_DEBUG(SYNC, ("target %d: sync negotiation\n", 573 xm->xm_target)); 574 ti->flags |= T_NEGOTIATE; 575 ti->period = dev->sc_minsync; 576 } 577 /* 578 * If we're not going to negotiate, send the notification 579 * now, since it won't happen later. 580 */ 581 if ((ti->flags & T_NEGOTIATE) == 0) 582 wd33c93_update_xfer_mode(dev, xm->xm_target); 583 return; 584 } 585 586 } 587 } 588 589 /* 590 * attempt to start the next available command 591 */ 592 void 593 wd33c93_sched(struct wd33c93_softc *dev) 594 { 595 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 596 struct wd33c93_acb *acb; 597 struct wd33c93_tinfo *ti; 598 struct wd33c93_linfo *li; 599 int lun, tag, flags; 600 601 if (dev->sc_state != SBIC_IDLE) 602 return; 603 604 KASSERT(dev->sc_nexus == NULL); 605 606 /* Loop through the ready list looking for work to do... */ 607 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 608 periph = acb->xs->xs_periph; 609 lun = periph->periph_lun; 610 ti = &dev->sc_tinfo[periph->periph_target]; 611 li = TINFO_LUN(ti, lun); 612 613 KASSERT(acb->flags & ACB_READY); 614 615 /* Select type of tag for this command */ 616 if ((ti->flags & T_NODISC) != 0) 617 tag = 0; 618 else if ((ti->flags & T_TAG) == 0) 619 tag = 0; 620 else if ((acb->flags & ACB_SENSE) != 0) 621 tag = 0; 622 else if (acb->xs->xs_control & XS_CTL_POLL) 623 tag = 0; /* No tags for polled commands */ 624 else 625 tag = acb->xs->xs_tag_type; 626 627 if (li == NULL) { 628 /* Initialize LUN info and add to list. */ 629 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 630 if (li == NULL) 631 continue; 632 memset(li, 0, sizeof(*li)); 633 li->lun = lun; 634 if (lun < SBIC_NLUN) 635 ti->lun[lun] = li; 636 } 637 li->last_used = time_second; 638 639 /* 640 * We've found a potential command, but is the target/lun busy? 641 */ 642 643 if (tag == 0 && li->untagged == NULL) 644 li->untagged = acb; /* Issue untagged */ 645 646 if (li->untagged != NULL) { 647 tag = 0; 648 if ((li->state != L_STATE_BUSY) && li->used == 0) { 649 /* Issue this untagged command now */ 650 acb = li->untagged; 651 periph = acb->xs->xs_periph; 652 } else /* Not ready yet */ 653 continue; 654 } 655 656 acb->tag_type = tag; 657 if (tag != 0) { 658 if (li->queued[acb->xs->xs_tag_id]) 659 printf("queueing to active tag\n"); 660 li->queued[acb->xs->xs_tag_id] = acb; 661 acb->tag_id = acb->xs->xs_tag_id; 662 li->used++; 663 break; 664 } 665 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 666 li->state = L_STATE_BUSY; 667 break; 668 } 669 if (li->untagged == NULL && tag != 0) { 670 break; 671 } else 672 printf("%d:%d busy\n", periph->periph_target, 673 periph->periph_lun); 674 } 675 676 if (acb == NULL) { 677 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 678 return; /* did not find an available command */ 679 } 680 681 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 682 periph->periph_lun)); 683 684 TAILQ_REMOVE(&dev->ready_list, acb, chain); 685 acb->flags &= ~ACB_READY; 686 687 flags = acb->xs->xs_control; 688 if (flags & XS_CTL_RESET) 689 wd33c93_reset(dev); 690 691 /* XXX - Implicitly call scsidone on select timeout */ 692 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 693 acb->dleft = dev->sc_dleft; 694 wd33c93_scsidone(dev, acb, dev->sc_status); 695 return; 696 } 697 698 return; 699 } 700 701 void 702 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 703 { 704 struct scsipi_xfer *xs = acb->xs; 705 struct wd33c93_tinfo *ti; 706 struct wd33c93_linfo *li; 707 int s; 708 709 #ifdef DIAGNOSTIC 710 KASSERT(dev->target == xs->xs_periph->periph_target); 711 KASSERT(dev->lun == xs->xs_periph->periph_lun); 712 if (acb == NULL || xs == NULL) { 713 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 714 dev->target, dev->lun); 715 } 716 KASSERT(acb->flags != ACB_FREE); 717 #endif 718 719 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 720 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 721 dev->target, dev->lun, status)); 722 callout_stop(&xs->xs_callout); 723 724 xs->status = status & SCSI_STATUS_MASK; 725 xs->resid = acb->dleft; 726 727 if (xs->error == XS_NOERROR) { 728 switch (xs->status) { 729 case SCSI_CHECK: 730 case SCSI_TERMINATED: 731 /* XXX Need to read sense - return busy for now */ 732 /*FALLTHROUGH*/ 733 case SCSI_QUEUE_FULL: 734 case SCSI_BUSY: 735 xs->error = XS_BUSY; 736 break; 737 } 738 } 739 740 ti = &dev->sc_tinfo[dev->target]; 741 li = TINFO_LUN(ti, dev->lun); 742 ti->cmds++; 743 if (xs->error == XS_SELTIMEOUT) { 744 /* Selection timeout -- discard this LUN if empty */ 745 if (li->untagged == NULL && li->used == 0) { 746 if (dev->lun < SBIC_NLUN) 747 ti->lun[dev->lun] = NULL; 748 free(li, M_DEVBUF); 749 } 750 } 751 752 wd33c93_dequeue(dev, acb); 753 if (dev->sc_nexus == acb) { 754 dev->sc_state = SBIC_IDLE; 755 dev->sc_nexus = NULL; 756 dev->sc_flags = 0; 757 758 if (!TAILQ_EMPTY(&dev->ready_list)) 759 wd33c93_sched(dev); 760 } 761 762 /* place control block back on free list. */ 763 s = splbio(); 764 acb->flags = ACB_FREE; 765 pool_put(&wd33c93_pool, (void *)acb); 766 splx(s); 767 768 scsipi_done(xs); 769 } 770 771 void 772 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 773 { 774 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 775 struct wd33c93_linfo *li; 776 int lun = acb->xs->xs_periph->periph_lun; 777 778 li = TINFO_LUN(ti, lun); 779 #ifdef DIAGNOSTIC 780 if (li == NULL || li->lun != lun) 781 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 782 lun, acb); 783 #endif 784 if (li->untagged == acb) { 785 li->state = L_STATE_IDLE; 786 li->untagged = NULL; 787 } 788 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 789 #ifdef DIAGNOSTIC 790 if (li->queued[acb->tag_id] != NULL && 791 (li->queued[acb->tag_id] != acb)) 792 panic("wd33c93_dequeue: slot %d for lun %d has %p " 793 "instead of acb %p\n", acb->tag_id, 794 lun, li->queued[acb->tag_id], acb); 795 #endif 796 li->queued[acb->tag_id] = NULL; 797 li->used--; 798 } 799 } 800 801 802 int 803 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 804 { 805 u_char val; 806 807 if (timeo == 0) 808 timeo = 1000000; /* some large value.. */ 809 GET_SBIC_asr(dev, val); 810 while ((val & until) == 0) { 811 if (timeo-- == 0) { 812 int csr; 813 GET_SBIC_csr(dev, csr); 814 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 815 line, val, csr); 816 #if defined(DDB) && defined(DEBUG) 817 Debugger(); 818 #endif 819 return(val); /* Maybe I should abort */ 820 break; 821 } 822 DELAY(1); 823 GET_SBIC_asr(dev, val); 824 } 825 return(val); 826 } 827 828 int 829 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 830 const char *where) 831 { 832 u_char csr, asr; 833 834 GET_SBIC_asr(dev, asr); 835 GET_SBIC_csr(dev, csr); 836 837 scsipi_printaddr(acb->xs->xs_periph); 838 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 839 840 acb->timeout = SBIC_ABORT_TIMEOUT; 841 acb->flags |= ACB_ABORT; 842 843 /* 844 * Clean up chip itself 845 */ 846 if (dev->sc_nexus == acb) { 847 /* Reschedule timeout. */ 848 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 849 wd33c93_timeout, acb); 850 851 while (asr & SBIC_ASR_DBR) { 852 /* 853 * wd33c93 is jammed w/data. need to clear it 854 * But we don't know what direction it needs to go 855 */ 856 GET_SBIC_data(dev, asr); 857 printf("abort %s: clearing data buffer 0x%02x\n", 858 where, asr); 859 GET_SBIC_asr(dev, asr); 860 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 861 SET_SBIC_data(dev, asr); 862 GET_SBIC_asr(dev, asr); 863 } 864 865 scsipi_printaddr(acb->xs->xs_periph); 866 printf("sending ABORT command\n"); 867 868 WAIT_CIP(dev); 869 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 870 WAIT_CIP(dev); 871 872 GET_SBIC_asr(dev, asr); 873 874 scsipi_printaddr(acb->xs->xs_periph); 875 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 876 /* 877 * ok, get more drastic.. 878 */ 879 printf("Resetting bus\n"); 880 wd33c93_reset(dev); 881 } else { 882 printf("sending DISCONNECT to target\n"); 883 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 884 WAIT_CIP(dev); 885 886 do { 887 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 888 GET_SBIC_asr(dev, asr); 889 GET_SBIC_csr(dev, csr); 890 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 891 csr, asr)); 892 } while ((csr != SBIC_CSR_DISC) && 893 (csr != SBIC_CSR_DISC_1) && 894 (csr != SBIC_CSR_CMD_INVALID)); 895 } 896 dev->sc_state = SBIC_ERROR; 897 dev->sc_flags = 0; 898 } 899 return SBIC_STATE_ERROR; 900 } 901 902 903 /* 904 * select the bus, return when selected or error. 905 * 906 * Returns the current CSR following selection and optionally MSG out phase. 907 * i.e. the returned CSR *should* indicate CMD phase... 908 * If the return value is 0, some error happened. 909 */ 910 u_char 911 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 912 { 913 struct scsipi_xfer *xs = acb->xs; 914 struct wd33c93_tinfo *ti; 915 u_char target, lun, asr, csr, id; 916 917 KASSERT(dev->sc_state == SBIC_IDLE); 918 919 target = xs->xs_periph->periph_target; 920 lun = xs->xs_periph->periph_lun; 921 ti = &dev->sc_tinfo[target]; 922 923 dev->sc_state = SBIC_SELECTING; 924 dev->target = target; 925 dev->lun = lun; 926 927 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 928 929 if ((xs->xs_control & XS_CTL_POLL) == 0) 930 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 931 wd33c93_timeout, acb); 932 933 /* 934 * issue select 935 */ 936 SBIC_TC_PUT(dev, 0); 937 SET_SBIC_selid(dev, target); 938 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 939 940 GET_SBIC_asr(dev, asr); 941 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 942 /* This means we got ourselves reselected upon */ 943 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 944 return 0; 945 } 946 947 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 948 WAIT_CIP(dev); 949 950 /* 951 * wait for select (merged from separate function may need 952 * cleanup) 953 */ 954 do { 955 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 956 if (asr & SBIC_ASR_LCI) { 957 QPRINTF(("late LCI: asr %02x\n", asr)); 958 return 0; 959 } 960 961 /* Clear interrupt */ 962 GET_SBIC_csr (dev, csr); 963 964 /* Reselected from under our feet? */ 965 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 966 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 967 /* 968 * We need to handle this now so we don't lock up later 969 */ 970 wd33c93_nextstate(dev, acb, csr, asr); 971 return 0; 972 } 973 974 /* Whoops! */ 975 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 976 panic("wd33c93_selectbus: target issued select!"); 977 return 0; 978 } 979 980 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 981 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 982 csr != SBIC_CSR_SEL_TIMEO); 983 984 /* Anyone at home? */ 985 if (csr == SBIC_CSR_SEL_TIMEO) { 986 xs->error = XS_SELTIMEOUT; 987 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 988 return 0; 989 } 990 991 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 992 993 /* Assume we're now selected */ 994 GET_SBIC_selid(dev, id); 995 if (id != target) { 996 /* Something went wrong - wrong target was select */ 997 printf("wd33c93_selectbus: wrong target selected;" 998 " WANTED %d GOT %d", target, id); 999 return 0; /* XXX: Need to call nexstate to handle? */ 1000 } 1001 1002 dev->sc_flags |= SBICF_SELECTED; 1003 dev->sc_state = SBIC_CONNECTED; 1004 1005 /* setup correct sync mode for this target */ 1006 wd33c93_setsync(dev, ti); 1007 1008 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1009 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1010 else 1011 SET_SBIC_rselid (dev, SBIC_RID_ER); 1012 1013 /* 1014 * We only really need to do anything when the target goes to MSG out 1015 * If the device ignored ATN, it's probably old and brain-dead, 1016 * but we'll try to support it anyhow. 1017 * If it doesn't support message out, it definately doesn't 1018 * support synchronous transfers, so no point in even asking... 1019 */ 1020 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1021 if (ti->flags & T_NEGOTIATE) { 1022 /* Inititae a SDTR message */ 1023 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1024 ti->period = dev->sc_minsync; 1025 ti->offset = dev->sc_maxoffset; 1026 1027 /* Send Sync negotiation message */ 1028 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1029 dev->sc_omsg[1] = MSG_EXTENDED; 1030 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1031 dev->sc_omsg[3] = MSG_EXT_SDTR; 1032 dev->sc_omsg[4] = dev->sc_minsync; 1033 dev->sc_omsg[5] = dev->sc_maxoffset; 1034 wd33c93_xfout(dev, 6, dev->sc_omsg); 1035 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1036 dev->sc_flags |= SBICF_SYNCNEGO; 1037 } else { 1038 if (dev->sc_nexus->tag_type != 0) { 1039 /* Use TAGS */ 1040 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1041 dev->target, dev->lun, 1042 dev->sc_nexus->tag_id)); 1043 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1044 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1045 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1046 wd33c93_xfout(dev, 3, dev->sc_omsg); 1047 dev->sc_msgout |= SEND_TAG; 1048 } else { 1049 int no_disc; 1050 1051 /* Setup LUN nexus and disconnect privilege */ 1052 no_disc = xs->xs_control & XS_CTL_POLL || 1053 ti->flags & T_NODISC; 1054 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1055 } 1056 } 1057 /* 1058 * There's one interrupt still to come: 1059 * the change to CMD phase... 1060 */ 1061 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1062 GET_SBIC_csr(dev, csr); 1063 } 1064 1065 return csr; 1066 } 1067 1068 /* 1069 * Information Transfer *to* a SCSI Target. 1070 * 1071 * Note: Don't expect there to be an interrupt immediately after all 1072 * the data is transferred out. The WD spec sheet says that the Transfer- 1073 * Info command for non-MSG_IN phases only completes when the target 1074 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1075 * 1076 * This can have a nasty effect on commands which take a relatively long 1077 * time to complete, for example a START/STOP unit command may remain in 1078 * CMD phase until the disk has spun up. Only then will the target change 1079 * to STATUS phase. This is really only a problem for immediate commands 1080 * since we don't allow disconnection for them (yet). 1081 */ 1082 int 1083 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1084 { 1085 int wait = wd33c93_data_wait; 1086 u_char asr, *buf = bp; 1087 1088 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1089 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1090 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1091 1092 /* 1093 * sigh.. WD-PROTO strikes again.. sending the command in one go 1094 * causes the chip to lock up if talking to certain (misbehaving?) 1095 * targets. Anyway, this procedure should work for all targets, but 1096 * it's slightly slower due to the overhead 1097 */ 1098 1099 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1100 SBIC_TC_PUT (dev, (unsigned)len); 1101 1102 WAIT_CIP (dev); 1103 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1104 1105 /* 1106 * Loop for each byte transferred 1107 */ 1108 do { 1109 GET_SBIC_asr (dev, asr); 1110 1111 if (asr & SBIC_ASR_DBR) { 1112 if (len) { 1113 SET_SBIC_data (dev, *buf); 1114 buf++; 1115 len--; 1116 } else { 1117 SET_SBIC_data (dev, 0); 1118 } 1119 wait = wd33c93_data_wait; 1120 } 1121 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1122 1123 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1124 1125 /* 1126 * Normally, an interrupt will be pending when this routing returns. 1127 */ 1128 return(len); 1129 } 1130 1131 /* 1132 * Information Transfer *from* a Scsi Target 1133 * returns # bytes left to read 1134 */ 1135 int 1136 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1137 { 1138 int wait = wd33c93_data_wait; 1139 u_char *buf = bp; 1140 u_char asr; 1141 #ifdef DEBUG 1142 u_char *obp = bp; 1143 #endif 1144 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1145 SBIC_TC_PUT (dev, (unsigned)len); 1146 1147 WAIT_CIP (dev); 1148 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1149 1150 /* 1151 * Loop for each byte transferred 1152 */ 1153 do { 1154 GET_SBIC_asr (dev, asr); 1155 1156 if (asr & SBIC_ASR_DBR) { 1157 if (len) { 1158 GET_SBIC_data (dev, *buf); 1159 buf++; 1160 len--; 1161 } else { 1162 u_char foo; 1163 GET_SBIC_data (dev, foo); 1164 } 1165 wait = wd33c93_data_wait; 1166 } 1167 1168 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1169 1170 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1171 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1172 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1173 1174 SBIC_TC_PUT (dev, 0); 1175 1176 /* 1177 * this leaves with one csr to be read 1178 */ 1179 return len; 1180 } 1181 1182 1183 /* 1184 * Finish SCSI xfer command: After the completion interrupt from 1185 * a read/write operation, sequence through the final phases in 1186 * programmed i/o. 1187 */ 1188 void 1189 wd33c93_xferdone(struct wd33c93_softc *dev) 1190 { 1191 u_char phase, csr; 1192 int s; 1193 1194 QPRINTF(("{")); 1195 s = splbio(); 1196 1197 /* 1198 * have the wd33c93 complete on its own 1199 */ 1200 SBIC_TC_PUT(dev, 0); 1201 SET_SBIC_cmd_phase(dev, 0x46); 1202 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1203 1204 do { 1205 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1206 GET_SBIC_csr (dev, csr); 1207 QPRINTF(("%02x:", csr)); 1208 } while ((csr != SBIC_CSR_DISC) && 1209 (csr != SBIC_CSR_DISC_1) && 1210 (csr != SBIC_CSR_S_XFERRED)); 1211 1212 dev->sc_flags &= ~SBICF_SELECTED; 1213 dev->sc_state = SBIC_DISCONNECT; 1214 1215 GET_SBIC_cmd_phase (dev, phase); 1216 QPRINTF(("}%02x", phase)); 1217 1218 if (phase == 0x60) 1219 GET_SBIC_tlun(dev, dev->sc_status); 1220 else 1221 wd33c93_error(dev, dev->sc_nexus); 1222 1223 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1224 splx(s); 1225 } 1226 1227 1228 int 1229 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1230 { 1231 struct scsipi_xfer *xs = acb->xs; 1232 int i, dmaok; 1233 u_char csr, asr; 1234 1235 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1236 1237 dev->sc_nexus = acb; 1238 1239 dev->target = xs->xs_periph->periph_target; 1240 dev->lun = xs->xs_periph->periph_lun; 1241 1242 dev->sc_status = STATUS_UNKNOWN; 1243 dev->sc_daddr = acb->daddr; 1244 dev->sc_dleft = acb->dleft; 1245 1246 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1247 dev->sc_flags = 0; 1248 1249 dmaok = wd33c93_dmaok(dev, xs); 1250 1251 if (dmaok == 0) 1252 dev->sc_flags |= SBICF_NODMA; 1253 1254 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1255 dev->target, dev->sc_tcnt, dmaok)); 1256 1257 /* select the SCSI bus (it's an error if bus isn't free) */ 1258 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1259 return(0); /* Not done: needs to be rescheduled */ 1260 1261 /* 1262 * Lets cycle a while then let the interrupt handler take over. 1263 */ 1264 GET_SBIC_asr(dev, asr); 1265 do { 1266 QPRINTF(("go[0x%x] ", csr)); 1267 1268 /* Handle the new phase */ 1269 i = wd33c93_nextstate(dev, acb, csr, asr); 1270 WAIT_CIP(dev); /* XXX */ 1271 if (dev->sc_state == SBIC_CONNECTED) { 1272 1273 GET_SBIC_asr(dev, asr); 1274 1275 if (asr & SBIC_ASR_LCI) 1276 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1277 1278 if (asr & SBIC_ASR_INT) 1279 GET_SBIC_csr(dev, csr); 1280 } 1281 1282 } while (dev->sc_state == SBIC_CONNECTED && 1283 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1284 1285 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1286 1287 if (i == SBIC_STATE_DONE) { 1288 if (dev->sc_status == STATUS_UNKNOWN) { 1289 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1290 return 1; /* Did we really finish that fast? */ 1291 } 1292 } 1293 return 0; 1294 } 1295 1296 1297 int 1298 wd33c93_intr(struct wd33c93_softc *dev) 1299 { 1300 u_char asr, csr; 1301 int i; 1302 1303 /* 1304 * pending interrupt? 1305 */ 1306 GET_SBIC_asr (dev, asr); 1307 if ((asr & SBIC_ASR_INT) == 0) 1308 return(0); 1309 1310 GET_SBIC_csr(dev, csr); 1311 1312 do { 1313 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1314 1315 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1316 WAIT_CIP(dev); /* XXX */ 1317 if (dev->sc_state == SBIC_CONNECTED) { 1318 GET_SBIC_asr(dev, asr); 1319 1320 if (asr & SBIC_ASR_LCI) 1321 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1322 asr, csr); 1323 1324 if (asr & SBIC_ASR_INT) 1325 GET_SBIC_csr(dev, csr); 1326 } 1327 } while (dev->sc_state == SBIC_CONNECTED && 1328 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1329 1330 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1331 1332 return(1); 1333 } 1334 1335 /* 1336 * Complete current command using polled I/O. Used when interrupt driven 1337 * I/O is not allowed (ie. during boot and shutdown) 1338 * 1339 * Polled I/O is very processor intensive 1340 */ 1341 int 1342 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1343 { 1344 u_char asr, csr=0; 1345 int i, count; 1346 struct scsipi_xfer *xs = acb->xs; 1347 1348 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1349 for (count=acb->timeout; count;) { 1350 GET_SBIC_asr (dev, asr); 1351 if (asr & SBIC_ASR_LCI) 1352 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1353 asr, csr); 1354 if (asr & SBIC_ASR_INT) { 1355 GET_SBIC_csr(dev, csr); 1356 dev->sc_flags |= SBICF_NODMA; 1357 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1358 WAIT_CIP(dev); /* XXX */ 1359 } else { 1360 DELAY(1000); 1361 count--; 1362 } 1363 1364 if ((xs->xs_status & XS_STS_DONE) != 0) 1365 return (0); 1366 1367 if (dev->sc_state == SBIC_IDLE) { 1368 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1369 wd33c93_sched(dev); 1370 } 1371 } 1372 return (1); 1373 } 1374 1375 static inline int 1376 __verify_msg_format(u_char *p, int len) 1377 { 1378 1379 if (len == 1 && MSG_IS1BYTE(p[0])) 1380 return 1; 1381 if (len == 2 && MSG_IS2BYTE(p[0])) 1382 return 1; 1383 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1384 len == p[1] + 2) 1385 return 1; 1386 return 0; 1387 } 1388 1389 /* 1390 * Handle message_in phase 1391 */ 1392 int 1393 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1394 { 1395 int len; 1396 u_char asr, csr, *msg; 1397 1398 GET_SBIC_asr(dev, asr); 1399 1400 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1401 1402 GET_SBIC_selid (dev, csr); 1403 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1404 1405 SBIC_TC_PUT(dev, 0); 1406 1407 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1408 1409 msg = dev->sc_imsg; 1410 len = 0; 1411 1412 do { 1413 /* Fetch the next byte of the message */ 1414 RECV_BYTE(dev, *msg++); 1415 len++; 1416 1417 /* 1418 * get the command completion interrupt, or we 1419 * can't send a new command (LCI) 1420 */ 1421 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1422 GET_SBIC_csr(dev, csr); 1423 1424 /* 1425 * Clear ACK, and wait for the interrupt 1426 * for the next byte or phase change 1427 */ 1428 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1429 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1430 1431 if (__verify_msg_format(dev->sc_imsg, len)) 1432 break; /* Complete message recieved */ 1433 1434 GET_SBIC_csr(dev, csr); 1435 } while (len < SBIC_MAX_MSGLEN); 1436 1437 if (__verify_msg_format(dev->sc_imsg, len)) 1438 wd33c93_msgin(dev, dev->sc_imsg, len); 1439 1440 /* Should still have one CSR to read */ 1441 return SBIC_STATE_RUNNING; 1442 } 1443 1444 1445 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1446 { 1447 struct wd33c93_acb *acb = dev->sc_nexus; 1448 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1449 struct wd33c93_linfo *li; 1450 u_char asr; 1451 1452 switch (dev->sc_state) { 1453 case SBIC_CONNECTED: 1454 switch (msgaddr[0]) { 1455 case MSG_MESSAGE_REJECT: 1456 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1457 "last msgout=%x\n", dev->sc_msgout)); 1458 switch (dev->sc_msgout) { 1459 case SEND_TAG: 1460 printf("%s: tagged queuing rejected: " 1461 "target %d\n", 1462 dev->sc_dev.dv_xname, dev->target); 1463 ti->flags &= ~T_TAG; 1464 li = TINFO_LUN(ti, dev->lun); 1465 if (acb->tag_type && 1466 li->queued[acb->tag_id] != NULL) { 1467 li->queued[acb->tag_id] = NULL; 1468 li->used--; 1469 } 1470 acb->tag_type = acb->tag_id = 0; 1471 li->untagged = acb; 1472 li->state = L_STATE_BUSY; 1473 break; 1474 1475 case SEND_SDTR: 1476 printf("%s: sync transfer rejected: target %d\n", 1477 dev->sc_dev.dv_xname, dev->target); 1478 1479 dev->sc_flags &= ~SBICF_SYNCNEGO; 1480 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1481 wd33c93_update_xfer_mode(dev, 1482 acb->xs->xs_periph->periph_target); 1483 wd33c93_setsync(dev, ti); 1484 1485 case SEND_INIT_DET_ERR: 1486 goto abort; 1487 1488 default: 1489 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1490 break; 1491 } 1492 dev->sc_msgout = 0; 1493 break; 1494 1495 case MSG_HEAD_OF_Q_TAG: 1496 case MSG_ORDERED_Q_TAG: 1497 case MSG_SIMPLE_Q_TAG: 1498 printf("-- Out of phase TAG;" 1499 "Nexus=%d:%d Tag=%02x/%02x\n", 1500 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1501 break; 1502 1503 case MSG_DISCONNECT: 1504 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1505 /* 1506 * Mark the fact that all bytes have moved. The 1507 * target may not bother to do a SAVE POINTERS 1508 * at this stage. This flag will set the residual 1509 * count to zero on MSG COMPLETE. 1510 */ 1511 if (dev->sc_dleft == 0) 1512 acb->flags |= ACB_COMPLETE; 1513 1514 if (acb->xs->xs_control & XS_CTL_POLL) 1515 /* Don't allow disconnect in immediate mode */ 1516 goto reject; 1517 else { /* Allow disconnect */ 1518 dev->sc_flags &= ~SBICF_SELECTED; 1519 dev->sc_state = SBIC_DISCONNECT; 1520 } 1521 if ((acb->xs->xs_periph->periph_quirks & 1522 PQUIRK_AUTOSAVE) == 0) 1523 break; 1524 /*FALLTHROUGH*/ 1525 1526 case MSG_SAVEDATAPOINTER: 1527 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1528 acb->daddr = dev->sc_daddr; 1529 acb->dleft = dev->sc_dleft; 1530 break; 1531 1532 case MSG_RESTOREPOINTERS: 1533 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1534 dev->sc_daddr = acb->daddr; 1535 dev->sc_dleft = acb->dleft; 1536 break; 1537 1538 case MSG_CMDCOMPLETE: 1539 /* 1540 * !! KLUDGE ALERT !! quite a few drives don't seem to 1541 * really like the current way of sending the 1542 * sync-handshake together with the ident-message, and 1543 * they react by sending command-complete and 1544 * disconnecting right after returning the valid sync 1545 * handshake. So, all I can do is reselect the drive, 1546 * and hope it won't disconnect again. I don't think 1547 * this is valid behavior, but I can't help fixing a 1548 * problem that apparently exists. 1549 * 1550 * Note: we should not get here on `normal' command 1551 * completion, as that condition is handled by the 1552 * high-level sel&xfer resume command used to walk 1553 * thru status/cc-phase. 1554 */ 1555 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1556 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1557 " acting weird.." 1558 " waiting for disconnect...\n", 1559 msgaddr[0], dev->target)); 1560 1561 /* Check to see if wd33c93 is handling this */ 1562 GET_SBIC_asr(dev, asr); 1563 if (asr & SBIC_ASR_BSY) 1564 break; 1565 1566 /* XXX: Assume it works and set status to 00 */ 1567 dev->sc_status = 0; 1568 dev->sc_state = SBIC_CMDCOMPLETE; 1569 break; 1570 1571 case MSG_EXTENDED: 1572 switch(msgaddr[2]) { 1573 case MSG_EXT_SDTR: /* Sync negotiation */ 1574 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1575 "period %d, offset %d", 1576 msgaddr[3], msgaddr[4])); 1577 if (msgaddr[1] != 3) 1578 goto reject; 1579 1580 ti->period = MAX(msgaddr[3], dev->sc_minsync); 1581 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1582 ti->flags &= ~T_NEGOTIATE; 1583 if (dev->sc_minsync == 0 || ti->period > 124) 1584 ti->offset = ti->period = 0; 1585 1586 if (ti->offset == 0) 1587 ti->flags &= ~T_SYNCMODE; /* Async */ 1588 else { 1589 int p; 1590 1591 p = wd33c93_stp2div(dev, ti->period); 1592 ti->period = wd33c93_div2stp(dev, p); 1593 ti->flags |= T_SYNCMODE; /* Sync */ 1594 } 1595 1596 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1597 /* target initiated negotiation */ 1598 wd33c93_sched_msgout(dev, SEND_SDTR); 1599 dev->sc_flags &= ~SBICF_SYNCNEGO; 1600 1601 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1602 dev->target, ti->offset, 1603 ti->period)); 1604 wd33c93_update_xfer_mode(dev, 1605 acb->xs->xs_periph->periph_target); 1606 wd33c93_setsync(dev, ti); 1607 break; 1608 1609 case MSG_EXT_WDTR: 1610 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR ignored")); 1611 break; 1612 1613 default: 1614 scsipi_printaddr(acb->xs->xs_periph); 1615 printf("unrecognized MESSAGE EXTENDED;" 1616 " sending REJECT\n"); 1617 goto reject; 1618 } 1619 break; 1620 1621 default: 1622 scsipi_printaddr(acb->xs->xs_periph); 1623 printf("unrecognized MESSAGE; sending REJECT\n"); 1624 1625 reject: 1626 /* We don't support whatever this message is... */ 1627 wd33c93_sched_msgout(dev, SEND_REJECT); 1628 break; 1629 } 1630 break; 1631 1632 case SBIC_IDENTIFIED: 1633 /* 1634 * IDENTIFY message was received and queue tag is expected now 1635 */ 1636 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1637 printf("%s: TAG reselect without IDENTIFY;" 1638 " MSG %x; sending DEVICE RESET\n", 1639 dev->sc_dev.dv_xname, msgaddr[0]); 1640 goto reset; 1641 } 1642 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1643 if (dev->sc_nexus) 1644 printf("*TAG Recv with active nexus!!\n"); 1645 wd33c93_reselect(dev, dev->target, dev->lun, 1646 msgaddr[0], msgaddr[1]); 1647 break; 1648 1649 case SBIC_RESELECTED: 1650 /* 1651 * IDENTIFY message with target 1652 */ 1653 if (MSG_ISIDENTIFY(msgaddr[0])) { 1654 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1655 dev->sc_msgify = msgaddr[0]; 1656 } else { 1657 printf("%s: reselect without IDENTIFY;" 1658 " MSG %x;" 1659 " sending DEVICE RESET\n", 1660 dev->sc_dev.dv_xname, msgaddr[0]); 1661 goto reset; 1662 } 1663 break; 1664 1665 default: 1666 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1667 dev->sc_state); 1668 reset: 1669 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1670 break; 1671 abort: 1672 wd33c93_sched_msgout(dev, SEND_ABORT); 1673 break; 1674 } 1675 } 1676 1677 void 1678 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1679 { 1680 u_char asr; 1681 1682 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1683 dev->sc_msgpriq |= msg; 1684 1685 /* Schedule MSGOUT Phase to send message */ 1686 1687 WAIT_CIP(dev); 1688 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1689 WAIT_CIP(dev); 1690 GET_SBIC_asr(dev, asr); 1691 if (asr & SBIC_ASR_LCI) { 1692 printf("MSGOUT Failed!\n"); 1693 } 1694 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1695 WAIT_CIP(dev); 1696 } 1697 1698 /* 1699 * Send the highest priority, scheduled message 1700 */ 1701 void 1702 wd33c93_msgout(struct wd33c93_softc *dev) 1703 { 1704 struct wd33c93_tinfo *ti; 1705 struct wd33c93_acb *acb = dev->sc_nexus; 1706 1707 if (acb == NULL) 1708 panic("MSGOUT with no nexus"); 1709 1710 if (dev->sc_omsglen == 0) { 1711 /* Pick up highest priority message */ 1712 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1713 dev->sc_msgoutq |= dev->sc_msgout; 1714 dev->sc_msgpriq &= ~dev->sc_msgout; 1715 dev->sc_omsglen = 1; /* "Default" message len */ 1716 switch (dev->sc_msgout) { 1717 case SEND_SDTR: 1718 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1719 dev->sc_omsg[0] = MSG_EXTENDED; 1720 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1721 dev->sc_omsg[2] = MSG_EXT_SDTR; 1722 dev->sc_omsg[3] = ti->period; 1723 dev->sc_omsg[4] = ti->offset; 1724 dev->sc_omsglen = 5; 1725 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1726 ti->flags |= T_SYNCMODE; 1727 wd33c93_setsync(dev, ti); 1728 } 1729 break; 1730 case SEND_IDENTIFY: 1731 if (dev->sc_state != SBIC_CONNECTED) { 1732 printf("%s at line %d: no nexus\n", 1733 dev->sc_dev.dv_xname, __LINE__); 1734 } 1735 dev->sc_omsg[0] = 1736 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1737 break; 1738 case SEND_TAG: 1739 if (dev->sc_state != SBIC_CONNECTED) { 1740 printf("%s at line %d: no nexus\n", 1741 dev->sc_dev.dv_xname, __LINE__); 1742 } 1743 dev->sc_omsg[0] = acb->tag_type; 1744 dev->sc_omsg[1] = acb->tag_id; 1745 dev->sc_omsglen = 2; 1746 break; 1747 case SEND_DEV_RESET: 1748 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1749 ti = &dev->sc_tinfo[dev->target]; 1750 ti->flags &= ~T_SYNCMODE; 1751 wd33c93_update_xfer_mode(dev, dev->target); 1752 if ((ti->flags & T_NOSYNC) == 0) 1753 /* We can re-start sync negotiation */ 1754 ti->flags |= T_NEGOTIATE; 1755 break; 1756 case SEND_PARITY_ERROR: 1757 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1758 break; 1759 case SEND_ABORT: 1760 dev->sc_flags |= SBICF_ABORTING; 1761 dev->sc_omsg[0] = MSG_ABORT; 1762 break; 1763 case SEND_INIT_DET_ERR: 1764 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1765 break; 1766 case SEND_REJECT: 1767 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1768 break; 1769 default: 1770 /* Wasn't expecting MSGOUT Phase */ 1771 dev->sc_omsg[0] = MSG_NOOP; 1772 break; 1773 } 1774 } 1775 1776 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1777 } 1778 1779 1780 /* 1781 * wd33c93_nextstate() 1782 * return: 1783 * SBIC_STATE_DONE == done 1784 * SBIC_STATE_RUNNING == working 1785 * SBIC_STATE_DISCONNECT == disconnected 1786 * SBIC_STATE_ERROR == error 1787 */ 1788 int 1789 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1790 { 1791 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1792 1793 switch (csr) { 1794 1795 case SBIC_CSR_XFERRED | CMD_PHASE: 1796 case SBIC_CSR_MIS | CMD_PHASE: 1797 case SBIC_CSR_MIS_1 | CMD_PHASE: 1798 case SBIC_CSR_MIS_2 | CMD_PHASE: 1799 1800 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1801 goto abort; 1802 break; 1803 1804 case SBIC_CSR_XFERRED | STATUS_PHASE: 1805 case SBIC_CSR_MIS | STATUS_PHASE: 1806 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1807 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1808 1809 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1810 1811 /* 1812 * this should be the normal i/o completion case. 1813 * get the status & cmd complete msg then let the 1814 * device driver look at what happened. 1815 */ 1816 wd33c93_xferdone(dev); 1817 1818 wd33c93_dma_stop(dev); 1819 1820 /* Fixup byte count to be passed to higher layer */ 1821 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1822 dev->sc_dleft; 1823 1824 /* 1825 * Indicate to the upper layers that the command is done 1826 */ 1827 wd33c93_scsidone(dev, acb, dev->sc_status); 1828 1829 return SBIC_STATE_DONE; 1830 1831 1832 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1833 case SBIC_CSR_MIS | DATA_IN_PHASE: 1834 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1835 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1836 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1837 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1838 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1839 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1840 /* 1841 * Verify that we expected to transfer data... 1842 */ 1843 if (acb->dleft <= 0) { 1844 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1845 acb->dleft, asr, csr); 1846 goto abort; 1847 } 1848 1849 /* 1850 * Should we transfer using PIO or DMA ? 1851 */ 1852 if (acb->xs->xs_control & XS_CTL_POLL || 1853 dev->sc_flags & SBICF_NODMA) { 1854 /* Perfrom transfer using PIO */ 1855 int resid; 1856 1857 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1858 dev->sc_daddr, dev->sc_dleft)); 1859 1860 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1861 /* data in */ 1862 resid = wd33c93_xfin(dev, dev->sc_dleft, 1863 dev->sc_daddr); 1864 else /* data out */ 1865 resid = wd33c93_xfout(dev, dev->sc_dleft, 1866 dev->sc_daddr); 1867 1868 dev->sc_daddr += (acb->dleft - resid); 1869 dev->sc_dleft = resid; 1870 } else { 1871 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1872 1873 /* Perform transfer using DMA */ 1874 wd33c93_dma_setup(dev, datain); 1875 1876 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1877 SBIC_CTL_DMA); 1878 1879 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1880 dev->sc_daddr, dev->sc_dleft)); 1881 1882 /* Setup byte count for transfer */ 1883 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1884 1885 /* Start the transfer */ 1886 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1887 1888 /* Start the DMA chip going */ 1889 dev->sc_tcnt = dev->sc_dmago(dev); 1890 1891 /* Indicate that we're in DMA mode */ 1892 dev->sc_flags |= SBICF_INDMA; 1893 } 1894 break; 1895 1896 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 1897 case SBIC_CSR_MIS | MESG_IN_PHASE: 1898 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 1899 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 1900 1901 wd33c93_dma_stop(dev); 1902 1903 /* Handle a single message in... */ 1904 return wd33c93_msgin_phase(dev, 0); 1905 1906 case SBIC_CSR_MSGIN_W_ACK: 1907 1908 /* 1909 * We should never see this since it's handled in 1910 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 1911 */ 1912 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1913 1914 printf("Acking unknown msgin CSR:%02x",csr); 1915 break; 1916 1917 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 1918 case SBIC_CSR_MIS | MESG_OUT_PHASE: 1919 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 1920 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 1921 1922 /* 1923 * Message out phase. ATN signal has been asserted 1924 */ 1925 wd33c93_dma_stop(dev); 1926 wd33c93_msgout(dev); 1927 return SBIC_STATE_RUNNING; 1928 1929 case SBIC_CSR_DISC: 1930 case SBIC_CSR_DISC_1: 1931 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 1932 dev->target)); 1933 wd33c93_dma_stop(dev); 1934 1935 dev->sc_nexus = NULL; 1936 dev->sc_state = SBIC_IDLE; 1937 dev->sc_flags = 0; 1938 1939 ++dev->sc_tinfo[dev->target].dconns; 1940 ++dev->sc_disc; 1941 1942 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 1943 return SBIC_STATE_DISCONNECT; 1944 1945 /* Try to schedule another target */ 1946 wd33c93_sched(dev); 1947 1948 return SBIC_STATE_DISCONNECT; 1949 1950 case SBIC_CSR_RSLT_NI: 1951 case SBIC_CSR_RSLT_IFY: 1952 { 1953 /* 1954 * A reselection. 1955 * Note that since we don't enable Advanced Features (assuming 1956 * the WD chip is at least the 'A' revision), we're only ever 1957 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 1958 * hell of it, we'll handle it anyway, for all the extra code 1959 * it needs... 1960 */ 1961 u_char newtarget, newlun; 1962 1963 if (dev->sc_flags & SBICF_INDMA) { 1964 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 1965 wd33c93_dma_stop(dev); 1966 } 1967 1968 dev->sc_state = SBIC_RESELECTED; 1969 GET_SBIC_rselid(dev, newtarget); 1970 1971 /* check SBIC_RID_SIV? */ 1972 newtarget &= SBIC_RID_MASK; 1973 1974 if (csr == SBIC_CSR_RSLT_IFY) { 1975 /* Read Identify msg to avoid lockup */ 1976 GET_SBIC_data(dev, newlun); 1977 WAIT_CIP(dev); 1978 newlun &= SBIC_TLUN_MASK; 1979 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 1980 } else { 1981 /* 1982 * Need to read Identify message the hard way, assuming 1983 * the target even sends us one... 1984 */ 1985 for (newlun = 255; newlun; --newlun) { 1986 GET_SBIC_asr(dev, asr); 1987 if (asr & SBIC_ASR_INT) 1988 break; 1989 DELAY(10); 1990 } 1991 1992 /* If we didn't get an interrupt, somethink's up */ 1993 if ((asr & SBIC_ASR_INT) == 0) { 1994 printf("%s: Reselect without identify? asr %x\n", 1995 dev->sc_dev.dv_xname, asr); 1996 newlun = 0; /* XXXX */ 1997 } else { 1998 /* 1999 * We got an interrupt, verify that it's a 2000 * change to message in phase, and if so 2001 * read the message. 2002 */ 2003 GET_SBIC_csr(dev,csr); 2004 2005 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2006 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2007 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2008 /* 2009 * Yup, gone to message in. 2010 * Fetch the target LUN 2011 */ 2012 dev->sc_msgify = 0; 2013 wd33c93_msgin_phase(dev, 1); 2014 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2015 } else { 2016 /* 2017 * Whoops! Target didn't go to msg_in 2018 * phase!! 2019 */ 2020 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2021 newlun = 0; /* XXXSCW */ 2022 } 2023 } 2024 } 2025 2026 /* Ok, we have the identity of the reselecting target. */ 2027 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2028 newtarget, newlun)); 2029 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2030 dev->sc_disc--; 2031 2032 if (csr == SBIC_CSR_RSLT_IFY) 2033 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2034 break; 2035 } 2036 2037 default: 2038 abort: 2039 /* Something unexpected happend -- deal with it. */ 2040 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2041 2042 #ifdef DDB 2043 Debugger(); 2044 #endif 2045 2046 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2047 if (acb->xs) 2048 wd33c93_error(dev, acb); 2049 wd33c93_abort(dev, acb, "next"); 2050 2051 if (dev->sc_flags & SBICF_INDMA) { 2052 wd33c93_dma_stop(dev); 2053 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2054 } 2055 return SBIC_STATE_ERROR; 2056 } 2057 return SBIC_STATE_RUNNING; 2058 } 2059 2060 2061 void 2062 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2063 { 2064 2065 struct wd33c93_tinfo *ti; 2066 struct wd33c93_linfo *li; 2067 struct wd33c93_acb *acb; 2068 2069 if (dev->sc_nexus) { 2070 /* 2071 * Whoops! We've been reselected with a 2072 * command in progress! 2073 * The best we can do is to put the current 2074 * command back on the ready list and hope 2075 * for the best. 2076 */ 2077 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2078 dev->sc_dev.dv_xname)); 2079 ti = &dev->sc_tinfo[dev->target]; 2080 li = TINFO_LUN(ti, dev->lun); 2081 li->state = L_STATE_IDLE; 2082 2083 wd33c93_dequeue(dev, dev->sc_nexus); 2084 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2085 dev->sc_nexus->flags |= ACB_READY; 2086 2087 dev->sc_nexus = NULL; 2088 } 2089 2090 /* Setup state for new nexus */ 2091 acb = NULL; 2092 dev->sc_flags = SBICF_SELECTED; 2093 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2094 2095 ti = &dev->sc_tinfo[target]; 2096 li = TINFO_LUN(ti, lun); 2097 2098 if (li != NULL) { 2099 if (li->untagged != NULL && li->state) 2100 acb = li->untagged; 2101 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2102 /* Wait for tag to come by during MESG_IN Phase */ 2103 dev->target = target; /* setup I_T_L nexus */ 2104 dev->lun = lun; 2105 dev->sc_state = SBIC_IDENTIFIED; 2106 return; 2107 } else if (tag_type) 2108 acb = li->queued[tag_id]; 2109 } 2110 2111 if (acb == NULL) { 2112 printf("%s: reselect from target %d lun %d tag %x:%x " 2113 "with no nexus; sending ABORT\n", 2114 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2115 goto abort; 2116 } 2117 2118 dev->target = target; 2119 dev->lun = lun; 2120 dev->sc_nexus = acb; 2121 dev->sc_state = SBIC_CONNECTED; 2122 2123 /* Do an implicit RESTORE POINTERS. */ 2124 dev->sc_daddr = acb->daddr; 2125 dev->sc_dleft = acb->dleft; 2126 2127 /* Set sync modes for new target */ 2128 wd33c93_setsync(dev, ti); 2129 2130 if (acb->flags & ACB_RESET) 2131 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2132 else if (acb->flags & ACB_ABORT) 2133 wd33c93_sched_msgout(dev, SEND_ABORT); 2134 return; 2135 2136 abort: 2137 wd33c93_sched_msgout(dev, SEND_ABORT); 2138 return; 2139 2140 } 2141 2142 void 2143 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2144 { 2145 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2146 struct scsipi_xfer_mode xm; 2147 2148 xm.xm_target = target; 2149 xm.xm_mode = 0; 2150 xm.xm_period = 0; 2151 xm.xm_offset = 0; 2152 2153 if (ti->flags & T_SYNCMODE) { 2154 xm.xm_mode |= PERIPH_CAP_SYNC; 2155 xm.xm_period = ti->period; 2156 xm.xm_offset = ti->offset; 2157 } 2158 2159 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2160 xm.xm_mode |= PERIPH_CAP_TQING; 2161 2162 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2163 } 2164 2165 2166 /* 2167 * Convert SCSI Transfer Period Factor (in 4ns units) to the divisor 2168 * value used by the WD33c93 controller. 2169 * 2170 * cycle = DIV / (2 * CLK) 2171 * DIV = FS + 2 2172 * best we can do is 200ns at 20 MHz, 2 cycles 2173 */ 2174 int 2175 wd33c93_div2stp(struct wd33c93_softc *dev, int div) 2176 { 2177 unsigned int fs; 2178 2179 GET_SBIC_myid(dev, fs); 2180 fs = (fs >> 6) + 2; /* DIV */ 2181 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2182 if (div < 2) 2183 div = 8; /* map to Cycles */ 2184 return ((fs * div) >> 2); /* in 4 ns units */ 2185 } 2186 2187 /* 2188 * Calculate SCSI Tranfser Period Factor (4ns units each) from the 2189 * WD33c93 divisor value 2190 */ 2191 int 2192 wd33c93_stp2div(struct wd33c93_softc *dev, int stp) 2193 { 2194 unsigned fs, div; 2195 2196 /* Just the inverse of the above */ 2197 GET_SBIC_myid(dev, fs); 2198 fs = (fs >> 6) + 2; /* DIV */ 2199 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2200 div = stp << 2; /* in ns units */ 2201 div = div / fs; /* in Cycles */ 2202 if (div < 2) 2203 return(2); 2204 2205 /* verify rounding */ 2206 if (wd33c93_div2stp(dev, div) < stp) 2207 div++; 2208 2209 return((div >= 8) ? 0 : div); 2210 } 2211 2212 void 2213 wd33c93_timeout(void *arg) 2214 { 2215 struct wd33c93_acb *acb = arg; 2216 struct scsipi_xfer *xs = acb->xs; 2217 struct scsipi_periph *periph = xs->xs_periph; 2218 struct wd33c93_softc *dev = 2219 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2220 int s, asr; 2221 2222 s = splbio(); 2223 2224 GET_SBIC_asr(dev, asr); 2225 2226 scsipi_printaddr(periph); 2227 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2228 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2229 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2230 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2231 dev->sc_msgpriq, dev->sc_msgout); 2232 2233 if (asr & SBIC_ASR_INT) { 2234 /* We need to service a missed IRQ */ 2235 wd33c93_intr(dev); 2236 } else { 2237 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2238 } 2239 splx(s); 2240 } 2241 2242 2243 void 2244 wd33c93_watchdog(void *arg) 2245 { 2246 struct wd33c93_softc *dev = arg; 2247 struct wd33c93_tinfo *ti; 2248 struct wd33c93_linfo *li; 2249 int t, s, l; 2250 /* scrub LUN's that have not been used in the last 10min. */ 2251 time_t old = time_second - (10 * 60); 2252 2253 for (t = 0; t < SBIC_NTARG; t++) { 2254 ti = &dev->sc_tinfo[t]; 2255 for (l = 0; l < SBIC_NLUN; l++) { 2256 s = splbio(); 2257 li = TINFO_LUN(ti, l); 2258 if (li && li->last_used < old && 2259 li->untagged == NULL && li->used == 0) { 2260 ti->lun[li->lun] = NULL; 2261 free(li, M_DEVBUF); 2262 } 2263 splx(s); 2264 } 2265 } 2266 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2267 } 2268 2269 2270 #ifdef DEBUG 2271 void 2272 wd33c93_hexdump(u_char *buf, int len) 2273 { 2274 printf("{%d}:", len); 2275 while (len--) 2276 printf(" %02x", *buf++); 2277 printf("\n"); 2278 } 2279 2280 2281 void 2282 wd33c93_print_csr(u_char csr) 2283 { 2284 switch (SCSI_PHASE(csr)) { 2285 case CMD_PHASE: 2286 printf("CMD_PHASE\n"); 2287 break; 2288 2289 case STATUS_PHASE: 2290 printf("STATUS_PHASE\n"); 2291 break; 2292 2293 case DATA_IN_PHASE: 2294 printf("DATAIN_PHASE\n"); 2295 break; 2296 2297 case DATA_OUT_PHASE: 2298 printf("DATAOUT_PHASE\n"); 2299 break; 2300 2301 case MESG_IN_PHASE: 2302 printf("MESG_IN_PHASE\n"); 2303 break; 2304 2305 case MESG_OUT_PHASE: 2306 printf("MESG_OUT_PHASE\n"); 2307 break; 2308 2309 default: 2310 switch (csr) { 2311 case SBIC_CSR_DISC_1: 2312 printf("DISC_1\n"); 2313 break; 2314 2315 case SBIC_CSR_RSLT_NI: 2316 printf("RESELECT_NO_IFY\n"); 2317 break; 2318 2319 case SBIC_CSR_RSLT_IFY: 2320 printf("RESELECT_IFY\n"); 2321 break; 2322 2323 case SBIC_CSR_SLT: 2324 printf("SELECT\n"); 2325 break; 2326 2327 case SBIC_CSR_SLT_ATN: 2328 printf("SELECT, ATN\n"); 2329 break; 2330 2331 case SBIC_CSR_UNK_GROUP: 2332 printf("UNK_GROUP\n"); 2333 break; 2334 2335 default: 2336 printf("UNKNOWN csr=%02x\n", csr); 2337 } 2338 } 2339 } 2340 #endif 2341
Indexes created Thu Sep 25 02:09:54 GMT 2025