wdc.c revision 1.245 1 1.245 bouyer /* $NetBSD: wdc.c,v 1.245 2007/01/18 21:42:57 bouyer Exp $ */
2 1.31 bouyer
3 1.31 bouyer /*
4 1.137 bouyer * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
5 1.31 bouyer *
6 1.31 bouyer * Redistribution and use in source and binary forms, with or without
7 1.31 bouyer * modification, are permitted provided that the following conditions
8 1.31 bouyer * are met:
9 1.31 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.31 bouyer * notice, this list of conditions and the following disclaimer.
11 1.31 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.31 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.31 bouyer * documentation and/or other materials provided with the distribution.
14 1.31 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.31 bouyer * must display the following acknowledgement:
16 1.31 bouyer * This product includes software developed by Manuel Bouyer.
17 1.31 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.31 bouyer * derived from this software without specific prior written permission.
19 1.31 bouyer *
20 1.31 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.31 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.31 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.31 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.31 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.31 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.31 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.31 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.31 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.31 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.31 bouyer */
31 1.2 bouyer
32 1.27 mycroft /*-
33 1.220 mycroft * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
34 1.27 mycroft * All rights reserved.
35 1.2 bouyer *
36 1.27 mycroft * This code is derived from software contributed to The NetBSD Foundation
37 1.27 mycroft * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
38 1.12 cgd *
39 1.2 bouyer * Redistribution and use in source and binary forms, with or without
40 1.2 bouyer * modification, are permitted provided that the following conditions
41 1.2 bouyer * are met:
42 1.2 bouyer * 1. Redistributions of source code must retain the above copyright
43 1.2 bouyer * notice, this list of conditions and the following disclaimer.
44 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright
45 1.2 bouyer * notice, this list of conditions and the following disclaimer in the
46 1.2 bouyer * documentation and/or other materials provided with the distribution.
47 1.2 bouyer * 3. All advertising materials mentioning features or use of this software
48 1.2 bouyer * must display the following acknowledgement:
49 1.27 mycroft * This product includes software developed by the NetBSD
50 1.27 mycroft * Foundation, Inc. and its contributors.
51 1.27 mycroft * 4. Neither the name of The NetBSD Foundation nor the names of its
52 1.27 mycroft * contributors may be used to endorse or promote products derived
53 1.27 mycroft * from this software without specific prior written permission.
54 1.2 bouyer *
55 1.27 mycroft * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
56 1.27 mycroft * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57 1.27 mycroft * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58 1.27 mycroft * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
59 1.27 mycroft * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60 1.27 mycroft * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61 1.27 mycroft * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62 1.27 mycroft * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63 1.27 mycroft * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64 1.27 mycroft * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65 1.27 mycroft * POSSIBILITY OF SUCH DAMAGE.
66 1.2 bouyer */
67 1.2 bouyer
68 1.12 cgd /*
69 1.12 cgd * CODE UNTESTED IN THE CURRENT REVISION:
70 1.12 cgd */
71 1.100 lukem
72 1.100 lukem #include <sys/cdefs.h>
73 1.245 bouyer __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.245 2007/01/18 21:42:57 bouyer Exp $");
74 1.12 cgd
75 1.204 thorpej #ifndef ATADEBUG
76 1.204 thorpej #define ATADEBUG
77 1.204 thorpej #endif /* ATADEBUG */
78 1.31 bouyer
79 1.2 bouyer #include <sys/param.h>
80 1.2 bouyer #include <sys/systm.h>
81 1.2 bouyer #include <sys/kernel.h>
82 1.2 bouyer #include <sys/conf.h>
83 1.2 bouyer #include <sys/buf.h>
84 1.31 bouyer #include <sys/device.h>
85 1.2 bouyer #include <sys/malloc.h>
86 1.2 bouyer #include <sys/syslog.h>
87 1.2 bouyer #include <sys/proc.h>
88 1.2 bouyer
89 1.2 bouyer #include <machine/intr.h>
90 1.2 bouyer #include <machine/bus.h>
91 1.2 bouyer
92 1.17 sakamoto #ifndef __BUS_SPACE_HAS_STREAM_METHODS
93 1.31 bouyer #define bus_space_write_multi_stream_2 bus_space_write_multi_2
94 1.31 bouyer #define bus_space_write_multi_stream_4 bus_space_write_multi_4
95 1.31 bouyer #define bus_space_read_multi_stream_2 bus_space_read_multi_2
96 1.31 bouyer #define bus_space_read_multi_stream_4 bus_space_read_multi_4
97 1.17 sakamoto #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
98 1.16 sakamoto
99 1.103 bouyer #include <dev/ata/atavar.h>
100 1.31 bouyer #include <dev/ata/atareg.h>
101 1.239 bouyer #include <dev/ata/satareg.h>
102 1.239 bouyer #include <dev/ata/satavar.h>
103 1.12 cgd #include <dev/ic/wdcreg.h>
104 1.12 cgd #include <dev/ic/wdcvar.h>
105 1.31 bouyer
106 1.137 bouyer #include "locators.h"
107 1.137 bouyer
108 1.2 bouyer #include "atapibus.h"
109 1.106 bouyer #include "wd.h"
110 1.240 bouyer #include "sata.h"
111 1.2 bouyer
112 1.31 bouyer #define WDCDELAY 100 /* 100 microseconds */
113 1.31 bouyer #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
114 1.2 bouyer #if 0
115 1.31 bouyer /* If you enable this, it will report any delays more than WDCDELAY * N long. */
116 1.2 bouyer #define WDCNDELAY_DEBUG 50
117 1.2 bouyer #endif
118 1.2 bouyer
119 1.137 bouyer /* When polling wait that much and then tsleep for 1/hz seconds */
120 1.219 perry #define WDCDELAY_POLL 1 /* ms */
121 1.137 bouyer
122 1.137 bouyer /* timeout for the control commands */
123 1.137 bouyer #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */
124 1.137 bouyer
125 1.224 bouyer /*
126 1.224 bouyer * timeout when waiting for BSY to deassert when probing.
127 1.224 bouyer * set to 5s. From the standards this could be up to 31, but we can't
128 1.224 bouyer * wait that much at boot time, and 5s seems to be enouth.
129 1.224 bouyer */
130 1.224 bouyer #define WDC_PROBE_WAIT 5
131 1.224 bouyer
132 1.224 bouyer
133 1.106 bouyer #if NWD > 0
134 1.103 bouyer extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */
135 1.106 bouyer #else
136 1.106 bouyer /* A fake one, the autoconfig will print "wd at foo ... not configured */
137 1.106 bouyer const struct ata_bustype wdc_ata_bustype = {
138 1.106 bouyer SCSIPI_BUSTYPE_ATA,
139 1.214 enami NULL, /* wdc_ata_bio */
140 1.214 enami NULL, /* wdc_reset_drive */
141 1.214 enami wdc_reset_channel,
142 1.214 enami wdc_exec_command,
143 1.214 enami NULL, /* ata_get_params */
144 1.214 enami NULL, /* wdc_ata_addref */
145 1.214 enami NULL, /* wdc_ata_delref */
146 1.214 enami NULL /* ata_kill_pending */
147 1.106 bouyer };
148 1.106 bouyer #endif
149 1.102 bouyer
150 1.213 thorpej /* Flags to wdcreset(). */
151 1.213 thorpej #define RESET_POLL 1
152 1.213 thorpej #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */
153 1.213 thorpej
154 1.213 thorpej static int wdcprobe1(struct ata_channel *, int);
155 1.213 thorpej static int wdcreset(struct ata_channel *, int);
156 1.222 christos static void __wdcerror(struct ata_channel *, const char *);
157 1.205 thorpej static int __wdcwait_reset(struct ata_channel *, int, int);
158 1.205 thorpej static void __wdccommand_done(struct ata_channel *, struct ata_xfer *);
159 1.205 thorpej static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *);
160 1.205 thorpej static void __wdccommand_kill_xfer(struct ata_channel *,
161 1.182 bouyer struct ata_xfer *, int);
162 1.205 thorpej static void __wdccommand_start(struct ata_channel *, struct ata_xfer *);
163 1.205 thorpej static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int);
164 1.205 thorpej static int __wdcwait(struct ata_channel *, int, int, int);
165 1.31 bouyer
166 1.213 thorpej static void wdc_datain_pio(struct ata_channel *, int, void *, size_t);
167 1.213 thorpej static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t);
168 1.213 thorpej
169 1.31 bouyer #define DEBUG_INTR 0x01
170 1.31 bouyer #define DEBUG_XFERS 0x02
171 1.31 bouyer #define DEBUG_STATUS 0x04
172 1.31 bouyer #define DEBUG_FUNCS 0x08
173 1.31 bouyer #define DEBUG_PROBE 0x10
174 1.74 enami #define DEBUG_DETACH 0x20
175 1.87 bouyer #define DEBUG_DELAY 0x40
176 1.204 thorpej #ifdef ATADEBUG
177 1.204 thorpej extern int atadebug_mask; /* init'ed in ata.c */
178 1.31 bouyer int wdc_nxfer = 0;
179 1.204 thorpej #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args
180 1.2 bouyer #else
181 1.204 thorpej #define ATADEBUG_PRINT(args, level)
182 1.2 bouyer #endif
183 1.2 bouyer
184 1.162 thorpej /*
185 1.176 thorpej * Initialize the "shadow register" handles for a standard wdc controller.
186 1.176 thorpej */
187 1.176 thorpej void
188 1.205 thorpej wdc_init_shadow_regs(struct ata_channel *chp)
189 1.176 thorpej {
190 1.206 thorpej struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
191 1.176 thorpej
192 1.205 thorpej wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command];
193 1.205 thorpej wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error];
194 1.205 thorpej }
195 1.205 thorpej
196 1.205 thorpej /*
197 1.205 thorpej * Allocate a wdc_regs array, based on the number of channels.
198 1.205 thorpej */
199 1.205 thorpej void
200 1.205 thorpej wdc_allocate_regs(struct wdc_softc *wdc)
201 1.205 thorpej {
202 1.205 thorpej
203 1.207 thorpej wdc->regs = malloc(wdc->sc_atac.atac_nchannels *
204 1.207 thorpej sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK);
205 1.176 thorpej }
206 1.176 thorpej
207 1.240 bouyer #if NSATA > 0
208 1.239 bouyer /*
209 1.239 bouyer * probe drives on SATA controllers with standard SATA registers:
210 1.239 bouyer * bring the PHYs online, read the drive signature and set drive flags
211 1.239 bouyer * appropriately.
212 1.239 bouyer */
213 1.239 bouyer void
214 1.239 bouyer wdc_sataprobe(struct ata_channel *chp)
215 1.239 bouyer {
216 1.239 bouyer struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
217 1.239 bouyer uint16_t scnt, sn, cl, ch;
218 1.239 bouyer int i, s;
219 1.239 bouyer
220 1.239 bouyer /* XXX This should be done by other code. */
221 1.239 bouyer for (i = 0; i < chp->ch_ndrive; i++) {
222 1.239 bouyer chp->ch_drive[i].chnl_softc = chp;
223 1.239 bouyer chp->ch_drive[i].drive = i;
224 1.239 bouyer }
225 1.239 bouyer
226 1.242 bouyer /* reset the PHY and bring online */
227 1.242 bouyer switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control,
228 1.242 bouyer wdr->sata_status)) {
229 1.239 bouyer case SStatus_DET_DEV:
230 1.239 bouyer bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
231 1.239 bouyer WDSD_IBM);
232 1.239 bouyer delay(10); /* 400ns delay */
233 1.239 bouyer scnt = bus_space_read_2(wdr->cmd_iot,
234 1.239 bouyer wdr->cmd_iohs[wd_seccnt], 0);
235 1.239 bouyer sn = bus_space_read_2(wdr->cmd_iot,
236 1.239 bouyer wdr->cmd_iohs[wd_sector], 0);
237 1.239 bouyer cl = bus_space_read_2(wdr->cmd_iot,
238 1.239 bouyer wdr->cmd_iohs[wd_cyl_lo], 0);
239 1.239 bouyer ch = bus_space_read_2(wdr->cmd_iot,
240 1.239 bouyer wdr->cmd_iohs[wd_cyl_hi], 0);
241 1.239 bouyer ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x "
242 1.239 bouyer "cl=0x%x ch=0x%x\n",
243 1.239 bouyer chp->ch_atac->atac_dev.dv_xname, chp->ch_channel,
244 1.239 bouyer scnt, sn, cl, ch), DEBUG_PROBE);
245 1.239 bouyer /*
246 1.239 bouyer * scnt and sn are supposed to be 0x1 for ATAPI, but in some
247 1.239 bouyer * cases we get wrong values here, so ignore it.
248 1.239 bouyer */
249 1.239 bouyer s = splbio();
250 1.239 bouyer if (cl == 0x14 && ch == 0xeb)
251 1.239 bouyer chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
252 1.239 bouyer else
253 1.239 bouyer chp->ch_drive[0].drive_flags |= DRIVE_ATA;
254 1.239 bouyer splx(s);
255 1.239 bouyer
256 1.241 bouyer /*
257 1.241 bouyer * issue a reset in case only the interface part of the drive
258 1.241 bouyer * is up
259 1.241 bouyer */
260 1.241 bouyer if (wdcreset(chp, RESET_SLEEP) != 0)
261 1.241 bouyer chp->ch_drive[0].drive_flags = 0;
262 1.239 bouyer break;
263 1.239 bouyer
264 1.239 bouyer default:
265 1.242 bouyer break;
266 1.239 bouyer }
267 1.239 bouyer }
268 1.240 bouyer #endif /* NSATA > 0 */
269 1.239 bouyer
270 1.239 bouyer
271 1.162 thorpej /* Test to see controller with at last one attached drive is there.
272 1.162 thorpej * Returns a bit for each possible drive found (0x01 for drive 0,
273 1.162 thorpej * 0x02 for drive 1).
274 1.162 thorpej * Logic:
275 1.162 thorpej * - If a status register is at 0xff, assume there is no drive here
276 1.162 thorpej * (ISA has pull-up resistors). Similarly if the status register has
277 1.162 thorpej * the value we last wrote to the bus (for IDE interfaces without pullups).
278 1.162 thorpej * If no drive at all -> return.
279 1.162 thorpej * - reset the controller, wait for it to complete (may take up to 31s !).
280 1.162 thorpej * If timeout -> return.
281 1.162 thorpej * - test ATA/ATAPI signatures. If at last one drive found -> return.
282 1.162 thorpej * - try an ATA command on the master.
283 1.162 thorpej */
284 1.137 bouyer
285 1.239 bouyer void
286 1.205 thorpej wdc_drvprobe(struct ata_channel *chp)
287 1.137 bouyer {
288 1.137 bouyer struct ataparams params;
289 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
290 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
291 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
292 1.145 christos u_int8_t st0 = 0, st1 = 0;
293 1.232 bouyer int i, j, error, s;
294 1.137 bouyer
295 1.164 thorpej if (wdcprobe1(chp, 0) == 0) {
296 1.164 thorpej /* No drives, abort the attach here. */
297 1.164 thorpej return;
298 1.161 thorpej }
299 1.137 bouyer
300 1.137 bouyer /* for ATA/OLD drives, wait for DRDY, 3s timeout */
301 1.137 bouyer for (i = 0; i < mstohz(3000); i++) {
302 1.174 bouyer if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
303 1.207 thorpej if (wdc->select)
304 1.174 bouyer wdc->select(chp,0);
305 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
306 1.174 bouyer 0, WDSD_IBM);
307 1.174 bouyer delay(10); /* 400ns delay */
308 1.205 thorpej st0 = bus_space_read_1(wdr->cmd_iot,
309 1.205 thorpej wdr->cmd_iohs[wd_status], 0);
310 1.174 bouyer }
311 1.219 perry
312 1.174 bouyer if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) {
313 1.207 thorpej if (wdc->select)
314 1.174 bouyer wdc->select(chp,1);
315 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
316 1.174 bouyer 0, WDSD_IBM | 0x10);
317 1.174 bouyer delay(10); /* 400ns delay */
318 1.205 thorpej st1 = bus_space_read_1(wdr->cmd_iot,
319 1.205 thorpej wdr->cmd_iohs[wd_status], 0);
320 1.174 bouyer }
321 1.219 perry
322 1.137 bouyer if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD))
323 1.137 bouyer == 0 ||
324 1.137 bouyer (st0 & WDCS_DRDY)) &&
325 1.137 bouyer ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD))
326 1.137 bouyer == 0 ||
327 1.137 bouyer (st1 & WDCS_DRDY)))
328 1.137 bouyer break;
329 1.164 thorpej tsleep(¶ms, PRIBIO, "atadrdy", 1);
330 1.137 bouyer }
331 1.212 thorpej s = splbio();
332 1.137 bouyer if ((st0 & WDCS_DRDY) == 0)
333 1.137 bouyer chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
334 1.137 bouyer if ((st1 & WDCS_DRDY) == 0)
335 1.137 bouyer chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD);
336 1.212 thorpej splx(s);
337 1.137 bouyer
338 1.204 thorpej ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n",
339 1.207 thorpej atac->atac_dev.dv_xname,
340 1.169 thorpej chp->ch_channel, st0, st1), DEBUG_PROBE);
341 1.137 bouyer
342 1.137 bouyer /* Wait a bit, some devices are weird just after a reset. */
343 1.137 bouyer delay(5000);
344 1.137 bouyer
345 1.232 bouyer for (i = 0; i < chp->ch_ndrive; i++) {
346 1.171 thorpej /* XXX This should be done by other code. */
347 1.137 bouyer chp->ch_drive[i].chnl_softc = chp;
348 1.137 bouyer chp->ch_drive[i].drive = i;
349 1.171 thorpej
350 1.238 itohy #if NATA_DMA
351 1.137 bouyer /*
352 1.137 bouyer * Init error counter so that an error withing the first xfers
353 1.137 bouyer * will trigger a downgrade
354 1.137 bouyer */
355 1.137 bouyer chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1;
356 1.238 itohy #endif
357 1.137 bouyer
358 1.137 bouyer /* If controller can't do 16bit flag the drives as 32bit */
359 1.207 thorpej if ((atac->atac_cap &
360 1.212 thorpej (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) {
361 1.212 thorpej s = splbio();
362 1.137 bouyer chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
363 1.212 thorpej splx(s);
364 1.212 thorpej }
365 1.137 bouyer if ((chp->ch_drive[i].drive_flags & DRIVE) == 0)
366 1.137 bouyer continue;
367 1.137 bouyer
368 1.144 briggs /* Shortcut in case we've been shutdown */
369 1.205 thorpej if (chp->ch_flags & ATACH_SHUTDOWN)
370 1.164 thorpej return;
371 1.144 briggs
372 1.216 bouyer /*
373 1.216 bouyer * Issue an identify, to try to detect ghosts.
374 1.216 bouyer * Note that we can't use interrupts here, because if there
375 1.216 bouyer * is no devices, we will get a command aborted without
376 1.216 bouyer * interrupts.
377 1.216 bouyer */
378 1.216 bouyer error = ata_get_params(&chp->ch_drive[i],
379 1.216 bouyer AT_WAIT | AT_POLL, ¶ms);
380 1.137 bouyer if (error != CMD_OK) {
381 1.164 thorpej tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000));
382 1.144 briggs
383 1.144 briggs /* Shortcut in case we've been shutdown */
384 1.205 thorpej if (chp->ch_flags & ATACH_SHUTDOWN)
385 1.164 thorpej return;
386 1.144 briggs
387 1.137 bouyer error = ata_get_params(&chp->ch_drive[i],
388 1.216 bouyer AT_WAIT | AT_POLL, ¶ms);
389 1.137 bouyer }
390 1.137 bouyer if (error == CMD_OK) {
391 1.152 wiz /* If IDENTIFY succeeded, this is not an OLD ctrl */
392 1.212 thorpej s = splbio();
393 1.232 bouyer for (j = 0; j < chp->ch_ndrive; j++)
394 1.232 bouyer chp->ch_drive[j].drive_flags &= ~DRIVE_OLD;
395 1.212 thorpej splx(s);
396 1.137 bouyer } else {
397 1.212 thorpej s = splbio();
398 1.155 bouyer chp->ch_drive[i].drive_flags &=
399 1.137 bouyer ~(DRIVE_ATA | DRIVE_ATAPI);
400 1.212 thorpej splx(s);
401 1.204 thorpej ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n",
402 1.207 thorpej atac->atac_dev.dv_xname,
403 1.169 thorpej chp->ch_channel, i, error), DEBUG_PROBE);
404 1.137 bouyer if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0)
405 1.137 bouyer continue;
406 1.137 bouyer /*
407 1.137 bouyer * Pre-ATA drive ?
408 1.137 bouyer * Test registers writability (Error register not
409 1.137 bouyer * writable, but cyllo is), then try an ATA command.
410 1.137 bouyer */
411 1.203 thorpej if (wdc->select)
412 1.169 thorpej wdc->select(chp,i);
413 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
414 1.205 thorpej wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4));
415 1.137 bouyer delay(10); /* 400ns delay */
416 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error],
417 1.157 fvdl 0, 0x58);
418 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
419 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5);
420 1.205 thorpej if (bus_space_read_1(wdr->cmd_iot,
421 1.205 thorpej wdr->cmd_iohs[wd_error], 0) == 0x58 ||
422 1.205 thorpej bus_space_read_1(wdr->cmd_iot,
423 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) {
424 1.204 thorpej ATADEBUG_PRINT(("%s:%d:%d: register "
425 1.137 bouyer "writability failed\n",
426 1.207 thorpej atac->atac_dev.dv_xname,
427 1.169 thorpej chp->ch_channel, i), DEBUG_PROBE);
428 1.212 thorpej s = splbio();
429 1.137 bouyer chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
430 1.212 thorpej splx(s);
431 1.155 bouyer continue;
432 1.137 bouyer }
433 1.166 thorpej if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
434 1.204 thorpej ATADEBUG_PRINT(("%s:%d:%d: not ready\n",
435 1.207 thorpej atac->atac_dev.dv_xname,
436 1.169 thorpej chp->ch_channel, i), DEBUG_PROBE);
437 1.212 thorpej s = splbio();
438 1.137 bouyer chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
439 1.212 thorpej splx(s);
440 1.137 bouyer continue;
441 1.137 bouyer }
442 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
443 1.205 thorpej wdr->cmd_iohs[wd_command], 0, WDCC_RECAL);
444 1.137 bouyer delay(10); /* 400ns delay */
445 1.166 thorpej if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) {
446 1.204 thorpej ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n",
447 1.207 thorpej atac->atac_dev.dv_xname,
448 1.169 thorpej chp->ch_channel, i), DEBUG_PROBE);
449 1.212 thorpej s = splbio();
450 1.137 bouyer chp->ch_drive[i].drive_flags &= ~DRIVE_OLD;
451 1.212 thorpej splx(s);
452 1.155 bouyer } else {
453 1.212 thorpej s = splbio();
454 1.232 bouyer for (j = 0; j < chp->ch_ndrive; j++)
455 1.232 bouyer chp->ch_drive[j].drive_flags &=
456 1.232 bouyer ~(DRIVE_ATA | DRIVE_ATAPI);
457 1.212 thorpej splx(s);
458 1.137 bouyer }
459 1.137 bouyer }
460 1.137 bouyer }
461 1.164 thorpej }
462 1.164 thorpej
463 1.2 bouyer int
464 1.205 thorpej wdcprobe(struct ata_channel *chp)
465 1.12 cgd {
466 1.228 bouyer struct wdc_softc *wdc = CHAN_TO_WDC(chp);
467 1.227 bouyer /* default reset method */
468 1.227 bouyer if (wdc->reset == NULL)
469 1.227 bouyer wdc->reset = wdc_do_reset;
470 1.163 thorpej
471 1.163 thorpej return (wdcprobe1(chp, 1));
472 1.137 bouyer }
473 1.137 bouyer
474 1.167 thorpej static int
475 1.205 thorpej wdcprobe1(struct ata_channel *chp, int poll)
476 1.137 bouyer {
477 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
478 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
479 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
480 1.224 bouyer u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch;
481 1.31 bouyer u_int8_t ret_value = 0x03;
482 1.31 bouyer u_int8_t drive;
483 1.156 bouyer int s;
484 1.224 bouyer int wdc_probe_count =
485 1.224 bouyer poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz);
486 1.31 bouyer
487 1.31 bouyer /*
488 1.31 bouyer * Sanity check to see if the wdc channel responds at all.
489 1.31 bouyer */
490 1.31 bouyer
491 1.174 bouyer s = splbio();
492 1.207 thorpej if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
493 1.224 bouyer while (wdc_probe_count-- > 0) {
494 1.224 bouyer if (wdc->select)
495 1.224 bouyer wdc->select(chp,0);
496 1.107 dbj
497 1.224 bouyer bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
498 1.224 bouyer 0, WDSD_IBM);
499 1.224 bouyer delay(10); /* 400ns delay */
500 1.224 bouyer st0 = bus_space_read_1(wdr->cmd_iot,
501 1.224 bouyer wdr->cmd_iohs[wd_status], 0);
502 1.137 bouyer
503 1.224 bouyer if (wdc->select)
504 1.224 bouyer wdc->select(chp,1);
505 1.219 perry
506 1.224 bouyer bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
507 1.224 bouyer 0, WDSD_IBM | 0x10);
508 1.224 bouyer delay(10); /* 400ns delay */
509 1.224 bouyer st1 = bus_space_read_1(wdr->cmd_iot,
510 1.224 bouyer wdr->cmd_iohs[wd_status], 0);
511 1.224 bouyer if ((st0 & WDCS_BSY) == 0)
512 1.224 bouyer break;
513 1.224 bouyer }
514 1.43 kenh
515 1.204 thorpej ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
516 1.207 thorpej atac->atac_dev.dv_xname,
517 1.169 thorpej chp->ch_channel, st0, st1), DEBUG_PROBE);
518 1.43 kenh
519 1.142 bouyer if (st0 == 0xff || st0 == WDSD_IBM)
520 1.43 kenh ret_value &= ~0x01;
521 1.142 bouyer if (st1 == 0xff || st1 == (WDSD_IBM | 0x10))
522 1.43 kenh ret_value &= ~0x02;
523 1.125 mycroft /* Register writability test, drive 0. */
524 1.125 mycroft if (ret_value & 0x01) {
525 1.207 thorpej if (wdc->select)
526 1.169 thorpej wdc->select(chp,0);
527 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
528 1.157 fvdl 0, WDSD_IBM);
529 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
530 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0, 0x02);
531 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
532 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
533 1.174 bouyer if (cl != 0x02) {
534 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
535 1.174 bouyer "got 0x%x != 0x02\n",
536 1.207 thorpej atac->atac_dev.dv_xname,
537 1.174 bouyer chp->ch_channel, cl),
538 1.174 bouyer DEBUG_PROBE);
539 1.125 mycroft ret_value &= ~0x01;
540 1.174 bouyer }
541 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
542 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0, 0x01);
543 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
544 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
545 1.174 bouyer if (cl != 0x01) {
546 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: "
547 1.174 bouyer "got 0x%x != 0x01\n",
548 1.207 thorpej atac->atac_dev.dv_xname,
549 1.174 bouyer chp->ch_channel, cl),
550 1.174 bouyer DEBUG_PROBE);
551 1.125 mycroft ret_value &= ~0x01;
552 1.174 bouyer }
553 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
554 1.205 thorpej wdr->cmd_iohs[wd_sector], 0, 0x01);
555 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
556 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
557 1.174 bouyer if (cl != 0x01) {
558 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: "
559 1.174 bouyer "got 0x%x != 0x01\n",
560 1.207 thorpej atac->atac_dev.dv_xname,
561 1.174 bouyer chp->ch_channel, cl),
562 1.174 bouyer DEBUG_PROBE);
563 1.125 mycroft ret_value &= ~0x01;
564 1.174 bouyer }
565 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
566 1.205 thorpej wdr->cmd_iohs[wd_sector], 0, 0x02);
567 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
568 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
569 1.174 bouyer if (cl != 0x02) {
570 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: "
571 1.174 bouyer "got 0x%x != 0x02\n",
572 1.207 thorpej atac->atac_dev.dv_xname,
573 1.174 bouyer chp->ch_channel, cl),
574 1.174 bouyer DEBUG_PROBE);
575 1.125 mycroft ret_value &= ~0x01;
576 1.174 bouyer }
577 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
578 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
579 1.174 bouyer if (cl != 0x01) {
580 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): "
581 1.174 bouyer "got 0x%x != 0x01\n",
582 1.207 thorpej atac->atac_dev.dv_xname,
583 1.174 bouyer chp->ch_channel, cl),
584 1.174 bouyer DEBUG_PROBE);
585 1.131 mycroft ret_value &= ~0x01;
586 1.174 bouyer }
587 1.125 mycroft }
588 1.125 mycroft /* Register writability test, drive 1. */
589 1.125 mycroft if (ret_value & 0x02) {
590 1.207 thorpej if (wdc->select)
591 1.169 thorpej wdc->select(chp,1);
592 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
593 1.157 fvdl 0, WDSD_IBM | 0x10);
594 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
595 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0, 0x02);
596 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
597 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
598 1.174 bouyer if (cl != 0x02) {
599 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
600 1.174 bouyer "got 0x%x != 0x02\n",
601 1.207 thorpej atac->atac_dev.dv_xname,
602 1.174 bouyer chp->ch_channel, cl),
603 1.174 bouyer DEBUG_PROBE);
604 1.125 mycroft ret_value &= ~0x02;
605 1.174 bouyer }
606 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
607 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0, 0x01);
608 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
609 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
610 1.174 bouyer if (cl != 0x01) {
611 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: "
612 1.174 bouyer "got 0x%x != 0x01\n",
613 1.207 thorpej atac->atac_dev.dv_xname,
614 1.174 bouyer chp->ch_channel, cl),
615 1.174 bouyer DEBUG_PROBE);
616 1.125 mycroft ret_value &= ~0x02;
617 1.174 bouyer }
618 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
619 1.205 thorpej wdr->cmd_iohs[wd_sector], 0, 0x01);
620 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
621 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
622 1.174 bouyer if (cl != 0x01) {
623 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: "
624 1.174 bouyer "got 0x%x != 0x01\n",
625 1.207 thorpej atac->atac_dev.dv_xname,
626 1.174 bouyer chp->ch_channel, cl),
627 1.174 bouyer DEBUG_PROBE);
628 1.125 mycroft ret_value &= ~0x02;
629 1.174 bouyer }
630 1.205 thorpej bus_space_write_1(wdr->cmd_iot,
631 1.205 thorpej wdr->cmd_iohs[wd_sector], 0, 0x02);
632 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
633 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
634 1.174 bouyer if (cl != 0x02) {
635 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: "
636 1.174 bouyer "got 0x%x != 0x02\n",
637 1.207 thorpej atac->atac_dev.dv_xname,
638 1.174 bouyer chp->ch_channel, cl),
639 1.174 bouyer DEBUG_PROBE);
640 1.125 mycroft ret_value &= ~0x02;
641 1.174 bouyer }
642 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
643 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
644 1.174 bouyer if (cl != 0x01) {
645 1.204 thorpej ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): "
646 1.174 bouyer "got 0x%x != 0x01\n",
647 1.207 thorpej atac->atac_dev.dv_xname,
648 1.174 bouyer chp->ch_channel, cl),
649 1.174 bouyer DEBUG_PROBE);
650 1.131 mycroft ret_value &= ~0x02;
651 1.174 bouyer }
652 1.125 mycroft }
653 1.137 bouyer
654 1.174 bouyer if (ret_value == 0) {
655 1.174 bouyer splx(s);
656 1.137 bouyer return 0;
657 1.174 bouyer }
658 1.62 bouyer }
659 1.31 bouyer
660 1.174 bouyer
661 1.181 bouyer #if 0 /* XXX this break some ATA or ATAPI devices */
662 1.174 bouyer /*
663 1.174 bouyer * reset bus. Also send an ATAPI_RESET to devices, in case there are
664 1.174 bouyer * ATAPI device out there which don't react to the bus reset
665 1.174 bouyer */
666 1.174 bouyer if (ret_value & 0x01) {
667 1.207 thorpej if (wdc->select)
668 1.174 bouyer wdc->select(chp,0);
669 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
670 1.174 bouyer 0, WDSD_IBM);
671 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0,
672 1.174 bouyer ATAPI_SOFT_RESET);
673 1.174 bouyer }
674 1.174 bouyer if (ret_value & 0x02) {
675 1.207 thorpej if (wdc->select)
676 1.174 bouyer wdc->select(chp,0);
677 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
678 1.174 bouyer 0, WDSD_IBM | 0x10);
679 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0,
680 1.174 bouyer ATAPI_SOFT_RESET);
681 1.174 bouyer }
682 1.156 bouyer
683 1.175 bouyer delay(5000);
684 1.181 bouyer #endif
685 1.175 bouyer
686 1.225 bouyer wdc->reset(chp, RESET_POLL);
687 1.137 bouyer DELAY(2000);
688 1.205 thorpej (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
689 1.205 thorpej bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
690 1.156 bouyer splx(s);
691 1.137 bouyer
692 1.137 bouyer ret_value = __wdcwait_reset(chp, ret_value, poll);
693 1.204 thorpej ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
694 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel,
695 1.137 bouyer ret_value), DEBUG_PROBE);
696 1.12 cgd
697 1.137 bouyer /* if reset failed, there's nothing here */
698 1.137 bouyer if (ret_value == 0)
699 1.137 bouyer return 0;
700 1.67 bouyer
701 1.12 cgd /*
702 1.167 thorpej * Test presence of drives. First test register signatures looking
703 1.167 thorpej * for ATAPI devices. If it's not an ATAPI and reset said there may
704 1.167 thorpej * be something here assume it's ATA or OLD. Ghost will be killed
705 1.167 thorpej * later in attach routine.
706 1.12 cgd */
707 1.232 bouyer for (drive = 0; drive < chp->ch_ndrive; drive++) {
708 1.137 bouyer if ((ret_value & (0x01 << drive)) == 0)
709 1.137 bouyer continue;
710 1.207 thorpej if (wdc->select)
711 1.169 thorpej wdc->select(chp,drive);
712 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
713 1.137 bouyer WDSD_IBM | (drive << 4));
714 1.137 bouyer delay(10); /* 400ns delay */
715 1.137 bouyer /* Save registers contents */
716 1.205 thorpej sc = bus_space_read_1(wdr->cmd_iot,
717 1.205 thorpej wdr->cmd_iohs[wd_seccnt], 0);
718 1.205 thorpej sn = bus_space_read_1(wdr->cmd_iot,
719 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
720 1.205 thorpej cl = bus_space_read_1(wdr->cmd_iot,
721 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
722 1.205 thorpej ch = bus_space_read_1(wdr->cmd_iot,
723 1.205 thorpej wdr->cmd_iohs[wd_cyl_hi], 0);
724 1.137 bouyer
725 1.204 thorpej ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
726 1.137 bouyer "cl=0x%x ch=0x%x\n",
727 1.207 thorpej atac->atac_dev.dv_xname,
728 1.169 thorpej chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
729 1.31 bouyer /*
730 1.137 bouyer * sc & sn are supposted to be 0x1 for ATAPI but in some cases
731 1.137 bouyer * we get wrong values here, so ignore it.
732 1.31 bouyer */
733 1.212 thorpej s = splbio();
734 1.137 bouyer if (cl == 0x14 && ch == 0xeb) {
735 1.137 bouyer chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
736 1.137 bouyer } else {
737 1.137 bouyer chp->ch_drive[drive].drive_flags |= DRIVE_ATA;
738 1.223 bouyer if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0)
739 1.137 bouyer chp->ch_drive[drive].drive_flags |= DRIVE_OLD;
740 1.137 bouyer }
741 1.212 thorpej splx(s);
742 1.31 bouyer }
743 1.219 perry return (ret_value);
744 1.137 bouyer }
745 1.31 bouyer
746 1.137 bouyer void
747 1.205 thorpej wdcattach(struct ata_channel *chp)
748 1.137 bouyer {
749 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
750 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
751 1.32 bouyer
752 1.232 bouyer KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3);
753 1.205 thorpej
754 1.191 mycroft /* default data transfer methods */
755 1.210 thorpej if (wdc->datain_pio == NULL)
756 1.191 mycroft wdc->datain_pio = wdc_datain_pio;
757 1.210 thorpej if (wdc->dataout_pio == NULL)
758 1.191 mycroft wdc->dataout_pio = wdc_dataout_pio;
759 1.225 bouyer /* default reset method */
760 1.225 bouyer if (wdc->reset == NULL)
761 1.225 bouyer wdc->reset = wdc_do_reset;
762 1.191 mycroft
763 1.137 bouyer /* initialise global data */
764 1.208 thorpej if (atac->atac_bustype_ata == NULL)
765 1.208 thorpej atac->atac_bustype_ata = &wdc_ata_bustype;
766 1.207 thorpej if (atac->atac_probe == NULL)
767 1.207 thorpej atac->atac_probe = wdc_drvprobe;
768 1.208 thorpej #if NATAPIBUS > 0
769 1.208 thorpej if (atac->atac_atapibus_attach == NULL)
770 1.208 thorpej atac->atac_atapibus_attach = wdc_atapibus_attach;
771 1.208 thorpej #endif
772 1.198 thorpej
773 1.210 thorpej ata_channel_attach(chp);
774 1.74 enami }
775 1.74 enami
776 1.163 thorpej int
777 1.163 thorpej wdcactivate(struct device *self, enum devact act)
778 1.137 bouyer {
779 1.207 thorpej struct atac_softc *atac = (struct atac_softc *) self;
780 1.137 bouyer int s, i, error = 0;
781 1.137 bouyer
782 1.137 bouyer s = splbio();
783 1.137 bouyer switch (act) {
784 1.137 bouyer case DVACT_ACTIVATE:
785 1.137 bouyer error = EOPNOTSUPP;
786 1.137 bouyer break;
787 1.137 bouyer
788 1.137 bouyer case DVACT_DEACTIVATE:
789 1.207 thorpej for (i = 0; i < atac->atac_nchannels; i++) {
790 1.207 thorpej error =
791 1.207 thorpej config_deactivate(atac->atac_channels[i]->atabus);
792 1.137 bouyer if (error)
793 1.137 bouyer break;
794 1.137 bouyer }
795 1.137 bouyer break;
796 1.137 bouyer }
797 1.137 bouyer splx(s);
798 1.137 bouyer return (error);
799 1.137 bouyer }
800 1.219 perry
801 1.137 bouyer int
802 1.163 thorpej wdcdetach(struct device *self, int flags)
803 1.137 bouyer {
804 1.207 thorpej struct atac_softc *atac = (struct atac_softc *) self;
805 1.205 thorpej struct ata_channel *chp;
806 1.207 thorpej struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
807 1.137 bouyer int i, error = 0;
808 1.137 bouyer
809 1.207 thorpej for (i = 0; i < atac->atac_nchannels; i++) {
810 1.207 thorpej chp = atac->atac_channels[i];
811 1.204 thorpej ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n",
812 1.207 thorpej atac->atac_dev.dv_xname, chp->atabus->dv_xname),
813 1.207 thorpej DEBUG_DETACH);
814 1.137 bouyer error = config_detach(chp->atabus, flags);
815 1.137 bouyer if (error)
816 1.137 bouyer break;
817 1.137 bouyer }
818 1.188 mycroft if (adapt->adapt_refcnt != 0) {
819 1.188 mycroft #ifdef DIAGNOSTIC
820 1.188 mycroft printf("wdcdetach: refcnt should be 0 here??\n");
821 1.188 mycroft #endif
822 1.207 thorpej (void) (*adapt->adapt_enable)(&atac->atac_dev, 0);
823 1.188 mycroft }
824 1.137 bouyer return (error);
825 1.137 bouyer }
826 1.137 bouyer
827 1.31 bouyer /* restart an interrupted I/O */
828 1.31 bouyer void
829 1.163 thorpej wdcrestart(void *v)
830 1.31 bouyer {
831 1.205 thorpej struct ata_channel *chp = v;
832 1.31 bouyer int s;
833 1.2 bouyer
834 1.31 bouyer s = splbio();
835 1.202 thorpej atastart(chp);
836 1.31 bouyer splx(s);
837 1.2 bouyer }
838 1.219 perry
839 1.2 bouyer
840 1.31 bouyer /*
841 1.31 bouyer * Interrupt routine for the controller. Acknowledge the interrupt, check for
842 1.31 bouyer * errors on the current operation, mark it done if necessary, and start the
843 1.31 bouyer * next request. Also check for a partially done transfer, and continue with
844 1.31 bouyer * the next chunk if so.
845 1.31 bouyer */
846 1.12 cgd int
847 1.163 thorpej wdcintr(void *arg)
848 1.12 cgd {
849 1.205 thorpej struct ata_channel *chp = arg;
850 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
851 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
852 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
853 1.165 thorpej struct ata_xfer *xfer;
854 1.76 bouyer int ret;
855 1.12 cgd
856 1.235 thorpej if (!device_is_active(&atac->atac_dev)) {
857 1.204 thorpej ATADEBUG_PRINT(("wdcintr: deactivated controller\n"),
858 1.80 enami DEBUG_INTR);
859 1.80 enami return (0);
860 1.80 enami }
861 1.205 thorpej if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) {
862 1.204 thorpej ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
863 1.113 bouyer /* try to clear the pending interrupt anyway */
864 1.205 thorpej (void)bus_space_read_1(wdr->cmd_iot,
865 1.205 thorpej wdr->cmd_iohs[wd_status], 0);
866 1.80 enami return (0);
867 1.31 bouyer }
868 1.12 cgd
869 1.204 thorpej ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
870 1.186 bouyer xfer = chp->ch_queue->active_xfer;
871 1.186 bouyer #ifdef DIAGNOSTIC
872 1.186 bouyer if (xfer == NULL)
873 1.186 bouyer panic("wdcintr: no xfer");
874 1.233 bouyer if (xfer->c_chp != chp) {
875 1.233 bouyer printf("channel %d expected %d\n", xfer->c_chp->ch_channel,
876 1.233 bouyer chp->ch_channel);
877 1.233 bouyer panic("wdcintr: wrong channel");
878 1.233 bouyer }
879 1.186 bouyer #endif
880 1.238 itohy #if NATA_DMA || NATA_PIOBM
881 1.205 thorpej if (chp->ch_flags & ATACH_DMA_WAIT) {
882 1.169 thorpej wdc->dma_status =
883 1.169 thorpej (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel,
884 1.185 bouyer xfer->c_drive, WDC_DMAEND_END);
885 1.169 thorpej if (wdc->dma_status & WDC_DMAST_NOIRQ) {
886 1.84 bouyer /* IRQ not for us, not detected by DMA engine */
887 1.84 bouyer return 0;
888 1.84 bouyer }
889 1.205 thorpej chp->ch_flags &= ~ATACH_DMA_WAIT;
890 1.84 bouyer }
891 1.238 itohy #endif
892 1.205 thorpej chp->ch_flags &= ~ATACH_IRQ_WAIT;
893 1.76 bouyer ret = xfer->c_intr(chp, xfer, 1);
894 1.76 bouyer if (ret == 0) /* irq was not for us, still waiting for irq */
895 1.205 thorpej chp->ch_flags |= ATACH_IRQ_WAIT;
896 1.76 bouyer return (ret);
897 1.12 cgd }
898 1.12 cgd
899 1.31 bouyer /* Put all disk in RESET state */
900 1.125 mycroft void
901 1.183 bouyer wdc_reset_drive(struct ata_drive_datas *drvp, int flags)
902 1.2 bouyer {
903 1.205 thorpej struct ata_channel *chp = drvp->chnl_softc;
904 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
905 1.207 thorpej
906 1.211 thorpej ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n",
907 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive),
908 1.34 bouyer DEBUG_FUNCS);
909 1.182 bouyer
910 1.211 thorpej ata_reset_channel(chp, flags);
911 1.182 bouyer }
912 1.182 bouyer
913 1.183 bouyer void
914 1.205 thorpej wdc_reset_channel(struct ata_channel *chp, int flags)
915 1.182 bouyer {
916 1.186 bouyer TAILQ_HEAD(, ata_xfer) reset_xfer;
917 1.183 bouyer struct ata_xfer *xfer, *next_xfer;
918 1.238 itohy #if NATA_DMA || NATA_PIOBM
919 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
920 1.238 itohy #endif
921 1.182 bouyer
922 1.186 bouyer TAILQ_INIT(&reset_xfer);
923 1.184 bouyer
924 1.211 thorpej chp->ch_flags &= ~ATACH_IRQ_WAIT;
925 1.184 bouyer
926 1.186 bouyer /*
927 1.186 bouyer * if the current command if on an ATAPI device, issue a
928 1.186 bouyer * ATAPI_SOFT_RESET
929 1.186 bouyer */
930 1.186 bouyer xfer = chp->ch_queue->active_xfer;
931 1.186 bouyer if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) {
932 1.186 bouyer wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET);
933 1.186 bouyer if (flags & AT_WAIT)
934 1.186 bouyer tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1);
935 1.219 perry else
936 1.186 bouyer delay(1000);
937 1.186 bouyer }
938 1.186 bouyer
939 1.184 bouyer /* reset the channel */
940 1.186 bouyer if (flags & AT_WAIT)
941 1.186 bouyer (void) wdcreset(chp, RESET_SLEEP);
942 1.186 bouyer else
943 1.184 bouyer (void) wdcreset(chp, RESET_POLL);
944 1.184 bouyer
945 1.184 bouyer /*
946 1.186 bouyer * wait a bit after reset; in case the DMA engines needs some time
947 1.184 bouyer * to recover.
948 1.184 bouyer */
949 1.184 bouyer if (flags & AT_WAIT)
950 1.186 bouyer tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1);
951 1.219 perry else
952 1.184 bouyer delay(1000);
953 1.182 bouyer /*
954 1.182 bouyer * look for pending xfers. If we have a shared queue, we'll also reset
955 1.182 bouyer * the other channel if the current xfer is running on it.
956 1.184 bouyer * Then we'll dequeue only the xfers for this channel.
957 1.182 bouyer */
958 1.182 bouyer if ((flags & AT_RST_NOCMD) == 0) {
959 1.186 bouyer /*
960 1.186 bouyer * move all xfers queued for this channel to the reset queue,
961 1.186 bouyer * and then process the current xfer and then the reset queue.
962 1.186 bouyer * We have to use a temporary queue because c_kill_xfer()
963 1.186 bouyer * may requeue commands.
964 1.186 bouyer */
965 1.186 bouyer for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
966 1.186 bouyer xfer != NULL; xfer = next_xfer) {
967 1.186 bouyer next_xfer = TAILQ_NEXT(xfer, c_xferchain);
968 1.186 bouyer if (xfer->c_chp != chp)
969 1.186 bouyer continue;
970 1.186 bouyer TAILQ_REMOVE(&chp->ch_queue->queue_xfer,
971 1.186 bouyer xfer, c_xferchain);
972 1.186 bouyer TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain);
973 1.186 bouyer }
974 1.186 bouyer xfer = chp->ch_queue->active_xfer;
975 1.184 bouyer if (xfer) {
976 1.184 bouyer if (xfer->c_chp != chp)
977 1.211 thorpej ata_reset_channel(xfer->c_chp, flags);
978 1.184 bouyer else {
979 1.186 bouyer callout_stop(&chp->ch_callout);
980 1.238 itohy #if NATA_DMA || NATA_PIOBM
981 1.184 bouyer /*
982 1.184 bouyer * If we're waiting for DMA, stop the
983 1.184 bouyer * DMA engine
984 1.184 bouyer */
985 1.205 thorpej if (chp->ch_flags & ATACH_DMA_WAIT) {
986 1.207 thorpej (*wdc->dma_finish)(
987 1.207 thorpej wdc->dma_arg,
988 1.184 bouyer chp->ch_channel,
989 1.184 bouyer xfer->c_drive,
990 1.185 bouyer WDC_DMAEND_ABRT_QUIET);
991 1.205 thorpej chp->ch_flags &= ~ATACH_DMA_WAIT;
992 1.184 bouyer }
993 1.238 itohy #endif
994 1.186 bouyer chp->ch_queue->active_xfer = NULL;
995 1.186 bouyer if ((flags & AT_RST_EMERG) == 0)
996 1.186 bouyer xfer->c_kill_xfer(
997 1.186 bouyer chp, xfer, KILL_RESET);
998 1.184 bouyer }
999 1.184 bouyer }
1000 1.186 bouyer
1001 1.186 bouyer for (xfer = TAILQ_FIRST(&reset_xfer);
1002 1.183 bouyer xfer != NULL; xfer = next_xfer) {
1003 1.183 bouyer next_xfer = TAILQ_NEXT(xfer, c_xferchain);
1004 1.186 bouyer TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain);
1005 1.182 bouyer if ((flags & AT_RST_EMERG) == 0)
1006 1.182 bouyer xfer->c_kill_xfer(chp, xfer, KILL_RESET);
1007 1.182 bouyer }
1008 1.182 bouyer }
1009 1.31 bouyer }
1010 1.12 cgd
1011 1.213 thorpej static int
1012 1.205 thorpej wdcreset(struct ata_channel *chp, int poll)
1013 1.31 bouyer {
1014 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1015 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1016 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1017 1.31 bouyer int drv_mask1, drv_mask2;
1018 1.225 bouyer
1019 1.225 bouyer wdc->reset(chp, poll);
1020 1.225 bouyer
1021 1.225 bouyer drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
1022 1.225 bouyer drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
1023 1.225 bouyer drv_mask2 = __wdcwait_reset(chp, drv_mask1,
1024 1.225 bouyer (poll == RESET_SLEEP) ? 0 : 1);
1025 1.225 bouyer if (drv_mask2 != drv_mask1) {
1026 1.225 bouyer printf("%s channel %d: reset failed for",
1027 1.225 bouyer atac->atac_dev.dv_xname, chp->ch_channel);
1028 1.225 bouyer if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
1029 1.225 bouyer printf(" drive 0");
1030 1.225 bouyer if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
1031 1.225 bouyer printf(" drive 1");
1032 1.225 bouyer printf("\n");
1033 1.225 bouyer }
1034 1.225 bouyer bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
1035 1.225 bouyer return (drv_mask1 != drv_mask2) ? 1 : 0;
1036 1.225 bouyer }
1037 1.225 bouyer
1038 1.225 bouyer void
1039 1.225 bouyer wdc_do_reset(struct ata_channel *chp, int poll)
1040 1.225 bouyer {
1041 1.225 bouyer struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1042 1.225 bouyer struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1043 1.156 bouyer int s = 0;
1044 1.2 bouyer
1045 1.225 bouyer if (poll != RESET_SLEEP)
1046 1.225 bouyer s = splbio();
1047 1.203 thorpej if (wdc->select)
1048 1.169 thorpej wdc->select(chp,0);
1049 1.157 fvdl /* master */
1050 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
1051 1.131 mycroft delay(10); /* 400ns delay */
1052 1.225 bouyer /* assert SRST, wait for reset to complete */
1053 1.205 thorpej bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
1054 1.131 mycroft WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
1055 1.131 mycroft delay(2000);
1056 1.205 thorpej (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
1057 1.205 thorpej bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
1058 1.137 bouyer WDCTL_4BIT | WDCTL_IDS);
1059 1.131 mycroft delay(10); /* 400ns delay */
1060 1.156 bouyer if (poll != RESET_SLEEP) {
1061 1.233 bouyer /* ACK interrupt in case there is one pending left */
1062 1.203 thorpej if (wdc->irqack)
1063 1.169 thorpej wdc->irqack(chp);
1064 1.156 bouyer splx(s);
1065 1.156 bouyer }
1066 1.31 bouyer }
1067 1.31 bouyer
1068 1.31 bouyer static int
1069 1.205 thorpej __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll)
1070 1.31 bouyer {
1071 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1072 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1073 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1074 1.137 bouyer int timeout, nloop;
1075 1.149 bouyer u_int8_t st0 = 0, st1 = 0;
1076 1.204 thorpej #ifdef ATADEBUG
1077 1.146 christos u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0;
1078 1.146 christos u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0;
1079 1.70 bouyer #endif
1080 1.137 bouyer
1081 1.137 bouyer if (poll)
1082 1.137 bouyer nloop = WDCNDELAY_RST;
1083 1.137 bouyer else
1084 1.137 bouyer nloop = WDC_RESET_WAIT * hz / 1000;
1085 1.31 bouyer /* wait for BSY to deassert */
1086 1.137 bouyer for (timeout = 0; timeout < nloop; timeout++) {
1087 1.174 bouyer if ((drv_mask & 0x01) != 0) {
1088 1.236 bouyer if (wdc->select)
1089 1.174 bouyer wdc->select(chp,0);
1090 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
1091 1.174 bouyer 0, WDSD_IBM); /* master */
1092 1.174 bouyer delay(10);
1093 1.205 thorpej st0 = bus_space_read_1(wdr->cmd_iot,
1094 1.205 thorpej wdr->cmd_iohs[wd_status], 0);
1095 1.204 thorpej #ifdef ATADEBUG
1096 1.205 thorpej sc0 = bus_space_read_1(wdr->cmd_iot,
1097 1.205 thorpej wdr->cmd_iohs[wd_seccnt], 0);
1098 1.205 thorpej sn0 = bus_space_read_1(wdr->cmd_iot,
1099 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
1100 1.205 thorpej cl0 = bus_space_read_1(wdr->cmd_iot,
1101 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
1102 1.205 thorpej ch0 = bus_space_read_1(wdr->cmd_iot,
1103 1.205 thorpej wdr->cmd_iohs[wd_cyl_hi], 0);
1104 1.70 bouyer #endif
1105 1.174 bouyer }
1106 1.174 bouyer if ((drv_mask & 0x02) != 0) {
1107 1.236 bouyer if (wdc->select)
1108 1.174 bouyer wdc->select(chp,1);
1109 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
1110 1.174 bouyer 0, WDSD_IBM | 0x10); /* slave */
1111 1.174 bouyer delay(10);
1112 1.205 thorpej st1 = bus_space_read_1(wdr->cmd_iot,
1113 1.205 thorpej wdr->cmd_iohs[wd_status], 0);
1114 1.204 thorpej #ifdef ATADEBUG
1115 1.205 thorpej sc1 = bus_space_read_1(wdr->cmd_iot,
1116 1.205 thorpej wdr->cmd_iohs[wd_seccnt], 0);
1117 1.205 thorpej sn1 = bus_space_read_1(wdr->cmd_iot,
1118 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
1119 1.205 thorpej cl1 = bus_space_read_1(wdr->cmd_iot,
1120 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
1121 1.205 thorpej ch1 = bus_space_read_1(wdr->cmd_iot,
1122 1.205 thorpej wdr->cmd_iohs[wd_cyl_hi], 0);
1123 1.70 bouyer #endif
1124 1.174 bouyer }
1125 1.31 bouyer
1126 1.31 bouyer if ((drv_mask & 0x01) == 0) {
1127 1.31 bouyer /* no master */
1128 1.31 bouyer if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
1129 1.31 bouyer /* No master, slave is ready, it's done */
1130 1.65 bouyer goto end;
1131 1.31 bouyer }
1132 1.231 bouyer if ((drv_mask & 0x02) == 0) {
1133 1.231 bouyer /* No master, no slave: it's done */
1134 1.231 bouyer goto end;
1135 1.231 bouyer }
1136 1.31 bouyer } else if ((drv_mask & 0x02) == 0) {
1137 1.31 bouyer /* no slave */
1138 1.31 bouyer if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
1139 1.31 bouyer /* No slave, master is ready, it's done */
1140 1.65 bouyer goto end;
1141 1.31 bouyer }
1142 1.2 bouyer } else {
1143 1.31 bouyer /* Wait for both master and slave to be ready */
1144 1.31 bouyer if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
1145 1.65 bouyer goto end;
1146 1.2 bouyer }
1147 1.2 bouyer }
1148 1.137 bouyer if (poll)
1149 1.137 bouyer delay(WDCDELAY);
1150 1.137 bouyer else
1151 1.137 bouyer tsleep(&nloop, PRIBIO, "atarst", 1);
1152 1.2 bouyer }
1153 1.116 wiz /* Reset timed out. Maybe it's because drv_mask was not right */
1154 1.31 bouyer if (st0 & WDCS_BSY)
1155 1.31 bouyer drv_mask &= ~0x01;
1156 1.31 bouyer if (st1 & WDCS_BSY)
1157 1.31 bouyer drv_mask &= ~0x02;
1158 1.65 bouyer end:
1159 1.204 thorpej ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x "
1160 1.70 bouyer "cl=0x%x ch=0x%x\n",
1161 1.207 thorpej atac->atac_dev.dv_xname,
1162 1.169 thorpej chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE);
1163 1.204 thorpej ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x "
1164 1.70 bouyer "cl=0x%x ch=0x%x\n",
1165 1.207 thorpej atac->atac_dev.dv_xname,
1166 1.169 thorpej chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE);
1167 1.70 bouyer
1168 1.204 thorpej ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n",
1169 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel,
1170 1.149 bouyer st0, st1), DEBUG_PROBE);
1171 1.65 bouyer
1172 1.31 bouyer return drv_mask;
1173 1.2 bouyer }
1174 1.2 bouyer
1175 1.2 bouyer /*
1176 1.31 bouyer * Wait for a drive to be !BSY, and have mask in its status register.
1177 1.31 bouyer * return -1 for a timeout after "timeout" ms.
1178 1.2 bouyer */
1179 1.167 thorpej static int
1180 1.205 thorpej __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout)
1181 1.2 bouyer {
1182 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1183 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1184 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1185 1.31 bouyer u_char status;
1186 1.222 christos int xtime = 0;
1187 1.60 abs
1188 1.207 thorpej ATADEBUG_PRINT(("__wdcwait %s:%d\n",
1189 1.207 thorpej atac->atac_dev.dv_xname,
1190 1.169 thorpej chp->ch_channel), DEBUG_STATUS);
1191 1.31 bouyer chp->ch_error = 0;
1192 1.31 bouyer
1193 1.31 bouyer timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1194 1.2 bouyer
1195 1.31 bouyer for (;;) {
1196 1.31 bouyer chp->ch_status = status =
1197 1.205 thorpej bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0);
1198 1.131 mycroft if ((status & (WDCS_BSY | mask)) == bits)
1199 1.31 bouyer break;
1200 1.222 christos if (++xtime > timeout) {
1201 1.204 thorpej ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), "
1202 1.87 bouyer "status %x error %x (mask 0x%x bits 0x%x)\n",
1203 1.222 christos xtime, status,
1204 1.205 thorpej bus_space_read_1(wdr->cmd_iot,
1205 1.205 thorpej wdr->cmd_iohs[wd_error], 0), mask, bits),
1206 1.87 bouyer DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY);
1207 1.137 bouyer return(WDCWAIT_TOUT);
1208 1.31 bouyer }
1209 1.31 bouyer delay(WDCDELAY);
1210 1.2 bouyer }
1211 1.204 thorpej #ifdef ATADEBUG
1212 1.222 christos if (xtime > 0 && (atadebug_mask & DEBUG_DELAY))
1213 1.222 christos printf("__wdcwait: did busy-wait, time=%d\n", xtime);
1214 1.87 bouyer #endif
1215 1.31 bouyer if (status & WDCS_ERR)
1216 1.205 thorpej chp->ch_error = bus_space_read_1(wdr->cmd_iot,
1217 1.205 thorpej wdr->cmd_iohs[wd_error], 0);
1218 1.31 bouyer #ifdef WDCNDELAY_DEBUG
1219 1.31 bouyer /* After autoconfig, there should be no long delays. */
1220 1.222 christos if (!cold && xtime > WDCNDELAY_DEBUG) {
1221 1.186 bouyer struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1222 1.31 bouyer if (xfer == NULL)
1223 1.31 bouyer printf("%s channel %d: warning: busy-wait took %dus\n",
1224 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel,
1225 1.222 christos WDCDELAY * xtime);
1226 1.219 perry else
1227 1.31 bouyer printf("%s:%d:%d: warning: busy-wait took %dus\n",
1228 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel,
1229 1.237 christos xfer->c_drive,
1230 1.222 christos WDCDELAY * xtime);
1231 1.2 bouyer }
1232 1.2 bouyer #endif
1233 1.137 bouyer return(WDCWAIT_OK);
1234 1.137 bouyer }
1235 1.137 bouyer
1236 1.137 bouyer /*
1237 1.137 bouyer * Call __wdcwait(), polling using tsleep() or waking up the kernel
1238 1.137 bouyer * thread if possible
1239 1.137 bouyer */
1240 1.137 bouyer int
1241 1.205 thorpej wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags)
1242 1.137 bouyer {
1243 1.137 bouyer int error, i, timeout_hz = mstohz(timeout);
1244 1.137 bouyer
1245 1.137 bouyer if (timeout_hz == 0 ||
1246 1.137 bouyer (flags & (AT_WAIT | AT_POLL)) == AT_POLL)
1247 1.137 bouyer error = __wdcwait(chp, mask, bits, timeout);
1248 1.137 bouyer else {
1249 1.137 bouyer error = __wdcwait(chp, mask, bits, WDCDELAY_POLL);
1250 1.137 bouyer if (error != 0) {
1251 1.205 thorpej if ((chp->ch_flags & ATACH_TH_RUN) ||
1252 1.147 bouyer (flags & AT_WAIT)) {
1253 1.137 bouyer /*
1254 1.147 bouyer * we're running in the channel thread
1255 1.147 bouyer * or some userland thread context
1256 1.137 bouyer */
1257 1.137 bouyer for (i = 0; i < timeout_hz; i++) {
1258 1.137 bouyer if (__wdcwait(chp, mask, bits,
1259 1.137 bouyer WDCDELAY_POLL) == 0) {
1260 1.137 bouyer error = 0;
1261 1.137 bouyer break;
1262 1.137 bouyer }
1263 1.137 bouyer tsleep(&chp, PRIBIO, "atapoll", 1);
1264 1.137 bouyer }
1265 1.137 bouyer } else {
1266 1.137 bouyer /*
1267 1.137 bouyer * we're probably in interrupt context,
1268 1.137 bouyer * ask the thread to come back here
1269 1.137 bouyer */
1270 1.147 bouyer #ifdef DIAGNOSTIC
1271 1.148 bouyer if (chp->ch_queue->queue_freeze > 0)
1272 1.148 bouyer panic("wdcwait: queue_freeze");
1273 1.147 bouyer #endif
1274 1.148 bouyer chp->ch_queue->queue_freeze++;
1275 1.170 thorpej wakeup(&chp->ch_thread);
1276 1.137 bouyer return(WDCWAIT_THR);
1277 1.137 bouyer }
1278 1.137 bouyer }
1279 1.137 bouyer }
1280 1.163 thorpej return (error);
1281 1.2 bouyer }
1282 1.2 bouyer
1283 1.137 bouyer
1284 1.238 itohy #if NATA_DMA
1285 1.84 bouyer /*
1286 1.84 bouyer * Busy-wait for DMA to complete
1287 1.84 bouyer */
1288 1.84 bouyer int
1289 1.205 thorpej wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout)
1290 1.84 bouyer {
1291 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1292 1.222 christos int xtime;
1293 1.169 thorpej
1294 1.222 christos for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) {
1295 1.169 thorpej wdc->dma_status =
1296 1.169 thorpej (*wdc->dma_finish)(wdc->dma_arg,
1297 1.185 bouyer chp->ch_channel, xfer->c_drive, WDC_DMAEND_END);
1298 1.169 thorpej if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
1299 1.84 bouyer return 0;
1300 1.84 bouyer delay(WDCDELAY);
1301 1.84 bouyer }
1302 1.84 bouyer /* timeout, force a DMA halt */
1303 1.169 thorpej wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg,
1304 1.185 bouyer chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT);
1305 1.84 bouyer return 1;
1306 1.84 bouyer }
1307 1.238 itohy #endif
1308 1.84 bouyer
1309 1.31 bouyer void
1310 1.163 thorpej wdctimeout(void *arg)
1311 1.2 bouyer {
1312 1.205 thorpej struct ata_channel *chp = (struct ata_channel *)arg;
1313 1.238 itohy #if NATA_DMA || NATA_PIOBM
1314 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1315 1.238 itohy #endif
1316 1.186 bouyer struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1317 1.31 bouyer int s;
1318 1.2 bouyer
1319 1.204 thorpej ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
1320 1.31 bouyer
1321 1.31 bouyer s = splbio();
1322 1.205 thorpej if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
1323 1.31 bouyer __wdcerror(chp, "lost interrupt");
1324 1.88 mrg printf("\ttype: %s tc_bcount: %d tc_skip: %d\n",
1325 1.88 mrg (xfer->c_flags & C_ATAPI) ? "atapi" : "ata",
1326 1.88 mrg xfer->c_bcount,
1327 1.88 mrg xfer->c_skip);
1328 1.238 itohy #if NATA_DMA || NATA_PIOBM
1329 1.205 thorpej if (chp->ch_flags & ATACH_DMA_WAIT) {
1330 1.169 thorpej wdc->dma_status =
1331 1.169 thorpej (*wdc->dma_finish)(wdc->dma_arg,
1332 1.185 bouyer chp->ch_channel, xfer->c_drive,
1333 1.185 bouyer WDC_DMAEND_ABRT);
1334 1.205 thorpej chp->ch_flags &= ~ATACH_DMA_WAIT;
1335 1.84 bouyer }
1336 1.238 itohy #endif
1337 1.31 bouyer /*
1338 1.119 drochner * Call the interrupt routine. If we just missed an interrupt,
1339 1.31 bouyer * it will do what's needed. Else, it will take the needed
1340 1.31 bouyer * action (reset the device).
1341 1.70 bouyer * Before that we need to reinstall the timeout callback,
1342 1.70 bouyer * in case it will miss another irq while in this transfer
1343 1.70 bouyer * We arbitray chose it to be 1s
1344 1.31 bouyer */
1345 1.81 thorpej callout_reset(&chp->ch_callout, hz, wdctimeout, chp);
1346 1.31 bouyer xfer->c_flags |= C_TIMEOU;
1347 1.205 thorpej chp->ch_flags &= ~ATACH_IRQ_WAIT;
1348 1.66 bouyer xfer->c_intr(chp, xfer, 1);
1349 1.31 bouyer } else
1350 1.31 bouyer __wdcerror(chp, "missing untimeout");
1351 1.31 bouyer splx(s);
1352 1.2 bouyer }
1353 1.2 bouyer
1354 1.2 bouyer int
1355 1.192 thorpej wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
1356 1.31 bouyer {
1357 1.205 thorpej struct ata_channel *chp = drvp->chnl_softc;
1358 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1359 1.165 thorpej struct ata_xfer *xfer;
1360 1.31 bouyer int s, ret;
1361 1.2 bouyer
1362 1.204 thorpej ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
1363 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive),
1364 1.34 bouyer DEBUG_FUNCS);
1365 1.2 bouyer
1366 1.31 bouyer /* set up an xfer and queue. Wait for completion */
1367 1.198 thorpej xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
1368 1.198 thorpej ATAXF_NOSLEEP);
1369 1.31 bouyer if (xfer == NULL) {
1370 1.193 thorpej return ATACMD_TRY_AGAIN;
1371 1.31 bouyer }
1372 1.2 bouyer
1373 1.207 thorpej if (atac->atac_cap & ATAC_CAP_NOIRQ)
1374 1.192 thorpej ata_c->flags |= AT_POLL;
1375 1.192 thorpej if (ata_c->flags & AT_POLL)
1376 1.31 bouyer xfer->c_flags |= C_POLL;
1377 1.217 bouyer if (ata_c->flags & AT_WAIT)
1378 1.217 bouyer xfer->c_flags |= C_WAIT;
1379 1.165 thorpej xfer->c_drive = drvp->drive;
1380 1.192 thorpej xfer->c_databuf = ata_c->data;
1381 1.192 thorpej xfer->c_bcount = ata_c->bcount;
1382 1.192 thorpej xfer->c_cmd = ata_c;
1383 1.31 bouyer xfer->c_start = __wdccommand_start;
1384 1.31 bouyer xfer->c_intr = __wdccommand_intr;
1385 1.182 bouyer xfer->c_kill_xfer = __wdccommand_kill_xfer;
1386 1.2 bouyer
1387 1.31 bouyer s = splbio();
1388 1.201 thorpej ata_exec_xfer(chp, xfer);
1389 1.31 bouyer #ifdef DIAGNOSTIC
1390 1.192 thorpej if ((ata_c->flags & AT_POLL) != 0 &&
1391 1.192 thorpej (ata_c->flags & AT_DONE) == 0)
1392 1.118 provos panic("wdc_exec_command: polled command not done");
1393 1.2 bouyer #endif
1394 1.192 thorpej if (ata_c->flags & AT_DONE) {
1395 1.193 thorpej ret = ATACMD_COMPLETE;
1396 1.31 bouyer } else {
1397 1.192 thorpej if (ata_c->flags & AT_WAIT) {
1398 1.192 thorpej while ((ata_c->flags & AT_DONE) == 0) {
1399 1.192 thorpej tsleep(ata_c, PRIBIO, "wdccmd", 0);
1400 1.69 bouyer }
1401 1.193 thorpej ret = ATACMD_COMPLETE;
1402 1.31 bouyer } else {
1403 1.193 thorpej ret = ATACMD_QUEUED;
1404 1.2 bouyer }
1405 1.2 bouyer }
1406 1.31 bouyer splx(s);
1407 1.31 bouyer return ret;
1408 1.2 bouyer }
1409 1.2 bouyer
1410 1.167 thorpej static void
1411 1.205 thorpej __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer)
1412 1.219 perry {
1413 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1414 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1415 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1416 1.165 thorpej int drive = xfer->c_drive;
1417 1.230 bouyer int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1418 1.192 thorpej struct ata_command *ata_c = xfer->c_cmd;
1419 1.31 bouyer
1420 1.204 thorpej ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
1421 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1422 1.34 bouyer DEBUG_FUNCS);
1423 1.31 bouyer
1424 1.203 thorpej if (wdc->select)
1425 1.169 thorpej wdc->select(chp,drive);
1426 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
1427 1.31 bouyer WDSD_IBM | (drive << 4));
1428 1.192 thorpej switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1429 1.230 bouyer ata_c->r_st_bmask, ata_c->timeout, wait_flags)) {
1430 1.137 bouyer case WDCWAIT_OK:
1431 1.137 bouyer break;
1432 1.137 bouyer case WDCWAIT_TOUT:
1433 1.192 thorpej ata_c->flags |= AT_TIMEOU;
1434 1.31 bouyer __wdccommand_done(chp, xfer);
1435 1.53 bouyer return;
1436 1.137 bouyer case WDCWAIT_THR:
1437 1.137 bouyer return;
1438 1.31 bouyer }
1439 1.192 thorpej if (ata_c->flags & AT_POLL) {
1440 1.135 bouyer /* polled command, disable interrupts */
1441 1.205 thorpej bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
1442 1.135 bouyer WDCTL_4BIT | WDCTL_IDS);
1443 1.135 bouyer }
1444 1.192 thorpej wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head,
1445 1.192 thorpej ata_c->r_sector, ata_c->r_count, ata_c->r_features);
1446 1.139 bouyer
1447 1.192 thorpej if ((ata_c->flags & AT_POLL) == 0) {
1448 1.205 thorpej chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1449 1.192 thorpej callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz,
1450 1.81 thorpej wdctimeout, chp);
1451 1.31 bouyer return;
1452 1.2 bouyer }
1453 1.2 bouyer /*
1454 1.31 bouyer * Polled command. Wait for drive ready or drq. Done in intr().
1455 1.31 bouyer * Wait for at last 400ns for status bit to be valid.
1456 1.2 bouyer */
1457 1.134 mycroft delay(10); /* 400ns delay */
1458 1.66 bouyer __wdccommand_intr(chp, xfer, 0);
1459 1.2 bouyer }
1460 1.2 bouyer
1461 1.167 thorpej static int
1462 1.205 thorpej __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1463 1.2 bouyer {
1464 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1465 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1466 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1467 1.192 thorpej struct ata_command *ata_c = xfer->c_cmd;
1468 1.192 thorpej int bcount = ata_c->bcount;
1469 1.192 thorpej char *data = ata_c->data;
1470 1.137 bouyer int wflags;
1471 1.226 bouyer int drive_flags;
1472 1.226 bouyer
1473 1.226 bouyer if (ata_c->r_command == WDCC_IDENTIFY ||
1474 1.226 bouyer ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
1475 1.226 bouyer /*
1476 1.226 bouyer * The IDENTIFY data has been designed as an array of
1477 1.226 bouyer * u_int16_t, so we can byteswap it on the fly.
1478 1.226 bouyer * Historically it's what we have always done so keeping it
1479 1.226 bouyer * here ensure binary backward compatibility.
1480 1.226 bouyer */
1481 1.229 tacha drive_flags = DRIVE_NOSTREAM |
1482 1.229 tacha chp->ch_drive[xfer->c_drive].drive_flags;
1483 1.226 bouyer } else {
1484 1.226 bouyer /*
1485 1.226 bouyer * Other data structure are opaque and should be transfered
1486 1.226 bouyer * as is.
1487 1.226 bouyer */
1488 1.226 bouyer drive_flags = chp->ch_drive[xfer->c_drive].drive_flags;
1489 1.226 bouyer }
1490 1.137 bouyer
1491 1.192 thorpej if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) {
1492 1.137 bouyer /* both wait and poll, we can tsleep here */
1493 1.147 bouyer wflags = AT_WAIT | AT_POLL;
1494 1.137 bouyer } else {
1495 1.137 bouyer wflags = AT_POLL;
1496 1.137 bouyer }
1497 1.31 bouyer
1498 1.163 thorpej again:
1499 1.204 thorpej ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
1500 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive),
1501 1.165 thorpej DEBUG_INTR);
1502 1.137 bouyer /*
1503 1.137 bouyer * after a ATAPI_SOFT_RESET, the device will have released the bus.
1504 1.137 bouyer * Reselect again, it doesn't hurt for others commands, and the time
1505 1.137 bouyer * penalty for the extra regiter write is acceptable,
1506 1.137 bouyer * wdc_exec_command() isn't called often (mosly for autoconfig)
1507 1.137 bouyer */
1508 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
1509 1.165 thorpej WDSD_IBM | (xfer->c_drive << 4));
1510 1.192 thorpej if ((ata_c->flags & AT_XFDONE) != 0) {
1511 1.114 bouyer /*
1512 1.114 bouyer * We have completed a data xfer. The drive should now be
1513 1.114 bouyer * in its initial state
1514 1.114 bouyer */
1515 1.192 thorpej if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1516 1.192 thorpej ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0,
1517 1.137 bouyer wflags) == WDCWAIT_TOUT) {
1518 1.219 perry if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1519 1.114 bouyer return 0; /* IRQ was not for us */
1520 1.192 thorpej ata_c->flags |= AT_TIMEOU;
1521 1.114 bouyer }
1522 1.131 mycroft goto out;
1523 1.114 bouyer }
1524 1.192 thorpej if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask,
1525 1.192 thorpej (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1526 1.219 perry if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1527 1.63 bouyer return 0; /* IRQ was not for us */
1528 1.192 thorpej ata_c->flags |= AT_TIMEOU;
1529 1.131 mycroft goto out;
1530 1.2 bouyer }
1531 1.203 thorpej if (wdc->irqack)
1532 1.169 thorpej wdc->irqack(chp);
1533 1.192 thorpej if (ata_c->flags & AT_READ) {
1534 1.131 mycroft if ((chp->ch_status & WDCS_DRQ) == 0) {
1535 1.192 thorpej ata_c->flags |= AT_TIMEOU;
1536 1.131 mycroft goto out;
1537 1.131 mycroft }
1538 1.226 bouyer wdc->datain_pio(chp, drive_flags, data, bcount);
1539 1.114 bouyer /* at this point the drive should be in its initial state */
1540 1.192 thorpej ata_c->flags |= AT_XFDONE;
1541 1.234 bouyer /*
1542 1.234 bouyer * XXX checking the status register again here cause some
1543 1.234 bouyer * hardware to timeout.
1544 1.234 bouyer */
1545 1.192 thorpej } else if (ata_c->flags & AT_WRITE) {
1546 1.131 mycroft if ((chp->ch_status & WDCS_DRQ) == 0) {
1547 1.192 thorpej ata_c->flags |= AT_TIMEOU;
1548 1.131 mycroft goto out;
1549 1.131 mycroft }
1550 1.226 bouyer wdc->dataout_pio(chp, drive_flags, data, bcount);
1551 1.192 thorpej ata_c->flags |= AT_XFDONE;
1552 1.192 thorpej if ((ata_c->flags & AT_POLL) == 0) {
1553 1.205 thorpej chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1554 1.114 bouyer callout_reset(&chp->ch_callout,
1555 1.243 bouyer mstohz(ata_c->timeout), wdctimeout, chp);
1556 1.114 bouyer return 1;
1557 1.114 bouyer } else {
1558 1.114 bouyer goto again;
1559 1.114 bouyer }
1560 1.2 bouyer }
1561 1.163 thorpej out:
1562 1.31 bouyer __wdccommand_done(chp, xfer);
1563 1.31 bouyer return 1;
1564 1.2 bouyer }
1565 1.2 bouyer
1566 1.167 thorpej static void
1567 1.205 thorpej __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer)
1568 1.2 bouyer {
1569 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1570 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1571 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1572 1.192 thorpej struct ata_command *ata_c = xfer->c_cmd;
1573 1.2 bouyer
1574 1.233 bouyer ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n",
1575 1.233 bouyer atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive,
1576 1.233 bouyer ata_c->flags), DEBUG_FUNCS);
1577 1.70 bouyer
1578 1.70 bouyer
1579 1.31 bouyer if (chp->ch_status & WDCS_DWF)
1580 1.192 thorpej ata_c->flags |= AT_DF;
1581 1.31 bouyer if (chp->ch_status & WDCS_ERR) {
1582 1.192 thorpej ata_c->flags |= AT_ERROR;
1583 1.192 thorpej ata_c->r_error = chp->ch_error;
1584 1.31 bouyer }
1585 1.192 thorpej if ((ata_c->flags & AT_READREG) != 0 &&
1586 1.235 thorpej device_is_active(&atac->atac_dev) &&
1587 1.192 thorpej (ata_c->flags & (AT_ERROR | AT_DF)) == 0) {
1588 1.205 thorpej ata_c->r_head = bus_space_read_1(wdr->cmd_iot,
1589 1.205 thorpej wdr->cmd_iohs[wd_sdh], 0);
1590 1.205 thorpej ata_c->r_count = bus_space_read_1(wdr->cmd_iot,
1591 1.205 thorpej wdr->cmd_iohs[wd_seccnt], 0);
1592 1.205 thorpej ata_c->r_sector = bus_space_read_1(wdr->cmd_iot,
1593 1.205 thorpej wdr->cmd_iohs[wd_sector], 0);
1594 1.221 fvdl ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot,
1595 1.221 fvdl wdr->cmd_iohs[wd_cyl_hi], 0) << 8;
1596 1.205 thorpej ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot,
1597 1.205 thorpej wdr->cmd_iohs[wd_cyl_lo], 0);
1598 1.205 thorpej ata_c->r_error = bus_space_read_1(wdr->cmd_iot,
1599 1.205 thorpej wdr->cmd_iohs[wd_error], 0);
1600 1.205 thorpej ata_c->r_features = bus_space_read_1(wdr->cmd_iot,
1601 1.205 thorpej wdr->cmd_iohs[wd_features], 0);
1602 1.135 bouyer }
1603 1.186 bouyer callout_stop(&chp->ch_callout);
1604 1.187 bouyer chp->ch_queue->active_xfer = NULL;
1605 1.192 thorpej if (ata_c->flags & AT_POLL) {
1606 1.187 bouyer /* enable interrupts */
1607 1.205 thorpej bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
1608 1.187 bouyer WDCTL_4BIT);
1609 1.187 bouyer delay(10); /* some drives need a little delay here */
1610 1.187 bouyer }
1611 1.187 bouyer if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
1612 1.187 bouyer __wdccommand_kill_xfer(chp, xfer, KILL_GONE);
1613 1.187 bouyer chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
1614 1.187 bouyer wakeup(&chp->ch_queue->active_xfer);
1615 1.219 perry } else
1616 1.187 bouyer __wdccommand_done_end(chp, xfer);
1617 1.182 bouyer }
1618 1.219 perry
1619 1.182 bouyer static void
1620 1.205 thorpej __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer)
1621 1.182 bouyer {
1622 1.192 thorpej struct ata_command *ata_c = xfer->c_cmd;
1623 1.182 bouyer
1624 1.192 thorpej ata_c->flags |= AT_DONE;
1625 1.198 thorpej ata_free_xfer(chp, xfer);
1626 1.192 thorpej if (ata_c->flags & AT_WAIT)
1627 1.192 thorpej wakeup(ata_c);
1628 1.192 thorpej else if (ata_c->callback)
1629 1.192 thorpej ata_c->callback(ata_c->callback_arg);
1630 1.202 thorpej atastart(chp);
1631 1.31 bouyer return;
1632 1.2 bouyer }
1633 1.2 bouyer
1634 1.182 bouyer static void
1635 1.205 thorpej __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
1636 1.182 bouyer int reason)
1637 1.182 bouyer {
1638 1.192 thorpej struct ata_command *ata_c = xfer->c_cmd;
1639 1.182 bouyer
1640 1.182 bouyer switch (reason) {
1641 1.182 bouyer case KILL_GONE:
1642 1.192 thorpej ata_c->flags |= AT_GONE;
1643 1.219 perry break;
1644 1.182 bouyer case KILL_RESET:
1645 1.192 thorpej ata_c->flags |= AT_RESET;
1646 1.182 bouyer break;
1647 1.182 bouyer default:
1648 1.182 bouyer printf("__wdccommand_kill_xfer: unknown reason %d\n",
1649 1.182 bouyer reason);
1650 1.182 bouyer panic("__wdccommand_kill_xfer");
1651 1.182 bouyer }
1652 1.182 bouyer __wdccommand_done_end(chp, xfer);
1653 1.182 bouyer }
1654 1.182 bouyer
1655 1.2 bouyer /*
1656 1.31 bouyer * Send a command. The drive should be ready.
1657 1.2 bouyer * Assumes interrupts are blocked.
1658 1.2 bouyer */
1659 1.31 bouyer void
1660 1.205 thorpej wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command,
1661 1.163 thorpej u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count,
1662 1.178 thorpej u_int8_t features)
1663 1.31 bouyer {
1664 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1665 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1666 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1667 1.163 thorpej
1668 1.204 thorpej ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1669 1.207 thorpej "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname,
1670 1.169 thorpej chp->ch_channel, drive, command, cylin, head, sector, count,
1671 1.178 thorpej features), DEBUG_FUNCS);
1672 1.31 bouyer
1673 1.203 thorpej if (wdc->select)
1674 1.169 thorpej wdc->select(chp,drive);
1675 1.107 dbj
1676 1.31 bouyer /* Select drive, head, and addressing mode. */
1677 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
1678 1.31 bouyer WDSD_IBM | (drive << 4) | head);
1679 1.177 thorpej /* Load parameters into the wd_features register. */
1680 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0,
1681 1.178 thorpej features);
1682 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count);
1683 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector);
1684 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin);
1685 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi],
1686 1.157 fvdl 0, cylin >> 8);
1687 1.108 christos
1688 1.108 christos /* Send command. */
1689 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command);
1690 1.108 christos return;
1691 1.108 christos }
1692 1.108 christos
1693 1.108 christos /*
1694 1.108 christos * Send a 48-bit addressing command. The drive should be ready.
1695 1.108 christos * Assumes interrupts are blocked.
1696 1.108 christos */
1697 1.108 christos void
1698 1.205 thorpej wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command,
1699 1.163 thorpej u_int64_t blkno, u_int16_t count)
1700 1.108 christos {
1701 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1702 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1703 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1704 1.163 thorpej
1705 1.204 thorpej ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d "
1706 1.207 thorpej "count=%d\n", atac->atac_dev.dv_xname,
1707 1.169 thorpej chp->ch_channel, drive, command, (u_int32_t) blkno, count),
1708 1.108 christos DEBUG_FUNCS);
1709 1.108 christos
1710 1.203 thorpej if (wdc->select)
1711 1.169 thorpej wdc->select(chp,drive);
1712 1.108 christos
1713 1.108 christos /* Select drive, head, and addressing mode. */
1714 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
1715 1.108 christos (drive << 4) | WDSD_LBA);
1716 1.108 christos
1717 1.218 rearnsha if (wdc->cap & WDC_CAPABILITY_WIDEREGS) {
1718 1.218 rearnsha bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0,
1719 1.218 rearnsha 0);
1720 1.218 rearnsha bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt],
1721 1.218 rearnsha 0, count);
1722 1.218 rearnsha bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo],
1723 1.218 rearnsha 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff)));
1724 1.218 rearnsha bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi],
1725 1.218 rearnsha 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff)));
1726 1.218 rearnsha bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi],
1727 1.218 rearnsha 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff)));
1728 1.218 rearnsha } else {
1729 1.218 rearnsha /* previous */
1730 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0,
1731 1.218 rearnsha 0);
1732 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt],
1733 1.218 rearnsha 0, count >> 8);
1734 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo],
1735 1.218 rearnsha 0, blkno >> 24);
1736 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi],
1737 1.218 rearnsha 0, blkno >> 32);
1738 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi],
1739 1.218 rearnsha 0, blkno >> 40);
1740 1.218 rearnsha
1741 1.218 rearnsha /* current */
1742 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0,
1743 1.218 rearnsha 0);
1744 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0,
1745 1.218 rearnsha count);
1746 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0,
1747 1.218 rearnsha blkno);
1748 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi],
1749 1.218 rearnsha 0, blkno >> 8);
1750 1.218 rearnsha bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi],
1751 1.218 rearnsha 0, blkno >> 16);
1752 1.218 rearnsha }
1753 1.2 bouyer
1754 1.31 bouyer /* Send command. */
1755 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command);
1756 1.31 bouyer return;
1757 1.2 bouyer }
1758 1.2 bouyer
1759 1.2 bouyer /*
1760 1.31 bouyer * Simplified version of wdccommand(). Unbusy/ready/drq must be
1761 1.31 bouyer * tested by the caller.
1762 1.2 bouyer */
1763 1.31 bouyer void
1764 1.205 thorpej wdccommandshort(struct ata_channel *chp, int drive, int command)
1765 1.2 bouyer {
1766 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1767 1.207 thorpej struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1768 1.205 thorpej struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
1769 1.2 bouyer
1770 1.204 thorpej ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1771 1.207 thorpej atac->atac_dev.dv_xname, chp->ch_channel, drive, command),
1772 1.31 bouyer DEBUG_FUNCS);
1773 1.107 dbj
1774 1.203 thorpej if (wdc->select)
1775 1.169 thorpej wdc->select(chp,drive);
1776 1.2 bouyer
1777 1.31 bouyer /* Select drive. */
1778 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
1779 1.31 bouyer WDSD_IBM | (drive << 4));
1780 1.2 bouyer
1781 1.205 thorpej bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command);
1782 1.31 bouyer }
1783 1.2 bouyer
1784 1.31 bouyer static void
1785 1.222 christos __wdcerror(struct ata_channel *chp, const char *msg)
1786 1.2 bouyer {
1787 1.207 thorpej struct atac_softc *atac = chp->ch_atac;
1788 1.217 bouyer struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1789 1.88 mrg
1790 1.2 bouyer if (xfer == NULL)
1791 1.207 thorpej printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel,
1792 1.31 bouyer msg);
1793 1.2 bouyer else
1794 1.207 thorpej printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname,
1795 1.169 thorpej chp->ch_channel, xfer->c_drive, msg);
1796 1.2 bouyer }
1797 1.2 bouyer
1798 1.219 perry /*
1799 1.2 bouyer * the bit bucket
1800 1.2 bouyer */
1801 1.2 bouyer void
1802 1.205 thorpej wdcbit_bucket(struct ata_channel *chp, int size)
1803 1.2 bouyer {
1804 1.207 thorpej struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
1805 1.2 bouyer
1806 1.12 cgd for (; size >= 2; size -= 2)
1807 1.205 thorpej (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0);
1808 1.12 cgd if (size)
1809 1.205 thorpej (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0);
1810 1.44 thorpej }
1811 1.44 thorpej
1812 1.213 thorpej static void
1813 1.222 christos wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len)
1814 1.190 mycroft {
1815 1.207 thorpej struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
1816 1.190 mycroft
1817 1.244 martin #ifndef __NO_STRICT_ALIGNMENT
1818 1.244 martin if ((uintptr_t)bf & 1)
1819 1.244 martin goto unaligned;
1820 1.244 martin if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3))
1821 1.244 martin goto unaligned;
1822 1.244 martin #endif
1823 1.244 martin
1824 1.190 mycroft if (flags & DRIVE_NOSTREAM) {
1825 1.190 mycroft if (flags & DRIVE_CAP32) {
1826 1.205 thorpej bus_space_read_multi_4(wdr->data32iot,
1827 1.222 christos wdr->data32ioh, 0, bf, len >> 2);
1828 1.222 christos bf = (char *)bf + (len & ~3);
1829 1.190 mycroft len &= 3;
1830 1.190 mycroft }
1831 1.190 mycroft if (len) {
1832 1.205 thorpej bus_space_read_multi_2(wdr->cmd_iot,
1833 1.222 christos wdr->cmd_iohs[wd_data], 0, bf, len >> 1);
1834 1.190 mycroft }
1835 1.190 mycroft } else {
1836 1.190 mycroft if (flags & DRIVE_CAP32) {
1837 1.205 thorpej bus_space_read_multi_stream_4(wdr->data32iot,
1838 1.222 christos wdr->data32ioh, 0, bf, len >> 2);
1839 1.222 christos bf = (char *)bf + (len & ~3);
1840 1.190 mycroft len &= 3;
1841 1.190 mycroft }
1842 1.190 mycroft if (len) {
1843 1.205 thorpej bus_space_read_multi_stream_2(wdr->cmd_iot,
1844 1.222 christos wdr->cmd_iohs[wd_data], 0, bf, len >> 1);
1845 1.190 mycroft }
1846 1.190 mycroft }
1847 1.244 martin return;
1848 1.244 martin
1849 1.244 martin #ifndef __NO_STRICT_ALIGNMENT
1850 1.244 martin unaligned:
1851 1.245 bouyer if (flags & DRIVE_NOSTREAM) {
1852 1.245 bouyer if (flags & DRIVE_CAP32) {
1853 1.245 bouyer while (len > 3) {
1854 1.245 bouyer uint32_t val;
1855 1.245 bouyer
1856 1.245 bouyer val = bus_space_read_4(wdr->data32iot,
1857 1.245 bouyer wdr->data32ioh, 0);
1858 1.245 bouyer memcpy(bf, &val, 4);
1859 1.245 bouyer bf = (char *)bf + 4;
1860 1.245 bouyer len -= 4;
1861 1.245 bouyer }
1862 1.245 bouyer }
1863 1.245 bouyer while (len > 1) {
1864 1.245 bouyer uint16_t val;
1865 1.245 bouyer
1866 1.245 bouyer val = bus_space_read_2(wdr->cmd_iot,
1867 1.245 bouyer wdr->cmd_iohs[wd_data], 0);
1868 1.245 bouyer memcpy(bf, &val, 2);
1869 1.245 bouyer bf = (char *)bf + 2;
1870 1.245 bouyer len -= 2;
1871 1.245 bouyer }
1872 1.245 bouyer } else {
1873 1.245 bouyer if (flags & DRIVE_CAP32) {
1874 1.245 bouyer while (len > 3) {
1875 1.245 bouyer uint32_t val;
1876 1.244 martin
1877 1.245 bouyer val = bus_space_read_stream_4(wdr->data32iot,
1878 1.245 bouyer wdr->data32ioh, 0);
1879 1.245 bouyer memcpy(bf, &val, 4);
1880 1.245 bouyer bf = (char *)bf + 4;
1881 1.245 bouyer len -= 4;
1882 1.245 bouyer }
1883 1.245 bouyer }
1884 1.245 bouyer while (len > 1) {
1885 1.245 bouyer uint16_t val;
1886 1.245 bouyer
1887 1.245 bouyer val = bus_space_read_stream_2(wdr->cmd_iot,
1888 1.244 martin wdr->cmd_iohs[wd_data], 0);
1889 1.245 bouyer memcpy(bf, &val, 2);
1890 1.245 bouyer bf = (char *)bf + 2;
1891 1.245 bouyer len -= 2;
1892 1.244 martin }
1893 1.244 martin }
1894 1.244 martin #endif
1895 1.190 mycroft }
1896 1.190 mycroft
1897 1.213 thorpej static void
1898 1.222 christos wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len)
1899 1.190 mycroft {
1900 1.207 thorpej struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
1901 1.190 mycroft
1902 1.244 martin #ifndef __NO_STRICT_ALIGNMENT
1903 1.244 martin if ((uintptr_t)bf & 1)
1904 1.244 martin goto unaligned;
1905 1.244 martin if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3))
1906 1.244 martin goto unaligned;
1907 1.244 martin #endif
1908 1.244 martin
1909 1.190 mycroft if (flags & DRIVE_NOSTREAM) {
1910 1.190 mycroft if (flags & DRIVE_CAP32) {
1911 1.205 thorpej bus_space_write_multi_4(wdr->data32iot,
1912 1.222 christos wdr->data32ioh, 0, bf, len >> 2);
1913 1.222 christos bf = (char *)bf + (len & ~3);
1914 1.190 mycroft len &= 3;
1915 1.190 mycroft }
1916 1.190 mycroft if (len) {
1917 1.205 thorpej bus_space_write_multi_2(wdr->cmd_iot,
1918 1.222 christos wdr->cmd_iohs[wd_data], 0, bf, len >> 1);
1919 1.190 mycroft }
1920 1.190 mycroft } else {
1921 1.190 mycroft if (flags & DRIVE_CAP32) {
1922 1.205 thorpej bus_space_write_multi_stream_4(wdr->data32iot,
1923 1.222 christos wdr->data32ioh, 0, bf, len >> 2);
1924 1.222 christos bf = (char *)bf + (len & ~3);
1925 1.190 mycroft len &= 3;
1926 1.190 mycroft }
1927 1.190 mycroft if (len) {
1928 1.205 thorpej bus_space_write_multi_stream_2(wdr->cmd_iot,
1929 1.222 christos wdr->cmd_iohs[wd_data], 0, bf, len >> 1);
1930 1.190 mycroft }
1931 1.190 mycroft }
1932 1.244 martin return;
1933 1.244 martin
1934 1.244 martin #ifndef __NO_STRICT_ALIGNMENT
1935 1.244 martin unaligned:
1936 1.245 bouyer if (flags & DRIVE_NOSTREAM) {
1937 1.245 bouyer if (flags & DRIVE_CAP32) {
1938 1.245 bouyer while (len > 3) {
1939 1.245 bouyer uint32_t val;
1940 1.244 martin
1941 1.245 bouyer memcpy(&val, bf, 4);
1942 1.245 bouyer bus_space_write_4(wdr->data32iot,
1943 1.245 bouyer wdr->data32ioh, 0, val);
1944 1.245 bouyer bf = (char *)bf + 4;
1945 1.245 bouyer len -= 4;
1946 1.245 bouyer }
1947 1.245 bouyer }
1948 1.245 bouyer while (len > 1) {
1949 1.245 bouyer uint16_t val;
1950 1.245 bouyer
1951 1.245 bouyer memcpy(&val, bf, 2);
1952 1.245 bouyer bus_space_write_2(wdr->cmd_iot,
1953 1.244 martin wdr->cmd_iohs[wd_data], 0, val);
1954 1.245 bouyer bf = (char *)bf + 2;
1955 1.245 bouyer len -= 2;
1956 1.244 martin }
1957 1.245 bouyer } else {
1958 1.245 bouyer if (flags & DRIVE_CAP32) {
1959 1.245 bouyer while (len > 3) {
1960 1.245 bouyer uint32_t val;
1961 1.245 bouyer
1962 1.245 bouyer memcpy(&val, bf, 4);
1963 1.245 bouyer bus_space_write_stream_4(wdr->data32iot,
1964 1.245 bouyer wdr->data32ioh, 0, val);
1965 1.245 bouyer bf = (char *)bf + 4;
1966 1.245 bouyer len -= 4;
1967 1.245 bouyer }
1968 1.245 bouyer }
1969 1.245 bouyer while (len > 1) {
1970 1.245 bouyer uint16_t val;
1971 1.244 martin
1972 1.245 bouyer memcpy(&val, bf, 2);
1973 1.245 bouyer bus_space_write_stream_2(wdr->cmd_iot,
1974 1.245 bouyer wdr->cmd_iohs[wd_data], 0, val);
1975 1.245 bouyer bf = (char *)bf + 2;
1976 1.245 bouyer len -= 2;
1977 1.245 bouyer }
1978 1.244 martin }
1979 1.244 martin #endif
1980 1.190 mycroft }
1981