wdc.c revision 1.51 1 1.51 bouyer /* $NetBSD: wdc.c,v 1.51 1998/12/03 17:30:32 bouyer Exp $ */
2 1.31 bouyer
3 1.31 bouyer
4 1.31 bouyer /*
5 1.31 bouyer * Copyright (c) 1998 Manuel Bouyer. All rights reserved.
6 1.31 bouyer *
7 1.31 bouyer * Redistribution and use in source and binary forms, with or without
8 1.31 bouyer * modification, are permitted provided that the following conditions
9 1.31 bouyer * are met:
10 1.31 bouyer * 1. Redistributions of source code must retain the above copyright
11 1.31 bouyer * notice, this list of conditions and the following disclaimer.
12 1.31 bouyer * 2. Redistributions in binary form must reproduce the above copyright
13 1.31 bouyer * notice, this list of conditions and the following disclaimer in the
14 1.31 bouyer * documentation and/or other materials provided with the distribution.
15 1.31 bouyer * 3. All advertising materials mentioning features or use of this software
16 1.31 bouyer * must display the following acknowledgement:
17 1.31 bouyer * This product includes software developed by Manuel Bouyer.
18 1.31 bouyer * 4. The name of the author may not be used to endorse or promote products
19 1.31 bouyer * derived from this software without specific prior written permission.
20 1.31 bouyer *
21 1.31 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.31 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.31 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.31 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.31 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.31 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.31 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.31 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.31 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.31 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.31 bouyer */
32 1.2 bouyer
33 1.27 mycroft /*-
34 1.27 mycroft * Copyright (c) 1998 The NetBSD Foundation, Inc.
35 1.27 mycroft * All rights reserved.
36 1.2 bouyer *
37 1.27 mycroft * This code is derived from software contributed to The NetBSD Foundation
38 1.27 mycroft * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
39 1.12 cgd *
40 1.2 bouyer * Redistribution and use in source and binary forms, with or without
41 1.2 bouyer * modification, are permitted provided that the following conditions
42 1.2 bouyer * are met:
43 1.2 bouyer * 1. Redistributions of source code must retain the above copyright
44 1.2 bouyer * notice, this list of conditions and the following disclaimer.
45 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright
46 1.2 bouyer * notice, this list of conditions and the following disclaimer in the
47 1.2 bouyer * documentation and/or other materials provided with the distribution.
48 1.2 bouyer * 3. All advertising materials mentioning features or use of this software
49 1.2 bouyer * must display the following acknowledgement:
50 1.27 mycroft * This product includes software developed by the NetBSD
51 1.27 mycroft * Foundation, Inc. and its contributors.
52 1.27 mycroft * 4. Neither the name of The NetBSD Foundation nor the names of its
53 1.27 mycroft * contributors may be used to endorse or promote products derived
54 1.27 mycroft * from this software without specific prior written permission.
55 1.2 bouyer *
56 1.27 mycroft * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
57 1.27 mycroft * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
58 1.27 mycroft * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
59 1.27 mycroft * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
60 1.27 mycroft * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
61 1.27 mycroft * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
62 1.27 mycroft * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
63 1.27 mycroft * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
64 1.27 mycroft * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
65 1.27 mycroft * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
66 1.27 mycroft * POSSIBILITY OF SUCH DAMAGE.
67 1.2 bouyer */
68 1.2 bouyer
69 1.12 cgd /*
70 1.12 cgd * CODE UNTESTED IN THE CURRENT REVISION:
71 1.31 bouyer *
72 1.12 cgd */
73 1.12 cgd
74 1.31 bouyer #define WDCDEBUG
75 1.31 bouyer
76 1.2 bouyer #include <sys/param.h>
77 1.2 bouyer #include <sys/systm.h>
78 1.2 bouyer #include <sys/kernel.h>
79 1.2 bouyer #include <sys/conf.h>
80 1.2 bouyer #include <sys/buf.h>
81 1.31 bouyer #include <sys/device.h>
82 1.2 bouyer #include <sys/malloc.h>
83 1.2 bouyer #include <sys/syslog.h>
84 1.2 bouyer #include <sys/proc.h>
85 1.2 bouyer
86 1.2 bouyer #include <vm/vm.h>
87 1.2 bouyer
88 1.2 bouyer #include <machine/intr.h>
89 1.2 bouyer #include <machine/bus.h>
90 1.2 bouyer
91 1.17 sakamoto #ifndef __BUS_SPACE_HAS_STREAM_METHODS
92 1.31 bouyer #define bus_space_write_multi_stream_2 bus_space_write_multi_2
93 1.31 bouyer #define bus_space_write_multi_stream_4 bus_space_write_multi_4
94 1.31 bouyer #define bus_space_read_multi_stream_2 bus_space_read_multi_2
95 1.31 bouyer #define bus_space_read_multi_stream_4 bus_space_read_multi_4
96 1.17 sakamoto #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
97 1.16 sakamoto
98 1.31 bouyer #include <dev/ata/atavar.h>
99 1.31 bouyer #include <dev/ata/atareg.h>
100 1.12 cgd #include <dev/ic/wdcreg.h>
101 1.12 cgd #include <dev/ic/wdcvar.h>
102 1.31 bouyer
103 1.2 bouyer #include "atapibus.h"
104 1.2 bouyer
105 1.31 bouyer #define WDCDELAY 100 /* 100 microseconds */
106 1.31 bouyer #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
107 1.2 bouyer #if 0
108 1.31 bouyer /* If you enable this, it will report any delays more than WDCDELAY * N long. */
109 1.2 bouyer #define WDCNDELAY_DEBUG 50
110 1.2 bouyer #endif
111 1.2 bouyer
112 1.2 bouyer LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list;
113 1.2 bouyer
114 1.31 bouyer static void __wdcerror __P((struct channel_softc*, char *));
115 1.31 bouyer static int __wdcwait_reset __P((struct channel_softc *, int));
116 1.31 bouyer void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *));
117 1.31 bouyer void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *));
118 1.31 bouyer int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *));
119 1.31 bouyer int wdprint __P((void *, const char *));
120 1.31 bouyer
121 1.31 bouyer
122 1.31 bouyer #define DEBUG_INTR 0x01
123 1.31 bouyer #define DEBUG_XFERS 0x02
124 1.31 bouyer #define DEBUG_STATUS 0x04
125 1.31 bouyer #define DEBUG_FUNCS 0x08
126 1.31 bouyer #define DEBUG_PROBE 0x10
127 1.31 bouyer #ifdef WDCDEBUG
128 1.32 bouyer int wdcdebug_mask = 0;
129 1.31 bouyer int wdc_nxfer = 0;
130 1.31 bouyer #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args
131 1.2 bouyer #else
132 1.31 bouyer #define WDCDEBUG_PRINT(args, level)
133 1.2 bouyer #endif
134 1.2 bouyer
135 1.31 bouyer int
136 1.31 bouyer wdprint(aux, pnp)
137 1.31 bouyer void *aux;
138 1.31 bouyer const char *pnp;
139 1.31 bouyer {
140 1.31 bouyer struct ata_atapi_attach *aa_link = aux;
141 1.31 bouyer if (pnp)
142 1.31 bouyer printf("drive at %s", pnp);
143 1.31 bouyer printf(" channel %d drive %d", aa_link->aa_channel,
144 1.31 bouyer aa_link->aa_drv_data->drive);
145 1.31 bouyer return (UNCONF);
146 1.31 bouyer }
147 1.2 bouyer
148 1.31 bouyer int
149 1.31 bouyer atapi_print(aux, pnp)
150 1.31 bouyer void *aux;
151 1.31 bouyer const char *pnp;
152 1.31 bouyer {
153 1.31 bouyer struct ata_atapi_attach *aa_link = aux;
154 1.31 bouyer if (pnp)
155 1.31 bouyer printf("atapibus at %s", pnp);
156 1.31 bouyer printf(" channel %d", aa_link->aa_channel);
157 1.31 bouyer return (UNCONF);
158 1.31 bouyer }
159 1.31 bouyer
160 1.31 bouyer /* Test to see controller with at last one attached drive is there.
161 1.31 bouyer * Returns a bit for each possible drive found (0x01 for drive 0,
162 1.31 bouyer * 0x02 for drive 1).
163 1.31 bouyer * Logic:
164 1.31 bouyer * - If a status register is at 0xff, assume there is no drive here
165 1.31 bouyer * (ISA has pull-up resistors). If no drive at all -> return.
166 1.31 bouyer * - reset the controller, wait for it to complete (may take up to 31s !).
167 1.31 bouyer * If timeout -> return.
168 1.31 bouyer * - test ATA/ATAPI signatures. If at last one drive found -> return.
169 1.31 bouyer * - try an ATA command on the master.
170 1.12 cgd */
171 1.31 bouyer
172 1.2 bouyer int
173 1.31 bouyer wdcprobe(chp)
174 1.31 bouyer struct channel_softc *chp;
175 1.12 cgd {
176 1.31 bouyer u_int8_t st0, st1, sc, sn, cl, ch;
177 1.31 bouyer u_int8_t ret_value = 0x03;
178 1.31 bouyer u_int8_t drive;
179 1.31 bouyer
180 1.31 bouyer /*
181 1.31 bouyer * Sanity check to see if the wdc channel responds at all.
182 1.31 bouyer */
183 1.31 bouyer
184 1.43 kenh if (chp->wdc == NULL ||
185 1.43 kenh (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
186 1.43 kenh bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
187 1.43 kenh WDSD_IBM);
188 1.43 kenh delay(1);
189 1.43 kenh st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
190 1.43 kenh bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
191 1.43 kenh WDSD_IBM | 0x10);
192 1.43 kenh delay(1);
193 1.43 kenh st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
194 1.43 kenh
195 1.43 kenh WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n",
196 1.43 kenh chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
197 1.43 kenh chp->channel, st0, st1), DEBUG_PROBE);
198 1.43 kenh
199 1.43 kenh if (st0 == 0xff)
200 1.43 kenh ret_value &= ~0x01;
201 1.43 kenh if (st1 == 0xff)
202 1.43 kenh ret_value &= ~0x02;
203 1.43 kenh if (ret_value == 0)
204 1.43 kenh return 0;
205 1.43 kenh }
206 1.42 thorpej
207 1.31 bouyer /* assert SRST, wait for reset to complete */
208 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
209 1.31 bouyer WDSD_IBM);
210 1.31 bouyer delay(1);
211 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
212 1.31 bouyer WDCTL_RST | WDCTL_IDS);
213 1.31 bouyer DELAY(1000);
214 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
215 1.31 bouyer WDCTL_IDS);
216 1.31 bouyer delay(1000);
217 1.31 bouyer (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
218 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
219 1.31 bouyer delay(1);
220 1.31 bouyer
221 1.31 bouyer ret_value = __wdcwait_reset(chp, ret_value);
222 1.31 bouyer WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
223 1.31 bouyer chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
224 1.31 bouyer ret_value), DEBUG_PROBE);
225 1.26 drochner
226 1.31 bouyer /* if reset failed, there's nothing here */
227 1.31 bouyer if (ret_value == 0)
228 1.31 bouyer return 0;
229 1.2 bouyer
230 1.31 bouyer /*
231 1.31 bouyer * Test presence of drives. First test register signatures looking for
232 1.31 bouyer * ATAPI devices , then rescan and try an ATA command, in case it's an
233 1.31 bouyer * old drive.
234 1.31 bouyer * Fill in drive_flags accordingly
235 1.31 bouyer */
236 1.31 bouyer for (drive = 0; drive < 2; drive++) {
237 1.31 bouyer if ((ret_value & (0x01 << drive)) == 0)
238 1.31 bouyer continue;
239 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
240 1.31 bouyer WDSD_IBM | (drive << 4));
241 1.31 bouyer delay(1);
242 1.31 bouyer /* Save registers contents */
243 1.31 bouyer sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
244 1.31 bouyer sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector);
245 1.31 bouyer cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo);
246 1.31 bouyer ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi);
247 1.31 bouyer
248 1.31 bouyer WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x "
249 1.31 bouyer "cl=0x%x ch=0x%x\n",
250 1.31 bouyer chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
251 1.31 bouyer chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE);
252 1.31 bouyer if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) {
253 1.31 bouyer chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
254 1.31 bouyer }
255 1.31 bouyer }
256 1.31 bouyer for (drive = 0; drive < 2; drive++) {
257 1.31 bouyer if ((ret_value & (0x01 << drive)) == 0 ||
258 1.31 bouyer (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0)
259 1.31 bouyer continue;
260 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
261 1.31 bouyer WDSD_IBM | (drive << 4));
262 1.31 bouyer delay(1);
263 1.2 bouyer /*
264 1.31 bouyer * Maybe it's an old device, so don't rely on ATA sig.
265 1.31 bouyer * Test registers writability (Error register not writable,
266 1.31 bouyer * but cyllo is), then try an ATA command.
267 1.2 bouyer */
268 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58);
269 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5);
270 1.31 bouyer if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) ==
271 1.31 bouyer 0x58 ||
272 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) !=
273 1.31 bouyer 0xa5) {
274 1.31 bouyer WDCDEBUG_PRINT(("%s:%d:%d: register writability "
275 1.31 bouyer "failed\n",
276 1.31 bouyer chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
277 1.31 bouyer chp->channel, drive), DEBUG_PROBE);
278 1.31 bouyer ret_value &= ~(0x01 << drive);
279 1.31 bouyer continue;
280 1.31 bouyer }
281 1.31 bouyer if (wait_for_ready(chp, 10000) != 0) {
282 1.31 bouyer WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
283 1.31 bouyer chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
284 1.31 bouyer chp->channel, drive), DEBUG_PROBE);
285 1.31 bouyer ret_value &= ~(0x01 << drive);
286 1.31 bouyer continue;
287 1.31 bouyer }
288 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command,
289 1.31 bouyer WDCC_DIAGNOSE);
290 1.31 bouyer if (wait_for_ready(chp, 10000) == 0) {
291 1.31 bouyer chp->ch_drive[drive].drive_flags |=
292 1.31 bouyer DRIVE_ATA;
293 1.7 bouyer } else {
294 1.31 bouyer WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n",
295 1.31 bouyer chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
296 1.31 bouyer chp->channel, drive), DEBUG_PROBE);
297 1.31 bouyer ret_value &= ~(0x01 << drive);
298 1.2 bouyer }
299 1.7 bouyer }
300 1.31 bouyer return (ret_value);
301 1.31 bouyer }
302 1.31 bouyer
303 1.31 bouyer void
304 1.31 bouyer wdcattach(chp)
305 1.31 bouyer struct channel_softc *chp;
306 1.31 bouyer {
307 1.44 thorpej int channel_flags, ctrl_flags, i, error;
308 1.31 bouyer struct ata_atapi_attach aa_link;
309 1.31 bouyer
310 1.31 bouyer LIST_INIT(&xfer_free_list);
311 1.31 bouyer for (i = 0; i < 2; i++) {
312 1.31 bouyer chp->ch_drive[i].chnl_softc = chp;
313 1.31 bouyer chp->ch_drive[i].drive = i;
314 1.31 bouyer /* If controller can't do 16bit flag the drives as 32bit */
315 1.31 bouyer if ((chp->wdc->cap &
316 1.31 bouyer (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
317 1.31 bouyer WDC_CAPABILITY_DATA32)
318 1.31 bouyer chp->ch_drive[i].drive_flags |= DRIVE_CAP32;
319 1.31 bouyer }
320 1.31 bouyer
321 1.44 thorpej if ((error = wdc_addref(chp)) != 0) {
322 1.44 thorpej printf("%s: unable to enable controller\n",
323 1.44 thorpej chp->wdc->sc_dev.dv_xname);
324 1.44 thorpej return;
325 1.44 thorpej }
326 1.44 thorpej
327 1.44 thorpej if (wdcprobe(chp) == 0) {
328 1.44 thorpej /* If no drives, abort attach here. */
329 1.44 thorpej wdc_delref(chp);
330 1.44 thorpej return;
331 1.44 thorpej }
332 1.31 bouyer
333 1.31 bouyer TAILQ_INIT(&chp->ch_queue->sc_xfer);
334 1.31 bouyer ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags;
335 1.31 bouyer channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff;
336 1.31 bouyer
337 1.31 bouyer WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n",
338 1.31 bouyer chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
339 1.31 bouyer DEBUG_PROBE);
340 1.12 cgd
341 1.12 cgd /*
342 1.31 bouyer * Attach an ATAPI bus, if needed.
343 1.12 cgd */
344 1.31 bouyer if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
345 1.31 bouyer (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
346 1.31 bouyer #if NATAPIBUS > 0
347 1.31 bouyer wdc_atapibus_attach(chp);
348 1.31 bouyer #else
349 1.31 bouyer /*
350 1.31 bouyer * Fills in a fake aa_link and call config_found, so that
351 1.31 bouyer * the config machinery will print
352 1.31 bouyer * "atapibus at xxx not configured"
353 1.31 bouyer */
354 1.31 bouyer memset(&aa_link, 0, sizeof(struct ata_atapi_attach));
355 1.31 bouyer aa_link.aa_type = T_ATAPI;
356 1.31 bouyer aa_link.aa_channel = chp->channel;
357 1.31 bouyer aa_link.aa_openings = 1;
358 1.31 bouyer aa_link.aa_drv_data = 0;
359 1.31 bouyer aa_link.aa_bus_private = NULL;
360 1.31 bouyer (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link,
361 1.31 bouyer atapi_print);
362 1.31 bouyer #endif
363 1.31 bouyer }
364 1.31 bouyer
365 1.31 bouyer for (i = 0; i < 2; i++) {
366 1.31 bouyer if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) {
367 1.31 bouyer continue;
368 1.31 bouyer }
369 1.31 bouyer memset(&aa_link, 0, sizeof(struct ata_atapi_attach));
370 1.31 bouyer aa_link.aa_type = T_ATA;
371 1.31 bouyer aa_link.aa_channel = chp->channel;
372 1.31 bouyer aa_link.aa_openings = 1;
373 1.31 bouyer aa_link.aa_drv_data = &chp->ch_drive[i];
374 1.31 bouyer if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint))
375 1.31 bouyer wdc_probe_caps(&chp->ch_drive[i]);
376 1.32 bouyer }
377 1.32 bouyer
378 1.32 bouyer /*
379 1.32 bouyer * reset drive_flags for unnatached devices, reset state for attached
380 1.32 bouyer * ones
381 1.32 bouyer */
382 1.32 bouyer for (i = 0; i < 2; i++) {
383 1.32 bouyer if (chp->ch_drive[i].drv_softc == NULL)
384 1.32 bouyer chp->ch_drive[i].drive_flags = 0;
385 1.32 bouyer else
386 1.32 bouyer chp->ch_drive[i].state = 0;
387 1.2 bouyer }
388 1.12 cgd
389 1.12 cgd /*
390 1.31 bouyer * Reset channel. The probe, with some combinations of ATA/ATAPI
391 1.31 bouyer * devices keep it in a mostly working, but strange state (with busy
392 1.31 bouyer * led on)
393 1.12 cgd */
394 1.31 bouyer if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
395 1.31 bouyer wdcreset(chp, VERBOSE);
396 1.31 bouyer /*
397 1.31 bouyer * Read status registers to avoid spurious interrupts.
398 1.31 bouyer */
399 1.31 bouyer for (i = 1; i >= 0; i--) {
400 1.31 bouyer if (chp->ch_drive[i].drive_flags & DRIVE) {
401 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
402 1.31 bouyer wd_sdh, WDSD_IBM | (i << 4));
403 1.31 bouyer if (wait_for_unbusy(chp, 10000) < 0)
404 1.31 bouyer printf("%s:%d:%d: device busy\n",
405 1.31 bouyer chp->wdc->sc_dev.dv_xname,
406 1.31 bouyer chp->channel, i);
407 1.31 bouyer }
408 1.31 bouyer }
409 1.31 bouyer }
410 1.44 thorpej wdc_delref(chp);
411 1.31 bouyer }
412 1.31 bouyer
413 1.31 bouyer /*
414 1.31 bouyer * Start I/O on a controller, for the given channel.
415 1.31 bouyer * The first xfer may be not for our channel if the channel queues
416 1.31 bouyer * are shared.
417 1.31 bouyer */
418 1.31 bouyer void
419 1.45 drochner wdcstart(chp)
420 1.45 drochner struct channel_softc *chp;
421 1.31 bouyer {
422 1.31 bouyer struct wdc_xfer *xfer;
423 1.38 bouyer
424 1.38 bouyer #ifdef WDC_DIAGNOSTIC
425 1.38 bouyer int spl1, spl2;
426 1.38 bouyer
427 1.38 bouyer spl1 = splbio();
428 1.38 bouyer spl2 = splbio();
429 1.38 bouyer if (spl2 != spl1) {
430 1.38 bouyer printf("wdcstart: not at splbio()\n");
431 1.38 bouyer panic("wdcstart");
432 1.38 bouyer }
433 1.38 bouyer splx(spl2);
434 1.38 bouyer splx(spl1);
435 1.38 bouyer #endif /* WDC_DIAGNOSTIC */
436 1.12 cgd
437 1.31 bouyer /* is there a xfer ? */
438 1.45 drochner if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL)
439 1.31 bouyer return;
440 1.47 bouyer
441 1.47 bouyer /* adjust chp, in case we have a shared queue */
442 1.49 bouyer chp = xfer->chp;
443 1.47 bouyer
444 1.31 bouyer if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
445 1.31 bouyer return; /* channel aleady active */
446 1.31 bouyer }
447 1.31 bouyer #ifdef DIAGNOSTIC
448 1.31 bouyer if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
449 1.31 bouyer panic("wdcstart: channel waiting for irq\n");
450 1.31 bouyer #endif
451 1.45 drochner if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK)
452 1.45 drochner if (!(*chp->wdc->claim_hw)(chp, 0))
453 1.31 bouyer return;
454 1.12 cgd
455 1.31 bouyer WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
456 1.49 bouyer chp->channel, xfer->drive), DEBUG_XFERS);
457 1.31 bouyer chp->ch_flags |= WDCF_ACTIVE;
458 1.37 bouyer if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) {
459 1.37 bouyer chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET;
460 1.37 bouyer chp->ch_drive[xfer->drive].state = 0;
461 1.37 bouyer }
462 1.31 bouyer xfer->c_start(chp, xfer);
463 1.31 bouyer }
464 1.2 bouyer
465 1.31 bouyer /* restart an interrupted I/O */
466 1.31 bouyer void
467 1.31 bouyer wdcrestart(v)
468 1.31 bouyer void *v;
469 1.31 bouyer {
470 1.31 bouyer struct channel_softc *chp = v;
471 1.31 bouyer int s;
472 1.2 bouyer
473 1.31 bouyer s = splbio();
474 1.45 drochner wdcstart(chp);
475 1.31 bouyer splx(s);
476 1.2 bouyer }
477 1.31 bouyer
478 1.2 bouyer
479 1.31 bouyer /*
480 1.31 bouyer * Interrupt routine for the controller. Acknowledge the interrupt, check for
481 1.31 bouyer * errors on the current operation, mark it done if necessary, and start the
482 1.31 bouyer * next request. Also check for a partially done transfer, and continue with
483 1.31 bouyer * the next chunk if so.
484 1.31 bouyer */
485 1.12 cgd int
486 1.31 bouyer wdcintr(arg)
487 1.31 bouyer void *arg;
488 1.12 cgd {
489 1.31 bouyer struct channel_softc *chp = arg;
490 1.31 bouyer struct wdc_xfer *xfer;
491 1.12 cgd
492 1.31 bouyer if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
493 1.31 bouyer #if 0
494 1.31 bouyer /* Clear the pending interrupt and abort. */
495 1.31 bouyer u_int8_t s =
496 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
497 1.31 bouyer #ifdef WDCDEBUG
498 1.31 bouyer u_int8_t e =
499 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
500 1.31 bouyer u_int8_t i =
501 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
502 1.31 bouyer #else
503 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
504 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt);
505 1.31 bouyer #endif
506 1.12 cgd
507 1.31 bouyer WDCDEBUG_PRINT(("wdcintr: inactive controller, "
508 1.31 bouyer "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR);
509 1.31 bouyer
510 1.31 bouyer if (s & WDCS_DRQ) {
511 1.31 bouyer int len;
512 1.31 bouyer len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
513 1.31 bouyer wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot,
514 1.31 bouyer chp->cmd_ioh, wd_cyl_hi);
515 1.31 bouyer WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n",
516 1.31 bouyer len), DEBUG_INTR);
517 1.31 bouyer wdcbit_bucket (chp, len);
518 1.31 bouyer }
519 1.31 bouyer #else
520 1.31 bouyer WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
521 1.31 bouyer #endif
522 1.31 bouyer return 0;
523 1.31 bouyer }
524 1.12 cgd
525 1.31 bouyer WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
526 1.31 bouyer untimeout(wdctimeout, chp);
527 1.31 bouyer chp->ch_flags &= ~WDCF_IRQ_WAIT;
528 1.31 bouyer xfer = chp->ch_queue->sc_xfer.tqh_first;
529 1.31 bouyer return xfer->c_intr(chp, xfer);
530 1.12 cgd }
531 1.12 cgd
532 1.31 bouyer /* Put all disk in RESET state */
533 1.31 bouyer void wdc_reset_channel(drvp)
534 1.31 bouyer struct ata_drive_datas *drvp;
535 1.2 bouyer {
536 1.31 bouyer struct channel_softc *chp = drvp->chnl_softc;
537 1.2 bouyer int drive;
538 1.34 bouyer WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
539 1.34 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
540 1.34 bouyer DEBUG_FUNCS);
541 1.31 bouyer (void) wdcreset(chp, VERBOSE);
542 1.31 bouyer for (drive = 0; drive < 2; drive++) {
543 1.31 bouyer chp->ch_drive[drive].state = 0;
544 1.12 cgd }
545 1.31 bouyer }
546 1.12 cgd
547 1.31 bouyer int
548 1.31 bouyer wdcreset(chp, verb)
549 1.31 bouyer struct channel_softc *chp;
550 1.31 bouyer int verb;
551 1.31 bouyer {
552 1.31 bouyer int drv_mask1, drv_mask2;
553 1.2 bouyer
554 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
555 1.31 bouyer WDSD_IBM); /* master */
556 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
557 1.31 bouyer WDCTL_RST | WDCTL_IDS);
558 1.31 bouyer delay(1000);
559 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
560 1.31 bouyer WDCTL_IDS);
561 1.31 bouyer delay(1000);
562 1.31 bouyer (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
563 1.31 bouyer bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
564 1.31 bouyer WDCTL_4BIT);
565 1.2 bouyer
566 1.31 bouyer drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
567 1.31 bouyer drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
568 1.31 bouyer drv_mask2 = __wdcwait_reset(chp, drv_mask1);
569 1.31 bouyer if (verb && drv_mask2 != drv_mask1) {
570 1.31 bouyer printf("%s channel %d: reset failed for",
571 1.31 bouyer chp->wdc->sc_dev.dv_xname, chp->channel);
572 1.31 bouyer if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
573 1.31 bouyer printf(" drive 0");
574 1.31 bouyer if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
575 1.31 bouyer printf(" drive 1");
576 1.31 bouyer printf("\n");
577 1.31 bouyer }
578 1.31 bouyer return (drv_mask1 != drv_mask2) ? 1 : 0;
579 1.31 bouyer }
580 1.31 bouyer
581 1.31 bouyer static int
582 1.31 bouyer __wdcwait_reset(chp, drv_mask)
583 1.31 bouyer struct channel_softc *chp;
584 1.31 bouyer int drv_mask;
585 1.31 bouyer {
586 1.31 bouyer int timeout;
587 1.31 bouyer u_int8_t st0, st1;
588 1.31 bouyer /* wait for BSY to deassert */
589 1.31 bouyer for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) {
590 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
591 1.31 bouyer WDSD_IBM); /* master */
592 1.31 bouyer delay(1);
593 1.31 bouyer st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
594 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
595 1.31 bouyer WDSD_IBM | 0x10); /* slave */
596 1.31 bouyer delay(1);
597 1.31 bouyer st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
598 1.31 bouyer
599 1.31 bouyer if ((drv_mask & 0x01) == 0) {
600 1.31 bouyer /* no master */
601 1.31 bouyer if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
602 1.31 bouyer /* No master, slave is ready, it's done */
603 1.31 bouyer return drv_mask;
604 1.31 bouyer }
605 1.31 bouyer } else if ((drv_mask & 0x02) == 0) {
606 1.31 bouyer /* no slave */
607 1.31 bouyer if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
608 1.31 bouyer /* No slave, master is ready, it's done */
609 1.31 bouyer return drv_mask;
610 1.31 bouyer }
611 1.2 bouyer } else {
612 1.31 bouyer /* Wait for both master and slave to be ready */
613 1.31 bouyer if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
614 1.31 bouyer return drv_mask;
615 1.2 bouyer }
616 1.2 bouyer }
617 1.31 bouyer delay(WDCDELAY);
618 1.2 bouyer }
619 1.31 bouyer /* Reset timed out. Maybe it's because drv_mask was not rigth */
620 1.31 bouyer if (st0 & WDCS_BSY)
621 1.31 bouyer drv_mask &= ~0x01;
622 1.31 bouyer if (st1 & WDCS_BSY)
623 1.31 bouyer drv_mask &= ~0x02;
624 1.31 bouyer return drv_mask;
625 1.2 bouyer }
626 1.2 bouyer
627 1.2 bouyer /*
628 1.31 bouyer * Wait for a drive to be !BSY, and have mask in its status register.
629 1.31 bouyer * return -1 for a timeout after "timeout" ms.
630 1.2 bouyer */
631 1.31 bouyer int
632 1.31 bouyer wdcwait(chp, mask, bits, timeout)
633 1.31 bouyer struct channel_softc *chp;
634 1.31 bouyer int mask, bits, timeout;
635 1.2 bouyer {
636 1.31 bouyer u_char status;
637 1.31 bouyer int time = 0;
638 1.31 bouyer #ifdef WDCNDELAY_DEBUG
639 1.31 bouyer extern int cold;
640 1.31 bouyer #endif
641 1.34 bouyer WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname,
642 1.34 bouyer chp->channel), DEBUG_STATUS);
643 1.31 bouyer chp->ch_error = 0;
644 1.31 bouyer
645 1.31 bouyer timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
646 1.2 bouyer
647 1.31 bouyer for (;;) {
648 1.31 bouyer chp->ch_status = status =
649 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status);
650 1.31 bouyer if ((status & WDCS_BSY) == 0 && (status & mask) == bits)
651 1.31 bouyer break;
652 1.31 bouyer if (++time > timeout) {
653 1.31 bouyer WDCDEBUG_PRINT(("wdcwait: timeout, status %x "
654 1.31 bouyer "error %x\n", status,
655 1.31 bouyer bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
656 1.31 bouyer wd_error)),
657 1.31 bouyer DEBUG_STATUS);
658 1.31 bouyer return -1;
659 1.31 bouyer }
660 1.31 bouyer delay(WDCDELAY);
661 1.2 bouyer }
662 1.31 bouyer if (status & WDCS_ERR)
663 1.31 bouyer chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
664 1.31 bouyer wd_error);
665 1.31 bouyer #ifdef WDCNDELAY_DEBUG
666 1.31 bouyer /* After autoconfig, there should be no long delays. */
667 1.31 bouyer if (!cold && time > WDCNDELAY_DEBUG) {
668 1.31 bouyer struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
669 1.31 bouyer if (xfer == NULL)
670 1.31 bouyer printf("%s channel %d: warning: busy-wait took %dus\n",
671 1.31 bouyer chp->wdc->sc_dev.dv_xname, chp->channel,
672 1.31 bouyer WDCDELAY * time);
673 1.31 bouyer else
674 1.31 bouyer printf("%s:%d:%d: warning: busy-wait took %dus\n",
675 1.49 bouyer chp->wdc->sc_dev.dv_xname, chp->channel,
676 1.31 bouyer xfer->drive,
677 1.31 bouyer WDCDELAY * time);
678 1.2 bouyer }
679 1.2 bouyer #endif
680 1.31 bouyer return 0;
681 1.2 bouyer }
682 1.2 bouyer
683 1.31 bouyer void
684 1.31 bouyer wdctimeout(arg)
685 1.31 bouyer void *arg;
686 1.2 bouyer {
687 1.31 bouyer struct channel_softc *chp = (struct channel_softc *)arg;
688 1.31 bouyer struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
689 1.31 bouyer int s;
690 1.2 bouyer
691 1.31 bouyer WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
692 1.31 bouyer
693 1.31 bouyer s = splbio();
694 1.31 bouyer if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
695 1.31 bouyer __wdcerror(chp, "lost interrupt");
696 1.31 bouyer printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ?
697 1.31 bouyer "atapi":"ata");
698 1.31 bouyer printf("\tc_bcount: %d\n", xfer->c_bcount);
699 1.31 bouyer printf("\tc_skip: %d\n", xfer->c_skip);
700 1.31 bouyer /*
701 1.31 bouyer * Call the interrupt routine. If we just missed and interrupt,
702 1.31 bouyer * it will do what's needed. Else, it will take the needed
703 1.31 bouyer * action (reset the device).
704 1.31 bouyer */
705 1.31 bouyer xfer->c_flags |= C_TIMEOU;
706 1.31 bouyer chp->ch_flags &= ~WDCF_IRQ_WAIT;
707 1.31 bouyer xfer->c_intr(chp, xfer);
708 1.31 bouyer } else
709 1.31 bouyer __wdcerror(chp, "missing untimeout");
710 1.31 bouyer splx(s);
711 1.2 bouyer }
712 1.2 bouyer
713 1.31 bouyer /*
714 1.31 bouyer * Probe drive's capabilites, for use by the controller later
715 1.31 bouyer * Assumes drvp points to an existing drive.
716 1.31 bouyer * XXX this should be a controller-indep function
717 1.31 bouyer */
718 1.2 bouyer void
719 1.31 bouyer wdc_probe_caps(drvp)
720 1.31 bouyer struct ata_drive_datas *drvp;
721 1.2 bouyer {
722 1.31 bouyer struct ataparams params, params2;
723 1.31 bouyer struct channel_softc *chp = drvp->chnl_softc;
724 1.31 bouyer struct device *drv_dev = drvp->drv_softc;
725 1.31 bouyer struct wdc_softc *wdc = chp->wdc;
726 1.31 bouyer int i, printed;
727 1.31 bouyer char *sep = "";
728 1.48 bouyer int cf_flags;
729 1.31 bouyer
730 1.31 bouyer if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) {
731 1.31 bouyer /* IDENTIFY failed. Can't tell more about the device */
732 1.2 bouyer return;
733 1.2 bouyer }
734 1.31 bouyer if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
735 1.31 bouyer (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
736 1.2 bouyer /*
737 1.39 bouyer * Controller claims 16 and 32 bit transfers.
738 1.39 bouyer * Re-do an IDENTIFY with 32-bit transfers,
739 1.31 bouyer * and compare results.
740 1.2 bouyer */
741 1.31 bouyer drvp->drive_flags |= DRIVE_CAP32;
742 1.31 bouyer ata_get_params(drvp, AT_POLL, ¶ms2);
743 1.31 bouyer if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) {
744 1.31 bouyer /* Not good. fall back to 16bits */
745 1.31 bouyer drvp->drive_flags &= ~DRIVE_CAP32;
746 1.31 bouyer } else {
747 1.39 bouyer printf("%s: 32-bits data port\n", drv_dev->dv_xname);
748 1.2 bouyer }
749 1.2 bouyer }
750 1.2 bouyer
751 1.31 bouyer /* An ATAPI device is at last PIO mode 3 */
752 1.31 bouyer if (drvp->drive_flags & DRIVE_ATAPI)
753 1.31 bouyer drvp->PIO_mode = 3;
754 1.2 bouyer
755 1.2 bouyer /*
756 1.31 bouyer * It's not in the specs, but it seems that some drive
757 1.31 bouyer * returns 0xffff in atap_extensions when this field is invalid
758 1.2 bouyer */
759 1.31 bouyer if (params.atap_extensions != 0xffff &&
760 1.31 bouyer (params.atap_extensions & WDC_EXT_MODES)) {
761 1.31 bouyer printed = 0;
762 1.31 bouyer /*
763 1.31 bouyer * XXX some drives report something wrong here (they claim to
764 1.31 bouyer * support PIO mode 8 !). As mode is coded on 3 bits in
765 1.31 bouyer * SET FEATURE, limit it to 7 (so limit i to 4).
766 1.39 bouyer * If higther mode than 7 is found, abort.
767 1.31 bouyer */
768 1.39 bouyer for (i = 7; i >= 0; i--) {
769 1.31 bouyer if ((params.atap_piomode_supp & (1 << i)) == 0)
770 1.31 bouyer continue;
771 1.39 bouyer if (i > 4)
772 1.39 bouyer return;
773 1.31 bouyer /*
774 1.31 bouyer * See if mode is accepted.
775 1.31 bouyer * If the controller can't set its PIO mode,
776 1.31 bouyer * assume the defaults are good, so don't try
777 1.31 bouyer * to set it
778 1.31 bouyer */
779 1.31 bouyer if ((wdc->cap & WDC_CAPABILITY_MODE) != 0)
780 1.31 bouyer if (ata_set_mode(drvp, 0x08 | (i + 3),
781 1.31 bouyer AT_POLL) != CMD_OK)
782 1.2 bouyer continue;
783 1.31 bouyer if (!printed) {
784 1.39 bouyer printf("%s: drive supports PIO mode %d",
785 1.39 bouyer drv_dev->dv_xname, i + 3);
786 1.31 bouyer sep = ",";
787 1.31 bouyer printed = 1;
788 1.31 bouyer }
789 1.31 bouyer /*
790 1.31 bouyer * If controller's driver can't set its PIO mode,
791 1.31 bouyer * get the highter one for the drive.
792 1.31 bouyer */
793 1.31 bouyer if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 ||
794 1.31 bouyer wdc->pio_mode >= i + 3) {
795 1.31 bouyer drvp->PIO_mode = i + 3;
796 1.48 bouyer drvp->PIO_cap = i + 3;
797 1.2 bouyer break;
798 1.2 bouyer }
799 1.2 bouyer }
800 1.31 bouyer if (!printed) {
801 1.31 bouyer /*
802 1.31 bouyer * We didn't find a valid PIO mode.
803 1.31 bouyer * Assume the values returned for DMA are buggy too
804 1.31 bouyer */
805 1.31 bouyer return;
806 1.2 bouyer }
807 1.35 bouyer drvp->drive_flags |= DRIVE_MODE;
808 1.31 bouyer printed = 0;
809 1.31 bouyer for (i = 7; i >= 0; i--) {
810 1.31 bouyer if ((params.atap_dmamode_supp & (1 << i)) == 0)
811 1.31 bouyer continue;
812 1.31 bouyer if ((wdc->cap & WDC_CAPABILITY_DMA) &&
813 1.31 bouyer (wdc->cap & WDC_CAPABILITY_MODE))
814 1.31 bouyer if (ata_set_mode(drvp, 0x20 | i, AT_POLL)
815 1.31 bouyer != CMD_OK)
816 1.31 bouyer continue;
817 1.31 bouyer if (!printed) {
818 1.31 bouyer printf("%s DMA mode %d", sep, i);
819 1.31 bouyer sep = ",";
820 1.31 bouyer printed = 1;
821 1.31 bouyer }
822 1.31 bouyer if (wdc->cap & WDC_CAPABILITY_DMA) {
823 1.31 bouyer if ((wdc->cap & WDC_CAPABILITY_MODE) &&
824 1.31 bouyer wdc->dma_mode < i)
825 1.31 bouyer continue;
826 1.31 bouyer drvp->DMA_mode = i;
827 1.48 bouyer drvp->DMA_cap = i;
828 1.31 bouyer drvp->drive_flags |= DRIVE_DMA;
829 1.31 bouyer }
830 1.2 bouyer break;
831 1.2 bouyer }
832 1.31 bouyer if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
833 1.31 bouyer for (i = 7; i >= 0; i--) {
834 1.31 bouyer if ((params.atap_udmamode_supp & (1 << i))
835 1.31 bouyer == 0)
836 1.31 bouyer continue;
837 1.31 bouyer if ((wdc->cap & WDC_CAPABILITY_MODE) &&
838 1.31 bouyer (wdc->cap & WDC_CAPABILITY_UDMA))
839 1.31 bouyer if (ata_set_mode(drvp, 0x40 | i,
840 1.31 bouyer AT_POLL) != CMD_OK)
841 1.31 bouyer continue;
842 1.51 bouyer printf("%s Ultra-DMA mode %d", sep, i);
843 1.31 bouyer sep = ",";
844 1.31 bouyer if (wdc->cap & WDC_CAPABILITY_UDMA) {
845 1.50 bouyer if ((wdc->cap & WDC_CAPABILITY_MODE) &&
846 1.50 bouyer wdc->udma_mode < i)
847 1.50 bouyer continue;
848 1.31 bouyer drvp->UDMA_mode = i;
849 1.48 bouyer drvp->UDMA_cap = i;
850 1.31 bouyer drvp->drive_flags |= DRIVE_UDMA;
851 1.31 bouyer }
852 1.31 bouyer break;
853 1.31 bouyer }
854 1.31 bouyer }
855 1.31 bouyer printf("\n");
856 1.48 bouyer }
857 1.48 bouyer cf_flags = drv_dev->dv_cfdata->cf_flags;
858 1.48 bouyer if (cf_flags & ATA_CONFIG_PIO_SET) {
859 1.48 bouyer drvp->PIO_mode =
860 1.48 bouyer (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
861 1.48 bouyer drvp->drive_flags |= DRIVE_MODE;
862 1.48 bouyer }
863 1.48 bouyer if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
864 1.48 bouyer /* don't care about DMA modes */
865 1.48 bouyer return;
866 1.48 bouyer }
867 1.48 bouyer if (cf_flags & ATA_CONFIG_DMA_SET) {
868 1.48 bouyer if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
869 1.48 bouyer ATA_CONFIG_DMA_DISABLE) {
870 1.48 bouyer drvp->drive_flags &= ~DRIVE_DMA;
871 1.48 bouyer } else {
872 1.48 bouyer drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
873 1.48 bouyer ATA_CONFIG_DMA_OFF;
874 1.48 bouyer drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
875 1.48 bouyer }
876 1.48 bouyer }
877 1.48 bouyer if (cf_flags & ATA_CONFIG_UDMA_SET) {
878 1.48 bouyer if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
879 1.48 bouyer ATA_CONFIG_UDMA_DISABLE) {
880 1.48 bouyer drvp->drive_flags &= ~DRIVE_UDMA;
881 1.48 bouyer } else {
882 1.48 bouyer drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
883 1.48 bouyer ATA_CONFIG_UDMA_OFF;
884 1.48 bouyer drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
885 1.48 bouyer }
886 1.2 bouyer }
887 1.2 bouyer }
888 1.2 bouyer
889 1.2 bouyer int
890 1.31 bouyer wdc_exec_command(drvp, wdc_c)
891 1.31 bouyer struct ata_drive_datas *drvp;
892 1.31 bouyer struct wdc_command *wdc_c;
893 1.31 bouyer {
894 1.31 bouyer struct channel_softc *chp = drvp->chnl_softc;
895 1.2 bouyer struct wdc_xfer *xfer;
896 1.31 bouyer int s, ret;
897 1.2 bouyer
898 1.34 bouyer WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
899 1.34 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
900 1.34 bouyer DEBUG_FUNCS);
901 1.2 bouyer
902 1.31 bouyer /* set up an xfer and queue. Wait for completion */
903 1.31 bouyer xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
904 1.31 bouyer WDC_NOSLEEP);
905 1.31 bouyer if (xfer == NULL) {
906 1.31 bouyer return WDC_TRY_AGAIN;
907 1.31 bouyer }
908 1.2 bouyer
909 1.31 bouyer if (wdc_c->flags & AT_POLL)
910 1.31 bouyer xfer->c_flags |= C_POLL;
911 1.31 bouyer xfer->drive = drvp->drive;
912 1.31 bouyer xfer->databuf = wdc_c->data;
913 1.31 bouyer xfer->c_bcount = wdc_c->bcount;
914 1.31 bouyer xfer->cmd = wdc_c;
915 1.31 bouyer xfer->c_start = __wdccommand_start;
916 1.31 bouyer xfer->c_intr = __wdccommand_intr;
917 1.2 bouyer
918 1.31 bouyer s = splbio();
919 1.31 bouyer wdc_exec_xfer(chp, xfer);
920 1.31 bouyer #ifdef DIAGNOSTIC
921 1.31 bouyer if ((wdc_c->flags & AT_POLL) != 0 &&
922 1.31 bouyer (wdc_c->flags & AT_DONE) == 0)
923 1.31 bouyer panic("wdc_exec_command: polled command not done\n");
924 1.2 bouyer #endif
925 1.31 bouyer if (wdc_c->flags & AT_DONE) {
926 1.31 bouyer ret = WDC_COMPLETE;
927 1.31 bouyer } else {
928 1.31 bouyer if (wdc_c->flags & AT_WAIT) {
929 1.31 bouyer tsleep(wdc_c, PRIBIO, "wdccmd", 0);
930 1.31 bouyer ret = WDC_COMPLETE;
931 1.31 bouyer } else {
932 1.31 bouyer ret = WDC_QUEUED;
933 1.2 bouyer }
934 1.2 bouyer }
935 1.31 bouyer splx(s);
936 1.31 bouyer return ret;
937 1.2 bouyer }
938 1.2 bouyer
939 1.2 bouyer void
940 1.31 bouyer __wdccommand_start(chp, xfer)
941 1.31 bouyer struct channel_softc *chp;
942 1.2 bouyer struct wdc_xfer *xfer;
943 1.31 bouyer {
944 1.31 bouyer int drive = xfer->drive;
945 1.31 bouyer struct wdc_command *wdc_c = xfer->cmd;
946 1.31 bouyer
947 1.34 bouyer WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
948 1.34 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
949 1.34 bouyer DEBUG_FUNCS);
950 1.31 bouyer
951 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
952 1.31 bouyer WDSD_IBM | (drive << 4));
953 1.31 bouyer if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask,
954 1.31 bouyer wdc_c->timeout) != 0) {
955 1.31 bouyer wdc_c->flags |= AT_TIMEOU;
956 1.31 bouyer __wdccommand_done(chp, xfer);
957 1.31 bouyer }
958 1.31 bouyer wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
959 1.31 bouyer wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp);
960 1.31 bouyer if ((wdc_c->flags & AT_POLL) == 0) {
961 1.31 bouyer chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
962 1.31 bouyer timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz);
963 1.31 bouyer return;
964 1.2 bouyer }
965 1.2 bouyer /*
966 1.31 bouyer * Polled command. Wait for drive ready or drq. Done in intr().
967 1.31 bouyer * Wait for at last 400ns for status bit to be valid.
968 1.2 bouyer */
969 1.31 bouyer delay(10);
970 1.31 bouyer if (__wdccommand_intr(chp, xfer) == 0) {
971 1.31 bouyer wdc_c->flags |= AT_TIMEOU;
972 1.31 bouyer __wdccommand_done(chp, xfer);
973 1.2 bouyer }
974 1.2 bouyer }
975 1.2 bouyer
976 1.2 bouyer int
977 1.31 bouyer __wdccommand_intr(chp, xfer)
978 1.31 bouyer struct channel_softc *chp;
979 1.31 bouyer struct wdc_xfer *xfer;
980 1.2 bouyer {
981 1.31 bouyer struct wdc_command *wdc_c = xfer->cmd;
982 1.31 bouyer int bcount = wdc_c->bcount;
983 1.31 bouyer char *data = wdc_c->data;
984 1.31 bouyer
985 1.34 bouyer WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
986 1.34 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR);
987 1.31 bouyer if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
988 1.31 bouyer wdc_c->timeout)) {
989 1.31 bouyer wdc_c->flags |= AT_ERROR;
990 1.31 bouyer __wdccommand_done(chp, xfer);
991 1.2 bouyer return 1;
992 1.2 bouyer }
993 1.31 bouyer if (wdc_c->flags & AT_READ) {
994 1.31 bouyer if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) {
995 1.31 bouyer bus_space_read_multi_4(chp->data32iot, chp->data32ioh,
996 1.31 bouyer 0, (u_int32_t*)data, bcount >> 2);
997 1.31 bouyer data += bcount & 0xfffffffc;
998 1.31 bouyer bcount = bcount & 0x03;
999 1.31 bouyer }
1000 1.31 bouyer if (bcount > 0)
1001 1.31 bouyer bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh,
1002 1.31 bouyer wd_data, (u_int16_t *)data, bcount >> 1);
1003 1.31 bouyer } else if (wdc_c->flags & AT_WRITE) {
1004 1.31 bouyer if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) {
1005 1.31 bouyer bus_space_write_multi_4(chp->data32iot, chp->data32ioh,
1006 1.31 bouyer 0, (u_int32_t*)data, bcount >> 2);
1007 1.31 bouyer data += bcount & 0xfffffffc;
1008 1.31 bouyer bcount = bcount & 0x03;
1009 1.31 bouyer }
1010 1.31 bouyer if (bcount > 0)
1011 1.31 bouyer bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh,
1012 1.31 bouyer wd_data, (u_int16_t *)data, bcount >> 1);
1013 1.2 bouyer }
1014 1.31 bouyer __wdccommand_done(chp, xfer);
1015 1.31 bouyer return 1;
1016 1.2 bouyer }
1017 1.2 bouyer
1018 1.2 bouyer void
1019 1.31 bouyer __wdccommand_done(chp, xfer)
1020 1.31 bouyer struct channel_softc *chp;
1021 1.31 bouyer struct wdc_xfer *xfer;
1022 1.2 bouyer {
1023 1.31 bouyer int needdone = xfer->c_flags & C_NEEDDONE;
1024 1.31 bouyer struct wdc_command *wdc_c = xfer->cmd;
1025 1.2 bouyer
1026 1.34 bouyer WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n",
1027 1.34 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS);
1028 1.31 bouyer if (chp->ch_status & WDCS_DWF)
1029 1.31 bouyer wdc_c->flags |= AT_DF;
1030 1.31 bouyer if (chp->ch_status & WDCS_ERR) {
1031 1.31 bouyer wdc_c->flags |= AT_ERROR;
1032 1.31 bouyer wdc_c->r_error = chp->ch_error;
1033 1.31 bouyer }
1034 1.31 bouyer wdc_c->flags |= AT_DONE;
1035 1.46 kenh if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF))
1036 1.46 kenh == 0) {
1037 1.46 kenh wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1038 1.46 kenh wd_sdh);
1039 1.46 kenh wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1040 1.46 kenh wd_cyl_hi) << 8;
1041 1.46 kenh wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1042 1.46 kenh wd_cyl_lo);
1043 1.46 kenh wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1044 1.46 kenh wd_sector);
1045 1.46 kenh wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1046 1.46 kenh wd_seccnt);
1047 1.46 kenh wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1048 1.46 kenh wd_error);
1049 1.46 kenh wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1050 1.46 kenh wd_precomp);
1051 1.46 kenh }
1052 1.31 bouyer wdc_free_xfer(chp, xfer);
1053 1.31 bouyer if (needdone) {
1054 1.31 bouyer if (wdc_c->flags & AT_WAIT)
1055 1.31 bouyer wakeup(wdc_c);
1056 1.31 bouyer else
1057 1.31 bouyer wdc_c->callback(wdc_c->callback_arg);
1058 1.2 bouyer }
1059 1.45 drochner wdcstart(chp);
1060 1.31 bouyer return;
1061 1.2 bouyer }
1062 1.2 bouyer
1063 1.2 bouyer /*
1064 1.31 bouyer * Send a command. The drive should be ready.
1065 1.2 bouyer * Assumes interrupts are blocked.
1066 1.2 bouyer */
1067 1.31 bouyer void
1068 1.31 bouyer wdccommand(chp, drive, command, cylin, head, sector, count, precomp)
1069 1.31 bouyer struct channel_softc *chp;
1070 1.31 bouyer u_int8_t drive;
1071 1.31 bouyer u_int8_t command;
1072 1.31 bouyer u_int16_t cylin;
1073 1.31 bouyer u_int8_t head, sector, count, precomp;
1074 1.31 bouyer {
1075 1.31 bouyer WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1076 1.31 bouyer "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname,
1077 1.31 bouyer chp->channel, drive, command, cylin, head, sector, count, precomp),
1078 1.31 bouyer DEBUG_FUNCS);
1079 1.31 bouyer
1080 1.31 bouyer /* Select drive, head, and addressing mode. */
1081 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
1082 1.31 bouyer WDSD_IBM | (drive << 4) | head);
1083 1.31 bouyer /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */
1084 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp,
1085 1.31 bouyer precomp);
1086 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin);
1087 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8);
1088 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector);
1089 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count);
1090 1.2 bouyer
1091 1.31 bouyer /* Send command. */
1092 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command);
1093 1.31 bouyer return;
1094 1.2 bouyer }
1095 1.2 bouyer
1096 1.2 bouyer /*
1097 1.31 bouyer * Simplified version of wdccommand(). Unbusy/ready/drq must be
1098 1.31 bouyer * tested by the caller.
1099 1.2 bouyer */
1100 1.31 bouyer void
1101 1.31 bouyer wdccommandshort(chp, drive, command)
1102 1.31 bouyer struct channel_softc *chp;
1103 1.31 bouyer int drive;
1104 1.31 bouyer int command;
1105 1.2 bouyer {
1106 1.2 bouyer
1107 1.31 bouyer WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1108 1.31 bouyer chp->wdc->sc_dev.dv_xname, chp->channel, drive, command),
1109 1.31 bouyer DEBUG_FUNCS);
1110 1.2 bouyer
1111 1.31 bouyer /* Select drive. */
1112 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
1113 1.31 bouyer WDSD_IBM | (drive << 4));
1114 1.2 bouyer
1115 1.31 bouyer bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command);
1116 1.31 bouyer }
1117 1.2 bouyer
1118 1.31 bouyer /* Add a command to the queue and start controller. Must be called at splbio */
1119 1.2 bouyer
1120 1.2 bouyer void
1121 1.31 bouyer wdc_exec_xfer(chp, xfer)
1122 1.31 bouyer struct channel_softc *chp;
1123 1.2 bouyer struct wdc_xfer *xfer;
1124 1.2 bouyer {
1125 1.33 bouyer WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer,
1126 1.33 bouyer chp->channel, xfer->drive), DEBUG_XFERS);
1127 1.2 bouyer
1128 1.31 bouyer /* complete xfer setup */
1129 1.49 bouyer xfer->chp = chp;
1130 1.2 bouyer
1131 1.31 bouyer /*
1132 1.31 bouyer * If we are a polled command, and the list is not empty,
1133 1.31 bouyer * we are doing a dump. Drop the list to allow the polled command
1134 1.31 bouyer * to complete, we're going to reboot soon anyway.
1135 1.31 bouyer */
1136 1.31 bouyer if ((xfer->c_flags & C_POLL) != 0 &&
1137 1.31 bouyer chp->ch_queue->sc_xfer.tqh_first != NULL) {
1138 1.31 bouyer TAILQ_INIT(&chp->ch_queue->sc_xfer);
1139 1.31 bouyer }
1140 1.2 bouyer /* insert at the end of command list */
1141 1.31 bouyer TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain);
1142 1.31 bouyer WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
1143 1.33 bouyer chp->ch_flags), DEBUG_XFERS);
1144 1.45 drochner wdcstart(chp);
1145 1.2 bouyer xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */
1146 1.31 bouyer }
1147 1.2 bouyer
1148 1.2 bouyer struct wdc_xfer *
1149 1.2 bouyer wdc_get_xfer(flags)
1150 1.2 bouyer int flags;
1151 1.2 bouyer {
1152 1.2 bouyer struct wdc_xfer *xfer;
1153 1.2 bouyer int s;
1154 1.2 bouyer
1155 1.2 bouyer s = splbio();
1156 1.2 bouyer if ((xfer = xfer_free_list.lh_first) != NULL) {
1157 1.2 bouyer LIST_REMOVE(xfer, free_list);
1158 1.2 bouyer splx(s);
1159 1.2 bouyer #ifdef DIAGNOSTIC
1160 1.2 bouyer if ((xfer->c_flags & C_INUSE) != 0)
1161 1.2 bouyer panic("wdc_get_xfer: xfer already in use\n");
1162 1.2 bouyer #endif
1163 1.2 bouyer } else {
1164 1.2 bouyer splx(s);
1165 1.31 bouyer WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS);
1166 1.2 bouyer xfer = malloc(sizeof(*xfer), M_DEVBUF,
1167 1.31 bouyer ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK));
1168 1.2 bouyer if (xfer == NULL)
1169 1.2 bouyer return 0;
1170 1.2 bouyer #ifdef DIAGNOSTIC
1171 1.2 bouyer xfer->c_flags &= ~C_INUSE;
1172 1.2 bouyer #endif
1173 1.31 bouyer #ifdef WDCDEBUG
1174 1.2 bouyer wdc_nxfer++;
1175 1.2 bouyer #endif
1176 1.2 bouyer }
1177 1.2 bouyer #ifdef DIAGNOSTIC
1178 1.2 bouyer if ((xfer->c_flags & C_INUSE) != 0)
1179 1.2 bouyer panic("wdc_get_xfer: xfer already in use\n");
1180 1.2 bouyer #endif
1181 1.31 bouyer memset(xfer, 0, sizeof(struct wdc_xfer));
1182 1.2 bouyer xfer->c_flags = C_INUSE;
1183 1.2 bouyer return xfer;
1184 1.2 bouyer }
1185 1.2 bouyer
1186 1.2 bouyer void
1187 1.31 bouyer wdc_free_xfer(chp, xfer)
1188 1.31 bouyer struct channel_softc *chp;
1189 1.2 bouyer struct wdc_xfer *xfer;
1190 1.2 bouyer {
1191 1.31 bouyer struct wdc_softc *wdc = chp->wdc;
1192 1.2 bouyer int s;
1193 1.2 bouyer
1194 1.31 bouyer if (wdc->cap & WDC_CAPABILITY_HWLOCK)
1195 1.31 bouyer (*wdc->free_hw)(chp);
1196 1.2 bouyer s = splbio();
1197 1.31 bouyer chp->ch_flags &= ~WDCF_ACTIVE;
1198 1.31 bouyer TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain);
1199 1.2 bouyer xfer->c_flags &= ~C_INUSE;
1200 1.2 bouyer LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list);
1201 1.2 bouyer splx(s);
1202 1.2 bouyer }
1203 1.2 bouyer
1204 1.31 bouyer static void
1205 1.31 bouyer __wdcerror(chp, msg)
1206 1.31 bouyer struct channel_softc *chp;
1207 1.2 bouyer char *msg;
1208 1.2 bouyer {
1209 1.31 bouyer struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first;
1210 1.2 bouyer if (xfer == NULL)
1211 1.31 bouyer printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel,
1212 1.31 bouyer msg);
1213 1.2 bouyer else
1214 1.31 bouyer printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname,
1215 1.49 bouyer chp->channel, xfer->drive, msg);
1216 1.2 bouyer }
1217 1.2 bouyer
1218 1.2 bouyer /*
1219 1.2 bouyer * the bit bucket
1220 1.2 bouyer */
1221 1.2 bouyer void
1222 1.31 bouyer wdcbit_bucket(chp, size)
1223 1.31 bouyer struct channel_softc *chp;
1224 1.2 bouyer int size;
1225 1.2 bouyer {
1226 1.2 bouyer
1227 1.12 cgd for (; size >= 2; size -= 2)
1228 1.31 bouyer (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data);
1229 1.12 cgd if (size)
1230 1.31 bouyer (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data);
1231 1.44 thorpej }
1232 1.44 thorpej
1233 1.44 thorpej int
1234 1.44 thorpej wdc_addref(chp)
1235 1.44 thorpej struct channel_softc *chp;
1236 1.44 thorpej {
1237 1.44 thorpej struct wdc_softc *wdc = chp->wdc;
1238 1.44 thorpej struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter;
1239 1.44 thorpej int s, error = 0;
1240 1.44 thorpej
1241 1.44 thorpej s = splbio();
1242 1.44 thorpej if (adapter->scsipi_refcnt++ == 0 &&
1243 1.44 thorpej adapter->scsipi_enable != NULL) {
1244 1.44 thorpej error = (*adapter->scsipi_enable)(wdc, 1);
1245 1.44 thorpej if (error)
1246 1.44 thorpej adapter->scsipi_refcnt--;
1247 1.44 thorpej }
1248 1.44 thorpej splx(s);
1249 1.44 thorpej return (error);
1250 1.44 thorpej }
1251 1.44 thorpej
1252 1.44 thorpej void
1253 1.44 thorpej wdc_delref(chp)
1254 1.44 thorpej struct channel_softc *chp;
1255 1.44 thorpej {
1256 1.44 thorpej struct wdc_softc *wdc = chp->wdc;
1257 1.44 thorpej struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter;
1258 1.44 thorpej int s;
1259 1.44 thorpej
1260 1.44 thorpej s = splbio();
1261 1.44 thorpej if (adapter->scsipi_refcnt-- == 1 &&
1262 1.44 thorpej adapter->scsipi_enable != NULL)
1263 1.44 thorpej (void) (*adapter->scsipi_enable)(wdc, 0);
1264 1.44 thorpej splx(s);
1265 1.2 bouyer }
1266