wdc.c revision 1.101
1 /* $NetBSD: wdc.c,v 1.101 2001/11/14 20:18:11 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.101 2001/11/14 20:18:11 bouyer Exp $"); 76 77 #ifndef WDCDEBUG 78 #define WDCDEBUG 79 #endif /* WDCDEBUG */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/conf.h> 85 #include <sys/buf.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/pool.h> 89 #include <sys/syslog.h> 90 #include <sys/proc.h> 91 92 #include <machine/intr.h> 93 #include <machine/bus.h> 94 95 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 96 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 97 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 98 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 99 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 100 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 101 102 #include <dev/ata/atavar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "atapibus.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 struct pool wdc_xfer_pool; 117 118 static void __wdcerror __P((struct channel_softc*, char *)); 119 static int __wdcwait_reset __P((struct channel_softc *, int)); 120 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 121 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 122 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 123 int wdprint __P((void *, const char *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #define DEBUG_DELAY 0x40 133 #ifdef WDCDEBUG 134 int wdcdebug_mask = 0; 135 int wdc_nxfer = 0; 136 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 137 #else 138 #define WDCDEBUG_PRINT(args, level) 139 #endif 140 141 int 142 wdprint(aux, pnp) 143 void *aux; 144 const char *pnp; 145 { 146 struct ata_atapi_attach *aa_link = aux; 147 if (pnp) 148 printf("drive at %s", pnp); 149 printf(" channel %d drive %d", aa_link->aa_channel, 150 aa_link->aa_drv_data->drive); 151 return (UNCONF); 152 } 153 154 int 155 atapiprint(aux, pnp) 156 void *aux; 157 const char *pnp; 158 { 159 struct ata_atapi_attach *aa_link = aux; 160 if (pnp) 161 printf("atapibus at %s", pnp); 162 printf(" channel %d", aa_link->aa_channel); 163 return (UNCONF); 164 } 165 166 /* Test to see controller with at last one attached drive is there. 167 * Returns a bit for each possible drive found (0x01 for drive 0, 168 * 0x02 for drive 1). 169 * Logic: 170 * - If a status register is at 0xff, assume there is no drive here 171 * (ISA has pull-up resistors). Similarly if the status register has 172 * the value we last wrote to the bus (for IDE interfaces without pullups). 173 * If no drive at all -> return. 174 * - reset the controller, wait for it to complete (may take up to 31s !). 175 * If timeout -> return. 176 * - test ATA/ATAPI signatures. If at last one drive found -> return. 177 * - try an ATA command on the master. 178 */ 179 180 int 181 wdcprobe(chp) 182 struct channel_softc *chp; 183 { 184 u_int8_t st0, st1, sc, sn, cl, ch; 185 u_int8_t ret_value = 0x03; 186 u_int8_t drive; 187 int found; 188 189 /* 190 * Sanity check to see if the wdc channel responds at all. 191 */ 192 193 if (chp->wdc == NULL || 194 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM); 197 delay(10); 198 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 200 WDSD_IBM | 0x10); 201 delay(10); 202 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 203 204 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 205 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 206 chp->channel, st0, st1), DEBUG_PROBE); 207 208 if (st0 == 0xff || st0 == WDSD_IBM) 209 ret_value &= ~0x01; 210 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 211 ret_value &= ~0x02; 212 if (ret_value == 0) 213 return 0; 214 } 215 216 /* assert SRST, wait for reset to complete */ 217 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 218 WDSD_IBM); 219 delay(10); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 221 WDCTL_RST | WDCTL_IDS); 222 DELAY(1000); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 224 WDCTL_IDS); 225 delay(1000); 226 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 227 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 228 delay(10); 229 230 ret_value = __wdcwait_reset(chp, ret_value); 231 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 232 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 233 ret_value), DEBUG_PROBE); 234 235 /* if reset failed, there's nothing here */ 236 if (ret_value == 0) 237 return 0; 238 239 /* 240 * Test presence of drives. First test register signatures looking for 241 * ATAPI devices. If it's not an ATAPI and reset said there may be 242 * something here assume it's ATA or OLD. Ghost will be killed later in 243 * attach routine. 244 */ 245 found = 0; 246 for (drive = 0; drive < 2; drive++) { 247 if ((ret_value & (0x01 << drive)) == 0) 248 continue; 249 if (1 < ++found && chp->wdc != NULL && 250 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 251 /* 252 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 253 * is set. 254 * 255 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 256 * doesn't seem to implement drive select command. In 257 * this case, you can't eliminate ghost drive properly. 258 */ 259 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 260 chp->wdc->sc_dev.dv_xname, 261 chp->channel, drive), DEBUG_PROBE); 262 break; 263 } 264 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 265 WDSD_IBM | (drive << 4)); 266 delay(10); 267 /* Save registers contents */ 268 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 269 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 270 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 271 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 272 273 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 274 "cl=0x%x ch=0x%x\n", 275 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 276 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 277 /* 278 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 279 * we get wrong values here, so ignore it. 280 */ 281 if (cl == 0x14 && ch == 0xeb) { 282 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 283 } else { 284 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 285 if (chp->wdc == NULL || 286 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 287 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 288 } 289 } 290 return (ret_value); 291 } 292 293 void 294 wdcattach(chp) 295 struct channel_softc *chp; 296 { 297 int channel_flags, ctrl_flags, i, error; 298 struct ata_atapi_attach aa_link; 299 struct ataparams params; 300 static int inited = 0; 301 302 callout_init(&chp->ch_callout); 303 304 if ((error = wdc_addref(chp)) != 0) { 305 printf("%s: unable to enable controller\n", 306 chp->wdc->sc_dev.dv_xname); 307 return; 308 } 309 310 if (wdcprobe(chp) == 0) 311 /* If no drives, abort attach here. */ 312 goto out; 313 314 /* initialise global data */ 315 if (inited == 0) { 316 /* Initialize the wdc_xfer pool. */ 317 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 318 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 319 inited++; 320 } 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 323 for (i = 0; i < 2; i++) { 324 chp->ch_drive[i].chnl_softc = chp; 325 chp->ch_drive[i].drive = i; 326 /* 327 * Init error counter so that an error withing the first xfers 328 * will trigger a downgrade 329 */ 330 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 331 332 /* If controller can't do 16bit flag the drives as 32bit */ 333 if ((chp->wdc->cap & 334 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 335 WDC_CAPABILITY_DATA32) 336 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 337 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 338 continue; 339 340 /* 341 * Wait a bit, some devices are weird just after a reset. 342 * Then issue a IDENTIFY command, to try to detect slave ghost 343 */ 344 delay(100); 345 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 346 if (error != CMD_OK) { 347 delay(1000000); 348 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 349 ¶ms); 350 } 351 if (error == CMD_OK) { 352 /* If IDENTIFY succeded, this is not an OLD ctrl */ 353 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 354 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 355 } else { 356 chp->ch_drive[i].drive_flags &= 357 ~(DRIVE_ATA | DRIVE_ATAPI); 358 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 359 chp->wdc->sc_dev.dv_xname, 360 chp->channel, i, error), DEBUG_PROBE); 361 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 362 continue; 363 /* 364 * Pre-ATA drive ? 365 * Test registers writability (Error register not 366 * writable, but cyllo is), then try an ATA command. 367 */ 368 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 369 WDSD_IBM | (i << 4)); 370 delay(10); 371 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 372 wd_error, 0x58); 373 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 374 wd_cyl_lo, 0xa5); 375 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 376 wd_error == 0x58) || 377 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 378 wd_cyl_lo) != 0xa5) { 379 WDCDEBUG_PRINT(("%s:%d:%d: register " 380 "writability failed\n", 381 chp->wdc->sc_dev.dv_xname, 382 chp->channel, i), DEBUG_PROBE); 383 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 384 } 385 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 386 WDSD_IBM | (i << 4)); 387 delay(100); 388 if (wait_for_ready(chp, 10000) != 0) { 389 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 390 chp->wdc->sc_dev.dv_xname, 391 chp->channel, i), DEBUG_PROBE); 392 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 393 continue; 394 } 395 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 396 wd_command, WDCC_RECAL); 397 if (wait_for_ready(chp, 10000) != 0) { 398 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 399 chp->wdc->sc_dev.dv_xname, 400 chp->channel, i), DEBUG_PROBE); 401 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 402 } 403 } 404 } 405 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 406 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 407 408 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 409 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 410 DEBUG_PROBE); 411 412 /* If no drives, abort here */ 413 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 414 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 415 goto out; 416 417 /* 418 * Attach an ATAPI bus, if needed. 419 */ 420 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 421 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 422 #if NATAPIBUS > 0 423 wdc_atapibus_attach(chp); 424 #else 425 /* 426 * Fills in a fake aa_link and call config_found, so that 427 * the config machinery will print 428 * "atapibus at xxx not configured" 429 */ 430 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 431 aa_link.aa_type = T_ATAPI; 432 aa_link.aa_channel = chp->channel; 433 aa_link.aa_openings = 1; 434 aa_link.aa_drv_data = 0; 435 aa_link.aa_bus_private = NULL; 436 chp->atapibus = config_found(&chp->wdc->sc_dev, 437 (void *)&aa_link, atapiprint); 438 #endif 439 } 440 441 for (i = 0; i < 2; i++) { 442 if ((chp->ch_drive[i].drive_flags & 443 (DRIVE_ATA | DRIVE_OLD)) == 0) { 444 continue; 445 } 446 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 447 aa_link.aa_type = T_ATA; 448 aa_link.aa_channel = chp->channel; 449 aa_link.aa_openings = 1; 450 aa_link.aa_drv_data = &chp->ch_drive[i]; 451 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 452 wdc_probe_caps(&chp->ch_drive[i]); 453 } 454 455 /* 456 * reset drive_flags for unnatached devices, reset state for attached 457 * ones 458 */ 459 for (i = 0; i < 2; i++) { 460 if (chp->ch_drive[i].drv_softc == NULL) 461 chp->ch_drive[i].drive_flags = 0; 462 else 463 chp->ch_drive[i].state = 0; 464 } 465 466 /* 467 * Reset channel. The probe, with some combinations of ATA/ATAPI 468 * devices keep it in a mostly working, but strange state (with busy 469 * led on) 470 */ 471 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 472 delay(50); 473 wdcreset(chp, VERBOSE); 474 /* 475 * Read status registers to avoid spurious interrupts. 476 */ 477 for (i = 1; i >= 0; i--) { 478 if (chp->ch_drive[i].drive_flags & DRIVE) { 479 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 480 wd_sdh, WDSD_IBM | (i << 4)); 481 if (wait_for_unbusy(chp, 10000) < 0) 482 printf("%s:%d:%d: device busy\n", 483 chp->wdc->sc_dev.dv_xname, 484 chp->channel, i); 485 } 486 } 487 } 488 489 out: 490 wdc_delref(chp); 491 } 492 493 /* 494 * Call activate routine of underlying devices. 495 */ 496 int 497 wdcactivate(self, act) 498 struct device *self; 499 enum devact act; 500 { 501 struct wdc_softc *wdc = (struct wdc_softc *)self; 502 struct channel_softc *chp; 503 struct device *sc = 0; 504 int s, i, j, error = 0; 505 506 s = splbio(); 507 switch (act) { 508 case DVACT_ACTIVATE: 509 error = EOPNOTSUPP; 510 break; 511 512 case DVACT_DEACTIVATE: 513 for (i = 0; i < wdc->nchannels; i++) { 514 chp = wdc->channels[i]; 515 516 /* 517 * We might call deactivate routine for 518 * the children of atapibus twice (once via 519 * atapibus, once directly), but since 520 * config_deactivate maintains DVF_ACTIVE flag, 521 * it's safe. 522 */ 523 sc = chp->atapibus; 524 if (sc != NULL) { 525 error = config_deactivate(sc); 526 if (error != 0) 527 goto out; 528 } 529 530 for (j = 0; j < 2; j++) { 531 sc = chp->ch_drive[j].drv_softc; 532 WDCDEBUG_PRINT(("wdcactivate: %s:" 533 " deactivating %s\n", wdc->sc_dev.dv_xname, 534 sc == NULL ? "nodrv" : sc->dv_xname), 535 DEBUG_DETACH); 536 if (sc != NULL) { 537 error = config_deactivate(sc); 538 if (error != 0) 539 goto out; 540 } 541 } 542 } 543 break; 544 } 545 546 out: 547 splx(s); 548 549 #ifdef WDCDEBUG 550 if (sc && error != 0) 551 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 552 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 553 #endif 554 return (error); 555 } 556 557 int 558 wdcdetach(self, flags) 559 struct device *self; 560 int flags; 561 { 562 struct wdc_softc *wdc = (struct wdc_softc *)self; 563 struct channel_softc *chp; 564 struct device *sc = 0; 565 int i, j, error = 0; 566 567 for (i = 0; i < wdc->nchannels; i++) { 568 chp = wdc->channels[i]; 569 570 /* 571 * Detach atapibus and its children. 572 */ 573 sc = chp->atapibus; 574 if (sc != NULL) { 575 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 576 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 577 error = config_detach(sc, flags); 578 if (error != 0) 579 goto out; 580 } 581 582 /* 583 * Detach our other children. 584 */ 585 for (j = 0; j < 2; j++) { 586 sc = chp->ch_drive[j].drv_softc; 587 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 588 wdc->sc_dev.dv_xname, 589 sc == NULL ? "nodrv" : sc->dv_xname), 590 DEBUG_DETACH); 591 if (sc != NULL) { 592 error = config_detach(sc, flags); 593 if (error != 0) 594 goto out; 595 } 596 } 597 598 wdc_kill_pending(chp); 599 } 600 601 out: 602 #ifdef WDCDEBUG 603 if (sc && error != 0) 604 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 605 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 606 #endif 607 return (error); 608 } 609 610 /* 611 * Start I/O on a controller, for the given channel. 612 * The first xfer may be not for our channel if the channel queues 613 * are shared. 614 */ 615 void 616 wdcstart(chp) 617 struct channel_softc *chp; 618 { 619 struct wdc_xfer *xfer; 620 621 #ifdef WDC_DIAGNOSTIC 622 int spl1, spl2; 623 624 spl1 = splbio(); 625 spl2 = splbio(); 626 if (spl2 != spl1) { 627 printf("wdcstart: not at splbio()\n"); 628 panic("wdcstart"); 629 } 630 splx(spl2); 631 splx(spl1); 632 #endif /* WDC_DIAGNOSTIC */ 633 634 /* is there a xfer ? */ 635 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 636 return; 637 638 /* adjust chp, in case we have a shared queue */ 639 chp = xfer->chp; 640 641 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 642 return; /* channel aleady active */ 643 } 644 #ifdef DIAGNOSTIC 645 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 646 panic("wdcstart: channel waiting for irq\n"); 647 #endif 648 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 649 if (!(*chp->wdc->claim_hw)(chp, 0)) 650 return; 651 652 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 653 chp->channel, xfer->drive), DEBUG_XFERS); 654 chp->ch_flags |= WDCF_ACTIVE; 655 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 656 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 657 chp->ch_drive[xfer->drive].state = 0; 658 } 659 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 660 KASSERT(xfer->c_flags & C_POLL); 661 xfer->c_start(chp, xfer); 662 } 663 664 /* restart an interrupted I/O */ 665 void 666 wdcrestart(v) 667 void *v; 668 { 669 struct channel_softc *chp = v; 670 int s; 671 672 s = splbio(); 673 wdcstart(chp); 674 splx(s); 675 } 676 677 678 /* 679 * Interrupt routine for the controller. Acknowledge the interrupt, check for 680 * errors on the current operation, mark it done if necessary, and start the 681 * next request. Also check for a partially done transfer, and continue with 682 * the next chunk if so. 683 */ 684 int 685 wdcintr(arg) 686 void *arg; 687 { 688 struct channel_softc *chp = arg; 689 struct wdc_xfer *xfer; 690 int ret; 691 692 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 693 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 694 DEBUG_INTR); 695 return (0); 696 } 697 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 698 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 699 return (0); 700 } 701 702 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 703 xfer = chp->ch_queue->sc_xfer.tqh_first; 704 if (chp->ch_flags & WDCF_DMA_WAIT) { 705 chp->wdc->dma_status = 706 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 707 xfer->drive, 0); 708 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 709 /* IRQ not for us, not detected by DMA engine */ 710 return 0; 711 } 712 chp->ch_flags &= ~WDCF_DMA_WAIT; 713 } 714 chp->ch_flags &= ~WDCF_IRQ_WAIT; 715 ret = xfer->c_intr(chp, xfer, 1); 716 if (ret == 0) /* irq was not for us, still waiting for irq */ 717 chp->ch_flags |= WDCF_IRQ_WAIT; 718 return (ret); 719 } 720 721 /* Put all disk in RESET state */ 722 void wdc_reset_channel(drvp) 723 struct ata_drive_datas *drvp; 724 { 725 struct channel_softc *chp = drvp->chnl_softc; 726 int drive; 727 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 728 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 729 DEBUG_FUNCS); 730 (void) wdcreset(chp, VERBOSE); 731 for (drive = 0; drive < 2; drive++) { 732 chp->ch_drive[drive].state = 0; 733 } 734 } 735 736 int 737 wdcreset(chp, verb) 738 struct channel_softc *chp; 739 int verb; 740 { 741 int drv_mask1, drv_mask2; 742 743 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 744 WDSD_IBM); /* master */ 745 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 746 WDCTL_RST | WDCTL_IDS); 747 delay(1000); 748 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 749 WDCTL_IDS); 750 delay(1000); 751 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 752 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 753 WDCTL_4BIT); 754 755 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 756 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 757 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 758 if (verb && drv_mask2 != drv_mask1) { 759 printf("%s channel %d: reset failed for", 760 chp->wdc->sc_dev.dv_xname, chp->channel); 761 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 762 printf(" drive 0"); 763 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 764 printf(" drive 1"); 765 printf("\n"); 766 } 767 return (drv_mask1 != drv_mask2) ? 1 : 0; 768 } 769 770 static int 771 __wdcwait_reset(chp, drv_mask) 772 struct channel_softc *chp; 773 int drv_mask; 774 { 775 int timeout; 776 u_int8_t st0, st1; 777 #ifdef WDCDEBUG 778 u_int8_t sc0, sn0, cl0, ch0; 779 u_int8_t sc1, sn1, cl1, ch1; 780 #endif 781 /* wait for BSY to deassert */ 782 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 783 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 784 WDSD_IBM); /* master */ 785 delay(10); 786 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 787 #ifdef WDCDEBUG 788 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 789 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 790 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 791 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 792 #endif 793 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 794 WDSD_IBM | 0x10); /* slave */ 795 delay(10); 796 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 797 #ifdef WDCDEBUG 798 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 799 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 800 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 801 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 802 #endif 803 804 if ((drv_mask & 0x01) == 0) { 805 /* no master */ 806 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 807 /* No master, slave is ready, it's done */ 808 goto end; 809 } 810 } else if ((drv_mask & 0x02) == 0) { 811 /* no slave */ 812 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 813 /* No slave, master is ready, it's done */ 814 goto end; 815 } 816 } else { 817 /* Wait for both master and slave to be ready */ 818 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 819 goto end; 820 } 821 } 822 delay(WDCDELAY); 823 } 824 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 825 if (st0 & WDCS_BSY) 826 drv_mask &= ~0x01; 827 if (st1 & WDCS_BSY) 828 drv_mask &= ~0x02; 829 end: 830 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 831 "cl=0x%x ch=0x%x\n", 832 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 833 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 834 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 835 "cl=0x%x ch=0x%x\n", 836 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 837 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 838 839 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 840 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 841 st0, st1), DEBUG_PROBE); 842 843 return drv_mask; 844 } 845 846 /* 847 * Wait for a drive to be !BSY, and have mask in its status register. 848 * return -1 for a timeout after "timeout" ms. 849 */ 850 int 851 wdcwait(chp, mask, bits, timeout) 852 struct channel_softc *chp; 853 int mask, bits, timeout; 854 { 855 u_char status; 856 int time = 0; 857 #ifdef WDCNDELAY_DEBUG 858 extern int cold; 859 #endif 860 861 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 862 :"none", chp->channel), DEBUG_STATUS); 863 chp->ch_error = 0; 864 865 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 866 867 for (;;) { 868 chp->ch_status = status = 869 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 870 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 871 break; 872 if (++time > timeout) { 873 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 874 "status %x error %x (mask 0x%x bits 0x%x)\n", 875 time, status, 876 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 877 wd_error), mask, bits), 878 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 879 return -1; 880 } 881 delay(WDCDELAY); 882 } 883 #ifdef WDCDEBUG 884 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 885 printf("wdcwait: did busy-wait, time=%d\n", time); 886 #endif 887 if (status & WDCS_ERR) 888 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 889 wd_error); 890 #ifdef WDCNDELAY_DEBUG 891 /* After autoconfig, there should be no long delays. */ 892 if (!cold && time > WDCNDELAY_DEBUG) { 893 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 894 if (xfer == NULL) 895 printf("%s channel %d: warning: busy-wait took %dus\n", 896 chp->wdc->sc_dev.dv_xname, chp->channel, 897 WDCDELAY * time); 898 else 899 printf("%s:%d:%d: warning: busy-wait took %dus\n", 900 chp->wdc->sc_dev.dv_xname, chp->channel, 901 xfer->drive, 902 WDCDELAY * time); 903 } 904 #endif 905 return 0; 906 } 907 908 /* 909 * Busy-wait for DMA to complete 910 */ 911 int 912 wdc_dmawait(chp, xfer, timeout) 913 struct channel_softc *chp; 914 struct wdc_xfer *xfer; 915 int timeout; 916 { 917 int time; 918 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 919 chp->wdc->dma_status = 920 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 921 chp->channel, xfer->drive, 0); 922 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 923 return 0; 924 delay(WDCDELAY); 925 } 926 /* timeout, force a DMA halt */ 927 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 928 chp->channel, xfer->drive, 1); 929 return 1; 930 } 931 932 void 933 wdctimeout(arg) 934 void *arg; 935 { 936 struct channel_softc *chp = (struct channel_softc *)arg; 937 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 938 int s; 939 940 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 941 942 s = splbio(); 943 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 944 __wdcerror(chp, "lost interrupt"); 945 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 946 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 947 xfer->c_bcount, 948 xfer->c_skip); 949 if (chp->ch_flags & WDCF_DMA_WAIT) { 950 chp->wdc->dma_status = 951 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 952 chp->channel, xfer->drive, 1); 953 chp->ch_flags &= ~WDCF_DMA_WAIT; 954 } 955 /* 956 * Call the interrupt routine. If we just missed and interrupt, 957 * it will do what's needed. Else, it will take the needed 958 * action (reset the device). 959 * Before that we need to reinstall the timeout callback, 960 * in case it will miss another irq while in this transfer 961 * We arbitray chose it to be 1s 962 */ 963 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 964 xfer->c_flags |= C_TIMEOU; 965 chp->ch_flags &= ~WDCF_IRQ_WAIT; 966 xfer->c_intr(chp, xfer, 1); 967 } else 968 __wdcerror(chp, "missing untimeout"); 969 splx(s); 970 } 971 972 /* 973 * Probe drive's capabilites, for use by the controller later 974 * Assumes drvp points to an existing drive. 975 * XXX this should be a controller-indep function 976 */ 977 void 978 wdc_probe_caps(drvp) 979 struct ata_drive_datas *drvp; 980 { 981 struct ataparams params, params2; 982 struct channel_softc *chp = drvp->chnl_softc; 983 struct device *drv_dev = drvp->drv_softc; 984 struct wdc_softc *wdc = chp->wdc; 985 int i, printed; 986 char *sep = ""; 987 int cf_flags; 988 989 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 990 /* IDENTIFY failed. Can't tell more about the device */ 991 return; 992 } 993 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 994 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 995 /* 996 * Controller claims 16 and 32 bit transfers. 997 * Re-do an IDENTIFY with 32-bit transfers, 998 * and compare results. 999 */ 1000 drvp->drive_flags |= DRIVE_CAP32; 1001 ata_get_params(drvp, AT_POLL, ¶ms2); 1002 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1003 /* Not good. fall back to 16bits */ 1004 drvp->drive_flags &= ~DRIVE_CAP32; 1005 } else { 1006 printf("%s: 32-bit data port", drv_dev->dv_xname); 1007 } 1008 } 1009 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1010 if (params.atap_ata_major > 0x01 && 1011 params.atap_ata_major != 0xffff) { 1012 for (i = 14; i > 0; i--) { 1013 if (params.atap_ata_major & (1 << i)) { 1014 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1015 printf("%s: ", drv_dev->dv_xname); 1016 else 1017 printf(", "); 1018 printf("ATA version %d\n", i); 1019 drvp->ata_vers = i; 1020 break; 1021 } 1022 } 1023 } else 1024 #endif 1025 if (drvp->drive_flags & DRIVE_CAP32) 1026 printf("\n"); 1027 1028 /* An ATAPI device is at last PIO mode 3 */ 1029 if (drvp->drive_flags & DRIVE_ATAPI) 1030 drvp->PIO_mode = 3; 1031 1032 /* 1033 * It's not in the specs, but it seems that some drive 1034 * returns 0xffff in atap_extensions when this field is invalid 1035 */ 1036 if (params.atap_extensions != 0xffff && 1037 (params.atap_extensions & WDC_EXT_MODES)) { 1038 printed = 0; 1039 /* 1040 * XXX some drives report something wrong here (they claim to 1041 * support PIO mode 8 !). As mode is coded on 3 bits in 1042 * SET FEATURE, limit it to 7 (so limit i to 4). 1043 * If higther mode than 7 is found, abort. 1044 */ 1045 for (i = 7; i >= 0; i--) { 1046 if ((params.atap_piomode_supp & (1 << i)) == 0) 1047 continue; 1048 if (i > 4) 1049 return; 1050 /* 1051 * See if mode is accepted. 1052 * If the controller can't set its PIO mode, 1053 * assume the defaults are good, so don't try 1054 * to set it 1055 */ 1056 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1057 if (ata_set_mode(drvp, 0x08 | (i + 3), 1058 AT_POLL) != CMD_OK) 1059 continue; 1060 if (!printed) { 1061 printf("%s: drive supports PIO mode %d", 1062 drv_dev->dv_xname, i + 3); 1063 sep = ","; 1064 printed = 1; 1065 } 1066 /* 1067 * If controller's driver can't set its PIO mode, 1068 * get the highter one for the drive. 1069 */ 1070 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1071 wdc->PIO_cap >= i + 3) { 1072 drvp->PIO_mode = i + 3; 1073 drvp->PIO_cap = i + 3; 1074 break; 1075 } 1076 } 1077 if (!printed) { 1078 /* 1079 * We didn't find a valid PIO mode. 1080 * Assume the values returned for DMA are buggy too 1081 */ 1082 return; 1083 } 1084 drvp->drive_flags |= DRIVE_MODE; 1085 printed = 0; 1086 for (i = 7; i >= 0; i--) { 1087 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1088 continue; 1089 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1090 (wdc->cap & WDC_CAPABILITY_MODE)) 1091 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1092 != CMD_OK) 1093 continue; 1094 if (!printed) { 1095 printf("%s DMA mode %d", sep, i); 1096 sep = ","; 1097 printed = 1; 1098 } 1099 if (wdc->cap & WDC_CAPABILITY_DMA) { 1100 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1101 wdc->DMA_cap < i) 1102 continue; 1103 drvp->DMA_mode = i; 1104 drvp->DMA_cap = i; 1105 drvp->drive_flags |= DRIVE_DMA; 1106 } 1107 break; 1108 } 1109 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1110 printed = 0; 1111 for (i = 7; i >= 0; i--) { 1112 if ((params.atap_udmamode_supp & (1 << i)) 1113 == 0) 1114 continue; 1115 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1116 (wdc->cap & WDC_CAPABILITY_UDMA)) 1117 if (ata_set_mode(drvp, 0x40 | i, 1118 AT_POLL) != CMD_OK) 1119 continue; 1120 if (!printed) { 1121 printf("%s Ultra-DMA mode %d", sep, i); 1122 if (i == 2) 1123 printf(" (Ultra/33)"); 1124 else if (i == 4) 1125 printf(" (Ultra/66)"); 1126 else if (i == 5) 1127 printf(" (Ultra/100)"); 1128 sep = ","; 1129 printed = 1; 1130 } 1131 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1132 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1133 wdc->UDMA_cap < i) 1134 continue; 1135 drvp->UDMA_mode = i; 1136 drvp->UDMA_cap = i; 1137 drvp->drive_flags |= DRIVE_UDMA; 1138 } 1139 break; 1140 } 1141 } 1142 printf("\n"); 1143 } 1144 1145 /* Try to guess ATA version here, if it didn't get reported */ 1146 if (drvp->ata_vers == 0) { 1147 if (drvp->drive_flags & DRIVE_UDMA) 1148 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1149 else if (drvp->PIO_cap > 2) 1150 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1151 } 1152 cf_flags = drv_dev->dv_cfdata->cf_flags; 1153 if (cf_flags & ATA_CONFIG_PIO_SET) { 1154 drvp->PIO_mode = 1155 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1156 drvp->drive_flags |= DRIVE_MODE; 1157 } 1158 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1159 /* don't care about DMA modes */ 1160 return; 1161 } 1162 if (cf_flags & ATA_CONFIG_DMA_SET) { 1163 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1164 ATA_CONFIG_DMA_DISABLE) { 1165 drvp->drive_flags &= ~DRIVE_DMA; 1166 } else { 1167 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1168 ATA_CONFIG_DMA_OFF; 1169 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1170 } 1171 } 1172 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1173 /* don't care about UDMA modes */ 1174 return; 1175 } 1176 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1177 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1178 ATA_CONFIG_UDMA_DISABLE) { 1179 drvp->drive_flags &= ~DRIVE_UDMA; 1180 } else { 1181 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1182 ATA_CONFIG_UDMA_OFF; 1183 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1184 } 1185 } 1186 } 1187 1188 /* 1189 * downgrade the transfer mode of a drive after an error. return 1 if 1190 * downgrade was possible, 0 otherwise. 1191 */ 1192 int 1193 wdc_downgrade_mode(drvp) 1194 struct ata_drive_datas *drvp; 1195 { 1196 struct channel_softc *chp = drvp->chnl_softc; 1197 struct device *drv_dev = drvp->drv_softc; 1198 struct wdc_softc *wdc = chp->wdc; 1199 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1200 1201 /* if drive or controller don't know its mode, we can't do much */ 1202 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1203 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1204 return 0; 1205 /* current drive mode was set by a config flag, let it this way */ 1206 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1207 (cf_flags & ATA_CONFIG_DMA_SET) || 1208 (cf_flags & ATA_CONFIG_UDMA_SET)) 1209 return 0; 1210 1211 /* 1212 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1213 * Maybe we didn't properly notice the cable type 1214 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1215 * It helps in some cases. 1216 */ 1217 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1218 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1219 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1220 drv_dev->dv_xname, drvp->UDMA_mode); 1221 } 1222 1223 /* 1224 * If we were using ultra-DMA, don't downgrade to multiword DMA 1225 * if we noticed a CRC error. It has been noticed that CRC errors 1226 * in ultra-DMA lead to silent data corruption in multiword DMA. 1227 * Data corruption is less likely to occur in PIO mode. 1228 */ 1229 else if ((drvp->drive_flags & DRIVE_UDMA) && 1230 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1231 drvp->drive_flags &= ~DRIVE_UDMA; 1232 drvp->drive_flags |= DRIVE_DMA; 1233 drvp->DMA_mode = drvp->DMA_cap; 1234 printf("%s: transfer error, downgrading to DMA mode %d\n", 1235 drv_dev->dv_xname, drvp->DMA_mode); 1236 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1237 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1238 drvp->PIO_mode = drvp->PIO_cap; 1239 printf("%s: transfer error, downgrading to PIO mode %d\n", 1240 drv_dev->dv_xname, drvp->PIO_mode); 1241 } else /* already using PIO, can't downgrade */ 1242 return 0; 1243 1244 wdc->set_modes(chp); 1245 /* reset the channel, which will shedule all drives for setup */ 1246 wdc_reset_channel(drvp); 1247 return 1; 1248 } 1249 1250 int 1251 wdc_exec_command(drvp, wdc_c) 1252 struct ata_drive_datas *drvp; 1253 struct wdc_command *wdc_c; 1254 { 1255 struct channel_softc *chp = drvp->chnl_softc; 1256 struct wdc_xfer *xfer; 1257 int s, ret; 1258 1259 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1260 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1261 DEBUG_FUNCS); 1262 1263 /* set up an xfer and queue. Wait for completion */ 1264 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1265 WDC_NOSLEEP); 1266 if (xfer == NULL) { 1267 return WDC_TRY_AGAIN; 1268 } 1269 1270 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1271 wdc_c->flags |= AT_POLL; 1272 if (wdc_c->flags & AT_POLL) 1273 xfer->c_flags |= C_POLL; 1274 xfer->drive = drvp->drive; 1275 xfer->databuf = wdc_c->data; 1276 xfer->c_bcount = wdc_c->bcount; 1277 xfer->cmd = wdc_c; 1278 xfer->c_start = __wdccommand_start; 1279 xfer->c_intr = __wdccommand_intr; 1280 xfer->c_kill_xfer = __wdccommand_done; 1281 1282 s = splbio(); 1283 wdc_exec_xfer(chp, xfer); 1284 #ifdef DIAGNOSTIC 1285 if ((wdc_c->flags & AT_POLL) != 0 && 1286 (wdc_c->flags & AT_DONE) == 0) 1287 panic("wdc_exec_command: polled command not done\n"); 1288 #endif 1289 if (wdc_c->flags & AT_DONE) { 1290 ret = WDC_COMPLETE; 1291 } else { 1292 if (wdc_c->flags & AT_WAIT) { 1293 while ((wdc_c->flags & AT_DONE) == 0) { 1294 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1295 } 1296 ret = WDC_COMPLETE; 1297 } else { 1298 ret = WDC_QUEUED; 1299 } 1300 } 1301 splx(s); 1302 return ret; 1303 } 1304 1305 void 1306 __wdccommand_start(chp, xfer) 1307 struct channel_softc *chp; 1308 struct wdc_xfer *xfer; 1309 { 1310 int drive = xfer->drive; 1311 struct wdc_command *wdc_c = xfer->cmd; 1312 1313 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1314 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1315 DEBUG_FUNCS); 1316 1317 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1318 WDSD_IBM | (drive << 4)); 1319 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1320 wdc_c->timeout) != 0) { 1321 wdc_c->flags |= AT_TIMEOU; 1322 __wdccommand_done(chp, xfer); 1323 return; 1324 } 1325 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1326 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1327 if ((wdc_c->flags & AT_POLL) == 0) { 1328 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1329 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1330 wdctimeout, chp); 1331 return; 1332 } 1333 /* 1334 * Polled command. Wait for drive ready or drq. Done in intr(). 1335 * Wait for at last 400ns for status bit to be valid. 1336 */ 1337 delay(10); 1338 __wdccommand_intr(chp, xfer, 0); 1339 } 1340 1341 int 1342 __wdccommand_intr(chp, xfer, irq) 1343 struct channel_softc *chp; 1344 struct wdc_xfer *xfer; 1345 int irq; 1346 { 1347 struct wdc_command *wdc_c = xfer->cmd; 1348 int bcount = wdc_c->bcount; 1349 char *data = wdc_c->data; 1350 1351 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1352 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1353 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1354 (irq == 0) ? wdc_c->timeout : 0)) { 1355 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1356 return 0; /* IRQ was not for us */ 1357 wdc_c->flags |= AT_TIMEOU; 1358 __wdccommand_done(chp, xfer); 1359 return 1; 1360 } 1361 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1362 chp->wdc->irqack(chp); 1363 if (wdc_c->flags & AT_READ) { 1364 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1365 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1366 0, (u_int32_t*)data, bcount >> 2); 1367 data += bcount & 0xfffffffc; 1368 bcount = bcount & 0x03; 1369 } 1370 if (bcount > 0) 1371 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1372 wd_data, (u_int16_t *)data, bcount >> 1); 1373 } else if (wdc_c->flags & AT_WRITE) { 1374 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1375 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1376 0, (u_int32_t*)data, bcount >> 2); 1377 data += bcount & 0xfffffffc; 1378 bcount = bcount & 0x03; 1379 } 1380 if (bcount > 0) 1381 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1382 wd_data, (u_int16_t *)data, bcount >> 1); 1383 } 1384 __wdccommand_done(chp, xfer); 1385 return 1; 1386 } 1387 1388 void 1389 __wdccommand_done(chp, xfer) 1390 struct channel_softc *chp; 1391 struct wdc_xfer *xfer; 1392 { 1393 struct wdc_command *wdc_c = xfer->cmd; 1394 1395 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1396 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1397 1398 callout_stop(&chp->ch_callout); 1399 1400 if (chp->ch_status & WDCS_DWF) 1401 wdc_c->flags |= AT_DF; 1402 if (chp->ch_status & WDCS_ERR) { 1403 wdc_c->flags |= AT_ERROR; 1404 wdc_c->r_error = chp->ch_error; 1405 } 1406 wdc_c->flags |= AT_DONE; 1407 if ((wdc_c->flags & AT_READREG) != 0 && 1408 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1409 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1410 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1411 wd_sdh); 1412 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1413 wd_cyl_hi) << 8; 1414 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1415 wd_cyl_lo); 1416 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1417 wd_sector); 1418 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1419 wd_seccnt); 1420 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1421 wd_error); 1422 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1423 wd_precomp); 1424 } 1425 wdc_free_xfer(chp, xfer); 1426 if (wdc_c->flags & AT_WAIT) 1427 wakeup(wdc_c); 1428 else if (wdc_c->callback) 1429 wdc_c->callback(wdc_c->callback_arg); 1430 wdcstart(chp); 1431 return; 1432 } 1433 1434 /* 1435 * Send a command. The drive should be ready. 1436 * Assumes interrupts are blocked. 1437 */ 1438 void 1439 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1440 struct channel_softc *chp; 1441 u_int8_t drive; 1442 u_int8_t command; 1443 u_int16_t cylin; 1444 u_int8_t head, sector, count, precomp; 1445 { 1446 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1447 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1448 chp->channel, drive, command, cylin, head, sector, count, precomp), 1449 DEBUG_FUNCS); 1450 1451 /* Select drive, head, and addressing mode. */ 1452 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1453 WDSD_IBM | (drive << 4) | head); 1454 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1455 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1456 precomp); 1457 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1458 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1459 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1460 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1461 1462 /* Send command. */ 1463 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1464 return; 1465 } 1466 1467 /* 1468 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1469 * tested by the caller. 1470 */ 1471 void 1472 wdccommandshort(chp, drive, command) 1473 struct channel_softc *chp; 1474 int drive; 1475 int command; 1476 { 1477 1478 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1479 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1480 DEBUG_FUNCS); 1481 1482 /* Select drive. */ 1483 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1484 WDSD_IBM | (drive << 4)); 1485 1486 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1487 } 1488 1489 /* Add a command to the queue and start controller. Must be called at splbio */ 1490 1491 void 1492 wdc_exec_xfer(chp, xfer) 1493 struct channel_softc *chp; 1494 struct wdc_xfer *xfer; 1495 { 1496 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1497 chp->channel, xfer->drive), DEBUG_XFERS); 1498 1499 /* complete xfer setup */ 1500 xfer->chp = chp; 1501 1502 /* 1503 * If we are a polled command, and the list is not empty, 1504 * we are doing a dump. Drop the list to allow the polled command 1505 * to complete, we're going to reboot soon anyway. 1506 */ 1507 if ((xfer->c_flags & C_POLL) != 0 && 1508 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1509 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1510 } 1511 /* insert at the end of command list */ 1512 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1513 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1514 chp->ch_flags), DEBUG_XFERS); 1515 wdcstart(chp); 1516 } 1517 1518 struct wdc_xfer * 1519 wdc_get_xfer(flags) 1520 int flags; 1521 { 1522 struct wdc_xfer *xfer; 1523 int s; 1524 1525 s = splbio(); 1526 xfer = pool_get(&wdc_xfer_pool, 1527 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1528 splx(s); 1529 if (xfer != NULL) { 1530 memset(xfer, 0, sizeof(struct wdc_xfer)); 1531 } 1532 return xfer; 1533 } 1534 1535 void 1536 wdc_free_xfer(chp, xfer) 1537 struct channel_softc *chp; 1538 struct wdc_xfer *xfer; 1539 { 1540 struct wdc_softc *wdc = chp->wdc; 1541 int s; 1542 1543 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1544 (*wdc->free_hw)(chp); 1545 s = splbio(); 1546 chp->ch_flags &= ~WDCF_ACTIVE; 1547 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1548 pool_put(&wdc_xfer_pool, xfer); 1549 splx(s); 1550 } 1551 1552 /* 1553 * Kill off all pending xfers for a channel_softc. 1554 * 1555 * Must be called at splbio(). 1556 */ 1557 void 1558 wdc_kill_pending(chp) 1559 struct channel_softc *chp; 1560 { 1561 struct wdc_xfer *xfer; 1562 1563 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1564 chp = xfer->chp; 1565 (*xfer->c_kill_xfer)(chp, xfer); 1566 } 1567 } 1568 1569 static void 1570 __wdcerror(chp, msg) 1571 struct channel_softc *chp; 1572 char *msg; 1573 { 1574 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1575 1576 if (xfer == NULL) 1577 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1578 msg); 1579 else 1580 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1581 chp->channel, xfer->drive, msg); 1582 } 1583 1584 /* 1585 * the bit bucket 1586 */ 1587 void 1588 wdcbit_bucket(chp, size) 1589 struct channel_softc *chp; 1590 int size; 1591 { 1592 1593 for (; size >= 2; size -= 2) 1594 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1595 if (size) 1596 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1597 } 1598 1599 int 1600 wdc_addref(chp) 1601 struct channel_softc *chp; 1602 { 1603 struct wdc_softc *wdc = chp->wdc; 1604 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1605 int s, error = 0; 1606 1607 s = splbio(); 1608 if (adapt->adapt_refcnt++ == 0 && 1609 adapt->adapt_enable != NULL) { 1610 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1611 if (error) 1612 adapt->adapt_refcnt--; 1613 } 1614 splx(s); 1615 return (error); 1616 } 1617 1618 void 1619 wdc_delref(chp) 1620 struct channel_softc *chp; 1621 { 1622 struct wdc_softc *wdc = chp->wdc; 1623 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1624 int s; 1625 1626 s = splbio(); 1627 if (adapt->adapt_refcnt-- == 1 && 1628 adapt->adapt_enable != NULL) 1629 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1630 splx(s); 1631 } 1632 1633 void 1634 wdc_print_modes(struct channel_softc *chp) 1635 { 1636 int drive; 1637 struct ata_drive_datas *drvp; 1638 1639 for (drive = 0; drive < 2; drive++) { 1640 drvp = &chp->ch_drive[drive]; 1641 if ((drvp->drive_flags & DRIVE) == 0) 1642 continue; 1643 printf("%s(%s:%d:%d): using PIO mode %d", 1644 drvp->drv_softc->dv_xname, 1645 chp->wdc->sc_dev.dv_xname, 1646 chp->channel, drive, drvp->PIO_mode); 1647 if (drvp->drive_flags & DRIVE_DMA) 1648 printf(", DMA mode %d", drvp->DMA_mode); 1649 if (drvp->drive_flags & DRIVE_UDMA) { 1650 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1651 if (drvp->UDMA_mode == 2) 1652 printf(" (Ultra/33)"); 1653 else if (drvp->UDMA_mode == 4) 1654 printf(" (Ultra/66)"); 1655 else if (drvp->UDMA_mode == 5) 1656 printf(" (Ultra/100)"); 1657 } 1658 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1659 printf(" (using DMA data transfers)"); 1660 printf("\n"); 1661 } 1662 } 1663
Indexes created Mon Sep 22 21:09:42 GMT 2025