wdc.c revision 1.102
1 /* $NetBSD: wdc.c,v 1.102 2001/12/02 22:44:33 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.102 2001/12/02 22:44:33 bouyer Exp $"); 76 77 #ifndef WDCDEBUG 78 #define WDCDEBUG 79 #endif /* WDCDEBUG */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/conf.h> 85 #include <sys/buf.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/pool.h> 89 #include <sys/syslog.h> 90 #include <sys/proc.h> 91 92 #include <machine/intr.h> 93 #include <machine/bus.h> 94 95 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 96 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 97 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 98 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 99 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 100 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 101 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atavar.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "atapibus.h" 109 110 #define WDCDELAY 100 /* 100 microseconds */ 111 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 112 #if 0 113 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 114 #define WDCNDELAY_DEBUG 50 115 #endif 116 117 struct pool wdc_xfer_pool; 118 119 const struct ata_bustype wdc_ata_bustype = {SCSIPI_BUSTYPE_ATA}; 120 121 static void __wdcerror __P((struct channel_softc*, char *)); 122 static int __wdcwait_reset __P((struct channel_softc *, int)); 123 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 124 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 125 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 126 int wdprint __P((void *, const char *)); 127 128 129 #define DEBUG_INTR 0x01 130 #define DEBUG_XFERS 0x02 131 #define DEBUG_STATUS 0x04 132 #define DEBUG_FUNCS 0x08 133 #define DEBUG_PROBE 0x10 134 #define DEBUG_DETACH 0x20 135 #define DEBUG_DELAY 0x40 136 #ifdef WDCDEBUG 137 int wdcdebug_mask = 0; 138 int wdc_nxfer = 0; 139 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 140 #else 141 #define WDCDEBUG_PRINT(args, level) 142 #endif 143 144 int 145 wdprint(aux, pnp) 146 void *aux; 147 const char *pnp; 148 { 149 struct ata_device *adev = aux; 150 if (pnp) 151 printf("drive at %s", pnp); 152 printf(" channel %d drive %d", adev->adev_channel, 153 adev->adev_drv_data->drive); 154 return (UNCONF); 155 } 156 157 /* Test to see controller with at last one attached drive is there. 158 * Returns a bit for each possible drive found (0x01 for drive 0, 159 * 0x02 for drive 1). 160 * Logic: 161 * - If a status register is at 0xff, assume there is no drive here 162 * (ISA has pull-up resistors). Similarly if the status register has 163 * the value we last wrote to the bus (for IDE interfaces without pullups). 164 * If no drive at all -> return. 165 * - reset the controller, wait for it to complete (may take up to 31s !). 166 * If timeout -> return. 167 * - test ATA/ATAPI signatures. If at last one drive found -> return. 168 * - try an ATA command on the master. 169 */ 170 171 int 172 wdcprobe(chp) 173 struct channel_softc *chp; 174 { 175 u_int8_t st0, st1, sc, sn, cl, ch; 176 u_int8_t ret_value = 0x03; 177 u_int8_t drive; 178 int found; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(10); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(10); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff || st0 == WDSD_IBM) 200 ret_value &= ~0x01; 201 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(10); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(10); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices. If it's not an ATAPI and reset said there may be 233 * something here assume it's ATA or OLD. Ghost will be killed later in 234 * attach routine. 235 */ 236 found = 0; 237 for (drive = 0; drive < 2; drive++) { 238 if ((ret_value & (0x01 << drive)) == 0) 239 continue; 240 if (1 < ++found && chp->wdc != NULL && 241 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 242 /* 243 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 244 * is set. 245 * 246 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 247 * doesn't seem to implement drive select command. In 248 * this case, you can't eliminate ghost drive properly. 249 */ 250 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 251 chp->wdc->sc_dev.dv_xname, 252 chp->channel, drive), DEBUG_PROBE); 253 break; 254 } 255 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 256 WDSD_IBM | (drive << 4)); 257 delay(10); 258 /* Save registers contents */ 259 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 260 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 261 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 262 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 263 264 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 265 "cl=0x%x ch=0x%x\n", 266 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 267 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 268 /* 269 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 270 * we get wrong values here, so ignore it. 271 */ 272 if (cl == 0x14 && ch == 0xeb) { 273 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 274 } else { 275 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 276 if (chp->wdc == NULL || 277 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 278 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 279 } 280 } 281 return (ret_value); 282 } 283 284 void 285 wdcattach(chp) 286 struct channel_softc *chp; 287 { 288 int channel_flags, ctrl_flags, i, error; 289 struct ataparams params; 290 static int inited = 0; 291 292 callout_init(&chp->ch_callout); 293 294 if ((error = wdc_addref(chp)) != 0) { 295 printf("%s: unable to enable controller\n", 296 chp->wdc->sc_dev.dv_xname); 297 return; 298 } 299 300 if (wdcprobe(chp) == 0) 301 /* If no drives, abort attach here. */ 302 goto out; 303 304 /* initialise global data */ 305 if (inited == 0) { 306 /* Initialize the wdc_xfer pool. */ 307 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 308 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 309 inited++; 310 } 311 TAILQ_INIT(&chp->ch_queue->sc_xfer); 312 313 for (i = 0; i < 2; i++) { 314 chp->ch_drive[i].chnl_softc = chp; 315 chp->ch_drive[i].drive = i; 316 /* 317 * Init error counter so that an error withing the first xfers 318 * will trigger a downgrade 319 */ 320 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 321 322 /* If controller can't do 16bit flag the drives as 32bit */ 323 if ((chp->wdc->cap & 324 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 325 WDC_CAPABILITY_DATA32) 326 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 327 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 328 continue; 329 330 /* 331 * Wait a bit, some devices are weird just after a reset. 332 * Then issue a IDENTIFY command, to try to detect slave ghost 333 */ 334 delay(100); 335 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 336 if (error != CMD_OK) { 337 delay(1000000); 338 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 339 ¶ms); 340 } 341 if (error == CMD_OK) { 342 /* If IDENTIFY succeded, this is not an OLD ctrl */ 343 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 344 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 345 } else { 346 chp->ch_drive[i].drive_flags &= 347 ~(DRIVE_ATA | DRIVE_ATAPI); 348 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 349 chp->wdc->sc_dev.dv_xname, 350 chp->channel, i, error), DEBUG_PROBE); 351 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 352 continue; 353 /* 354 * Pre-ATA drive ? 355 * Test registers writability (Error register not 356 * writable, but cyllo is), then try an ATA command. 357 */ 358 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 359 WDSD_IBM | (i << 4)); 360 delay(10); 361 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 362 wd_error, 0x58); 363 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 364 wd_cyl_lo, 0xa5); 365 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 366 wd_error == 0x58) || 367 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 368 wd_cyl_lo) != 0xa5) { 369 WDCDEBUG_PRINT(("%s:%d:%d: register " 370 "writability failed\n", 371 chp->wdc->sc_dev.dv_xname, 372 chp->channel, i), DEBUG_PROBE); 373 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 374 } 375 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 376 WDSD_IBM | (i << 4)); 377 delay(100); 378 if (wait_for_ready(chp, 10000) != 0) { 379 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 380 chp->wdc->sc_dev.dv_xname, 381 chp->channel, i), DEBUG_PROBE); 382 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 383 continue; 384 } 385 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 386 wd_command, WDCC_RECAL); 387 if (wait_for_ready(chp, 10000) != 0) { 388 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 389 chp->wdc->sc_dev.dv_xname, 390 chp->channel, i), DEBUG_PROBE); 391 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 392 } 393 } 394 } 395 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 396 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 397 398 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 399 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 400 DEBUG_PROBE); 401 402 /* If no drives, abort here */ 403 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 404 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 405 goto out; 406 407 /* 408 * Attach an ATAPI bus, if needed. 409 */ 410 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 411 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 412 #if NATAPIBUS > 0 413 wdc_atapibus_attach(chp); 414 #else 415 /* 416 * Fake the autoconfig "not configured" message 417 */ 418 printf("atapibus at %s channel %s not configured\n", 419 chp->wdc->sc_dev.dv_xname, chp->channel); 420 chp->atapibus = NULL; 421 #endif 422 } 423 424 for (i = 0; i < 2; i++) { 425 struct ata_device adev; 426 if ((chp->ch_drive[i].drive_flags & 427 (DRIVE_ATA | DRIVE_OLD)) == 0) { 428 continue; 429 } 430 memset(&adev, 0, sizeof(struct ata_device)); 431 adev.adev_bustype = &wdc_ata_bustype; 432 adev.adev_channel = chp->channel; 433 adev.adev_openings = 1; 434 adev.adev_drv_data = &chp->ch_drive[i]; 435 if (config_found(&chp->wdc->sc_dev, (void *)&adev, wdprint)) 436 wdc_probe_caps(&chp->ch_drive[i]); 437 } 438 439 /* 440 * reset drive_flags for unnatached devices, reset state for attached 441 * ones 442 */ 443 for (i = 0; i < 2; i++) { 444 if (chp->ch_drive[i].drv_softc == NULL) 445 chp->ch_drive[i].drive_flags = 0; 446 else 447 chp->ch_drive[i].state = 0; 448 } 449 450 /* 451 * Reset channel. The probe, with some combinations of ATA/ATAPI 452 * devices keep it in a mostly working, but strange state (with busy 453 * led on) 454 */ 455 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 456 delay(50); 457 wdcreset(chp, VERBOSE); 458 /* 459 * Read status registers to avoid spurious interrupts. 460 */ 461 for (i = 1; i >= 0; i--) { 462 if (chp->ch_drive[i].drive_flags & DRIVE) { 463 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 464 wd_sdh, WDSD_IBM | (i << 4)); 465 if (wait_for_unbusy(chp, 10000) < 0) 466 printf("%s:%d:%d: device busy\n", 467 chp->wdc->sc_dev.dv_xname, 468 chp->channel, i); 469 } 470 } 471 } 472 473 out: 474 wdc_delref(chp); 475 } 476 477 /* 478 * Call activate routine of underlying devices. 479 */ 480 int 481 wdcactivate(self, act) 482 struct device *self; 483 enum devact act; 484 { 485 struct wdc_softc *wdc = (struct wdc_softc *)self; 486 struct channel_softc *chp; 487 struct device *sc = 0; 488 int s, i, j, error = 0; 489 490 s = splbio(); 491 switch (act) { 492 case DVACT_ACTIVATE: 493 error = EOPNOTSUPP; 494 break; 495 496 case DVACT_DEACTIVATE: 497 for (i = 0; i < wdc->nchannels; i++) { 498 chp = wdc->channels[i]; 499 500 /* 501 * We might call deactivate routine for 502 * the children of atapibus twice (once via 503 * atapibus, once directly), but since 504 * config_deactivate maintains DVF_ACTIVE flag, 505 * it's safe. 506 */ 507 sc = chp->atapibus; 508 if (sc != NULL) { 509 error = config_deactivate(sc); 510 if (error != 0) 511 goto out; 512 } 513 514 for (j = 0; j < 2; j++) { 515 sc = chp->ch_drive[j].drv_softc; 516 WDCDEBUG_PRINT(("wdcactivate: %s:" 517 " deactivating %s\n", wdc->sc_dev.dv_xname, 518 sc == NULL ? "nodrv" : sc->dv_xname), 519 DEBUG_DETACH); 520 if (sc != NULL) { 521 error = config_deactivate(sc); 522 if (error != 0) 523 goto out; 524 } 525 } 526 } 527 break; 528 } 529 530 out: 531 splx(s); 532 533 #ifdef WDCDEBUG 534 if (sc && error != 0) 535 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 536 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 537 #endif 538 return (error); 539 } 540 541 int 542 wdcdetach(self, flags) 543 struct device *self; 544 int flags; 545 { 546 struct wdc_softc *wdc = (struct wdc_softc *)self; 547 struct channel_softc *chp; 548 struct device *sc = 0; 549 int i, j, error = 0; 550 551 for (i = 0; i < wdc->nchannels; i++) { 552 chp = wdc->channels[i]; 553 554 /* 555 * Detach atapibus and its children. 556 */ 557 sc = chp->atapibus; 558 if (sc != NULL) { 559 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 560 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 561 error = config_detach(sc, flags); 562 if (error != 0) 563 goto out; 564 } 565 566 /* 567 * Detach our other children. 568 */ 569 for (j = 0; j < 2; j++) { 570 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 571 continue; 572 sc = chp->ch_drive[j].drv_softc; 573 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 574 wdc->sc_dev.dv_xname, 575 sc == NULL ? "nodrv" : sc->dv_xname), 576 DEBUG_DETACH); 577 if (sc != NULL) { 578 error = config_detach(sc, flags); 579 if (error != 0) 580 goto out; 581 } 582 } 583 584 wdc_kill_pending(chp); 585 } 586 587 out: 588 #ifdef WDCDEBUG 589 if (sc && error != 0) 590 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 591 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 592 #endif 593 return (error); 594 } 595 596 /* 597 * Start I/O on a controller, for the given channel. 598 * The first xfer may be not for our channel if the channel queues 599 * are shared. 600 */ 601 void 602 wdcstart(chp) 603 struct channel_softc *chp; 604 { 605 struct wdc_xfer *xfer; 606 607 #ifdef WDC_DIAGNOSTIC 608 int spl1, spl2; 609 610 spl1 = splbio(); 611 spl2 = splbio(); 612 if (spl2 != spl1) { 613 printf("wdcstart: not at splbio()\n"); 614 panic("wdcstart"); 615 } 616 splx(spl2); 617 splx(spl1); 618 #endif /* WDC_DIAGNOSTIC */ 619 620 /* is there a xfer ? */ 621 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 622 return; 623 624 /* adjust chp, in case we have a shared queue */ 625 chp = xfer->chp; 626 627 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 628 return; /* channel aleady active */ 629 } 630 #ifdef DIAGNOSTIC 631 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 632 panic("wdcstart: channel waiting for irq\n"); 633 #endif 634 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 635 if (!(*chp->wdc->claim_hw)(chp, 0)) 636 return; 637 638 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 639 chp->channel, xfer->drive), DEBUG_XFERS); 640 chp->ch_flags |= WDCF_ACTIVE; 641 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 642 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 643 chp->ch_drive[xfer->drive].state = 0; 644 } 645 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 646 KASSERT(xfer->c_flags & C_POLL); 647 xfer->c_start(chp, xfer); 648 } 649 650 /* restart an interrupted I/O */ 651 void 652 wdcrestart(v) 653 void *v; 654 { 655 struct channel_softc *chp = v; 656 int s; 657 658 s = splbio(); 659 wdcstart(chp); 660 splx(s); 661 } 662 663 664 /* 665 * Interrupt routine for the controller. Acknowledge the interrupt, check for 666 * errors on the current operation, mark it done if necessary, and start the 667 * next request. Also check for a partially done transfer, and continue with 668 * the next chunk if so. 669 */ 670 int 671 wdcintr(arg) 672 void *arg; 673 { 674 struct channel_softc *chp = arg; 675 struct wdc_xfer *xfer; 676 int ret; 677 678 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 679 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 680 DEBUG_INTR); 681 return (0); 682 } 683 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 684 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 685 return (0); 686 } 687 688 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 689 xfer = chp->ch_queue->sc_xfer.tqh_first; 690 if (chp->ch_flags & WDCF_DMA_WAIT) { 691 chp->wdc->dma_status = 692 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 693 xfer->drive, 0); 694 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 695 /* IRQ not for us, not detected by DMA engine */ 696 return 0; 697 } 698 chp->ch_flags &= ~WDCF_DMA_WAIT; 699 } 700 chp->ch_flags &= ~WDCF_IRQ_WAIT; 701 ret = xfer->c_intr(chp, xfer, 1); 702 if (ret == 0) /* irq was not for us, still waiting for irq */ 703 chp->ch_flags |= WDCF_IRQ_WAIT; 704 return (ret); 705 } 706 707 /* Put all disk in RESET state */ 708 void wdc_reset_channel(drvp) 709 struct ata_drive_datas *drvp; 710 { 711 struct channel_softc *chp = drvp->chnl_softc; 712 int drive; 713 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 714 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 715 DEBUG_FUNCS); 716 (void) wdcreset(chp, VERBOSE); 717 for (drive = 0; drive < 2; drive++) { 718 chp->ch_drive[drive].state = 0; 719 } 720 } 721 722 int 723 wdcreset(chp, verb) 724 struct channel_softc *chp; 725 int verb; 726 { 727 int drv_mask1, drv_mask2; 728 729 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 730 WDSD_IBM); /* master */ 731 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 732 WDCTL_RST | WDCTL_IDS); 733 delay(1000); 734 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 735 WDCTL_IDS); 736 delay(1000); 737 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 738 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 739 WDCTL_4BIT); 740 741 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 742 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 743 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 744 if (verb && drv_mask2 != drv_mask1) { 745 printf("%s channel %d: reset failed for", 746 chp->wdc->sc_dev.dv_xname, chp->channel); 747 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 748 printf(" drive 0"); 749 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 750 printf(" drive 1"); 751 printf("\n"); 752 } 753 return (drv_mask1 != drv_mask2) ? 1 : 0; 754 } 755 756 static int 757 __wdcwait_reset(chp, drv_mask) 758 struct channel_softc *chp; 759 int drv_mask; 760 { 761 int timeout; 762 u_int8_t st0, st1; 763 #ifdef WDCDEBUG 764 u_int8_t sc0, sn0, cl0, ch0; 765 u_int8_t sc1, sn1, cl1, ch1; 766 #endif 767 /* wait for BSY to deassert */ 768 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 769 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 770 WDSD_IBM); /* master */ 771 delay(10); 772 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 773 #ifdef WDCDEBUG 774 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 775 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 776 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 777 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 778 #endif 779 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 780 WDSD_IBM | 0x10); /* slave */ 781 delay(10); 782 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 783 #ifdef WDCDEBUG 784 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 785 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 786 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 787 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 788 #endif 789 790 if ((drv_mask & 0x01) == 0) { 791 /* no master */ 792 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 793 /* No master, slave is ready, it's done */ 794 goto end; 795 } 796 } else if ((drv_mask & 0x02) == 0) { 797 /* no slave */ 798 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 799 /* No slave, master is ready, it's done */ 800 goto end; 801 } 802 } else { 803 /* Wait for both master and slave to be ready */ 804 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 805 goto end; 806 } 807 } 808 delay(WDCDELAY); 809 } 810 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 811 if (st0 & WDCS_BSY) 812 drv_mask &= ~0x01; 813 if (st1 & WDCS_BSY) 814 drv_mask &= ~0x02; 815 end: 816 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 817 "cl=0x%x ch=0x%x\n", 818 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 819 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 820 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 821 "cl=0x%x ch=0x%x\n", 822 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 823 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 824 825 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 826 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 827 st0, st1), DEBUG_PROBE); 828 829 return drv_mask; 830 } 831 832 /* 833 * Wait for a drive to be !BSY, and have mask in its status register. 834 * return -1 for a timeout after "timeout" ms. 835 */ 836 int 837 wdcwait(chp, mask, bits, timeout) 838 struct channel_softc *chp; 839 int mask, bits, timeout; 840 { 841 u_char status; 842 int time = 0; 843 #ifdef WDCNDELAY_DEBUG 844 extern int cold; 845 #endif 846 847 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 848 :"none", chp->channel), DEBUG_STATUS); 849 chp->ch_error = 0; 850 851 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 852 853 for (;;) { 854 chp->ch_status = status = 855 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 856 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 857 break; 858 if (++time > timeout) { 859 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 860 "status %x error %x (mask 0x%x bits 0x%x)\n", 861 time, status, 862 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 863 wd_error), mask, bits), 864 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 865 return -1; 866 } 867 delay(WDCDELAY); 868 } 869 #ifdef WDCDEBUG 870 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 871 printf("wdcwait: did busy-wait, time=%d\n", time); 872 #endif 873 if (status & WDCS_ERR) 874 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 875 wd_error); 876 #ifdef WDCNDELAY_DEBUG 877 /* After autoconfig, there should be no long delays. */ 878 if (!cold && time > WDCNDELAY_DEBUG) { 879 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 880 if (xfer == NULL) 881 printf("%s channel %d: warning: busy-wait took %dus\n", 882 chp->wdc->sc_dev.dv_xname, chp->channel, 883 WDCDELAY * time); 884 else 885 printf("%s:%d:%d: warning: busy-wait took %dus\n", 886 chp->wdc->sc_dev.dv_xname, chp->channel, 887 xfer->drive, 888 WDCDELAY * time); 889 } 890 #endif 891 return 0; 892 } 893 894 /* 895 * Busy-wait for DMA to complete 896 */ 897 int 898 wdc_dmawait(chp, xfer, timeout) 899 struct channel_softc *chp; 900 struct wdc_xfer *xfer; 901 int timeout; 902 { 903 int time; 904 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 905 chp->wdc->dma_status = 906 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 907 chp->channel, xfer->drive, 0); 908 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 909 return 0; 910 delay(WDCDELAY); 911 } 912 /* timeout, force a DMA halt */ 913 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 914 chp->channel, xfer->drive, 1); 915 return 1; 916 } 917 918 void 919 wdctimeout(arg) 920 void *arg; 921 { 922 struct channel_softc *chp = (struct channel_softc *)arg; 923 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 924 int s; 925 926 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 927 928 s = splbio(); 929 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 930 __wdcerror(chp, "lost interrupt"); 931 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 932 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 933 xfer->c_bcount, 934 xfer->c_skip); 935 if (chp->ch_flags & WDCF_DMA_WAIT) { 936 chp->wdc->dma_status = 937 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 938 chp->channel, xfer->drive, 1); 939 chp->ch_flags &= ~WDCF_DMA_WAIT; 940 } 941 /* 942 * Call the interrupt routine. If we just missed and interrupt, 943 * it will do what's needed. Else, it will take the needed 944 * action (reset the device). 945 * Before that we need to reinstall the timeout callback, 946 * in case it will miss another irq while in this transfer 947 * We arbitray chose it to be 1s 948 */ 949 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 950 xfer->c_flags |= C_TIMEOU; 951 chp->ch_flags &= ~WDCF_IRQ_WAIT; 952 xfer->c_intr(chp, xfer, 1); 953 } else 954 __wdcerror(chp, "missing untimeout"); 955 splx(s); 956 } 957 958 /* 959 * Probe drive's capabilites, for use by the controller later 960 * Assumes drvp points to an existing drive. 961 * XXX this should be a controller-indep function 962 */ 963 void 964 wdc_probe_caps(drvp) 965 struct ata_drive_datas *drvp; 966 { 967 struct ataparams params, params2; 968 struct channel_softc *chp = drvp->chnl_softc; 969 struct device *drv_dev = drvp->drv_softc; 970 struct wdc_softc *wdc = chp->wdc; 971 int i, printed; 972 char *sep = ""; 973 int cf_flags; 974 975 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 976 /* IDENTIFY failed. Can't tell more about the device */ 977 return; 978 } 979 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 980 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 981 /* 982 * Controller claims 16 and 32 bit transfers. 983 * Re-do an IDENTIFY with 32-bit transfers, 984 * and compare results. 985 */ 986 drvp->drive_flags |= DRIVE_CAP32; 987 ata_get_params(drvp, AT_POLL, ¶ms2); 988 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 989 /* Not good. fall back to 16bits */ 990 drvp->drive_flags &= ~DRIVE_CAP32; 991 } else { 992 printf("%s: 32-bit data port", drv_dev->dv_xname); 993 } 994 } 995 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 996 if (params.atap_ata_major > 0x01 && 997 params.atap_ata_major != 0xffff) { 998 for (i = 14; i > 0; i--) { 999 if (params.atap_ata_major & (1 << i)) { 1000 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1001 printf("%s: ", drv_dev->dv_xname); 1002 else 1003 printf(", "); 1004 printf("ATA version %d\n", i); 1005 drvp->ata_vers = i; 1006 break; 1007 } 1008 } 1009 } else 1010 #endif 1011 if (drvp->drive_flags & DRIVE_CAP32) 1012 printf("\n"); 1013 1014 /* An ATAPI device is at last PIO mode 3 */ 1015 if (drvp->drive_flags & DRIVE_ATAPI) 1016 drvp->PIO_mode = 3; 1017 1018 /* 1019 * It's not in the specs, but it seems that some drive 1020 * returns 0xffff in atap_extensions when this field is invalid 1021 */ 1022 if (params.atap_extensions != 0xffff && 1023 (params.atap_extensions & WDC_EXT_MODES)) { 1024 printed = 0; 1025 /* 1026 * XXX some drives report something wrong here (they claim to 1027 * support PIO mode 8 !). As mode is coded on 3 bits in 1028 * SET FEATURE, limit it to 7 (so limit i to 4). 1029 * If higther mode than 7 is found, abort. 1030 */ 1031 for (i = 7; i >= 0; i--) { 1032 if ((params.atap_piomode_supp & (1 << i)) == 0) 1033 continue; 1034 if (i > 4) 1035 return; 1036 /* 1037 * See if mode is accepted. 1038 * If the controller can't set its PIO mode, 1039 * assume the defaults are good, so don't try 1040 * to set it 1041 */ 1042 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1043 if (ata_set_mode(drvp, 0x08 | (i + 3), 1044 AT_POLL) != CMD_OK) 1045 continue; 1046 if (!printed) { 1047 printf("%s: drive supports PIO mode %d", 1048 drv_dev->dv_xname, i + 3); 1049 sep = ","; 1050 printed = 1; 1051 } 1052 /* 1053 * If controller's driver can't set its PIO mode, 1054 * get the highter one for the drive. 1055 */ 1056 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1057 wdc->PIO_cap >= i + 3) { 1058 drvp->PIO_mode = i + 3; 1059 drvp->PIO_cap = i + 3; 1060 break; 1061 } 1062 } 1063 if (!printed) { 1064 /* 1065 * We didn't find a valid PIO mode. 1066 * Assume the values returned for DMA are buggy too 1067 */ 1068 return; 1069 } 1070 drvp->drive_flags |= DRIVE_MODE; 1071 printed = 0; 1072 for (i = 7; i >= 0; i--) { 1073 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1074 continue; 1075 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1076 (wdc->cap & WDC_CAPABILITY_MODE)) 1077 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1078 != CMD_OK) 1079 continue; 1080 if (!printed) { 1081 printf("%s DMA mode %d", sep, i); 1082 sep = ","; 1083 printed = 1; 1084 } 1085 if (wdc->cap & WDC_CAPABILITY_DMA) { 1086 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1087 wdc->DMA_cap < i) 1088 continue; 1089 drvp->DMA_mode = i; 1090 drvp->DMA_cap = i; 1091 drvp->drive_flags |= DRIVE_DMA; 1092 } 1093 break; 1094 } 1095 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1096 printed = 0; 1097 for (i = 7; i >= 0; i--) { 1098 if ((params.atap_udmamode_supp & (1 << i)) 1099 == 0) 1100 continue; 1101 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1102 (wdc->cap & WDC_CAPABILITY_UDMA)) 1103 if (ata_set_mode(drvp, 0x40 | i, 1104 AT_POLL) != CMD_OK) 1105 continue; 1106 if (!printed) { 1107 printf("%s Ultra-DMA mode %d", sep, i); 1108 if (i == 2) 1109 printf(" (Ultra/33)"); 1110 else if (i == 4) 1111 printf(" (Ultra/66)"); 1112 else if (i == 5) 1113 printf(" (Ultra/100)"); 1114 sep = ","; 1115 printed = 1; 1116 } 1117 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1118 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1119 wdc->UDMA_cap < i) 1120 continue; 1121 drvp->UDMA_mode = i; 1122 drvp->UDMA_cap = i; 1123 drvp->drive_flags |= DRIVE_UDMA; 1124 } 1125 break; 1126 } 1127 } 1128 printf("\n"); 1129 } 1130 1131 /* Try to guess ATA version here, if it didn't get reported */ 1132 if (drvp->ata_vers == 0) { 1133 if (drvp->drive_flags & DRIVE_UDMA) 1134 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1135 else if (drvp->PIO_cap > 2) 1136 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1137 } 1138 cf_flags = drv_dev->dv_cfdata->cf_flags; 1139 if (cf_flags & ATA_CONFIG_PIO_SET) { 1140 drvp->PIO_mode = 1141 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1142 drvp->drive_flags |= DRIVE_MODE; 1143 } 1144 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1145 /* don't care about DMA modes */ 1146 return; 1147 } 1148 if (cf_flags & ATA_CONFIG_DMA_SET) { 1149 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1150 ATA_CONFIG_DMA_DISABLE) { 1151 drvp->drive_flags &= ~DRIVE_DMA; 1152 } else { 1153 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1154 ATA_CONFIG_DMA_OFF; 1155 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1156 } 1157 } 1158 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1159 /* don't care about UDMA modes */ 1160 return; 1161 } 1162 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1163 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1164 ATA_CONFIG_UDMA_DISABLE) { 1165 drvp->drive_flags &= ~DRIVE_UDMA; 1166 } else { 1167 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1168 ATA_CONFIG_UDMA_OFF; 1169 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1170 } 1171 } 1172 } 1173 1174 /* 1175 * downgrade the transfer mode of a drive after an error. return 1 if 1176 * downgrade was possible, 0 otherwise. 1177 */ 1178 int 1179 wdc_downgrade_mode(drvp) 1180 struct ata_drive_datas *drvp; 1181 { 1182 struct channel_softc *chp = drvp->chnl_softc; 1183 struct device *drv_dev = drvp->drv_softc; 1184 struct wdc_softc *wdc = chp->wdc; 1185 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1186 1187 /* if drive or controller don't know its mode, we can't do much */ 1188 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1189 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1190 return 0; 1191 /* current drive mode was set by a config flag, let it this way */ 1192 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1193 (cf_flags & ATA_CONFIG_DMA_SET) || 1194 (cf_flags & ATA_CONFIG_UDMA_SET)) 1195 return 0; 1196 1197 /* 1198 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1199 * Maybe we didn't properly notice the cable type 1200 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1201 * It helps in some cases. 1202 */ 1203 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1204 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1205 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1206 drv_dev->dv_xname, drvp->UDMA_mode); 1207 } 1208 1209 /* 1210 * If we were using ultra-DMA, don't downgrade to multiword DMA 1211 * if we noticed a CRC error. It has been noticed that CRC errors 1212 * in ultra-DMA lead to silent data corruption in multiword DMA. 1213 * Data corruption is less likely to occur in PIO mode. 1214 */ 1215 else if ((drvp->drive_flags & DRIVE_UDMA) && 1216 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1217 drvp->drive_flags &= ~DRIVE_UDMA; 1218 drvp->drive_flags |= DRIVE_DMA; 1219 drvp->DMA_mode = drvp->DMA_cap; 1220 printf("%s: transfer error, downgrading to DMA mode %d\n", 1221 drv_dev->dv_xname, drvp->DMA_mode); 1222 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1223 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1224 drvp->PIO_mode = drvp->PIO_cap; 1225 printf("%s: transfer error, downgrading to PIO mode %d\n", 1226 drv_dev->dv_xname, drvp->PIO_mode); 1227 } else /* already using PIO, can't downgrade */ 1228 return 0; 1229 1230 wdc->set_modes(chp); 1231 /* reset the channel, which will shedule all drives for setup */ 1232 wdc_reset_channel(drvp); 1233 return 1; 1234 } 1235 1236 int 1237 wdc_exec_command(drvp, wdc_c) 1238 struct ata_drive_datas *drvp; 1239 struct wdc_command *wdc_c; 1240 { 1241 struct channel_softc *chp = drvp->chnl_softc; 1242 struct wdc_xfer *xfer; 1243 int s, ret; 1244 1245 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1246 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1247 DEBUG_FUNCS); 1248 1249 /* set up an xfer and queue. Wait for completion */ 1250 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1251 WDC_NOSLEEP); 1252 if (xfer == NULL) { 1253 return WDC_TRY_AGAIN; 1254 } 1255 1256 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1257 wdc_c->flags |= AT_POLL; 1258 if (wdc_c->flags & AT_POLL) 1259 xfer->c_flags |= C_POLL; 1260 xfer->drive = drvp->drive; 1261 xfer->databuf = wdc_c->data; 1262 xfer->c_bcount = wdc_c->bcount; 1263 xfer->cmd = wdc_c; 1264 xfer->c_start = __wdccommand_start; 1265 xfer->c_intr = __wdccommand_intr; 1266 xfer->c_kill_xfer = __wdccommand_done; 1267 1268 s = splbio(); 1269 wdc_exec_xfer(chp, xfer); 1270 #ifdef DIAGNOSTIC 1271 if ((wdc_c->flags & AT_POLL) != 0 && 1272 (wdc_c->flags & AT_DONE) == 0) 1273 panic("wdc_exec_command: polled command not done\n"); 1274 #endif 1275 if (wdc_c->flags & AT_DONE) { 1276 ret = WDC_COMPLETE; 1277 } else { 1278 if (wdc_c->flags & AT_WAIT) { 1279 while ((wdc_c->flags & AT_DONE) == 0) { 1280 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1281 } 1282 ret = WDC_COMPLETE; 1283 } else { 1284 ret = WDC_QUEUED; 1285 } 1286 } 1287 splx(s); 1288 return ret; 1289 } 1290 1291 void 1292 __wdccommand_start(chp, xfer) 1293 struct channel_softc *chp; 1294 struct wdc_xfer *xfer; 1295 { 1296 int drive = xfer->drive; 1297 struct wdc_command *wdc_c = xfer->cmd; 1298 1299 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1300 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1301 DEBUG_FUNCS); 1302 1303 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1304 WDSD_IBM | (drive << 4)); 1305 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1306 wdc_c->timeout) != 0) { 1307 wdc_c->flags |= AT_TIMEOU; 1308 __wdccommand_done(chp, xfer); 1309 return; 1310 } 1311 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1312 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1313 if ((wdc_c->flags & AT_POLL) == 0) { 1314 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1315 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1316 wdctimeout, chp); 1317 return; 1318 } 1319 /* 1320 * Polled command. Wait for drive ready or drq. Done in intr(). 1321 * Wait for at last 400ns for status bit to be valid. 1322 */ 1323 delay(10); 1324 __wdccommand_intr(chp, xfer, 0); 1325 } 1326 1327 int 1328 __wdccommand_intr(chp, xfer, irq) 1329 struct channel_softc *chp; 1330 struct wdc_xfer *xfer; 1331 int irq; 1332 { 1333 struct wdc_command *wdc_c = xfer->cmd; 1334 int bcount = wdc_c->bcount; 1335 char *data = wdc_c->data; 1336 1337 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1338 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1339 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1340 (irq == 0) ? wdc_c->timeout : 0)) { 1341 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1342 return 0; /* IRQ was not for us */ 1343 wdc_c->flags |= AT_TIMEOU; 1344 __wdccommand_done(chp, xfer); 1345 return 1; 1346 } 1347 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1348 chp->wdc->irqack(chp); 1349 if (wdc_c->flags & AT_READ) { 1350 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1351 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1352 0, (u_int32_t*)data, bcount >> 2); 1353 data += bcount & 0xfffffffc; 1354 bcount = bcount & 0x03; 1355 } 1356 if (bcount > 0) 1357 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1358 wd_data, (u_int16_t *)data, bcount >> 1); 1359 } else if (wdc_c->flags & AT_WRITE) { 1360 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1361 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1362 0, (u_int32_t*)data, bcount >> 2); 1363 data += bcount & 0xfffffffc; 1364 bcount = bcount & 0x03; 1365 } 1366 if (bcount > 0) 1367 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1368 wd_data, (u_int16_t *)data, bcount >> 1); 1369 } 1370 __wdccommand_done(chp, xfer); 1371 return 1; 1372 } 1373 1374 void 1375 __wdccommand_done(chp, xfer) 1376 struct channel_softc *chp; 1377 struct wdc_xfer *xfer; 1378 { 1379 struct wdc_command *wdc_c = xfer->cmd; 1380 1381 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1382 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1383 1384 callout_stop(&chp->ch_callout); 1385 1386 if (chp->ch_status & WDCS_DWF) 1387 wdc_c->flags |= AT_DF; 1388 if (chp->ch_status & WDCS_ERR) { 1389 wdc_c->flags |= AT_ERROR; 1390 wdc_c->r_error = chp->ch_error; 1391 } 1392 wdc_c->flags |= AT_DONE; 1393 if ((wdc_c->flags & AT_READREG) != 0 && 1394 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1395 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1396 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1397 wd_sdh); 1398 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1399 wd_cyl_hi) << 8; 1400 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1401 wd_cyl_lo); 1402 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1403 wd_sector); 1404 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1405 wd_seccnt); 1406 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1407 wd_error); 1408 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1409 wd_precomp); 1410 } 1411 wdc_free_xfer(chp, xfer); 1412 if (wdc_c->flags & AT_WAIT) 1413 wakeup(wdc_c); 1414 else if (wdc_c->callback) 1415 wdc_c->callback(wdc_c->callback_arg); 1416 wdcstart(chp); 1417 return; 1418 } 1419 1420 /* 1421 * Send a command. The drive should be ready. 1422 * Assumes interrupts are blocked. 1423 */ 1424 void 1425 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1426 struct channel_softc *chp; 1427 u_int8_t drive; 1428 u_int8_t command; 1429 u_int16_t cylin; 1430 u_int8_t head, sector, count, precomp; 1431 { 1432 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1433 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1434 chp->channel, drive, command, cylin, head, sector, count, precomp), 1435 DEBUG_FUNCS); 1436 1437 /* Select drive, head, and addressing mode. */ 1438 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1439 WDSD_IBM | (drive << 4) | head); 1440 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1441 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1442 precomp); 1443 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1444 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1445 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1447 1448 /* Send command. */ 1449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1450 return; 1451 } 1452 1453 /* 1454 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1455 * tested by the caller. 1456 */ 1457 void 1458 wdccommandshort(chp, drive, command) 1459 struct channel_softc *chp; 1460 int drive; 1461 int command; 1462 { 1463 1464 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1465 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1466 DEBUG_FUNCS); 1467 1468 /* Select drive. */ 1469 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1470 WDSD_IBM | (drive << 4)); 1471 1472 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1473 } 1474 1475 /* Add a command to the queue and start controller. Must be called at splbio */ 1476 1477 void 1478 wdc_exec_xfer(chp, xfer) 1479 struct channel_softc *chp; 1480 struct wdc_xfer *xfer; 1481 { 1482 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1483 chp->channel, xfer->drive), DEBUG_XFERS); 1484 1485 /* complete xfer setup */ 1486 xfer->chp = chp; 1487 1488 /* 1489 * If we are a polled command, and the list is not empty, 1490 * we are doing a dump. Drop the list to allow the polled command 1491 * to complete, we're going to reboot soon anyway. 1492 */ 1493 if ((xfer->c_flags & C_POLL) != 0 && 1494 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1495 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1496 } 1497 /* insert at the end of command list */ 1498 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1499 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1500 chp->ch_flags), DEBUG_XFERS); 1501 wdcstart(chp); 1502 } 1503 1504 struct wdc_xfer * 1505 wdc_get_xfer(flags) 1506 int flags; 1507 { 1508 struct wdc_xfer *xfer; 1509 int s; 1510 1511 s = splbio(); 1512 xfer = pool_get(&wdc_xfer_pool, 1513 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1514 splx(s); 1515 if (xfer != NULL) { 1516 memset(xfer, 0, sizeof(struct wdc_xfer)); 1517 } 1518 return xfer; 1519 } 1520 1521 void 1522 wdc_free_xfer(chp, xfer) 1523 struct channel_softc *chp; 1524 struct wdc_xfer *xfer; 1525 { 1526 struct wdc_softc *wdc = chp->wdc; 1527 int s; 1528 1529 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1530 (*wdc->free_hw)(chp); 1531 s = splbio(); 1532 chp->ch_flags &= ~WDCF_ACTIVE; 1533 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1534 pool_put(&wdc_xfer_pool, xfer); 1535 splx(s); 1536 } 1537 1538 /* 1539 * Kill off all pending xfers for a channel_softc. 1540 * 1541 * Must be called at splbio(). 1542 */ 1543 void 1544 wdc_kill_pending(chp) 1545 struct channel_softc *chp; 1546 { 1547 struct wdc_xfer *xfer; 1548 1549 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1550 chp = xfer->chp; 1551 (*xfer->c_kill_xfer)(chp, xfer); 1552 } 1553 } 1554 1555 static void 1556 __wdcerror(chp, msg) 1557 struct channel_softc *chp; 1558 char *msg; 1559 { 1560 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1561 1562 if (xfer == NULL) 1563 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1564 msg); 1565 else 1566 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1567 chp->channel, xfer->drive, msg); 1568 } 1569 1570 /* 1571 * the bit bucket 1572 */ 1573 void 1574 wdcbit_bucket(chp, size) 1575 struct channel_softc *chp; 1576 int size; 1577 { 1578 1579 for (; size >= 2; size -= 2) 1580 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1581 if (size) 1582 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1583 } 1584 1585 int 1586 wdc_addref(chp) 1587 struct channel_softc *chp; 1588 { 1589 struct wdc_softc *wdc = chp->wdc; 1590 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1591 int s, error = 0; 1592 1593 s = splbio(); 1594 if (adapt->adapt_refcnt++ == 0 && 1595 adapt->adapt_enable != NULL) { 1596 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1597 if (error) 1598 adapt->adapt_refcnt--; 1599 } 1600 splx(s); 1601 return (error); 1602 } 1603 1604 void 1605 wdc_delref(chp) 1606 struct channel_softc *chp; 1607 { 1608 struct wdc_softc *wdc = chp->wdc; 1609 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1610 int s; 1611 1612 s = splbio(); 1613 if (adapt->adapt_refcnt-- == 1 && 1614 adapt->adapt_enable != NULL) 1615 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1616 splx(s); 1617 } 1618 1619 void 1620 wdc_print_modes(struct channel_softc *chp) 1621 { 1622 int drive; 1623 struct ata_drive_datas *drvp; 1624 1625 for (drive = 0; drive < 2; drive++) { 1626 drvp = &chp->ch_drive[drive]; 1627 if ((drvp->drive_flags & DRIVE) == 0) 1628 continue; 1629 printf("%s(%s:%d:%d): using PIO mode %d", 1630 drvp->drv_softc->dv_xname, 1631 chp->wdc->sc_dev.dv_xname, 1632 chp->channel, drive, drvp->PIO_mode); 1633 if (drvp->drive_flags & DRIVE_DMA) 1634 printf(", DMA mode %d", drvp->DMA_mode); 1635 if (drvp->drive_flags & DRIVE_UDMA) { 1636 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1637 if (drvp->UDMA_mode == 2) 1638 printf(" (Ultra/33)"); 1639 else if (drvp->UDMA_mode == 4) 1640 printf(" (Ultra/66)"); 1641 else if (drvp->UDMA_mode == 5) 1642 printf(" (Ultra/100)"); 1643 } 1644 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1645 printf(" (using DMA data transfers)"); 1646 printf("\n"); 1647 } 1648 } 1649
Indexes created Tue Sep 23 23:09:58 GMT 2025