wdc.c revision 1.105
1 /* $NetBSD: wdc.c,v 1.105 2001/12/03 11:07:34 enami Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.105 2001/12/03 11:07:34 enami Exp $"); 76 77 #ifndef WDCDEBUG 78 #define WDCDEBUG 79 #endif /* WDCDEBUG */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/conf.h> 85 #include <sys/buf.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/pool.h> 89 #include <sys/syslog.h> 90 #include <sys/proc.h> 91 92 #include <machine/intr.h> 93 #include <machine/bus.h> 94 95 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 96 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 97 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 98 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 99 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 100 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 101 102 #include <dev/ata/atavar.h> 103 #include <dev/ata/wdvar.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "atapibus.h" 109 110 #define WDCDELAY 100 /* 100 microseconds */ 111 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 112 #if 0 113 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 114 #define WDCNDELAY_DEBUG 50 115 #endif 116 117 struct pool wdc_xfer_pool; 118 119 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 120 121 static void __wdcerror __P((struct channel_softc*, char *)); 122 static int __wdcwait_reset __P((struct channel_softc *, int)); 123 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 124 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 125 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 126 int wdprint __P((void *, const char *)); 127 128 #define DEBUG_INTR 0x01 129 #define DEBUG_XFERS 0x02 130 #define DEBUG_STATUS 0x04 131 #define DEBUG_FUNCS 0x08 132 #define DEBUG_PROBE 0x10 133 #define DEBUG_DETACH 0x20 134 #define DEBUG_DELAY 0x40 135 #ifdef WDCDEBUG 136 int wdcdebug_mask = 0; 137 int wdc_nxfer = 0; 138 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 139 #else 140 #define WDCDEBUG_PRINT(args, level) 141 #endif 142 143 int 144 wdprint(aux, pnp) 145 void *aux; 146 const char *pnp; 147 { 148 struct ata_device *adev = aux; 149 if (pnp) 150 printf("drive at %s", pnp); 151 printf(" channel %d drive %d", adev->adev_channel, 152 adev->adev_drv_data->drive); 153 return (UNCONF); 154 } 155 156 /* Test to see controller with at last one attached drive is there. 157 * Returns a bit for each possible drive found (0x01 for drive 0, 158 * 0x02 for drive 1). 159 * Logic: 160 * - If a status register is at 0xff, assume there is no drive here 161 * (ISA has pull-up resistors). Similarly if the status register has 162 * the value we last wrote to the bus (for IDE interfaces without pullups). 163 * If no drive at all -> return. 164 * - reset the controller, wait for it to complete (may take up to 31s !). 165 * If timeout -> return. 166 * - test ATA/ATAPI signatures. If at last one drive found -> return. 167 * - try an ATA command on the master. 168 */ 169 170 int 171 wdcprobe(chp) 172 struct channel_softc *chp; 173 { 174 u_int8_t st0, st1, sc, sn, cl, ch; 175 u_int8_t ret_value = 0x03; 176 u_int8_t drive; 177 int found; 178 179 /* 180 * Sanity check to see if the wdc channel responds at all. 181 */ 182 183 if (chp->wdc == NULL || 184 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 185 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 186 WDSD_IBM); 187 delay(10); 188 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 189 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 190 WDSD_IBM | 0x10); 191 delay(10); 192 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 193 194 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 195 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 196 chp->channel, st0, st1), DEBUG_PROBE); 197 198 if (st0 == 0xff || st0 == WDSD_IBM) 199 ret_value &= ~0x01; 200 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 201 ret_value &= ~0x02; 202 if (ret_value == 0) 203 return 0; 204 } 205 206 /* assert SRST, wait for reset to complete */ 207 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 208 WDSD_IBM); 209 delay(10); 210 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 211 WDCTL_RST | WDCTL_IDS); 212 DELAY(1000); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_IDS); 215 delay(1000); 216 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 217 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 218 delay(10); 219 220 ret_value = __wdcwait_reset(chp, ret_value); 221 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 222 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 223 ret_value), DEBUG_PROBE); 224 225 /* if reset failed, there's nothing here */ 226 if (ret_value == 0) 227 return 0; 228 229 /* 230 * Test presence of drives. First test register signatures looking for 231 * ATAPI devices. If it's not an ATAPI and reset said there may be 232 * something here assume it's ATA or OLD. Ghost will be killed later in 233 * attach routine. 234 */ 235 found = 0; 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 if (1 < ++found && chp->wdc != NULL && 240 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 241 /* 242 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 243 * is set. 244 * 245 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 246 * doesn't seem to implement drive select command. In 247 * this case, you can't eliminate ghost drive properly. 248 */ 249 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 250 chp->wdc->sc_dev.dv_xname, 251 chp->channel, drive), DEBUG_PROBE); 252 break; 253 } 254 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 255 WDSD_IBM | (drive << 4)); 256 delay(10); 257 /* Save registers contents */ 258 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 259 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 260 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 261 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 262 263 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 264 "cl=0x%x ch=0x%x\n", 265 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 266 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 267 /* 268 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 269 * we get wrong values here, so ignore it. 270 */ 271 if (cl == 0x14 && ch == 0xeb) { 272 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 273 } else { 274 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 275 if (chp->wdc == NULL || 276 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 277 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 278 } 279 } 280 return (ret_value); 281 } 282 283 void 284 wdcattach(chp) 285 struct channel_softc *chp; 286 { 287 int channel_flags, ctrl_flags, i, error; 288 struct ataparams params; 289 static int inited = 0; 290 291 callout_init(&chp->ch_callout); 292 293 if ((error = wdc_addref(chp)) != 0) { 294 printf("%s: unable to enable controller\n", 295 chp->wdc->sc_dev.dv_xname); 296 return; 297 } 298 299 if (wdcprobe(chp) == 0) 300 /* If no drives, abort attach here. */ 301 goto out; 302 303 /* initialise global data */ 304 if (inited == 0) { 305 /* Initialize the wdc_xfer pool. */ 306 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 307 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 308 inited++; 309 } 310 TAILQ_INIT(&chp->ch_queue->sc_xfer); 311 312 for (i = 0; i < 2; i++) { 313 chp->ch_drive[i].chnl_softc = chp; 314 chp->ch_drive[i].drive = i; 315 /* 316 * Init error counter so that an error withing the first xfers 317 * will trigger a downgrade 318 */ 319 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 320 321 /* If controller can't do 16bit flag the drives as 32bit */ 322 if ((chp->wdc->cap & 323 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 324 WDC_CAPABILITY_DATA32) 325 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 326 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 327 continue; 328 329 /* 330 * Wait a bit, some devices are weird just after a reset. 331 * Then issue a IDENTIFY command, to try to detect slave ghost 332 */ 333 delay(100); 334 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 335 if (error != CMD_OK) { 336 delay(1000000); 337 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 338 ¶ms); 339 } 340 if (error == CMD_OK) { 341 /* If IDENTIFY succeded, this is not an OLD ctrl */ 342 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 343 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 344 } else { 345 chp->ch_drive[i].drive_flags &= 346 ~(DRIVE_ATA | DRIVE_ATAPI); 347 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 348 chp->wdc->sc_dev.dv_xname, 349 chp->channel, i, error), DEBUG_PROBE); 350 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 351 continue; 352 /* 353 * Pre-ATA drive ? 354 * Test registers writability (Error register not 355 * writable, but cyllo is), then try an ATA command. 356 */ 357 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 358 WDSD_IBM | (i << 4)); 359 delay(10); 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 361 wd_error, 0x58); 362 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 363 wd_cyl_lo, 0xa5); 364 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 365 wd_error == 0x58) || 366 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 367 wd_cyl_lo) != 0xa5) { 368 WDCDEBUG_PRINT(("%s:%d:%d: register " 369 "writability failed\n", 370 chp->wdc->sc_dev.dv_xname, 371 chp->channel, i), DEBUG_PROBE); 372 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 373 } 374 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 375 WDSD_IBM | (i << 4)); 376 delay(100); 377 if (wait_for_ready(chp, 10000) != 0) { 378 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 379 chp->wdc->sc_dev.dv_xname, 380 chp->channel, i), DEBUG_PROBE); 381 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 382 continue; 383 } 384 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 385 wd_command, WDCC_RECAL); 386 if (wait_for_ready(chp, 10000) != 0) { 387 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 388 chp->wdc->sc_dev.dv_xname, 389 chp->channel, i), DEBUG_PROBE); 390 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 391 } 392 } 393 } 394 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 395 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 396 397 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 398 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 399 DEBUG_PROBE); 400 401 /* If no drives, abort here */ 402 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 403 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 404 goto out; 405 406 /* 407 * Attach an ATAPI bus, if needed. 408 */ 409 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 410 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 411 #if NATAPIBUS > 0 412 wdc_atapibus_attach(chp); 413 #else 414 /* 415 * Fake the autoconfig "not configured" message 416 */ 417 printf("atapibus at %s channel %d not configured\n", 418 chp->wdc->sc_dev.dv_xname, chp->channel); 419 chp->atapibus = NULL; 420 #endif 421 } 422 423 for (i = 0; i < 2; i++) { 424 struct ata_device adev; 425 if ((chp->ch_drive[i].drive_flags & 426 (DRIVE_ATA | DRIVE_OLD)) == 0) { 427 continue; 428 } 429 memset(&adev, 0, sizeof(struct ata_device)); 430 adev.adev_bustype = &wdc_ata_bustype; 431 adev.adev_channel = chp->channel; 432 adev.adev_openings = 1; 433 adev.adev_drv_data = &chp->ch_drive[i]; 434 if (config_found(&chp->wdc->sc_dev, (void *)&adev, wdprint)) 435 wdc_probe_caps(&chp->ch_drive[i]); 436 } 437 438 /* 439 * reset drive_flags for unnatached devices, reset state for attached 440 * ones 441 */ 442 for (i = 0; i < 2; i++) { 443 if (chp->ch_drive[i].drv_softc == NULL) 444 chp->ch_drive[i].drive_flags = 0; 445 else 446 chp->ch_drive[i].state = 0; 447 } 448 449 /* 450 * Reset channel. The probe, with some combinations of ATA/ATAPI 451 * devices keep it in a mostly working, but strange state (with busy 452 * led on) 453 */ 454 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 455 delay(50); 456 wdcreset(chp, VERBOSE); 457 /* 458 * Read status registers to avoid spurious interrupts. 459 */ 460 for (i = 1; i >= 0; i--) { 461 if (chp->ch_drive[i].drive_flags & DRIVE) { 462 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 463 wd_sdh, WDSD_IBM | (i << 4)); 464 if (wait_for_unbusy(chp, 10000) < 0) 465 printf("%s:%d:%d: device busy\n", 466 chp->wdc->sc_dev.dv_xname, 467 chp->channel, i); 468 } 469 } 470 } 471 472 out: 473 wdc_delref(chp); 474 } 475 476 /* 477 * Call activate routine of underlying devices. 478 */ 479 int 480 wdcactivate(self, act) 481 struct device *self; 482 enum devact act; 483 { 484 struct wdc_softc *wdc = (struct wdc_softc *)self; 485 struct channel_softc *chp; 486 struct device *sc = 0; 487 int s, i, j, error = 0; 488 489 s = splbio(); 490 switch (act) { 491 case DVACT_ACTIVATE: 492 error = EOPNOTSUPP; 493 break; 494 495 case DVACT_DEACTIVATE: 496 for (i = 0; i < wdc->nchannels; i++) { 497 chp = wdc->channels[i]; 498 499 /* 500 * We might call deactivate routine for 501 * the children of atapibus twice (once via 502 * atapibus, once directly), but since 503 * config_deactivate maintains DVF_ACTIVE flag, 504 * it's safe. 505 */ 506 sc = chp->atapibus; 507 if (sc != NULL) { 508 error = config_deactivate(sc); 509 if (error != 0) 510 goto out; 511 } 512 513 for (j = 0; j < 2; j++) { 514 sc = chp->ch_drive[j].drv_softc; 515 WDCDEBUG_PRINT(("wdcactivate: %s:" 516 " deactivating %s\n", wdc->sc_dev.dv_xname, 517 sc == NULL ? "nodrv" : sc->dv_xname), 518 DEBUG_DETACH); 519 if (sc != NULL) { 520 error = config_deactivate(sc); 521 if (error != 0) 522 goto out; 523 } 524 } 525 } 526 break; 527 } 528 529 out: 530 splx(s); 531 532 #ifdef WDCDEBUG 533 if (sc && error != 0) 534 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 535 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 536 #endif 537 return (error); 538 } 539 540 int 541 wdcdetach(self, flags) 542 struct device *self; 543 int flags; 544 { 545 struct wdc_softc *wdc = (struct wdc_softc *)self; 546 struct channel_softc *chp; 547 struct device *sc = 0; 548 int i, j, error = 0; 549 550 for (i = 0; i < wdc->nchannels; i++) { 551 chp = wdc->channels[i]; 552 553 /* 554 * Detach atapibus and its children. 555 */ 556 sc = chp->atapibus; 557 if (sc != NULL) { 558 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 559 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 560 error = config_detach(sc, flags); 561 if (error != 0) 562 goto out; 563 } 564 565 /* 566 * Detach our other children. 567 */ 568 for (j = 0; j < 2; j++) { 569 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 570 continue; 571 sc = chp->ch_drive[j].drv_softc; 572 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 573 wdc->sc_dev.dv_xname, 574 sc == NULL ? "nodrv" : sc->dv_xname), 575 DEBUG_DETACH); 576 if (sc != NULL) { 577 error = config_detach(sc, flags); 578 if (error != 0) 579 goto out; 580 } 581 } 582 583 wdc_kill_pending(chp); 584 } 585 586 out: 587 #ifdef WDCDEBUG 588 if (sc && error != 0) 589 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 590 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 591 #endif 592 return (error); 593 } 594 595 /* 596 * Start I/O on a controller, for the given channel. 597 * The first xfer may be not for our channel if the channel queues 598 * are shared. 599 */ 600 void 601 wdcstart(chp) 602 struct channel_softc *chp; 603 { 604 struct wdc_xfer *xfer; 605 606 #ifdef WDC_DIAGNOSTIC 607 int spl1, spl2; 608 609 spl1 = splbio(); 610 spl2 = splbio(); 611 if (spl2 != spl1) { 612 printf("wdcstart: not at splbio()\n"); 613 panic("wdcstart"); 614 } 615 splx(spl2); 616 splx(spl1); 617 #endif /* WDC_DIAGNOSTIC */ 618 619 /* is there a xfer ? */ 620 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 621 return; 622 623 /* adjust chp, in case we have a shared queue */ 624 chp = xfer->chp; 625 626 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 627 return; /* channel aleady active */ 628 } 629 #ifdef DIAGNOSTIC 630 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 631 panic("wdcstart: channel waiting for irq\n"); 632 #endif 633 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 634 if (!(*chp->wdc->claim_hw)(chp, 0)) 635 return; 636 637 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 638 chp->channel, xfer->drive), DEBUG_XFERS); 639 chp->ch_flags |= WDCF_ACTIVE; 640 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 641 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 642 chp->ch_drive[xfer->drive].state = 0; 643 } 644 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 645 KASSERT(xfer->c_flags & C_POLL); 646 xfer->c_start(chp, xfer); 647 } 648 649 /* restart an interrupted I/O */ 650 void 651 wdcrestart(v) 652 void *v; 653 { 654 struct channel_softc *chp = v; 655 int s; 656 657 s = splbio(); 658 wdcstart(chp); 659 splx(s); 660 } 661 662 663 /* 664 * Interrupt routine for the controller. Acknowledge the interrupt, check for 665 * errors on the current operation, mark it done if necessary, and start the 666 * next request. Also check for a partially done transfer, and continue with 667 * the next chunk if so. 668 */ 669 int 670 wdcintr(arg) 671 void *arg; 672 { 673 struct channel_softc *chp = arg; 674 struct wdc_xfer *xfer; 675 int ret; 676 677 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 678 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 679 DEBUG_INTR); 680 return (0); 681 } 682 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 683 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 684 return (0); 685 } 686 687 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 688 xfer = chp->ch_queue->sc_xfer.tqh_first; 689 if (chp->ch_flags & WDCF_DMA_WAIT) { 690 chp->wdc->dma_status = 691 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 692 xfer->drive, 0); 693 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 694 /* IRQ not for us, not detected by DMA engine */ 695 return 0; 696 } 697 chp->ch_flags &= ~WDCF_DMA_WAIT; 698 } 699 chp->ch_flags &= ~WDCF_IRQ_WAIT; 700 ret = xfer->c_intr(chp, xfer, 1); 701 if (ret == 0) /* irq was not for us, still waiting for irq */ 702 chp->ch_flags |= WDCF_IRQ_WAIT; 703 return (ret); 704 } 705 706 /* Put all disk in RESET state */ 707 void wdc_reset_channel(drvp) 708 struct ata_drive_datas *drvp; 709 { 710 struct channel_softc *chp = drvp->chnl_softc; 711 int drive; 712 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 713 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 714 DEBUG_FUNCS); 715 (void) wdcreset(chp, VERBOSE); 716 for (drive = 0; drive < 2; drive++) { 717 chp->ch_drive[drive].state = 0; 718 } 719 } 720 721 int 722 wdcreset(chp, verb) 723 struct channel_softc *chp; 724 int verb; 725 { 726 int drv_mask1, drv_mask2; 727 728 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 729 WDSD_IBM); /* master */ 730 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 731 WDCTL_RST | WDCTL_IDS); 732 delay(1000); 733 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 734 WDCTL_IDS); 735 delay(1000); 736 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 737 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 738 WDCTL_4BIT); 739 740 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 741 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 742 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 743 if (verb && drv_mask2 != drv_mask1) { 744 printf("%s channel %d: reset failed for", 745 chp->wdc->sc_dev.dv_xname, chp->channel); 746 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 747 printf(" drive 0"); 748 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 749 printf(" drive 1"); 750 printf("\n"); 751 } 752 return (drv_mask1 != drv_mask2) ? 1 : 0; 753 } 754 755 static int 756 __wdcwait_reset(chp, drv_mask) 757 struct channel_softc *chp; 758 int drv_mask; 759 { 760 int timeout; 761 u_int8_t st0, st1; 762 #ifdef WDCDEBUG 763 u_int8_t sc0, sn0, cl0, ch0; 764 u_int8_t sc1, sn1, cl1, ch1; 765 #endif 766 /* wait for BSY to deassert */ 767 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 768 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 769 WDSD_IBM); /* master */ 770 delay(10); 771 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 772 #ifdef WDCDEBUG 773 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 774 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 775 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 776 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 777 #endif 778 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 779 WDSD_IBM | 0x10); /* slave */ 780 delay(10); 781 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 782 #ifdef WDCDEBUG 783 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 784 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 785 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 786 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 787 #endif 788 789 if ((drv_mask & 0x01) == 0) { 790 /* no master */ 791 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 792 /* No master, slave is ready, it's done */ 793 goto end; 794 } 795 } else if ((drv_mask & 0x02) == 0) { 796 /* no slave */ 797 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 798 /* No slave, master is ready, it's done */ 799 goto end; 800 } 801 } else { 802 /* Wait for both master and slave to be ready */ 803 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 804 goto end; 805 } 806 } 807 delay(WDCDELAY); 808 } 809 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 810 if (st0 & WDCS_BSY) 811 drv_mask &= ~0x01; 812 if (st1 & WDCS_BSY) 813 drv_mask &= ~0x02; 814 end: 815 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 816 "cl=0x%x ch=0x%x\n", 817 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 818 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 819 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 820 "cl=0x%x ch=0x%x\n", 821 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 822 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 823 824 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 825 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 826 st0, st1), DEBUG_PROBE); 827 828 return drv_mask; 829 } 830 831 /* 832 * Wait for a drive to be !BSY, and have mask in its status register. 833 * return -1 for a timeout after "timeout" ms. 834 */ 835 int 836 wdcwait(chp, mask, bits, timeout) 837 struct channel_softc *chp; 838 int mask, bits, timeout; 839 { 840 u_char status; 841 int time = 0; 842 #ifdef WDCNDELAY_DEBUG 843 extern int cold; 844 #endif 845 846 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 847 :"none", chp->channel), DEBUG_STATUS); 848 chp->ch_error = 0; 849 850 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 851 852 for (;;) { 853 chp->ch_status = status = 854 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 855 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 856 break; 857 if (++time > timeout) { 858 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 859 "status %x error %x (mask 0x%x bits 0x%x)\n", 860 time, status, 861 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 862 wd_error), mask, bits), 863 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 864 return -1; 865 } 866 delay(WDCDELAY); 867 } 868 #ifdef WDCDEBUG 869 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 870 printf("wdcwait: did busy-wait, time=%d\n", time); 871 #endif 872 if (status & WDCS_ERR) 873 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 874 wd_error); 875 #ifdef WDCNDELAY_DEBUG 876 /* After autoconfig, there should be no long delays. */ 877 if (!cold && time > WDCNDELAY_DEBUG) { 878 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 879 if (xfer == NULL) 880 printf("%s channel %d: warning: busy-wait took %dus\n", 881 chp->wdc->sc_dev.dv_xname, chp->channel, 882 WDCDELAY * time); 883 else 884 printf("%s:%d:%d: warning: busy-wait took %dus\n", 885 chp->wdc->sc_dev.dv_xname, chp->channel, 886 xfer->drive, 887 WDCDELAY * time); 888 } 889 #endif 890 return 0; 891 } 892 893 /* 894 * Busy-wait for DMA to complete 895 */ 896 int 897 wdc_dmawait(chp, xfer, timeout) 898 struct channel_softc *chp; 899 struct wdc_xfer *xfer; 900 int timeout; 901 { 902 int time; 903 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 904 chp->wdc->dma_status = 905 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 906 chp->channel, xfer->drive, 0); 907 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 908 return 0; 909 delay(WDCDELAY); 910 } 911 /* timeout, force a DMA halt */ 912 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 913 chp->channel, xfer->drive, 1); 914 return 1; 915 } 916 917 void 918 wdctimeout(arg) 919 void *arg; 920 { 921 struct channel_softc *chp = (struct channel_softc *)arg; 922 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 923 int s; 924 925 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 926 927 s = splbio(); 928 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 929 __wdcerror(chp, "lost interrupt"); 930 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 931 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 932 xfer->c_bcount, 933 xfer->c_skip); 934 if (chp->ch_flags & WDCF_DMA_WAIT) { 935 chp->wdc->dma_status = 936 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 937 chp->channel, xfer->drive, 1); 938 chp->ch_flags &= ~WDCF_DMA_WAIT; 939 } 940 /* 941 * Call the interrupt routine. If we just missed and interrupt, 942 * it will do what's needed. Else, it will take the needed 943 * action (reset the device). 944 * Before that we need to reinstall the timeout callback, 945 * in case it will miss another irq while in this transfer 946 * We arbitray chose it to be 1s 947 */ 948 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 949 xfer->c_flags |= C_TIMEOU; 950 chp->ch_flags &= ~WDCF_IRQ_WAIT; 951 xfer->c_intr(chp, xfer, 1); 952 } else 953 __wdcerror(chp, "missing untimeout"); 954 splx(s); 955 } 956 957 /* 958 * Probe drive's capabilites, for use by the controller later 959 * Assumes drvp points to an existing drive. 960 * XXX this should be a controller-indep function 961 */ 962 void 963 wdc_probe_caps(drvp) 964 struct ata_drive_datas *drvp; 965 { 966 struct ataparams params, params2; 967 struct channel_softc *chp = drvp->chnl_softc; 968 struct device *drv_dev = drvp->drv_softc; 969 struct wdc_softc *wdc = chp->wdc; 970 int i, printed; 971 char *sep = ""; 972 int cf_flags; 973 974 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 975 /* IDENTIFY failed. Can't tell more about the device */ 976 return; 977 } 978 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 979 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 980 /* 981 * Controller claims 16 and 32 bit transfers. 982 * Re-do an IDENTIFY with 32-bit transfers, 983 * and compare results. 984 */ 985 drvp->drive_flags |= DRIVE_CAP32; 986 ata_get_params(drvp, AT_POLL, ¶ms2); 987 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 988 /* Not good. fall back to 16bits */ 989 drvp->drive_flags &= ~DRIVE_CAP32; 990 } else { 991 printf("%s: 32-bit data port", drv_dev->dv_xname); 992 } 993 } 994 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 995 if (params.atap_ata_major > 0x01 && 996 params.atap_ata_major != 0xffff) { 997 for (i = 14; i > 0; i--) { 998 if (params.atap_ata_major & (1 << i)) { 999 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1000 printf("%s: ", drv_dev->dv_xname); 1001 else 1002 printf(", "); 1003 printf("ATA version %d\n", i); 1004 drvp->ata_vers = i; 1005 break; 1006 } 1007 } 1008 } else 1009 #endif 1010 if (drvp->drive_flags & DRIVE_CAP32) 1011 printf("\n"); 1012 1013 /* An ATAPI device is at last PIO mode 3 */ 1014 if (drvp->drive_flags & DRIVE_ATAPI) 1015 drvp->PIO_mode = 3; 1016 1017 /* 1018 * It's not in the specs, but it seems that some drive 1019 * returns 0xffff in atap_extensions when this field is invalid 1020 */ 1021 if (params.atap_extensions != 0xffff && 1022 (params.atap_extensions & WDC_EXT_MODES)) { 1023 printed = 0; 1024 /* 1025 * XXX some drives report something wrong here (they claim to 1026 * support PIO mode 8 !). As mode is coded on 3 bits in 1027 * SET FEATURE, limit it to 7 (so limit i to 4). 1028 * If higther mode than 7 is found, abort. 1029 */ 1030 for (i = 7; i >= 0; i--) { 1031 if ((params.atap_piomode_supp & (1 << i)) == 0) 1032 continue; 1033 if (i > 4) 1034 return; 1035 /* 1036 * See if mode is accepted. 1037 * If the controller can't set its PIO mode, 1038 * assume the defaults are good, so don't try 1039 * to set it 1040 */ 1041 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1042 if (ata_set_mode(drvp, 0x08 | (i + 3), 1043 AT_POLL) != CMD_OK) 1044 continue; 1045 if (!printed) { 1046 printf("%s: drive supports PIO mode %d", 1047 drv_dev->dv_xname, i + 3); 1048 sep = ","; 1049 printed = 1; 1050 } 1051 /* 1052 * If controller's driver can't set its PIO mode, 1053 * get the highter one for the drive. 1054 */ 1055 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1056 wdc->PIO_cap >= i + 3) { 1057 drvp->PIO_mode = i + 3; 1058 drvp->PIO_cap = i + 3; 1059 break; 1060 } 1061 } 1062 if (!printed) { 1063 /* 1064 * We didn't find a valid PIO mode. 1065 * Assume the values returned for DMA are buggy too 1066 */ 1067 return; 1068 } 1069 drvp->drive_flags |= DRIVE_MODE; 1070 printed = 0; 1071 for (i = 7; i >= 0; i--) { 1072 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1073 continue; 1074 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1075 (wdc->cap & WDC_CAPABILITY_MODE)) 1076 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1077 != CMD_OK) 1078 continue; 1079 if (!printed) { 1080 printf("%s DMA mode %d", sep, i); 1081 sep = ","; 1082 printed = 1; 1083 } 1084 if (wdc->cap & WDC_CAPABILITY_DMA) { 1085 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1086 wdc->DMA_cap < i) 1087 continue; 1088 drvp->DMA_mode = i; 1089 drvp->DMA_cap = i; 1090 drvp->drive_flags |= DRIVE_DMA; 1091 } 1092 break; 1093 } 1094 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1095 printed = 0; 1096 for (i = 7; i >= 0; i--) { 1097 if ((params.atap_udmamode_supp & (1 << i)) 1098 == 0) 1099 continue; 1100 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1101 (wdc->cap & WDC_CAPABILITY_UDMA)) 1102 if (ata_set_mode(drvp, 0x40 | i, 1103 AT_POLL) != CMD_OK) 1104 continue; 1105 if (!printed) { 1106 printf("%s Ultra-DMA mode %d", sep, i); 1107 if (i == 2) 1108 printf(" (Ultra/33)"); 1109 else if (i == 4) 1110 printf(" (Ultra/66)"); 1111 else if (i == 5) 1112 printf(" (Ultra/100)"); 1113 sep = ","; 1114 printed = 1; 1115 } 1116 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1117 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1118 wdc->UDMA_cap < i) 1119 continue; 1120 drvp->UDMA_mode = i; 1121 drvp->UDMA_cap = i; 1122 drvp->drive_flags |= DRIVE_UDMA; 1123 } 1124 break; 1125 } 1126 } 1127 printf("\n"); 1128 } 1129 1130 /* Try to guess ATA version here, if it didn't get reported */ 1131 if (drvp->ata_vers == 0) { 1132 if (drvp->drive_flags & DRIVE_UDMA) 1133 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1134 else if (drvp->PIO_cap > 2) 1135 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1136 } 1137 cf_flags = drv_dev->dv_cfdata->cf_flags; 1138 if (cf_flags & ATA_CONFIG_PIO_SET) { 1139 drvp->PIO_mode = 1140 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1141 drvp->drive_flags |= DRIVE_MODE; 1142 } 1143 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1144 /* don't care about DMA modes */ 1145 return; 1146 } 1147 if (cf_flags & ATA_CONFIG_DMA_SET) { 1148 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1149 ATA_CONFIG_DMA_DISABLE) { 1150 drvp->drive_flags &= ~DRIVE_DMA; 1151 } else { 1152 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1153 ATA_CONFIG_DMA_OFF; 1154 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1155 } 1156 } 1157 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1158 /* don't care about UDMA modes */ 1159 return; 1160 } 1161 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1162 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1163 ATA_CONFIG_UDMA_DISABLE) { 1164 drvp->drive_flags &= ~DRIVE_UDMA; 1165 } else { 1166 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1167 ATA_CONFIG_UDMA_OFF; 1168 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1169 } 1170 } 1171 } 1172 1173 /* 1174 * downgrade the transfer mode of a drive after an error. return 1 if 1175 * downgrade was possible, 0 otherwise. 1176 */ 1177 int 1178 wdc_downgrade_mode(drvp) 1179 struct ata_drive_datas *drvp; 1180 { 1181 struct channel_softc *chp = drvp->chnl_softc; 1182 struct device *drv_dev = drvp->drv_softc; 1183 struct wdc_softc *wdc = chp->wdc; 1184 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1185 1186 /* if drive or controller don't know its mode, we can't do much */ 1187 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1188 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1189 return 0; 1190 /* current drive mode was set by a config flag, let it this way */ 1191 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1192 (cf_flags & ATA_CONFIG_DMA_SET) || 1193 (cf_flags & ATA_CONFIG_UDMA_SET)) 1194 return 0; 1195 1196 /* 1197 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1198 * Maybe we didn't properly notice the cable type 1199 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1200 * It helps in some cases. 1201 */ 1202 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1203 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1204 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1205 drv_dev->dv_xname, drvp->UDMA_mode); 1206 } 1207 1208 /* 1209 * If we were using ultra-DMA, don't downgrade to multiword DMA 1210 * if we noticed a CRC error. It has been noticed that CRC errors 1211 * in ultra-DMA lead to silent data corruption in multiword DMA. 1212 * Data corruption is less likely to occur in PIO mode. 1213 */ 1214 else if ((drvp->drive_flags & DRIVE_UDMA) && 1215 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1216 drvp->drive_flags &= ~DRIVE_UDMA; 1217 drvp->drive_flags |= DRIVE_DMA; 1218 drvp->DMA_mode = drvp->DMA_cap; 1219 printf("%s: transfer error, downgrading to DMA mode %d\n", 1220 drv_dev->dv_xname, drvp->DMA_mode); 1221 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1222 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1223 drvp->PIO_mode = drvp->PIO_cap; 1224 printf("%s: transfer error, downgrading to PIO mode %d\n", 1225 drv_dev->dv_xname, drvp->PIO_mode); 1226 } else /* already using PIO, can't downgrade */ 1227 return 0; 1228 1229 wdc->set_modes(chp); 1230 /* reset the channel, which will shedule all drives for setup */ 1231 wdc_reset_channel(drvp); 1232 return 1; 1233 } 1234 1235 int 1236 wdc_exec_command(drvp, wdc_c) 1237 struct ata_drive_datas *drvp; 1238 struct wdc_command *wdc_c; 1239 { 1240 struct channel_softc *chp = drvp->chnl_softc; 1241 struct wdc_xfer *xfer; 1242 int s, ret; 1243 1244 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1245 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1246 DEBUG_FUNCS); 1247 1248 /* set up an xfer and queue. Wait for completion */ 1249 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1250 WDC_NOSLEEP); 1251 if (xfer == NULL) { 1252 return WDC_TRY_AGAIN; 1253 } 1254 1255 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1256 wdc_c->flags |= AT_POLL; 1257 if (wdc_c->flags & AT_POLL) 1258 xfer->c_flags |= C_POLL; 1259 xfer->drive = drvp->drive; 1260 xfer->databuf = wdc_c->data; 1261 xfer->c_bcount = wdc_c->bcount; 1262 xfer->cmd = wdc_c; 1263 xfer->c_start = __wdccommand_start; 1264 xfer->c_intr = __wdccommand_intr; 1265 xfer->c_kill_xfer = __wdccommand_done; 1266 1267 s = splbio(); 1268 wdc_exec_xfer(chp, xfer); 1269 #ifdef DIAGNOSTIC 1270 if ((wdc_c->flags & AT_POLL) != 0 && 1271 (wdc_c->flags & AT_DONE) == 0) 1272 panic("wdc_exec_command: polled command not done\n"); 1273 #endif 1274 if (wdc_c->flags & AT_DONE) { 1275 ret = WDC_COMPLETE; 1276 } else { 1277 if (wdc_c->flags & AT_WAIT) { 1278 while ((wdc_c->flags & AT_DONE) == 0) { 1279 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1280 } 1281 ret = WDC_COMPLETE; 1282 } else { 1283 ret = WDC_QUEUED; 1284 } 1285 } 1286 splx(s); 1287 return ret; 1288 } 1289 1290 void 1291 __wdccommand_start(chp, xfer) 1292 struct channel_softc *chp; 1293 struct wdc_xfer *xfer; 1294 { 1295 int drive = xfer->drive; 1296 struct wdc_command *wdc_c = xfer->cmd; 1297 1298 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1299 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1300 DEBUG_FUNCS); 1301 1302 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1303 WDSD_IBM | (drive << 4)); 1304 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1305 wdc_c->timeout) != 0) { 1306 wdc_c->flags |= AT_TIMEOU; 1307 __wdccommand_done(chp, xfer); 1308 return; 1309 } 1310 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1311 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1312 if ((wdc_c->flags & AT_POLL) == 0) { 1313 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1314 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1315 wdctimeout, chp); 1316 return; 1317 } 1318 /* 1319 * Polled command. Wait for drive ready or drq. Done in intr(). 1320 * Wait for at last 400ns for status bit to be valid. 1321 */ 1322 delay(10); 1323 __wdccommand_intr(chp, xfer, 0); 1324 } 1325 1326 int 1327 __wdccommand_intr(chp, xfer, irq) 1328 struct channel_softc *chp; 1329 struct wdc_xfer *xfer; 1330 int irq; 1331 { 1332 struct wdc_command *wdc_c = xfer->cmd; 1333 int bcount = wdc_c->bcount; 1334 char *data = wdc_c->data; 1335 1336 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1337 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1338 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1339 (irq == 0) ? wdc_c->timeout : 0)) { 1340 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1341 return 0; /* IRQ was not for us */ 1342 wdc_c->flags |= AT_TIMEOU; 1343 __wdccommand_done(chp, xfer); 1344 return 1; 1345 } 1346 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1347 chp->wdc->irqack(chp); 1348 if (wdc_c->flags & AT_READ) { 1349 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1350 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1351 0, (u_int32_t*)data, bcount >> 2); 1352 data += bcount & 0xfffffffc; 1353 bcount = bcount & 0x03; 1354 } 1355 if (bcount > 0) 1356 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1357 wd_data, (u_int16_t *)data, bcount >> 1); 1358 } else if (wdc_c->flags & AT_WRITE) { 1359 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1360 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1361 0, (u_int32_t*)data, bcount >> 2); 1362 data += bcount & 0xfffffffc; 1363 bcount = bcount & 0x03; 1364 } 1365 if (bcount > 0) 1366 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1367 wd_data, (u_int16_t *)data, bcount >> 1); 1368 } 1369 __wdccommand_done(chp, xfer); 1370 return 1; 1371 } 1372 1373 void 1374 __wdccommand_done(chp, xfer) 1375 struct channel_softc *chp; 1376 struct wdc_xfer *xfer; 1377 { 1378 struct wdc_command *wdc_c = xfer->cmd; 1379 1380 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1381 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1382 1383 callout_stop(&chp->ch_callout); 1384 1385 if (chp->ch_status & WDCS_DWF) 1386 wdc_c->flags |= AT_DF; 1387 if (chp->ch_status & WDCS_ERR) { 1388 wdc_c->flags |= AT_ERROR; 1389 wdc_c->r_error = chp->ch_error; 1390 } 1391 wdc_c->flags |= AT_DONE; 1392 if ((wdc_c->flags & AT_READREG) != 0 && 1393 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1394 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1395 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1396 wd_sdh); 1397 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1398 wd_cyl_hi) << 8; 1399 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1400 wd_cyl_lo); 1401 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1402 wd_sector); 1403 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1404 wd_seccnt); 1405 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1406 wd_error); 1407 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1408 wd_precomp); 1409 } 1410 wdc_free_xfer(chp, xfer); 1411 if (wdc_c->flags & AT_WAIT) 1412 wakeup(wdc_c); 1413 else if (wdc_c->callback) 1414 wdc_c->callback(wdc_c->callback_arg); 1415 wdcstart(chp); 1416 return; 1417 } 1418 1419 /* 1420 * Send a command. The drive should be ready. 1421 * Assumes interrupts are blocked. 1422 */ 1423 void 1424 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1425 struct channel_softc *chp; 1426 u_int8_t drive; 1427 u_int8_t command; 1428 u_int16_t cylin; 1429 u_int8_t head, sector, count, precomp; 1430 { 1431 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1432 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1433 chp->channel, drive, command, cylin, head, sector, count, precomp), 1434 DEBUG_FUNCS); 1435 1436 /* Select drive, head, and addressing mode. */ 1437 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1438 WDSD_IBM | (drive << 4) | head); 1439 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1440 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1441 precomp); 1442 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1443 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1444 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1445 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1446 1447 /* Send command. */ 1448 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1449 return; 1450 } 1451 1452 /* 1453 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1454 * tested by the caller. 1455 */ 1456 void 1457 wdccommandshort(chp, drive, command) 1458 struct channel_softc *chp; 1459 int drive; 1460 int command; 1461 { 1462 1463 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1464 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1465 DEBUG_FUNCS); 1466 1467 /* Select drive. */ 1468 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1469 WDSD_IBM | (drive << 4)); 1470 1471 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1472 } 1473 1474 /* Add a command to the queue and start controller. Must be called at splbio */ 1475 1476 void 1477 wdc_exec_xfer(chp, xfer) 1478 struct channel_softc *chp; 1479 struct wdc_xfer *xfer; 1480 { 1481 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1482 chp->channel, xfer->drive), DEBUG_XFERS); 1483 1484 /* complete xfer setup */ 1485 xfer->chp = chp; 1486 1487 /* 1488 * If we are a polled command, and the list is not empty, 1489 * we are doing a dump. Drop the list to allow the polled command 1490 * to complete, we're going to reboot soon anyway. 1491 */ 1492 if ((xfer->c_flags & C_POLL) != 0 && 1493 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1494 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1495 } 1496 /* insert at the end of command list */ 1497 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1498 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1499 chp->ch_flags), DEBUG_XFERS); 1500 wdcstart(chp); 1501 } 1502 1503 struct wdc_xfer * 1504 wdc_get_xfer(flags) 1505 int flags; 1506 { 1507 struct wdc_xfer *xfer; 1508 int s; 1509 1510 s = splbio(); 1511 xfer = pool_get(&wdc_xfer_pool, 1512 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1513 splx(s); 1514 if (xfer != NULL) { 1515 memset(xfer, 0, sizeof(struct wdc_xfer)); 1516 } 1517 return xfer; 1518 } 1519 1520 void 1521 wdc_free_xfer(chp, xfer) 1522 struct channel_softc *chp; 1523 struct wdc_xfer *xfer; 1524 { 1525 struct wdc_softc *wdc = chp->wdc; 1526 int s; 1527 1528 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1529 (*wdc->free_hw)(chp); 1530 s = splbio(); 1531 chp->ch_flags &= ~WDCF_ACTIVE; 1532 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1533 pool_put(&wdc_xfer_pool, xfer); 1534 splx(s); 1535 } 1536 1537 /* 1538 * Kill off all pending xfers for a channel_softc. 1539 * 1540 * Must be called at splbio(). 1541 */ 1542 void 1543 wdc_kill_pending(chp) 1544 struct channel_softc *chp; 1545 { 1546 struct wdc_xfer *xfer; 1547 1548 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1549 chp = xfer->chp; 1550 (*xfer->c_kill_xfer)(chp, xfer); 1551 } 1552 } 1553 1554 static void 1555 __wdcerror(chp, msg) 1556 struct channel_softc *chp; 1557 char *msg; 1558 { 1559 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1560 1561 if (xfer == NULL) 1562 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1563 msg); 1564 else 1565 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1566 chp->channel, xfer->drive, msg); 1567 } 1568 1569 /* 1570 * the bit bucket 1571 */ 1572 void 1573 wdcbit_bucket(chp, size) 1574 struct channel_softc *chp; 1575 int size; 1576 { 1577 1578 for (; size >= 2; size -= 2) 1579 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1580 if (size) 1581 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1582 } 1583 1584 int 1585 wdc_addref(chp) 1586 struct channel_softc *chp; 1587 { 1588 struct wdc_softc *wdc = chp->wdc; 1589 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1590 int s, error = 0; 1591 1592 s = splbio(); 1593 if (adapt->adapt_refcnt++ == 0 && 1594 adapt->adapt_enable != NULL) { 1595 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1596 if (error) 1597 adapt->adapt_refcnt--; 1598 } 1599 splx(s); 1600 return (error); 1601 } 1602 1603 void 1604 wdc_delref(chp) 1605 struct channel_softc *chp; 1606 { 1607 struct wdc_softc *wdc = chp->wdc; 1608 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1609 int s; 1610 1611 s = splbio(); 1612 if (adapt->adapt_refcnt-- == 1 && 1613 adapt->adapt_enable != NULL) 1614 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1615 splx(s); 1616 } 1617 1618 void 1619 wdc_print_modes(struct channel_softc *chp) 1620 { 1621 int drive; 1622 struct ata_drive_datas *drvp; 1623 1624 for (drive = 0; drive < 2; drive++) { 1625 drvp = &chp->ch_drive[drive]; 1626 if ((drvp->drive_flags & DRIVE) == 0) 1627 continue; 1628 printf("%s(%s:%d:%d): using PIO mode %d", 1629 drvp->drv_softc->dv_xname, 1630 chp->wdc->sc_dev.dv_xname, 1631 chp->channel, drive, drvp->PIO_mode); 1632 if (drvp->drive_flags & DRIVE_DMA) 1633 printf(", DMA mode %d", drvp->DMA_mode); 1634 if (drvp->drive_flags & DRIVE_UDMA) { 1635 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1636 if (drvp->UDMA_mode == 2) 1637 printf(" (Ultra/33)"); 1638 else if (drvp->UDMA_mode == 4) 1639 printf(" (Ultra/66)"); 1640 else if (drvp->UDMA_mode == 5) 1641 printf(" (Ultra/100)"); 1642 } 1643 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1644 printf(" (using DMA data transfers)"); 1645 printf("\n"); 1646 } 1647 } 1648
Indexes created Mon Sep 22 21:09:42 GMT 2025