wdc.c revision 1.108
1 /* $NetBSD: wdc.c,v 1.108 2002/01/13 17:24:28 christos Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.108 2002/01/13 17:24:28 christos Exp $"); 76 77 #ifndef WDCDEBUG 78 #define WDCDEBUG 79 #endif /* WDCDEBUG */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/conf.h> 85 #include <sys/buf.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/pool.h> 89 #include <sys/syslog.h> 90 #include <sys/proc.h> 91 92 #include <machine/intr.h> 93 #include <machine/bus.h> 94 95 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 96 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 97 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 98 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 99 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 100 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 101 102 #include <dev/ata/atavar.h> 103 #include <dev/ata/wdvar.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #define WDCDELAY 100 /* 100 microseconds */ 112 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 113 #if 0 114 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 115 #define WDCNDELAY_DEBUG 50 116 #endif 117 118 struct pool wdc_xfer_pool; 119 120 #if NWD > 0 121 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 122 #else 123 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 124 const struct ata_bustype wdc_ata_bustype = { 125 SCSIPI_BUSTYPE_ATA, 126 NULL, 127 NULL, 128 NULL, 129 NULL, 130 NULL, 131 NULL, 132 NULL 133 }; 134 #endif 135 136 static void __wdcerror __P((struct channel_softc*, char *)); 137 static int __wdcwait_reset __P((struct channel_softc *, int)); 138 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 139 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 140 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 141 int wdprint __P((void *, const char *)); 142 143 #define DEBUG_INTR 0x01 144 #define DEBUG_XFERS 0x02 145 #define DEBUG_STATUS 0x04 146 #define DEBUG_FUNCS 0x08 147 #define DEBUG_PROBE 0x10 148 #define DEBUG_DETACH 0x20 149 #define DEBUG_DELAY 0x40 150 #ifdef WDCDEBUG 151 int wdcdebug_mask = 0; 152 int wdc_nxfer = 0; 153 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 154 #else 155 #define WDCDEBUG_PRINT(args, level) 156 #endif 157 158 int 159 wdprint(aux, pnp) 160 void *aux; 161 const char *pnp; 162 { 163 struct ata_device *adev = aux; 164 if (pnp) 165 printf("wd at %s", pnp); 166 printf(" channel %d drive %d", adev->adev_channel, 167 adev->adev_drv_data->drive); 168 return (UNCONF); 169 } 170 171 /* Test to see controller with at last one attached drive is there. 172 * Returns a bit for each possible drive found (0x01 for drive 0, 173 * 0x02 for drive 1). 174 * Logic: 175 * - If a status register is at 0xff, assume there is no drive here 176 * (ISA has pull-up resistors). Similarly if the status register has 177 * the value we last wrote to the bus (for IDE interfaces without pullups). 178 * If no drive at all -> return. 179 * - reset the controller, wait for it to complete (may take up to 31s !). 180 * If timeout -> return. 181 * - test ATA/ATAPI signatures. If at last one drive found -> return. 182 * - try an ATA command on the master. 183 */ 184 185 int 186 wdcprobe(chp) 187 struct channel_softc *chp; 188 { 189 u_int8_t st0, st1, sc, sn, cl, ch; 190 u_int8_t ret_value = 0x03; 191 u_int8_t drive; 192 int found; 193 194 /* 195 * Sanity check to see if the wdc channel responds at all. 196 */ 197 198 if (chp->wdc == NULL || 199 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 200 201 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 202 chp->wdc->select(chp,0); 203 204 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 205 WDSD_IBM); 206 delay(10); 207 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 208 209 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 210 chp->wdc->select(chp,1); 211 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM | 0x10); 214 delay(10); 215 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 216 217 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 218 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 219 chp->channel, st0, st1), DEBUG_PROBE); 220 221 if (st0 == 0xff || st0 == WDSD_IBM) 222 ret_value &= ~0x01; 223 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 224 ret_value &= ~0x02; 225 if (ret_value == 0) 226 return 0; 227 } 228 229 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 230 chp->wdc->select(chp,0); 231 /* assert SRST, wait for reset to complete */ 232 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 233 WDSD_IBM); 234 delay(10); 235 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 236 WDCTL_RST | WDCTL_IDS); 237 DELAY(1000); 238 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 239 WDCTL_IDS); 240 delay(1000); 241 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 242 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 243 delay(10); 244 245 ret_value = __wdcwait_reset(chp, ret_value); 246 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 248 ret_value), DEBUG_PROBE); 249 250 /* if reset failed, there's nothing here */ 251 if (ret_value == 0) 252 return 0; 253 254 /* 255 * Test presence of drives. First test register signatures looking for 256 * ATAPI devices. If it's not an ATAPI and reset said there may be 257 * something here assume it's ATA or OLD. Ghost will be killed later in 258 * attach routine. 259 */ 260 found = 0; 261 for (drive = 0; drive < 2; drive++) { 262 if ((ret_value & (0x01 << drive)) == 0) 263 continue; 264 if (1 < ++found && chp->wdc != NULL && 265 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 266 /* 267 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 268 * is set. 269 * 270 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 271 * doesn't seem to implement drive select command. In 272 * this case, you can't eliminate ghost drive properly. 273 */ 274 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 275 chp->wdc->sc_dev.dv_xname, 276 chp->channel, drive), DEBUG_PROBE); 277 break; 278 } 279 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 280 chp->wdc->select(chp,drive); 281 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 282 WDSD_IBM | (drive << 4)); 283 delay(10); 284 /* Save registers contents */ 285 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 286 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 287 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 288 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 289 290 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 291 "cl=0x%x ch=0x%x\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 294 /* 295 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 296 * we get wrong values here, so ignore it. 297 */ 298 if (cl == 0x14 && ch == 0xeb) { 299 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 300 } else { 301 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 302 if (chp->wdc == NULL || 303 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 304 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 305 } 306 } 307 return (ret_value); 308 } 309 310 void 311 wdcattach(chp) 312 struct channel_softc *chp; 313 { 314 int channel_flags, ctrl_flags, i, error; 315 struct ataparams params; 316 static int inited = 0; 317 318 callout_init(&chp->ch_callout); 319 320 if ((error = wdc_addref(chp)) != 0) { 321 printf("%s: unable to enable controller\n", 322 chp->wdc->sc_dev.dv_xname); 323 return; 324 } 325 326 if (wdcprobe(chp) == 0) 327 /* If no drives, abort attach here. */ 328 goto out; 329 330 /* initialise global data */ 331 if (inited == 0) { 332 /* Initialize the wdc_xfer pool. */ 333 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 334 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 335 inited++; 336 } 337 TAILQ_INIT(&chp->ch_queue->sc_xfer); 338 339 for (i = 0; i < 2; i++) { 340 chp->ch_drive[i].chnl_softc = chp; 341 chp->ch_drive[i].drive = i; 342 /* 343 * Init error counter so that an error withing the first xfers 344 * will trigger a downgrade 345 */ 346 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 347 348 /* If controller can't do 16bit flag the drives as 32bit */ 349 if ((chp->wdc->cap & 350 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 351 WDC_CAPABILITY_DATA32) 352 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 353 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 354 continue; 355 356 /* 357 * Wait a bit, some devices are weird just after a reset. 358 * Then issue a IDENTIFY command, to try to detect slave ghost 359 */ 360 delay(100); 361 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 362 if (error != CMD_OK) { 363 delay(1000000); 364 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 365 ¶ms); 366 } 367 if (error == CMD_OK) { 368 /* If IDENTIFY succeded, this is not an OLD ctrl */ 369 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 370 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 371 } else { 372 chp->ch_drive[i].drive_flags &= 373 ~(DRIVE_ATA | DRIVE_ATAPI); 374 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 375 chp->wdc->sc_dev.dv_xname, 376 chp->channel, i, error), DEBUG_PROBE); 377 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 378 continue; 379 /* 380 * Pre-ATA drive ? 381 * Test registers writability (Error register not 382 * writable, but cyllo is), then try an ATA command. 383 */ 384 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 385 chp->wdc->select(chp,i); 386 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 387 WDSD_IBM | (i << 4)); 388 delay(10); 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_error, 0x58); 391 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 392 wd_cyl_lo, 0xa5); 393 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 394 wd_error == 0x58) || 395 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 396 wd_cyl_lo) != 0xa5) { 397 WDCDEBUG_PRINT(("%s:%d:%d: register " 398 "writability failed\n", 399 chp->wdc->sc_dev.dv_xname, 400 chp->channel, i), DEBUG_PROBE); 401 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 402 } 403 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 404 chp->wdc->select(chp,i); 405 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 406 WDSD_IBM | (i << 4)); 407 delay(100); 408 if (wait_for_ready(chp, 10000) != 0) { 409 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 410 chp->wdc->sc_dev.dv_xname, 411 chp->channel, i), DEBUG_PROBE); 412 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 413 continue; 414 } 415 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 416 wd_command, WDCC_RECAL); 417 if (wait_for_ready(chp, 10000) != 0) { 418 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 419 chp->wdc->sc_dev.dv_xname, 420 chp->channel, i), DEBUG_PROBE); 421 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 422 } 423 } 424 } 425 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 426 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 427 428 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 429 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 430 DEBUG_PROBE); 431 432 /* If no drives, abort here */ 433 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 434 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 435 goto out; 436 437 /* 438 * Attach an ATAPI bus, if needed. 439 */ 440 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 441 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 442 #if NATAPIBUS > 0 443 wdc_atapibus_attach(chp); 444 #else 445 /* 446 * Fake the autoconfig "not configured" message 447 */ 448 printf("atapibus at %s channel %d not configured\n", 449 chp->wdc->sc_dev.dv_xname, chp->channel); 450 chp->atapibus = NULL; 451 #endif 452 } 453 454 for (i = 0; i < 2; i++) { 455 struct ata_device adev; 456 if ((chp->ch_drive[i].drive_flags & 457 (DRIVE_ATA | DRIVE_OLD)) == 0) { 458 continue; 459 } 460 memset(&adev, 0, sizeof(struct ata_device)); 461 adev.adev_bustype = &wdc_ata_bustype; 462 adev.adev_channel = chp->channel; 463 adev.adev_openings = 1; 464 adev.adev_drv_data = &chp->ch_drive[i]; 465 if (config_found(&chp->wdc->sc_dev, (void *)&adev, wdprint)) 466 wdc_probe_caps(&chp->ch_drive[i]); 467 } 468 469 /* 470 * reset drive_flags for unnatached devices, reset state for attached 471 * ones 472 */ 473 for (i = 0; i < 2; i++) { 474 if (chp->ch_drive[i].drv_softc == NULL) 475 chp->ch_drive[i].drive_flags = 0; 476 else 477 chp->ch_drive[i].state = 0; 478 } 479 480 /* 481 * Reset channel. The probe, with some combinations of ATA/ATAPI 482 * devices keep it in a mostly working, but strange state (with busy 483 * led on) 484 */ 485 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 486 delay(50); 487 wdcreset(chp, VERBOSE); 488 /* 489 * Read status registers to avoid spurious interrupts. 490 */ 491 for (i = 1; i >= 0; i--) { 492 if (chp->ch_drive[i].drive_flags & DRIVE) { 493 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 494 chp->wdc->select(chp,i); 495 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 496 wd_sdh, WDSD_IBM | (i << 4)); 497 if (wait_for_unbusy(chp, 10000) < 0) 498 printf("%s:%d:%d: device busy\n", 499 chp->wdc->sc_dev.dv_xname, 500 chp->channel, i); 501 } 502 } 503 } 504 505 out: 506 wdc_delref(chp); 507 } 508 509 /* 510 * Call activate routine of underlying devices. 511 */ 512 int 513 wdcactivate(self, act) 514 struct device *self; 515 enum devact act; 516 { 517 struct wdc_softc *wdc = (struct wdc_softc *)self; 518 struct channel_softc *chp; 519 struct device *sc = 0; 520 int s, i, j, error = 0; 521 522 s = splbio(); 523 switch (act) { 524 case DVACT_ACTIVATE: 525 error = EOPNOTSUPP; 526 break; 527 528 case DVACT_DEACTIVATE: 529 for (i = 0; i < wdc->nchannels; i++) { 530 chp = wdc->channels[i]; 531 532 /* 533 * We might call deactivate routine for 534 * the children of atapibus twice (once via 535 * atapibus, once directly), but since 536 * config_deactivate maintains DVF_ACTIVE flag, 537 * it's safe. 538 */ 539 sc = chp->atapibus; 540 if (sc != NULL) { 541 error = config_deactivate(sc); 542 if (error != 0) 543 goto out; 544 } 545 546 for (j = 0; j < 2; j++) { 547 sc = chp->ch_drive[j].drv_softc; 548 WDCDEBUG_PRINT(("wdcactivate: %s:" 549 " deactivating %s\n", wdc->sc_dev.dv_xname, 550 sc == NULL ? "nodrv" : sc->dv_xname), 551 DEBUG_DETACH); 552 if (sc != NULL) { 553 error = config_deactivate(sc); 554 if (error != 0) 555 goto out; 556 } 557 } 558 } 559 break; 560 } 561 562 out: 563 splx(s); 564 565 #ifdef WDCDEBUG 566 if (sc && error != 0) 567 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 568 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 569 #endif 570 return (error); 571 } 572 573 int 574 wdcdetach(self, flags) 575 struct device *self; 576 int flags; 577 { 578 struct wdc_softc *wdc = (struct wdc_softc *)self; 579 struct channel_softc *chp; 580 struct device *sc = 0; 581 int i, j, error = 0; 582 583 for (i = 0; i < wdc->nchannels; i++) { 584 chp = wdc->channels[i]; 585 586 /* 587 * Detach atapibus and its children. 588 */ 589 sc = chp->atapibus; 590 if (sc != NULL) { 591 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 592 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 593 error = config_detach(sc, flags); 594 if (error != 0) 595 goto out; 596 } 597 598 /* 599 * Detach our other children. 600 */ 601 for (j = 0; j < 2; j++) { 602 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 603 continue; 604 sc = chp->ch_drive[j].drv_softc; 605 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 606 wdc->sc_dev.dv_xname, 607 sc == NULL ? "nodrv" : sc->dv_xname), 608 DEBUG_DETACH); 609 if (sc != NULL) { 610 error = config_detach(sc, flags); 611 if (error != 0) 612 goto out; 613 } 614 } 615 616 wdc_kill_pending(chp); 617 } 618 619 out: 620 #ifdef WDCDEBUG 621 if (sc && error != 0) 622 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 623 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 624 #endif 625 return (error); 626 } 627 628 /* 629 * Start I/O on a controller, for the given channel. 630 * The first xfer may be not for our channel if the channel queues 631 * are shared. 632 */ 633 void 634 wdcstart(chp) 635 struct channel_softc *chp; 636 { 637 struct wdc_xfer *xfer; 638 639 #ifdef WDC_DIAGNOSTIC 640 int spl1, spl2; 641 642 spl1 = splbio(); 643 spl2 = splbio(); 644 if (spl2 != spl1) { 645 printf("wdcstart: not at splbio()\n"); 646 panic("wdcstart"); 647 } 648 splx(spl2); 649 splx(spl1); 650 #endif /* WDC_DIAGNOSTIC */ 651 652 /* is there a xfer ? */ 653 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 654 return; 655 656 /* adjust chp, in case we have a shared queue */ 657 chp = xfer->chp; 658 659 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 660 return; /* channel aleady active */ 661 } 662 #ifdef DIAGNOSTIC 663 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 664 panic("wdcstart: channel waiting for irq\n"); 665 #endif 666 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 667 if (!(*chp->wdc->claim_hw)(chp, 0)) 668 return; 669 670 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 671 chp->channel, xfer->drive), DEBUG_XFERS); 672 chp->ch_flags |= WDCF_ACTIVE; 673 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 674 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 675 chp->ch_drive[xfer->drive].state = 0; 676 } 677 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 678 KASSERT(xfer->c_flags & C_POLL); 679 xfer->c_start(chp, xfer); 680 } 681 682 /* restart an interrupted I/O */ 683 void 684 wdcrestart(v) 685 void *v; 686 { 687 struct channel_softc *chp = v; 688 int s; 689 690 s = splbio(); 691 wdcstart(chp); 692 splx(s); 693 } 694 695 696 /* 697 * Interrupt routine for the controller. Acknowledge the interrupt, check for 698 * errors on the current operation, mark it done if necessary, and start the 699 * next request. Also check for a partially done transfer, and continue with 700 * the next chunk if so. 701 */ 702 int 703 wdcintr(arg) 704 void *arg; 705 { 706 struct channel_softc *chp = arg; 707 struct wdc_xfer *xfer; 708 int ret; 709 710 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 711 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 712 DEBUG_INTR); 713 return (0); 714 } 715 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 716 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 717 return (0); 718 } 719 720 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 721 xfer = chp->ch_queue->sc_xfer.tqh_first; 722 if (chp->ch_flags & WDCF_DMA_WAIT) { 723 chp->wdc->dma_status = 724 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 725 xfer->drive, 0); 726 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 727 /* IRQ not for us, not detected by DMA engine */ 728 return 0; 729 } 730 chp->ch_flags &= ~WDCF_DMA_WAIT; 731 } 732 chp->ch_flags &= ~WDCF_IRQ_WAIT; 733 ret = xfer->c_intr(chp, xfer, 1); 734 if (ret == 0) /* irq was not for us, still waiting for irq */ 735 chp->ch_flags |= WDCF_IRQ_WAIT; 736 return (ret); 737 } 738 739 /* Put all disk in RESET state */ 740 void wdc_reset_channel(drvp) 741 struct ata_drive_datas *drvp; 742 { 743 struct channel_softc *chp = drvp->chnl_softc; 744 int drive; 745 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 746 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 747 DEBUG_FUNCS); 748 (void) wdcreset(chp, VERBOSE); 749 for (drive = 0; drive < 2; drive++) { 750 chp->ch_drive[drive].state = 0; 751 } 752 } 753 754 int 755 wdcreset(chp, verb) 756 struct channel_softc *chp; 757 int verb; 758 { 759 int drv_mask1, drv_mask2; 760 761 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 762 chp->wdc->select(chp,0); 763 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 764 WDSD_IBM); /* master */ 765 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 766 WDCTL_RST | WDCTL_IDS); 767 delay(1000); 768 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 769 WDCTL_IDS); 770 delay(1000); 771 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 772 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 773 WDCTL_4BIT); 774 775 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 776 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 777 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 778 if (verb && drv_mask2 != drv_mask1) { 779 printf("%s channel %d: reset failed for", 780 chp->wdc->sc_dev.dv_xname, chp->channel); 781 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 782 printf(" drive 0"); 783 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 784 printf(" drive 1"); 785 printf("\n"); 786 } 787 return (drv_mask1 != drv_mask2) ? 1 : 0; 788 } 789 790 static int 791 __wdcwait_reset(chp, drv_mask) 792 struct channel_softc *chp; 793 int drv_mask; 794 { 795 int timeout; 796 u_int8_t st0, st1; 797 #ifdef WDCDEBUG 798 u_int8_t sc0, sn0, cl0, ch0; 799 u_int8_t sc1, sn1, cl1, ch1; 800 #endif 801 /* wait for BSY to deassert */ 802 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 803 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 804 chp->wdc->select(chp,0); 805 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 806 WDSD_IBM); /* master */ 807 delay(10); 808 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 809 #ifdef WDCDEBUG 810 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 811 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 812 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 813 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 814 #endif 815 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 816 chp->wdc->select(chp,1); 817 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 818 WDSD_IBM | 0x10); /* slave */ 819 delay(10); 820 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 821 #ifdef WDCDEBUG 822 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 823 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 824 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 825 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 826 #endif 827 828 if ((drv_mask & 0x01) == 0) { 829 /* no master */ 830 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 831 /* No master, slave is ready, it's done */ 832 goto end; 833 } 834 } else if ((drv_mask & 0x02) == 0) { 835 /* no slave */ 836 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 837 /* No slave, master is ready, it's done */ 838 goto end; 839 } 840 } else { 841 /* Wait for both master and slave to be ready */ 842 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 843 goto end; 844 } 845 } 846 delay(WDCDELAY); 847 } 848 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 849 if (st0 & WDCS_BSY) 850 drv_mask &= ~0x01; 851 if (st1 & WDCS_BSY) 852 drv_mask &= ~0x02; 853 end: 854 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 855 "cl=0x%x ch=0x%x\n", 856 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 857 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 858 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 859 "cl=0x%x ch=0x%x\n", 860 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 861 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 862 863 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 864 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 865 st0, st1), DEBUG_PROBE); 866 867 return drv_mask; 868 } 869 870 /* 871 * Wait for a drive to be !BSY, and have mask in its status register. 872 * return -1 for a timeout after "timeout" ms. 873 */ 874 int 875 wdcwait(chp, mask, bits, timeout) 876 struct channel_softc *chp; 877 int mask, bits, timeout; 878 { 879 u_char status; 880 int time = 0; 881 #ifdef WDCNDELAY_DEBUG 882 extern int cold; 883 #endif 884 885 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 886 :"none", chp->channel), DEBUG_STATUS); 887 chp->ch_error = 0; 888 889 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 890 891 for (;;) { 892 chp->ch_status = status = 893 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 894 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 895 break; 896 if (++time > timeout) { 897 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 898 "status %x error %x (mask 0x%x bits 0x%x)\n", 899 time, status, 900 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 901 wd_error), mask, bits), 902 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 903 return -1; 904 } 905 delay(WDCDELAY); 906 } 907 #ifdef WDCDEBUG 908 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 909 printf("wdcwait: did busy-wait, time=%d\n", time); 910 #endif 911 if (status & WDCS_ERR) 912 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 913 wd_error); 914 #ifdef WDCNDELAY_DEBUG 915 /* After autoconfig, there should be no long delays. */ 916 if (!cold && time > WDCNDELAY_DEBUG) { 917 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 918 if (xfer == NULL) 919 printf("%s channel %d: warning: busy-wait took %dus\n", 920 chp->wdc->sc_dev.dv_xname, chp->channel, 921 WDCDELAY * time); 922 else 923 printf("%s:%d:%d: warning: busy-wait took %dus\n", 924 chp->wdc->sc_dev.dv_xname, chp->channel, 925 xfer->drive, 926 WDCDELAY * time); 927 } 928 #endif 929 return 0; 930 } 931 932 /* 933 * Busy-wait for DMA to complete 934 */ 935 int 936 wdc_dmawait(chp, xfer, timeout) 937 struct channel_softc *chp; 938 struct wdc_xfer *xfer; 939 int timeout; 940 { 941 int time; 942 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 943 chp->wdc->dma_status = 944 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 945 chp->channel, xfer->drive, 0); 946 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 947 return 0; 948 delay(WDCDELAY); 949 } 950 /* timeout, force a DMA halt */ 951 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 952 chp->channel, xfer->drive, 1); 953 return 1; 954 } 955 956 void 957 wdctimeout(arg) 958 void *arg; 959 { 960 struct channel_softc *chp = (struct channel_softc *)arg; 961 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 962 int s; 963 964 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 965 966 s = splbio(); 967 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 968 __wdcerror(chp, "lost interrupt"); 969 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 970 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 971 xfer->c_bcount, 972 xfer->c_skip); 973 if (chp->ch_flags & WDCF_DMA_WAIT) { 974 chp->wdc->dma_status = 975 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 976 chp->channel, xfer->drive, 1); 977 chp->ch_flags &= ~WDCF_DMA_WAIT; 978 } 979 /* 980 * Call the interrupt routine. If we just missed and interrupt, 981 * it will do what's needed. Else, it will take the needed 982 * action (reset the device). 983 * Before that we need to reinstall the timeout callback, 984 * in case it will miss another irq while in this transfer 985 * We arbitray chose it to be 1s 986 */ 987 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 988 xfer->c_flags |= C_TIMEOU; 989 chp->ch_flags &= ~WDCF_IRQ_WAIT; 990 xfer->c_intr(chp, xfer, 1); 991 } else 992 __wdcerror(chp, "missing untimeout"); 993 splx(s); 994 } 995 996 /* 997 * Probe drive's capabilites, for use by the controller later 998 * Assumes drvp points to an existing drive. 999 * XXX this should be a controller-indep function 1000 */ 1001 void 1002 wdc_probe_caps(drvp) 1003 struct ata_drive_datas *drvp; 1004 { 1005 struct ataparams params, params2; 1006 struct channel_softc *chp = drvp->chnl_softc; 1007 struct device *drv_dev = drvp->drv_softc; 1008 struct wdc_softc *wdc = chp->wdc; 1009 int i, printed; 1010 char *sep = ""; 1011 int cf_flags; 1012 1013 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 1014 /* IDENTIFY failed. Can't tell more about the device */ 1015 return; 1016 } 1017 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1018 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1019 /* 1020 * Controller claims 16 and 32 bit transfers. 1021 * Re-do an IDENTIFY with 32-bit transfers, 1022 * and compare results. 1023 */ 1024 drvp->drive_flags |= DRIVE_CAP32; 1025 ata_get_params(drvp, AT_POLL, ¶ms2); 1026 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1027 /* Not good. fall back to 16bits */ 1028 drvp->drive_flags &= ~DRIVE_CAP32; 1029 } else { 1030 printf("%s: 32-bit data port", drv_dev->dv_xname); 1031 } 1032 } 1033 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1034 if (params.atap_ata_major > 0x01 && 1035 params.atap_ata_major != 0xffff) { 1036 for (i = 14; i > 0; i--) { 1037 if (params.atap_ata_major & (1 << i)) { 1038 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1039 printf("%s: ", drv_dev->dv_xname); 1040 else 1041 printf(", "); 1042 printf("ATA version %d\n", i); 1043 drvp->ata_vers = i; 1044 break; 1045 } 1046 } 1047 } else 1048 #endif 1049 if (drvp->drive_flags & DRIVE_CAP32) 1050 printf("\n"); 1051 1052 /* An ATAPI device is at last PIO mode 3 */ 1053 if (drvp->drive_flags & DRIVE_ATAPI) 1054 drvp->PIO_mode = 3; 1055 1056 /* 1057 * It's not in the specs, but it seems that some drive 1058 * returns 0xffff in atap_extensions when this field is invalid 1059 */ 1060 if (params.atap_extensions != 0xffff && 1061 (params.atap_extensions & WDC_EXT_MODES)) { 1062 printed = 0; 1063 /* 1064 * XXX some drives report something wrong here (they claim to 1065 * support PIO mode 8 !). As mode is coded on 3 bits in 1066 * SET FEATURE, limit it to 7 (so limit i to 4). 1067 * If higther mode than 7 is found, abort. 1068 */ 1069 for (i = 7; i >= 0; i--) { 1070 if ((params.atap_piomode_supp & (1 << i)) == 0) 1071 continue; 1072 if (i > 4) 1073 return; 1074 /* 1075 * See if mode is accepted. 1076 * If the controller can't set its PIO mode, 1077 * assume the defaults are good, so don't try 1078 * to set it 1079 */ 1080 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1081 if (ata_set_mode(drvp, 0x08 | (i + 3), 1082 AT_POLL) != CMD_OK) 1083 continue; 1084 if (!printed) { 1085 printf("%s: drive supports PIO mode %d", 1086 drv_dev->dv_xname, i + 3); 1087 sep = ","; 1088 printed = 1; 1089 } 1090 /* 1091 * If controller's driver can't set its PIO mode, 1092 * get the highter one for the drive. 1093 */ 1094 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1095 wdc->PIO_cap >= i + 3) { 1096 drvp->PIO_mode = i + 3; 1097 drvp->PIO_cap = i + 3; 1098 break; 1099 } 1100 } 1101 if (!printed) { 1102 /* 1103 * We didn't find a valid PIO mode. 1104 * Assume the values returned for DMA are buggy too 1105 */ 1106 return; 1107 } 1108 drvp->drive_flags |= DRIVE_MODE; 1109 printed = 0; 1110 for (i = 7; i >= 0; i--) { 1111 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1112 continue; 1113 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1114 (wdc->cap & WDC_CAPABILITY_MODE)) 1115 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1116 != CMD_OK) 1117 continue; 1118 if (!printed) { 1119 printf("%s DMA mode %d", sep, i); 1120 sep = ","; 1121 printed = 1; 1122 } 1123 if (wdc->cap & WDC_CAPABILITY_DMA) { 1124 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1125 wdc->DMA_cap < i) 1126 continue; 1127 drvp->DMA_mode = i; 1128 drvp->DMA_cap = i; 1129 drvp->drive_flags |= DRIVE_DMA; 1130 } 1131 break; 1132 } 1133 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1134 printed = 0; 1135 for (i = 7; i >= 0; i--) { 1136 if ((params.atap_udmamode_supp & (1 << i)) 1137 == 0) 1138 continue; 1139 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1140 (wdc->cap & WDC_CAPABILITY_UDMA)) 1141 if (ata_set_mode(drvp, 0x40 | i, 1142 AT_POLL) != CMD_OK) 1143 continue; 1144 if (!printed) { 1145 printf("%s Ultra-DMA mode %d", sep, i); 1146 if (i == 2) 1147 printf(" (Ultra/33)"); 1148 else if (i == 4) 1149 printf(" (Ultra/66)"); 1150 else if (i == 5) 1151 printf(" (Ultra/100)"); 1152 sep = ","; 1153 printed = 1; 1154 } 1155 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1156 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1157 wdc->UDMA_cap < i) 1158 continue; 1159 drvp->UDMA_mode = i; 1160 drvp->UDMA_cap = i; 1161 drvp->drive_flags |= DRIVE_UDMA; 1162 } 1163 break; 1164 } 1165 } 1166 printf("\n"); 1167 } 1168 1169 /* Try to guess ATA version here, if it didn't get reported */ 1170 if (drvp->ata_vers == 0) { 1171 if (drvp->drive_flags & DRIVE_UDMA) 1172 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1173 else if (drvp->PIO_cap > 2) 1174 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1175 } 1176 cf_flags = drv_dev->dv_cfdata->cf_flags; 1177 if (cf_flags & ATA_CONFIG_PIO_SET) { 1178 drvp->PIO_mode = 1179 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1180 drvp->drive_flags |= DRIVE_MODE; 1181 } 1182 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1183 /* don't care about DMA modes */ 1184 return; 1185 } 1186 if (cf_flags & ATA_CONFIG_DMA_SET) { 1187 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1188 ATA_CONFIG_DMA_DISABLE) { 1189 drvp->drive_flags &= ~DRIVE_DMA; 1190 } else { 1191 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1192 ATA_CONFIG_DMA_OFF; 1193 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1194 } 1195 } 1196 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1197 /* don't care about UDMA modes */ 1198 return; 1199 } 1200 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1201 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1202 ATA_CONFIG_UDMA_DISABLE) { 1203 drvp->drive_flags &= ~DRIVE_UDMA; 1204 } else { 1205 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1206 ATA_CONFIG_UDMA_OFF; 1207 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1208 } 1209 } 1210 } 1211 1212 /* 1213 * downgrade the transfer mode of a drive after an error. return 1 if 1214 * downgrade was possible, 0 otherwise. 1215 */ 1216 int 1217 wdc_downgrade_mode(drvp) 1218 struct ata_drive_datas *drvp; 1219 { 1220 struct channel_softc *chp = drvp->chnl_softc; 1221 struct device *drv_dev = drvp->drv_softc; 1222 struct wdc_softc *wdc = chp->wdc; 1223 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1224 1225 /* if drive or controller don't know its mode, we can't do much */ 1226 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1227 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1228 return 0; 1229 /* current drive mode was set by a config flag, let it this way */ 1230 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1231 (cf_flags & ATA_CONFIG_DMA_SET) || 1232 (cf_flags & ATA_CONFIG_UDMA_SET)) 1233 return 0; 1234 1235 /* 1236 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1237 * Maybe we didn't properly notice the cable type 1238 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1239 * It helps in some cases. 1240 */ 1241 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1242 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1243 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1244 drv_dev->dv_xname, drvp->UDMA_mode); 1245 } 1246 1247 /* 1248 * If we were using ultra-DMA, don't downgrade to multiword DMA 1249 * if we noticed a CRC error. It has been noticed that CRC errors 1250 * in ultra-DMA lead to silent data corruption in multiword DMA. 1251 * Data corruption is less likely to occur in PIO mode. 1252 */ 1253 else if ((drvp->drive_flags & DRIVE_UDMA) && 1254 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1255 drvp->drive_flags &= ~DRIVE_UDMA; 1256 drvp->drive_flags |= DRIVE_DMA; 1257 drvp->DMA_mode = drvp->DMA_cap; 1258 printf("%s: transfer error, downgrading to DMA mode %d\n", 1259 drv_dev->dv_xname, drvp->DMA_mode); 1260 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1261 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1262 drvp->PIO_mode = drvp->PIO_cap; 1263 printf("%s: transfer error, downgrading to PIO mode %d\n", 1264 drv_dev->dv_xname, drvp->PIO_mode); 1265 } else /* already using PIO, can't downgrade */ 1266 return 0; 1267 1268 wdc->set_modes(chp); 1269 /* reset the channel, which will shedule all drives for setup */ 1270 wdc_reset_channel(drvp); 1271 return 1; 1272 } 1273 1274 int 1275 wdc_exec_command(drvp, wdc_c) 1276 struct ata_drive_datas *drvp; 1277 struct wdc_command *wdc_c; 1278 { 1279 struct channel_softc *chp = drvp->chnl_softc; 1280 struct wdc_xfer *xfer; 1281 int s, ret; 1282 1283 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1284 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1285 DEBUG_FUNCS); 1286 1287 /* set up an xfer and queue. Wait for completion */ 1288 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1289 WDC_NOSLEEP); 1290 if (xfer == NULL) { 1291 return WDC_TRY_AGAIN; 1292 } 1293 1294 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1295 wdc_c->flags |= AT_POLL; 1296 if (wdc_c->flags & AT_POLL) 1297 xfer->c_flags |= C_POLL; 1298 xfer->drive = drvp->drive; 1299 xfer->databuf = wdc_c->data; 1300 xfer->c_bcount = wdc_c->bcount; 1301 xfer->cmd = wdc_c; 1302 xfer->c_start = __wdccommand_start; 1303 xfer->c_intr = __wdccommand_intr; 1304 xfer->c_kill_xfer = __wdccommand_done; 1305 1306 s = splbio(); 1307 wdc_exec_xfer(chp, xfer); 1308 #ifdef DIAGNOSTIC 1309 if ((wdc_c->flags & AT_POLL) != 0 && 1310 (wdc_c->flags & AT_DONE) == 0) 1311 panic("wdc_exec_command: polled command not done\n"); 1312 #endif 1313 if (wdc_c->flags & AT_DONE) { 1314 ret = WDC_COMPLETE; 1315 } else { 1316 if (wdc_c->flags & AT_WAIT) { 1317 while ((wdc_c->flags & AT_DONE) == 0) { 1318 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1319 } 1320 ret = WDC_COMPLETE; 1321 } else { 1322 ret = WDC_QUEUED; 1323 } 1324 } 1325 splx(s); 1326 return ret; 1327 } 1328 1329 void 1330 __wdccommand_start(chp, xfer) 1331 struct channel_softc *chp; 1332 struct wdc_xfer *xfer; 1333 { 1334 int drive = xfer->drive; 1335 struct wdc_command *wdc_c = xfer->cmd; 1336 1337 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1338 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1339 DEBUG_FUNCS); 1340 1341 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1342 chp->wdc->select(chp,drive); 1343 1344 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1345 WDSD_IBM | (drive << 4)); 1346 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1347 wdc_c->timeout) != 0) { 1348 wdc_c->flags |= AT_TIMEOU; 1349 __wdccommand_done(chp, xfer); 1350 return; 1351 } 1352 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1353 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1354 if ((wdc_c->flags & AT_POLL) == 0) { 1355 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1356 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1357 wdctimeout, chp); 1358 return; 1359 } 1360 /* 1361 * Polled command. Wait for drive ready or drq. Done in intr(). 1362 * Wait for at last 400ns for status bit to be valid. 1363 */ 1364 delay(10); 1365 __wdccommand_intr(chp, xfer, 0); 1366 } 1367 1368 int 1369 __wdccommand_intr(chp, xfer, irq) 1370 struct channel_softc *chp; 1371 struct wdc_xfer *xfer; 1372 int irq; 1373 { 1374 struct wdc_command *wdc_c = xfer->cmd; 1375 int bcount = wdc_c->bcount; 1376 char *data = wdc_c->data; 1377 1378 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1379 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1380 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1381 (irq == 0) ? wdc_c->timeout : 0)) { 1382 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1383 return 0; /* IRQ was not for us */ 1384 wdc_c->flags |= AT_TIMEOU; 1385 __wdccommand_done(chp, xfer); 1386 return 1; 1387 } 1388 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1389 chp->wdc->irqack(chp); 1390 if (wdc_c->flags & AT_READ) { 1391 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1392 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1393 0, (u_int32_t*)data, bcount >> 2); 1394 data += bcount & 0xfffffffc; 1395 bcount = bcount & 0x03; 1396 } 1397 if (bcount > 0) 1398 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1399 wd_data, (u_int16_t *)data, bcount >> 1); 1400 } else if (wdc_c->flags & AT_WRITE) { 1401 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1402 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1403 0, (u_int32_t*)data, bcount >> 2); 1404 data += bcount & 0xfffffffc; 1405 bcount = bcount & 0x03; 1406 } 1407 if (bcount > 0) 1408 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1409 wd_data, (u_int16_t *)data, bcount >> 1); 1410 } 1411 __wdccommand_done(chp, xfer); 1412 return 1; 1413 } 1414 1415 void 1416 __wdccommand_done(chp, xfer) 1417 struct channel_softc *chp; 1418 struct wdc_xfer *xfer; 1419 { 1420 struct wdc_command *wdc_c = xfer->cmd; 1421 1422 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1423 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1424 1425 callout_stop(&chp->ch_callout); 1426 1427 if (chp->ch_status & WDCS_DWF) 1428 wdc_c->flags |= AT_DF; 1429 if (chp->ch_status & WDCS_ERR) { 1430 wdc_c->flags |= AT_ERROR; 1431 wdc_c->r_error = chp->ch_error; 1432 } 1433 wdc_c->flags |= AT_DONE; 1434 if ((wdc_c->flags & AT_READREG) != 0 && 1435 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1436 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1437 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1438 wd_sdh); 1439 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1440 wd_cyl_hi) << 8; 1441 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1442 wd_cyl_lo); 1443 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1444 wd_sector); 1445 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1446 wd_seccnt); 1447 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1448 wd_error); 1449 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1450 wd_precomp); 1451 } 1452 wdc_free_xfer(chp, xfer); 1453 if (wdc_c->flags & AT_WAIT) 1454 wakeup(wdc_c); 1455 else if (wdc_c->callback) 1456 wdc_c->callback(wdc_c->callback_arg); 1457 wdcstart(chp); 1458 return; 1459 } 1460 1461 /* 1462 * Send a command. The drive should be ready. 1463 * Assumes interrupts are blocked. 1464 */ 1465 void 1466 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1467 struct channel_softc *chp; 1468 u_int8_t drive; 1469 u_int8_t command; 1470 u_int16_t cylin; 1471 u_int8_t head, sector, count, precomp; 1472 { 1473 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1474 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1475 chp->channel, drive, command, cylin, head, sector, count, precomp), 1476 DEBUG_FUNCS); 1477 1478 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1479 chp->wdc->select(chp,drive); 1480 1481 /* Select drive, head, and addressing mode. */ 1482 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1483 WDSD_IBM | (drive << 4) | head); 1484 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1485 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1486 precomp); 1487 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1488 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1489 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1490 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1491 1492 /* Send command. */ 1493 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1494 return; 1495 } 1496 1497 /* 1498 * Send a 48-bit addressing command. The drive should be ready. 1499 * Assumes interrupts are blocked. 1500 */ 1501 void 1502 wdccommandext(chp, drive, command, blkno, count) 1503 struct channel_softc *chp; 1504 u_int8_t drive; 1505 u_int8_t command; 1506 u_int64_t blkno; 1507 u_int16_t count; 1508 { 1509 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1510 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1511 chp->channel, drive, command, (u_int32_t) blkno, count), 1512 DEBUG_FUNCS); 1513 1514 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1515 chp->wdc->select(chp,drive); 1516 1517 /* Select drive, head, and addressing mode. */ 1518 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1519 (drive << 4) | WDSD_LBA); 1520 1521 /* previous */ 1522 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1523 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1524 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1525 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1526 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1527 1528 /* current */ 1529 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1530 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1531 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1532 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1533 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1534 1535 /* Send command. */ 1536 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1537 return; 1538 } 1539 1540 /* 1541 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1542 * tested by the caller. 1543 */ 1544 void 1545 wdccommandshort(chp, drive, command) 1546 struct channel_softc *chp; 1547 int drive; 1548 int command; 1549 { 1550 1551 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1552 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1553 DEBUG_FUNCS); 1554 1555 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1556 chp->wdc->select(chp,drive); 1557 1558 /* Select drive. */ 1559 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1560 WDSD_IBM | (drive << 4)); 1561 1562 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1563 } 1564 1565 /* Add a command to the queue and start controller. Must be called at splbio */ 1566 1567 void 1568 wdc_exec_xfer(chp, xfer) 1569 struct channel_softc *chp; 1570 struct wdc_xfer *xfer; 1571 { 1572 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1573 chp->channel, xfer->drive), DEBUG_XFERS); 1574 1575 /* complete xfer setup */ 1576 xfer->chp = chp; 1577 1578 /* 1579 * If we are a polled command, and the list is not empty, 1580 * we are doing a dump. Drop the list to allow the polled command 1581 * to complete, we're going to reboot soon anyway. 1582 */ 1583 if ((xfer->c_flags & C_POLL) != 0 && 1584 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1585 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1586 } 1587 /* insert at the end of command list */ 1588 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1589 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1590 chp->ch_flags), DEBUG_XFERS); 1591 wdcstart(chp); 1592 } 1593 1594 struct wdc_xfer * 1595 wdc_get_xfer(flags) 1596 int flags; 1597 { 1598 struct wdc_xfer *xfer; 1599 int s; 1600 1601 s = splbio(); 1602 xfer = pool_get(&wdc_xfer_pool, 1603 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1604 splx(s); 1605 if (xfer != NULL) { 1606 memset(xfer, 0, sizeof(struct wdc_xfer)); 1607 } 1608 return xfer; 1609 } 1610 1611 void 1612 wdc_free_xfer(chp, xfer) 1613 struct channel_softc *chp; 1614 struct wdc_xfer *xfer; 1615 { 1616 struct wdc_softc *wdc = chp->wdc; 1617 int s; 1618 1619 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1620 (*wdc->free_hw)(chp); 1621 s = splbio(); 1622 chp->ch_flags &= ~WDCF_ACTIVE; 1623 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1624 pool_put(&wdc_xfer_pool, xfer); 1625 splx(s); 1626 } 1627 1628 /* 1629 * Kill off all pending xfers for a channel_softc. 1630 * 1631 * Must be called at splbio(). 1632 */ 1633 void 1634 wdc_kill_pending(chp) 1635 struct channel_softc *chp; 1636 { 1637 struct wdc_xfer *xfer; 1638 1639 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1640 chp = xfer->chp; 1641 (*xfer->c_kill_xfer)(chp, xfer); 1642 } 1643 } 1644 1645 static void 1646 __wdcerror(chp, msg) 1647 struct channel_softc *chp; 1648 char *msg; 1649 { 1650 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1651 1652 if (xfer == NULL) 1653 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1654 msg); 1655 else 1656 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1657 chp->channel, xfer->drive, msg); 1658 } 1659 1660 /* 1661 * the bit bucket 1662 */ 1663 void 1664 wdcbit_bucket(chp, size) 1665 struct channel_softc *chp; 1666 int size; 1667 { 1668 1669 for (; size >= 2; size -= 2) 1670 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1671 if (size) 1672 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1673 } 1674 1675 int 1676 wdc_addref(chp) 1677 struct channel_softc *chp; 1678 { 1679 struct wdc_softc *wdc = chp->wdc; 1680 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1681 int s, error = 0; 1682 1683 s = splbio(); 1684 if (adapt->adapt_refcnt++ == 0 && 1685 adapt->adapt_enable != NULL) { 1686 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1687 if (error) 1688 adapt->adapt_refcnt--; 1689 } 1690 splx(s); 1691 return (error); 1692 } 1693 1694 void 1695 wdc_delref(chp) 1696 struct channel_softc *chp; 1697 { 1698 struct wdc_softc *wdc = chp->wdc; 1699 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1700 int s; 1701 1702 s = splbio(); 1703 if (adapt->adapt_refcnt-- == 1 && 1704 adapt->adapt_enable != NULL) 1705 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1706 splx(s); 1707 } 1708 1709 void 1710 wdc_print_modes(struct channel_softc *chp) 1711 { 1712 int drive; 1713 struct ata_drive_datas *drvp; 1714 1715 for (drive = 0; drive < 2; drive++) { 1716 drvp = &chp->ch_drive[drive]; 1717 if ((drvp->drive_flags & DRIVE) == 0) 1718 continue; 1719 printf("%s(%s:%d:%d): using PIO mode %d", 1720 drvp->drv_softc->dv_xname, 1721 chp->wdc->sc_dev.dv_xname, 1722 chp->channel, drive, drvp->PIO_mode); 1723 if (drvp->drive_flags & DRIVE_DMA) 1724 printf(", DMA mode %d", drvp->DMA_mode); 1725 if (drvp->drive_flags & DRIVE_UDMA) { 1726 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1727 if (drvp->UDMA_mode == 2) 1728 printf(" (Ultra/33)"); 1729 else if (drvp->UDMA_mode == 4) 1730 printf(" (Ultra/66)"); 1731 else if (drvp->UDMA_mode == 5) 1732 printf(" (Ultra/100)"); 1733 } 1734 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1735 printf(" (using DMA data transfers)"); 1736 printf("\n"); 1737 } 1738 } 1739
Indexes created Wed Sep 24 05:09:52 GMT 2025