wdc.c revision 1.119
1 /* $NetBSD: wdc.c,v 1.119 2002/12/06 14:05:34 drochner Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.119 2002/12/06 14:05:34 drochner Exp $"); 76 77 #ifndef WDCDEBUG 78 #define WDCDEBUG 79 #endif /* WDCDEBUG */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/conf.h> 85 #include <sys/buf.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #include <sys/pool.h> 89 #include <sys/syslog.h> 90 #include <sys/proc.h> 91 92 #include <machine/intr.h> 93 #include <machine/bus.h> 94 95 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 96 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 97 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 98 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 99 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 100 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 101 102 #include <dev/ata/atavar.h> 103 #include <dev/ata/wdvar.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #define WDCDELAY 100 /* 100 microseconds */ 112 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 113 #if 0 114 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 115 #define WDCNDELAY_DEBUG 50 116 #endif 117 118 struct pool wdc_xfer_pool; 119 120 #if NWD > 0 121 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 122 #else 123 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 124 const struct ata_bustype wdc_ata_bustype = { 125 SCSIPI_BUSTYPE_ATA, 126 NULL, 127 NULL, 128 NULL, 129 NULL, 130 NULL, 131 NULL, 132 NULL 133 }; 134 #endif 135 136 static void __wdcerror __P((struct channel_softc*, char *)); 137 static int __wdcwait_reset __P((struct channel_softc *, int)); 138 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 139 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 140 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 141 int wdprint __P((void *, const char *)); 142 143 #define DEBUG_INTR 0x01 144 #define DEBUG_XFERS 0x02 145 #define DEBUG_STATUS 0x04 146 #define DEBUG_FUNCS 0x08 147 #define DEBUG_PROBE 0x10 148 #define DEBUG_DETACH 0x20 149 #define DEBUG_DELAY 0x40 150 #ifdef WDCDEBUG 151 int wdcdebug_mask = 0; 152 int wdc_nxfer = 0; 153 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 154 #else 155 #define WDCDEBUG_PRINT(args, level) 156 #endif 157 158 int 159 wdprint(aux, pnp) 160 void *aux; 161 const char *pnp; 162 { 163 struct ata_device *adev = aux; 164 if (pnp) 165 printf("wd at %s", pnp); 166 printf(" channel %d drive %d", adev->adev_channel, 167 adev->adev_drv_data->drive); 168 return (UNCONF); 169 } 170 171 /* Test to see controller with at last one attached drive is there. 172 * Returns a bit for each possible drive found (0x01 for drive 0, 173 * 0x02 for drive 1). 174 * Logic: 175 * - If a status register is at 0xff, assume there is no drive here 176 * (ISA has pull-up resistors). Similarly if the status register has 177 * the value we last wrote to the bus (for IDE interfaces without pullups). 178 * If no drive at all -> return. 179 * - reset the controller, wait for it to complete (may take up to 31s !). 180 * If timeout -> return. 181 * - test ATA/ATAPI signatures. If at last one drive found -> return. 182 * - try an ATA command on the master. 183 */ 184 185 int 186 wdcprobe(chp) 187 struct channel_softc *chp; 188 { 189 u_int8_t st0, st1, sc, sn, cl, ch; 190 u_int8_t ret_value = 0x03; 191 u_int8_t drive; 192 int found; 193 194 /* 195 * Sanity check to see if the wdc channel responds at all. 196 */ 197 198 if (chp->wdc == NULL || 199 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 200 201 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 202 chp->wdc->select(chp,0); 203 204 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 205 WDSD_IBM); 206 delay(10); 207 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 208 209 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 210 chp->wdc->select(chp,1); 211 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM | 0x10); 214 delay(10); 215 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 216 217 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 218 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 219 chp->channel, st0, st1), DEBUG_PROBE); 220 221 if (st0 == 0xff || st0 == WDSD_IBM) 222 ret_value &= ~0x01; 223 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 224 ret_value &= ~0x02; 225 if (ret_value == 0) 226 return 0; 227 } 228 229 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 230 chp->wdc->select(chp,0); 231 /* assert SRST, wait for reset to complete */ 232 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 233 WDSD_IBM); 234 delay(10); 235 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 236 WDCTL_RST | WDCTL_IDS); 237 DELAY(1000); 238 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 239 WDCTL_IDS); 240 delay(1000); 241 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 242 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 243 delay(10); 244 245 ret_value = __wdcwait_reset(chp, ret_value); 246 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 248 ret_value), DEBUG_PROBE); 249 250 /* if reset failed, there's nothing here */ 251 if (ret_value == 0) 252 return 0; 253 254 /* 255 * Test presence of drives. First test register signatures looking for 256 * ATAPI devices. If it's not an ATAPI and reset said there may be 257 * something here assume it's ATA or OLD. Ghost will be killed later in 258 * attach routine. 259 */ 260 found = 0; 261 for (drive = 0; drive < 2; drive++) { 262 if ((ret_value & (0x01 << drive)) == 0) 263 continue; 264 if (1 < ++found && chp->wdc != NULL && 265 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 266 /* 267 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 268 * is set. 269 * 270 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 271 * doesn't seem to implement drive select command. In 272 * this case, you can't eliminate ghost drive properly. 273 */ 274 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 275 chp->wdc->sc_dev.dv_xname, 276 chp->channel, drive), DEBUG_PROBE); 277 break; 278 } 279 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 280 chp->wdc->select(chp,drive); 281 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 282 WDSD_IBM | (drive << 4)); 283 delay(10); 284 /* Save registers contents */ 285 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 286 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 287 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 288 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 289 290 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 291 "cl=0x%x ch=0x%x\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 294 /* 295 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 296 * we get wrong values here, so ignore it. 297 */ 298 if (cl == 0x14 && ch == 0xeb) { 299 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 300 } else { 301 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 302 if (chp->wdc == NULL || 303 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 304 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 305 } 306 } 307 return (ret_value); 308 } 309 310 void 311 wdcattach(chp) 312 struct channel_softc *chp; 313 { 314 int channel_flags, ctrl_flags, i, error; 315 struct ataparams params; 316 static int inited = 0; 317 318 callout_init(&chp->ch_callout); 319 320 if ((error = wdc_addref(chp)) != 0) { 321 printf("%s: unable to enable controller\n", 322 chp->wdc->sc_dev.dv_xname); 323 return; 324 } 325 326 if (wdcprobe(chp) == 0) 327 /* If no drives, abort attach here. */ 328 goto out; 329 330 /* initialise global data */ 331 if (inited == 0) { 332 /* Initialize the wdc_xfer pool. */ 333 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 334 0, 0, "wdcspl", NULL); 335 inited++; 336 } 337 TAILQ_INIT(&chp->ch_queue->sc_xfer); 338 339 for (i = 0; i < 2; i++) { 340 chp->ch_drive[i].chnl_softc = chp; 341 chp->ch_drive[i].drive = i; 342 /* 343 * Init error counter so that an error withing the first xfers 344 * will trigger a downgrade 345 */ 346 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 347 348 /* If controller can't do 16bit flag the drives as 32bit */ 349 if ((chp->wdc->cap & 350 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 351 WDC_CAPABILITY_DATA32) 352 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 353 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 354 continue; 355 356 /* 357 * Wait a bit, some devices are weird just after a reset. 358 * Then issue a IDENTIFY command, to try to detect slave ghost 359 */ 360 delay(5000); 361 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 362 if (error != CMD_OK) { 363 delay(1000000); 364 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 365 ¶ms); 366 } 367 if (error == CMD_OK) { 368 /* If IDENTIFY succeded, this is not an OLD ctrl */ 369 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 370 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 371 } else { 372 chp->ch_drive[i].drive_flags &= 373 ~(DRIVE_ATA | DRIVE_ATAPI); 374 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 375 chp->wdc->sc_dev.dv_xname, 376 chp->channel, i, error), DEBUG_PROBE); 377 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 378 continue; 379 /* 380 * Pre-ATA drive ? 381 * Test registers writability (Error register not 382 * writable, but cyllo is), then try an ATA command. 383 */ 384 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 385 chp->wdc->select(chp,i); 386 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 387 WDSD_IBM | (i << 4)); 388 delay(10); 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_error, 0x58); 391 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 392 wd_cyl_lo, 0xa5); 393 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 394 wd_error == 0x58) || 395 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 396 wd_cyl_lo) != 0xa5) { 397 WDCDEBUG_PRINT(("%s:%d:%d: register " 398 "writability failed\n", 399 chp->wdc->sc_dev.dv_xname, 400 chp->channel, i), DEBUG_PROBE); 401 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 402 } 403 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 404 chp->wdc->select(chp,i); 405 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 406 WDSD_IBM | (i << 4)); 407 delay(100); 408 if (wait_for_ready(chp, 10000) != 0) { 409 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 410 chp->wdc->sc_dev.dv_xname, 411 chp->channel, i), DEBUG_PROBE); 412 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 413 continue; 414 } 415 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 416 wd_command, WDCC_RECAL); 417 if (wait_for_ready(chp, 10000) != 0) { 418 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 419 chp->wdc->sc_dev.dv_xname, 420 chp->channel, i), DEBUG_PROBE); 421 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 422 } 423 } 424 } 425 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 426 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 427 428 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 429 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 430 DEBUG_PROBE); 431 432 /* If no drives, abort here */ 433 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 434 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 435 goto out; 436 437 /* 438 * Attach an ATAPI bus, if needed. 439 */ 440 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 441 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 442 #if NATAPIBUS > 0 443 wdc_atapibus_attach(chp); 444 #else 445 /* 446 * Fake the autoconfig "not configured" message 447 */ 448 printf("atapibus at %s channel %d not configured\n", 449 chp->wdc->sc_dev.dv_xname, chp->channel); 450 chp->atapibus = NULL; 451 #endif 452 } 453 454 for (i = 0; i < 2; i++) { 455 struct ata_device adev; 456 if ((chp->ch_drive[i].drive_flags & 457 (DRIVE_ATA | DRIVE_OLD)) == 0) { 458 continue; 459 } 460 memset(&adev, 0, sizeof(struct ata_device)); 461 adev.adev_bustype = &wdc_ata_bustype; 462 adev.adev_channel = chp->channel; 463 adev.adev_openings = 1; 464 adev.adev_drv_data = &chp->ch_drive[i]; 465 if (config_found(&chp->wdc->sc_dev, (void *)&adev, wdprint)) 466 wdc_probe_caps(&chp->ch_drive[i]); 467 } 468 469 /* 470 * reset drive_flags for unnatached devices, reset state for attached 471 * ones 472 */ 473 for (i = 0; i < 2; i++) { 474 if (chp->ch_drive[i].drv_softc == NULL) 475 chp->ch_drive[i].drive_flags = 0; 476 else 477 chp->ch_drive[i].state = 0; 478 } 479 480 /* 481 * Reset channel. The probe, with some combinations of ATA/ATAPI 482 * devices keep it in a mostly working, but strange state (with busy 483 * led on) 484 */ 485 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 486 delay(50); 487 wdcreset(chp, VERBOSE); 488 /* 489 * Read status registers to avoid spurious interrupts. 490 */ 491 for (i = 1; i >= 0; i--) { 492 if (chp->ch_drive[i].drive_flags & DRIVE) { 493 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 494 chp->wdc->select(chp,i); 495 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 496 wd_sdh, WDSD_IBM | (i << 4)); 497 if (wait_for_unbusy(chp, 10000) < 0) 498 printf("%s:%d:%d: device busy\n", 499 chp->wdc->sc_dev.dv_xname, 500 chp->channel, i); 501 } 502 } 503 } 504 505 out: 506 wdc_delref(chp); 507 } 508 509 /* 510 * Call activate routine of underlying devices. 511 */ 512 int 513 wdcactivate(self, act) 514 struct device *self; 515 enum devact act; 516 { 517 struct wdc_softc *wdc = (struct wdc_softc *)self; 518 struct channel_softc *chp; 519 struct device *sc = 0; 520 int s, i, j, error = 0; 521 522 s = splbio(); 523 switch (act) { 524 case DVACT_ACTIVATE: 525 error = EOPNOTSUPP; 526 break; 527 528 case DVACT_DEACTIVATE: 529 for (i = 0; i < wdc->nchannels; i++) { 530 chp = wdc->channels[i]; 531 532 /* 533 * We might call deactivate routine for 534 * the children of atapibus twice (once via 535 * atapibus, once directly), but since 536 * config_deactivate maintains DVF_ACTIVE flag, 537 * it's safe. 538 */ 539 sc = chp->atapibus; 540 if (sc != NULL) { 541 error = config_deactivate(sc); 542 if (error != 0) 543 goto out; 544 } 545 546 for (j = 0; j < 2; j++) { 547 sc = chp->ch_drive[j].drv_softc; 548 WDCDEBUG_PRINT(("wdcactivate: %s:" 549 " deactivating %s\n", wdc->sc_dev.dv_xname, 550 sc == NULL ? "nodrv" : sc->dv_xname), 551 DEBUG_DETACH); 552 if (sc != NULL) { 553 error = config_deactivate(sc); 554 if (error != 0) 555 goto out; 556 } 557 } 558 } 559 break; 560 } 561 562 out: 563 splx(s); 564 565 #ifdef WDCDEBUG 566 if (sc && error != 0) 567 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 568 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 569 #endif 570 return (error); 571 } 572 573 int 574 wdcdetach(self, flags) 575 struct device *self; 576 int flags; 577 { 578 struct wdc_softc *wdc = (struct wdc_softc *)self; 579 struct channel_softc *chp; 580 struct device *sc = 0; 581 int i, j, error = 0; 582 583 for (i = 0; i < wdc->nchannels; i++) { 584 chp = wdc->channels[i]; 585 586 /* 587 * Detach atapibus and its children. 588 */ 589 sc = chp->atapibus; 590 if (sc != NULL) { 591 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 592 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 593 error = config_detach(sc, flags); 594 if (error != 0) 595 goto out; 596 } 597 598 /* 599 * Detach our other children. 600 */ 601 for (j = 0; j < 2; j++) { 602 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 603 continue; 604 sc = chp->ch_drive[j].drv_softc; 605 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 606 wdc->sc_dev.dv_xname, 607 sc == NULL ? "nodrv" : sc->dv_xname), 608 DEBUG_DETACH); 609 if (sc != NULL) { 610 error = config_detach(sc, flags); 611 if (error != 0) 612 goto out; 613 } 614 } 615 616 wdc_kill_pending(chp); 617 } 618 619 out: 620 #ifdef WDCDEBUG 621 if (sc && error != 0) 622 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 623 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 624 #endif 625 return (error); 626 } 627 628 /* 629 * Start I/O on a controller, for the given channel. 630 * The first xfer may be not for our channel if the channel queues 631 * are shared. 632 */ 633 void 634 wdcstart(chp) 635 struct channel_softc *chp; 636 { 637 struct wdc_xfer *xfer; 638 639 #ifdef WDC_DIAGNOSTIC 640 int spl1, spl2; 641 642 spl1 = splbio(); 643 spl2 = splbio(); 644 if (spl2 != spl1) { 645 printf("wdcstart: not at splbio()\n"); 646 panic("wdcstart"); 647 } 648 splx(spl2); 649 splx(spl1); 650 #endif /* WDC_DIAGNOSTIC */ 651 652 /* is there a xfer ? */ 653 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 654 return; 655 656 /* adjust chp, in case we have a shared queue */ 657 chp = xfer->chp; 658 659 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 660 return; /* channel aleady active */ 661 } 662 #ifdef DIAGNOSTIC 663 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 664 panic("wdcstart: channel waiting for irq"); 665 #endif 666 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 667 if (!(*chp->wdc->claim_hw)(chp, 0)) 668 return; 669 670 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 671 chp->channel, xfer->drive), DEBUG_XFERS); 672 chp->ch_flags |= WDCF_ACTIVE; 673 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 674 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 675 chp->ch_drive[xfer->drive].state = 0; 676 } 677 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 678 KASSERT(xfer->c_flags & C_POLL); 679 xfer->c_start(chp, xfer); 680 } 681 682 /* restart an interrupted I/O */ 683 void 684 wdcrestart(v) 685 void *v; 686 { 687 struct channel_softc *chp = v; 688 int s; 689 690 s = splbio(); 691 wdcstart(chp); 692 splx(s); 693 } 694 695 696 /* 697 * Interrupt routine for the controller. Acknowledge the interrupt, check for 698 * errors on the current operation, mark it done if necessary, and start the 699 * next request. Also check for a partially done transfer, and continue with 700 * the next chunk if so. 701 */ 702 int 703 wdcintr(arg) 704 void *arg; 705 { 706 struct channel_softc *chp = arg; 707 struct wdc_xfer *xfer; 708 int ret; 709 710 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 711 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 712 DEBUG_INTR); 713 return (0); 714 } 715 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 716 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 717 /* try to clear the pending interrupt anyway */ 718 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 719 return (0); 720 } 721 722 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 723 xfer = chp->ch_queue->sc_xfer.tqh_first; 724 if (chp->ch_flags & WDCF_DMA_WAIT) { 725 chp->wdc->dma_status = 726 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 727 xfer->drive, 0); 728 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 729 /* IRQ not for us, not detected by DMA engine */ 730 return 0; 731 } 732 chp->ch_flags &= ~WDCF_DMA_WAIT; 733 } 734 chp->ch_flags &= ~WDCF_IRQ_WAIT; 735 ret = xfer->c_intr(chp, xfer, 1); 736 if (ret == 0) /* irq was not for us, still waiting for irq */ 737 chp->ch_flags |= WDCF_IRQ_WAIT; 738 return (ret); 739 } 740 741 /* Put all disk in RESET state */ 742 void wdc_reset_channel(drvp) 743 struct ata_drive_datas *drvp; 744 { 745 struct channel_softc *chp = drvp->chnl_softc; 746 int drive; 747 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 748 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 749 DEBUG_FUNCS); 750 (void) wdcreset(chp, VERBOSE); 751 for (drive = 0; drive < 2; drive++) { 752 chp->ch_drive[drive].state = 0; 753 } 754 } 755 756 int 757 wdcreset(chp, verb) 758 struct channel_softc *chp; 759 int verb; 760 { 761 int drv_mask1, drv_mask2; 762 763 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 764 chp->wdc->select(chp,0); 765 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 766 WDSD_IBM); /* master */ 767 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 768 WDCTL_RST | WDCTL_IDS); 769 delay(1000); 770 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 771 WDCTL_IDS); 772 delay(1000); 773 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 774 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 775 WDCTL_4BIT); 776 777 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 778 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 779 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 780 if (verb && drv_mask2 != drv_mask1) { 781 printf("%s channel %d: reset failed for", 782 chp->wdc->sc_dev.dv_xname, chp->channel); 783 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 784 printf(" drive 0"); 785 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 786 printf(" drive 1"); 787 printf("\n"); 788 } 789 return (drv_mask1 != drv_mask2) ? 1 : 0; 790 } 791 792 static int 793 __wdcwait_reset(chp, drv_mask) 794 struct channel_softc *chp; 795 int drv_mask; 796 { 797 int timeout; 798 u_int8_t st0, st1; 799 #ifdef WDCDEBUG 800 u_int8_t sc0, sn0, cl0, ch0; 801 u_int8_t sc1, sn1, cl1, ch1; 802 #endif 803 /* wait for BSY to deassert */ 804 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 805 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 806 chp->wdc->select(chp,0); 807 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 808 WDSD_IBM); /* master */ 809 delay(10); 810 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 811 #ifdef WDCDEBUG 812 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 813 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 814 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 815 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 816 #endif 817 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 818 chp->wdc->select(chp,1); 819 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 820 WDSD_IBM | 0x10); /* slave */ 821 delay(10); 822 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 823 #ifdef WDCDEBUG 824 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 825 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 826 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 827 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 828 #endif 829 830 if ((drv_mask & 0x01) == 0) { 831 /* no master */ 832 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 833 /* No master, slave is ready, it's done */ 834 goto end; 835 } 836 } else if ((drv_mask & 0x02) == 0) { 837 /* no slave */ 838 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 839 /* No slave, master is ready, it's done */ 840 goto end; 841 } 842 } else { 843 /* Wait for both master and slave to be ready */ 844 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 845 goto end; 846 } 847 } 848 delay(WDCDELAY); 849 } 850 /* Reset timed out. Maybe it's because drv_mask was not right */ 851 if (st0 & WDCS_BSY) 852 drv_mask &= ~0x01; 853 if (st1 & WDCS_BSY) 854 drv_mask &= ~0x02; 855 end: 856 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 857 "cl=0x%x ch=0x%x\n", 858 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 859 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 860 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 861 "cl=0x%x ch=0x%x\n", 862 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 863 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 864 865 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 866 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 867 st0, st1), DEBUG_PROBE); 868 869 return drv_mask; 870 } 871 872 /* 873 * Wait for a drive to be !BSY, and have mask in its status register. 874 * return -1 for a timeout after "timeout" ms. 875 */ 876 int 877 wdcwait(chp, mask, bits, timeout) 878 struct channel_softc *chp; 879 int mask, bits, timeout; 880 { 881 u_char status; 882 int time = 0; 883 884 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 885 :"none", chp->channel), DEBUG_STATUS); 886 chp->ch_error = 0; 887 888 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 889 890 for (;;) { 891 chp->ch_status = status = 892 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 893 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 894 break; 895 if (++time > timeout) { 896 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 897 "status %x error %x (mask 0x%x bits 0x%x)\n", 898 time, status, 899 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 900 wd_error), mask, bits), 901 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 902 return -1; 903 } 904 delay(WDCDELAY); 905 } 906 #ifdef WDCDEBUG 907 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 908 printf("wdcwait: did busy-wait, time=%d\n", time); 909 #endif 910 if (status & WDCS_ERR) 911 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 912 wd_error); 913 #ifdef WDCNDELAY_DEBUG 914 /* After autoconfig, there should be no long delays. */ 915 if (!cold && time > WDCNDELAY_DEBUG) { 916 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 917 if (xfer == NULL) 918 printf("%s channel %d: warning: busy-wait took %dus\n", 919 chp->wdc->sc_dev.dv_xname, chp->channel, 920 WDCDELAY * time); 921 else 922 printf("%s:%d:%d: warning: busy-wait took %dus\n", 923 chp->wdc->sc_dev.dv_xname, chp->channel, 924 xfer->drive, 925 WDCDELAY * time); 926 } 927 #endif 928 return 0; 929 } 930 931 /* 932 * Busy-wait for DMA to complete 933 */ 934 int 935 wdc_dmawait(chp, xfer, timeout) 936 struct channel_softc *chp; 937 struct wdc_xfer *xfer; 938 int timeout; 939 { 940 int time; 941 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 942 chp->wdc->dma_status = 943 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 944 chp->channel, xfer->drive, 0); 945 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 946 return 0; 947 delay(WDCDELAY); 948 } 949 /* timeout, force a DMA halt */ 950 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 951 chp->channel, xfer->drive, 1); 952 return 1; 953 } 954 955 void 956 wdctimeout(arg) 957 void *arg; 958 { 959 struct channel_softc *chp = (struct channel_softc *)arg; 960 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 961 int s; 962 963 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 964 965 s = splbio(); 966 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 967 __wdcerror(chp, "lost interrupt"); 968 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 969 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 970 xfer->c_bcount, 971 xfer->c_skip); 972 if (chp->ch_flags & WDCF_DMA_WAIT) { 973 chp->wdc->dma_status = 974 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 975 chp->channel, xfer->drive, 1); 976 chp->ch_flags &= ~WDCF_DMA_WAIT; 977 } 978 /* 979 * Call the interrupt routine. If we just missed an interrupt, 980 * it will do what's needed. Else, it will take the needed 981 * action (reset the device). 982 * Before that we need to reinstall the timeout callback, 983 * in case it will miss another irq while in this transfer 984 * We arbitray chose it to be 1s 985 */ 986 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 987 xfer->c_flags |= C_TIMEOU; 988 chp->ch_flags &= ~WDCF_IRQ_WAIT; 989 xfer->c_intr(chp, xfer, 1); 990 } else 991 __wdcerror(chp, "missing untimeout"); 992 splx(s); 993 } 994 995 /* 996 * Probe drive's capabilites, for use by the controller later 997 * Assumes drvp points to an existing drive. 998 * XXX this should be a controller-indep function 999 */ 1000 void 1001 wdc_probe_caps(drvp) 1002 struct ata_drive_datas *drvp; 1003 { 1004 struct ataparams params, params2; 1005 struct channel_softc *chp = drvp->chnl_softc; 1006 struct device *drv_dev = drvp->drv_softc; 1007 struct wdc_softc *wdc = chp->wdc; 1008 int i, printed; 1009 char *sep = ""; 1010 int cf_flags; 1011 1012 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 1013 /* IDENTIFY failed. Can't tell more about the device */ 1014 return; 1015 } 1016 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1017 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1018 /* 1019 * Controller claims 16 and 32 bit transfers. 1020 * Re-do an IDENTIFY with 32-bit transfers, 1021 * and compare results. 1022 */ 1023 drvp->drive_flags |= DRIVE_CAP32; 1024 ata_get_params(drvp, AT_POLL, ¶ms2); 1025 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1026 /* Not good. fall back to 16bits */ 1027 drvp->drive_flags &= ~DRIVE_CAP32; 1028 } else { 1029 printf("%s: 32-bit data port", drv_dev->dv_xname); 1030 } 1031 } 1032 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1033 if (params.atap_ata_major > 0x01 && 1034 params.atap_ata_major != 0xffff) { 1035 for (i = 14; i > 0; i--) { 1036 if (params.atap_ata_major & (1 << i)) { 1037 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1038 printf("%s: ", drv_dev->dv_xname); 1039 else 1040 printf(", "); 1041 printf("ATA version %d\n", i); 1042 drvp->ata_vers = i; 1043 break; 1044 } 1045 } 1046 } else 1047 #endif 1048 if (drvp->drive_flags & DRIVE_CAP32) 1049 printf("\n"); 1050 1051 /* An ATAPI device is at last PIO mode 3 */ 1052 if (drvp->drive_flags & DRIVE_ATAPI) 1053 drvp->PIO_mode = 3; 1054 1055 /* 1056 * It's not in the specs, but it seems that some drive 1057 * returns 0xffff in atap_extensions when this field is invalid 1058 */ 1059 if (params.atap_extensions != 0xffff && 1060 (params.atap_extensions & WDC_EXT_MODES)) { 1061 printed = 0; 1062 /* 1063 * XXX some drives report something wrong here (they claim to 1064 * support PIO mode 8 !). As mode is coded on 3 bits in 1065 * SET FEATURE, limit it to 7 (so limit i to 4). 1066 * If higher mode than 7 is found, abort. 1067 */ 1068 for (i = 7; i >= 0; i--) { 1069 if ((params.atap_piomode_supp & (1 << i)) == 0) 1070 continue; 1071 if (i > 4) 1072 return; 1073 /* 1074 * See if mode is accepted. 1075 * If the controller can't set its PIO mode, 1076 * assume the defaults are good, so don't try 1077 * to set it 1078 */ 1079 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1080 if (ata_set_mode(drvp, 0x08 | (i + 3), 1081 AT_POLL) != CMD_OK) 1082 continue; 1083 if (!printed) { 1084 printf("%s: drive supports PIO mode %d", 1085 drv_dev->dv_xname, i + 3); 1086 sep = ","; 1087 printed = 1; 1088 } 1089 /* 1090 * If controller's driver can't set its PIO mode, 1091 * get the highter one for the drive. 1092 */ 1093 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1094 wdc->PIO_cap >= i + 3) { 1095 drvp->PIO_mode = i + 3; 1096 drvp->PIO_cap = i + 3; 1097 break; 1098 } 1099 } 1100 if (!printed) { 1101 /* 1102 * We didn't find a valid PIO mode. 1103 * Assume the values returned for DMA are buggy too 1104 */ 1105 return; 1106 } 1107 drvp->drive_flags |= DRIVE_MODE; 1108 printed = 0; 1109 for (i = 7; i >= 0; i--) { 1110 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1111 continue; 1112 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1113 (wdc->cap & WDC_CAPABILITY_MODE)) 1114 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1115 != CMD_OK) 1116 continue; 1117 if (!printed) { 1118 printf("%s DMA mode %d", sep, i); 1119 sep = ","; 1120 printed = 1; 1121 } 1122 if (wdc->cap & WDC_CAPABILITY_DMA) { 1123 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1124 wdc->DMA_cap < i) 1125 continue; 1126 drvp->DMA_mode = i; 1127 drvp->DMA_cap = i; 1128 drvp->drive_flags |= DRIVE_DMA; 1129 } 1130 break; 1131 } 1132 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1133 printed = 0; 1134 for (i = 7; i >= 0; i--) { 1135 if ((params.atap_udmamode_supp & (1 << i)) 1136 == 0) 1137 continue; 1138 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1139 (wdc->cap & WDC_CAPABILITY_UDMA)) 1140 if (ata_set_mode(drvp, 0x40 | i, 1141 AT_POLL) != CMD_OK) 1142 continue; 1143 if (!printed) { 1144 printf("%s Ultra-DMA mode %d", sep, i); 1145 if (i == 2) 1146 printf(" (Ultra/33)"); 1147 else if (i == 4) 1148 printf(" (Ultra/66)"); 1149 else if (i == 5) 1150 printf(" (Ultra/100)"); 1151 else if (i == 6) 1152 printf(" (Ultra/133)"); 1153 sep = ","; 1154 printed = 1; 1155 } 1156 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1157 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1158 wdc->UDMA_cap < i) 1159 continue; 1160 drvp->UDMA_mode = i; 1161 drvp->UDMA_cap = i; 1162 drvp->drive_flags |= DRIVE_UDMA; 1163 } 1164 break; 1165 } 1166 } 1167 printf("\n"); 1168 } 1169 1170 /* Try to guess ATA version here, if it didn't get reported */ 1171 if (drvp->ata_vers == 0) { 1172 if (drvp->drive_flags & DRIVE_UDMA) 1173 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1174 else if (drvp->PIO_cap > 2) 1175 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1176 } 1177 cf_flags = drv_dev->dv_cfdata->cf_flags; 1178 if (cf_flags & ATA_CONFIG_PIO_SET) { 1179 drvp->PIO_mode = 1180 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1181 drvp->drive_flags |= DRIVE_MODE; 1182 } 1183 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1184 /* don't care about DMA modes */ 1185 return; 1186 } 1187 if (cf_flags & ATA_CONFIG_DMA_SET) { 1188 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1189 ATA_CONFIG_DMA_DISABLE) { 1190 drvp->drive_flags &= ~DRIVE_DMA; 1191 } else { 1192 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1193 ATA_CONFIG_DMA_OFF; 1194 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1195 } 1196 } 1197 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1198 /* don't care about UDMA modes */ 1199 return; 1200 } 1201 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1202 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1203 ATA_CONFIG_UDMA_DISABLE) { 1204 drvp->drive_flags &= ~DRIVE_UDMA; 1205 } else { 1206 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1207 ATA_CONFIG_UDMA_OFF; 1208 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1209 } 1210 } 1211 } 1212 1213 /* 1214 * downgrade the transfer mode of a drive after an error. return 1 if 1215 * downgrade was possible, 0 otherwise. 1216 */ 1217 int 1218 wdc_downgrade_mode(drvp) 1219 struct ata_drive_datas *drvp; 1220 { 1221 struct channel_softc *chp = drvp->chnl_softc; 1222 struct device *drv_dev = drvp->drv_softc; 1223 struct wdc_softc *wdc = chp->wdc; 1224 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1225 1226 /* if drive or controller don't know its mode, we can't do much */ 1227 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1228 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1229 return 0; 1230 /* current drive mode was set by a config flag, let it this way */ 1231 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1232 (cf_flags & ATA_CONFIG_DMA_SET) || 1233 (cf_flags & ATA_CONFIG_UDMA_SET)) 1234 return 0; 1235 1236 /* 1237 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1238 * Maybe we didn't properly notice the cable type 1239 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1240 * It helps in some cases. 1241 */ 1242 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1243 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1244 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1245 drv_dev->dv_xname, drvp->UDMA_mode); 1246 } 1247 1248 /* 1249 * If we were using ultra-DMA, don't downgrade to multiword DMA 1250 * if we noticed a CRC error. It has been noticed that CRC errors 1251 * in ultra-DMA lead to silent data corruption in multiword DMA. 1252 * Data corruption is less likely to occur in PIO mode. 1253 */ 1254 else if ((drvp->drive_flags & DRIVE_UDMA) && 1255 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1256 drvp->drive_flags &= ~DRIVE_UDMA; 1257 drvp->drive_flags |= DRIVE_DMA; 1258 drvp->DMA_mode = drvp->DMA_cap; 1259 printf("%s: transfer error, downgrading to DMA mode %d\n", 1260 drv_dev->dv_xname, drvp->DMA_mode); 1261 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1262 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1263 drvp->PIO_mode = drvp->PIO_cap; 1264 printf("%s: transfer error, downgrading to PIO mode %d\n", 1265 drv_dev->dv_xname, drvp->PIO_mode); 1266 } else /* already using PIO, can't downgrade */ 1267 return 0; 1268 1269 wdc->set_modes(chp); 1270 /* reset the channel, which will shedule all drives for setup */ 1271 wdc_reset_channel(drvp); 1272 return 1; 1273 } 1274 1275 int 1276 wdc_exec_command(drvp, wdc_c) 1277 struct ata_drive_datas *drvp; 1278 struct wdc_command *wdc_c; 1279 { 1280 struct channel_softc *chp = drvp->chnl_softc; 1281 struct wdc_xfer *xfer; 1282 int s, ret; 1283 1284 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1285 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1286 DEBUG_FUNCS); 1287 1288 /* set up an xfer and queue. Wait for completion */ 1289 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1290 WDC_NOSLEEP); 1291 if (xfer == NULL) { 1292 return WDC_TRY_AGAIN; 1293 } 1294 1295 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1296 wdc_c->flags |= AT_POLL; 1297 if (wdc_c->flags & AT_POLL) 1298 xfer->c_flags |= C_POLL; 1299 xfer->drive = drvp->drive; 1300 xfer->databuf = wdc_c->data; 1301 xfer->c_bcount = wdc_c->bcount; 1302 xfer->cmd = wdc_c; 1303 xfer->c_start = __wdccommand_start; 1304 xfer->c_intr = __wdccommand_intr; 1305 xfer->c_kill_xfer = __wdccommand_done; 1306 1307 s = splbio(); 1308 wdc_exec_xfer(chp, xfer); 1309 #ifdef DIAGNOSTIC 1310 if ((wdc_c->flags & AT_POLL) != 0 && 1311 (wdc_c->flags & AT_DONE) == 0) 1312 panic("wdc_exec_command: polled command not done"); 1313 #endif 1314 if (wdc_c->flags & AT_DONE) { 1315 ret = WDC_COMPLETE; 1316 } else { 1317 if (wdc_c->flags & AT_WAIT) { 1318 while ((wdc_c->flags & AT_DONE) == 0) { 1319 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1320 } 1321 ret = WDC_COMPLETE; 1322 } else { 1323 ret = WDC_QUEUED; 1324 } 1325 } 1326 splx(s); 1327 return ret; 1328 } 1329 1330 void 1331 __wdccommand_start(chp, xfer) 1332 struct channel_softc *chp; 1333 struct wdc_xfer *xfer; 1334 { 1335 int drive = xfer->drive; 1336 struct wdc_command *wdc_c = xfer->cmd; 1337 1338 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1339 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1340 DEBUG_FUNCS); 1341 1342 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1343 chp->wdc->select(chp,drive); 1344 1345 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1346 WDSD_IBM | (drive << 4)); 1347 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1348 wdc_c->timeout) != 0) { 1349 wdc_c->flags |= AT_TIMEOU; 1350 __wdccommand_done(chp, xfer); 1351 return; 1352 } 1353 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1354 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1355 if ((wdc_c->flags & AT_POLL) == 0) { 1356 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1357 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1358 wdctimeout, chp); 1359 return; 1360 } 1361 /* 1362 * Polled command. Wait for drive ready or drq. Done in intr(). 1363 * Wait for at last 400ns for status bit to be valid. 1364 */ 1365 delay(10); 1366 __wdccommand_intr(chp, xfer, 0); 1367 } 1368 1369 int 1370 __wdccommand_intr(chp, xfer, irq) 1371 struct channel_softc *chp; 1372 struct wdc_xfer *xfer; 1373 int irq; 1374 { 1375 struct wdc_command *wdc_c = xfer->cmd; 1376 int bcount = wdc_c->bcount; 1377 char *data = wdc_c->data; 1378 1379 again: 1380 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1381 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1382 if ((wdc_c->flags & AT_XFDONE) != 0) { 1383 /* 1384 * We have completed a data xfer. The drive should now be 1385 * in its initial state 1386 */ 1387 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1388 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0) != 0) { 1389 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1390 return 0; /* IRQ was not for us */ 1391 wdc_c->flags |= AT_TIMEOU; 1392 __wdccommand_done(chp, xfer); 1393 return 1; 1394 } 1395 wdc_c->flags |= AT_DONE; 1396 __wdccommand_done(chp, xfer); 1397 return 1; 1398 } 1399 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1400 (irq == 0) ? wdc_c->timeout : 0)) { 1401 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1402 return 0; /* IRQ was not for us */ 1403 wdc_c->flags |= AT_TIMEOU; 1404 __wdccommand_done(chp, xfer); 1405 return 1; 1406 } 1407 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1408 chp->wdc->irqack(chp); 1409 if (wdc_c->flags & AT_READ) { 1410 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1411 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1412 0, (u_int32_t*)data, bcount >> 2); 1413 data += bcount & 0xfffffffc; 1414 bcount = bcount & 0x03; 1415 } 1416 if (bcount > 0) 1417 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1418 wd_data, (u_int16_t *)data, bcount >> 1); 1419 /* at this point the drive should be in its initial state */ 1420 wdc_c->flags |= AT_XFDONE; 1421 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1422 wdc_c->r_st_bmask, 100) != 0) 1423 wdc_c->flags |= AT_TIMEOU; 1424 } else if (wdc_c->flags & AT_WRITE) { 1425 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1426 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1427 0, (u_int32_t*)data, bcount >> 2); 1428 data += bcount & 0xfffffffc; 1429 bcount = bcount & 0x03; 1430 } 1431 if (bcount > 0) 1432 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1433 wd_data, (u_int16_t *)data, bcount >> 1); 1434 wdc_c->flags |= AT_XFDONE; 1435 if ((wdc_c->flags & AT_POLL) == 0) { 1436 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1437 callout_reset(&chp->ch_callout, 1438 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1439 return 1; 1440 } else { 1441 goto again; 1442 } 1443 } 1444 __wdccommand_done(chp, xfer); 1445 return 1; 1446 } 1447 1448 void 1449 __wdccommand_done(chp, xfer) 1450 struct channel_softc *chp; 1451 struct wdc_xfer *xfer; 1452 { 1453 struct wdc_command *wdc_c = xfer->cmd; 1454 1455 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1456 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1457 1458 callout_stop(&chp->ch_callout); 1459 1460 if (chp->ch_status & WDCS_DWF) 1461 wdc_c->flags |= AT_DF; 1462 if (chp->ch_status & WDCS_ERR) { 1463 wdc_c->flags |= AT_ERROR; 1464 wdc_c->r_error = chp->ch_error; 1465 } 1466 wdc_c->flags |= AT_DONE; 1467 if ((wdc_c->flags & AT_READREG) != 0 && 1468 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1469 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1470 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1471 wd_sdh); 1472 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1473 wd_cyl_hi) << 8; 1474 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1475 wd_cyl_lo); 1476 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1477 wd_sector); 1478 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1479 wd_seccnt); 1480 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1481 wd_error); 1482 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1483 wd_precomp); 1484 } 1485 wdc_free_xfer(chp, xfer); 1486 if (wdc_c->flags & AT_WAIT) 1487 wakeup(wdc_c); 1488 else if (wdc_c->callback) 1489 wdc_c->callback(wdc_c->callback_arg); 1490 wdcstart(chp); 1491 return; 1492 } 1493 1494 /* 1495 * Send a command. The drive should be ready. 1496 * Assumes interrupts are blocked. 1497 */ 1498 void 1499 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1500 struct channel_softc *chp; 1501 u_int8_t drive; 1502 u_int8_t command; 1503 u_int16_t cylin; 1504 u_int8_t head, sector, count, precomp; 1505 { 1506 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1507 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1508 chp->channel, drive, command, cylin, head, sector, count, precomp), 1509 DEBUG_FUNCS); 1510 1511 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1512 chp->wdc->select(chp,drive); 1513 1514 /* Select drive, head, and addressing mode. */ 1515 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1516 WDSD_IBM | (drive << 4) | head); 1517 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1518 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1519 precomp); 1520 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1521 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1522 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1523 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1524 1525 /* Send command. */ 1526 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1527 return; 1528 } 1529 1530 /* 1531 * Send a 48-bit addressing command. The drive should be ready. 1532 * Assumes interrupts are blocked. 1533 */ 1534 void 1535 wdccommandext(chp, drive, command, blkno, count) 1536 struct channel_softc *chp; 1537 u_int8_t drive; 1538 u_int8_t command; 1539 u_int64_t blkno; 1540 u_int16_t count; 1541 { 1542 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1543 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1544 chp->channel, drive, command, (u_int32_t) blkno, count), 1545 DEBUG_FUNCS); 1546 1547 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1548 chp->wdc->select(chp,drive); 1549 1550 /* Select drive, head, and addressing mode. */ 1551 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1552 (drive << 4) | WDSD_LBA); 1553 1554 /* previous */ 1555 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1556 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1557 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1558 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1559 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1560 1561 /* current */ 1562 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1563 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1564 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1565 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1566 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1567 1568 /* Send command. */ 1569 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1570 return; 1571 } 1572 1573 /* 1574 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1575 * tested by the caller. 1576 */ 1577 void 1578 wdccommandshort(chp, drive, command) 1579 struct channel_softc *chp; 1580 int drive; 1581 int command; 1582 { 1583 1584 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1585 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1586 DEBUG_FUNCS); 1587 1588 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1589 chp->wdc->select(chp,drive); 1590 1591 /* Select drive. */ 1592 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1593 WDSD_IBM | (drive << 4)); 1594 1595 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1596 } 1597 1598 /* Add a command to the queue and start controller. Must be called at splbio */ 1599 1600 void 1601 wdc_exec_xfer(chp, xfer) 1602 struct channel_softc *chp; 1603 struct wdc_xfer *xfer; 1604 { 1605 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1606 chp->channel, xfer->drive), DEBUG_XFERS); 1607 1608 /* complete xfer setup */ 1609 xfer->chp = chp; 1610 1611 /* 1612 * If we are a polled command, and the list is not empty, 1613 * we are doing a dump. Drop the list to allow the polled command 1614 * to complete, we're going to reboot soon anyway. 1615 */ 1616 if ((xfer->c_flags & C_POLL) != 0 && 1617 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1618 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1619 } 1620 /* insert at the end of command list */ 1621 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1622 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1623 chp->ch_flags), DEBUG_XFERS); 1624 wdcstart(chp); 1625 } 1626 1627 struct wdc_xfer * 1628 wdc_get_xfer(flags) 1629 int flags; 1630 { 1631 struct wdc_xfer *xfer; 1632 int s; 1633 1634 s = splbio(); 1635 xfer = pool_get(&wdc_xfer_pool, 1636 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1637 splx(s); 1638 if (xfer != NULL) { 1639 memset(xfer, 0, sizeof(struct wdc_xfer)); 1640 } 1641 return xfer; 1642 } 1643 1644 void 1645 wdc_free_xfer(chp, xfer) 1646 struct channel_softc *chp; 1647 struct wdc_xfer *xfer; 1648 { 1649 struct wdc_softc *wdc = chp->wdc; 1650 int s; 1651 1652 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1653 (*wdc->free_hw)(chp); 1654 s = splbio(); 1655 chp->ch_flags &= ~WDCF_ACTIVE; 1656 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1657 pool_put(&wdc_xfer_pool, xfer); 1658 splx(s); 1659 } 1660 1661 /* 1662 * Kill off all pending xfers for a channel_softc. 1663 * 1664 * Must be called at splbio(). 1665 */ 1666 void 1667 wdc_kill_pending(chp) 1668 struct channel_softc *chp; 1669 { 1670 struct wdc_xfer *xfer; 1671 1672 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1673 chp = xfer->chp; 1674 (*xfer->c_kill_xfer)(chp, xfer); 1675 } 1676 } 1677 1678 static void 1679 __wdcerror(chp, msg) 1680 struct channel_softc *chp; 1681 char *msg; 1682 { 1683 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1684 1685 if (xfer == NULL) 1686 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1687 msg); 1688 else 1689 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1690 chp->channel, xfer->drive, msg); 1691 } 1692 1693 /* 1694 * the bit bucket 1695 */ 1696 void 1697 wdcbit_bucket(chp, size) 1698 struct channel_softc *chp; 1699 int size; 1700 { 1701 1702 for (; size >= 2; size -= 2) 1703 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1704 if (size) 1705 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1706 } 1707 1708 int 1709 wdc_addref(chp) 1710 struct channel_softc *chp; 1711 { 1712 struct wdc_softc *wdc = chp->wdc; 1713 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1714 int s, error = 0; 1715 1716 s = splbio(); 1717 if (adapt->adapt_refcnt++ == 0 && 1718 adapt->adapt_enable != NULL) { 1719 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1720 if (error) 1721 adapt->adapt_refcnt--; 1722 } 1723 splx(s); 1724 return (error); 1725 } 1726 1727 void 1728 wdc_delref(chp) 1729 struct channel_softc *chp; 1730 { 1731 struct wdc_softc *wdc = chp->wdc; 1732 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1733 int s; 1734 1735 s = splbio(); 1736 if (adapt->adapt_refcnt-- == 1 && 1737 adapt->adapt_enable != NULL) 1738 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1739 splx(s); 1740 } 1741 1742 void 1743 wdc_print_modes(struct channel_softc *chp) 1744 { 1745 int drive; 1746 struct ata_drive_datas *drvp; 1747 1748 for (drive = 0; drive < 2; drive++) { 1749 drvp = &chp->ch_drive[drive]; 1750 if ((drvp->drive_flags & DRIVE) == 0) 1751 continue; 1752 printf("%s(%s:%d:%d): using PIO mode %d", 1753 drvp->drv_softc->dv_xname, 1754 chp->wdc->sc_dev.dv_xname, 1755 chp->channel, drive, drvp->PIO_mode); 1756 if (drvp->drive_flags & DRIVE_DMA) 1757 printf(", DMA mode %d", drvp->DMA_mode); 1758 if (drvp->drive_flags & DRIVE_UDMA) { 1759 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1760 if (drvp->UDMA_mode == 2) 1761 printf(" (Ultra/33)"); 1762 else if (drvp->UDMA_mode == 4) 1763 printf(" (Ultra/66)"); 1764 else if (drvp->UDMA_mode == 5) 1765 printf(" (Ultra/100)"); 1766 } 1767 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1768 printf(" (using DMA data transfers)"); 1769 printf("\n"); 1770 } 1771 } 1772
Indexes created Tue Sep 23 07:09:52 GMT 2025