wdc.c revision 1.122
1 /* $NetBSD: wdc.c,v 1.122 2003/01/27 18:21:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.122 2003/01/27 18:21:25 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/wdvar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 struct pool wdc_xfer_pool; 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL 136 }; 137 #endif 138 139 static void __wdcerror __P((struct channel_softc*, char *)); 140 static int __wdcwait_reset __P((struct channel_softc *, int)); 141 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 142 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 143 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 144 int wdprint __P((void *, const char *)); 145 146 #define DEBUG_INTR 0x01 147 #define DEBUG_XFERS 0x02 148 #define DEBUG_STATUS 0x04 149 #define DEBUG_FUNCS 0x08 150 #define DEBUG_PROBE 0x10 151 #define DEBUG_DETACH 0x20 152 #define DEBUG_DELAY 0x40 153 #ifdef WDCDEBUG 154 int wdcdebug_mask = 0; 155 int wdc_nxfer = 0; 156 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 157 #else 158 #define WDCDEBUG_PRINT(args, level) 159 #endif 160 161 int 162 wdprint(aux, pnp) 163 void *aux; 164 const char *pnp; 165 { 166 struct ata_device *adev = aux; 167 if (pnp) 168 aprint_normal("wd at %s", pnp); 169 aprint_normal(" channel %d drive %d", adev->adev_channel, 170 adev->adev_drv_data->drive); 171 return (UNCONF); 172 } 173 174 /* Test to see controller with at last one attached drive is there. 175 * Returns a bit for each possible drive found (0x01 for drive 0, 176 * 0x02 for drive 1). 177 * Logic: 178 * - If a status register is at 0xff, assume there is no drive here 179 * (ISA has pull-up resistors). Similarly if the status register has 180 * the value we last wrote to the bus (for IDE interfaces without pullups). 181 * If no drive at all -> return. 182 * - reset the controller, wait for it to complete (may take up to 31s !). 183 * If timeout -> return. 184 * - test ATA/ATAPI signatures. If at last one drive found -> return. 185 * - try an ATA command on the master. 186 */ 187 188 int 189 wdcprobe(chp) 190 struct channel_softc *chp; 191 { 192 u_int8_t st0, st1, sc, sn, cl, ch; 193 u_int8_t ret_value = 0x03; 194 u_int8_t drive; 195 int found; 196 197 /* 198 * Sanity check to see if the wdc channel responds at all. 199 */ 200 201 if (chp->wdc == NULL || 202 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 203 204 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 205 chp->wdc->select(chp,0); 206 207 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 208 WDSD_IBM); 209 delay(10); 210 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 211 212 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 213 chp->wdc->select(chp,1); 214 215 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 216 WDSD_IBM | 0x10); 217 delay(10); 218 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 219 220 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 221 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 222 chp->channel, st0, st1), DEBUG_PROBE); 223 224 if (st0 == 0xff || st0 == WDSD_IBM) 225 ret_value &= ~0x01; 226 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 227 ret_value &= ~0x02; 228 if (ret_value == 0) 229 return 0; 230 } 231 232 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 233 chp->wdc->select(chp,0); 234 /* assert SRST, wait for reset to complete */ 235 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 236 WDSD_IBM); 237 delay(10); 238 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 239 WDCTL_RST | WDCTL_IDS); 240 DELAY(1000); 241 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 242 WDCTL_IDS); 243 delay(1000); 244 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 245 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 246 delay(10); 247 248 ret_value = __wdcwait_reset(chp, ret_value); 249 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 251 ret_value), DEBUG_PROBE); 252 253 /* if reset failed, there's nothing here */ 254 if (ret_value == 0) 255 return 0; 256 257 /* 258 * Test presence of drives. First test register signatures looking for 259 * ATAPI devices. If it's not an ATAPI and reset said there may be 260 * something here assume it's ATA or OLD. Ghost will be killed later in 261 * attach routine. 262 */ 263 found = 0; 264 for (drive = 0; drive < 2; drive++) { 265 if ((ret_value & (0x01 << drive)) == 0) 266 continue; 267 if (1 < ++found && chp->wdc != NULL && 268 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 269 /* 270 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 271 * is set. 272 * 273 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 274 * doesn't seem to implement drive select command. In 275 * this case, you can't eliminate ghost drive properly. 276 */ 277 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 278 chp->wdc->sc_dev.dv_xname, 279 chp->channel, drive), DEBUG_PROBE); 280 break; 281 } 282 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 283 chp->wdc->select(chp,drive); 284 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 285 WDSD_IBM | (drive << 4)); 286 delay(10); 287 /* Save registers contents */ 288 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 289 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 290 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 291 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 292 293 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 294 "cl=0x%x ch=0x%x\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 297 /* 298 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 299 * we get wrong values here, so ignore it. 300 */ 301 if (cl == 0x14 && ch == 0xeb) { 302 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 303 } else { 304 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 305 if (chp->wdc == NULL || 306 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 307 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 308 } 309 } 310 return (ret_value); 311 } 312 313 void 314 wdcattach(chp) 315 struct channel_softc *chp; 316 { 317 int ctrl_flags, i, error; 318 struct ataparams params; 319 static int inited = 0; 320 321 callout_init(&chp->ch_callout); 322 323 if ((error = wdc_addref(chp)) != 0) { 324 printf("%s: unable to enable controller\n", 325 chp->wdc->sc_dev.dv_xname); 326 return; 327 } 328 329 if (wdcprobe(chp) == 0) 330 /* If no drives, abort attach here. */ 331 goto out; 332 333 /* initialise global data */ 334 if (inited == 0) { 335 /* Initialize the wdc_xfer pool. */ 336 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 337 0, 0, "wdcspl", NULL); 338 inited++; 339 } 340 TAILQ_INIT(&chp->ch_queue->sc_xfer); 341 342 for (i = 0; i < 2; i++) { 343 chp->ch_drive[i].chnl_softc = chp; 344 chp->ch_drive[i].drive = i; 345 /* 346 * Init error counter so that an error withing the first xfers 347 * will trigger a downgrade 348 */ 349 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 350 351 /* If controller can't do 16bit flag the drives as 32bit */ 352 if ((chp->wdc->cap & 353 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 354 WDC_CAPABILITY_DATA32) 355 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 356 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 357 continue; 358 359 /* 360 * Wait a bit, some devices are weird just after a reset. 361 * Then issue a IDENTIFY command, to try to detect slave ghost 362 */ 363 delay(5000); 364 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 365 if (error != CMD_OK) { 366 delay(1000000); 367 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 368 ¶ms); 369 } 370 if (error == CMD_OK) { 371 /* If IDENTIFY succeded, this is not an OLD ctrl */ 372 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 373 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 374 } else { 375 chp->ch_drive[i].drive_flags &= 376 ~(DRIVE_ATA | DRIVE_ATAPI); 377 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 378 chp->wdc->sc_dev.dv_xname, 379 chp->channel, i, error), DEBUG_PROBE); 380 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 381 continue; 382 /* 383 * Pre-ATA drive ? 384 * Test registers writability (Error register not 385 * writable, but cyllo is), then try an ATA command. 386 */ 387 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 388 chp->wdc->select(chp,i); 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 390 WDSD_IBM | (i << 4)); 391 delay(10); 392 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 393 wd_error, 0x58); 394 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 395 wd_cyl_lo, 0xa5); 396 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 397 wd_error == 0x58) || 398 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 399 wd_cyl_lo) != 0xa5) { 400 WDCDEBUG_PRINT(("%s:%d:%d: register " 401 "writability failed\n", 402 chp->wdc->sc_dev.dv_xname, 403 chp->channel, i), DEBUG_PROBE); 404 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 405 } 406 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 407 chp->wdc->select(chp,i); 408 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 409 WDSD_IBM | (i << 4)); 410 delay(100); 411 if (wait_for_ready(chp, 10000) != 0) { 412 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 413 chp->wdc->sc_dev.dv_xname, 414 chp->channel, i), DEBUG_PROBE); 415 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 416 continue; 417 } 418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 419 wd_command, WDCC_RECAL); 420 if (wait_for_ready(chp, 10000) != 0) { 421 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 422 chp->wdc->sc_dev.dv_xname, 423 chp->channel, i), DEBUG_PROBE); 424 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 425 } 426 } 427 } 428 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 429 430 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 431 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 432 DEBUG_PROBE); 433 434 /* If no drives, abort here */ 435 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 436 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 437 goto out; 438 439 /* 440 * Attach an ATAPI bus, if needed. 441 */ 442 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 443 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 444 #if NATAPIBUS > 0 445 wdc_atapibus_attach(chp); 446 #else 447 /* 448 * Fake the autoconfig "not configured" message 449 */ 450 printf("atapibus at %s channel %d not configured\n", 451 chp->wdc->sc_dev.dv_xname, chp->channel); 452 chp->atapibus = NULL; 453 #endif 454 } 455 456 for (i = 0; i < 2; i++) { 457 struct ata_device adev; 458 if ((chp->ch_drive[i].drive_flags & 459 (DRIVE_ATA | DRIVE_OLD)) == 0) { 460 continue; 461 } 462 memset(&adev, 0, sizeof(struct ata_device)); 463 adev.adev_bustype = &wdc_ata_bustype; 464 adev.adev_channel = chp->channel; 465 adev.adev_openings = 1; 466 adev.adev_drv_data = &chp->ch_drive[i]; 467 chp->ata_drives[i] = config_found(&chp->wdc->sc_dev, 468 &adev, wdprint); 469 if (chp->ata_drives[i] != NULL) { 470 wdc_probe_caps(&chp->ch_drive[i]); 471 #if NATARAID > 0 472 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 473 config_interrupts(chp->ata_drives[i], 474 ata_raid_check_component); 475 #endif /* NATARAID > 0 */ 476 } 477 } 478 479 /* 480 * reset drive_flags for unnatached devices, reset state for attached 481 * ones 482 */ 483 for (i = 0; i < 2; i++) { 484 if (chp->ch_drive[i].drv_softc == NULL) 485 chp->ch_drive[i].drive_flags = 0; 486 else 487 chp->ch_drive[i].state = 0; 488 } 489 490 /* 491 * Reset channel. The probe, with some combinations of ATA/ATAPI 492 * devices keep it in a mostly working, but strange state (with busy 493 * led on) 494 */ 495 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 496 delay(50); 497 wdcreset(chp, VERBOSE); 498 /* 499 * Read status registers to avoid spurious interrupts. 500 */ 501 for (i = 1; i >= 0; i--) { 502 if (chp->ch_drive[i].drive_flags & DRIVE) { 503 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 504 chp->wdc->select(chp,i); 505 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 506 wd_sdh, WDSD_IBM | (i << 4)); 507 if (wait_for_unbusy(chp, 10000) < 0) 508 printf("%s:%d:%d: device busy\n", 509 chp->wdc->sc_dev.dv_xname, 510 chp->channel, i); 511 } 512 } 513 } 514 515 out: 516 wdc_delref(chp); 517 } 518 519 /* 520 * Call activate routine of underlying devices. 521 */ 522 int 523 wdcactivate(self, act) 524 struct device *self; 525 enum devact act; 526 { 527 struct wdc_softc *wdc = (struct wdc_softc *)self; 528 struct channel_softc *chp; 529 struct device *sc = 0; 530 int s, i, j, error = 0; 531 532 s = splbio(); 533 switch (act) { 534 case DVACT_ACTIVATE: 535 error = EOPNOTSUPP; 536 break; 537 538 case DVACT_DEACTIVATE: 539 for (i = 0; i < wdc->nchannels; i++) { 540 chp = wdc->channels[i]; 541 542 /* 543 * We might call deactivate routine for 544 * the children of atapibus twice (once via 545 * atapibus, once directly), but since 546 * config_deactivate maintains DVF_ACTIVE flag, 547 * it's safe. 548 */ 549 sc = chp->atapibus; 550 if (sc != NULL) { 551 error = config_deactivate(sc); 552 if (error != 0) 553 goto out; 554 } 555 556 for (j = 0; j < 2; j++) { 557 sc = chp->ch_drive[j].drv_softc; 558 WDCDEBUG_PRINT(("wdcactivate: %s:" 559 " deactivating %s\n", wdc->sc_dev.dv_xname, 560 sc == NULL ? "nodrv" : sc->dv_xname), 561 DEBUG_DETACH); 562 if (sc != NULL) { 563 error = config_deactivate(sc); 564 if (error != 0) 565 goto out; 566 } 567 } 568 } 569 break; 570 } 571 572 out: 573 splx(s); 574 575 #ifdef WDCDEBUG 576 if (sc && error != 0) 577 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 578 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 579 #endif 580 return (error); 581 } 582 583 int 584 wdcdetach(self, flags) 585 struct device *self; 586 int flags; 587 { 588 struct wdc_softc *wdc = (struct wdc_softc *)self; 589 struct channel_softc *chp; 590 struct device *sc = 0; 591 int i, j, error = 0; 592 593 for (i = 0; i < wdc->nchannels; i++) { 594 chp = wdc->channels[i]; 595 596 /* 597 * Detach atapibus and its children. 598 */ 599 sc = chp->atapibus; 600 if (sc != NULL) { 601 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 602 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 603 error = config_detach(sc, flags); 604 if (error != 0) 605 goto out; 606 } 607 608 /* 609 * Detach our other children. 610 */ 611 for (j = 0; j < 2; j++) { 612 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 613 continue; 614 sc = chp->ch_drive[j].drv_softc; 615 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 616 wdc->sc_dev.dv_xname, 617 sc == NULL ? "nodrv" : sc->dv_xname), 618 DEBUG_DETACH); 619 if (sc != NULL) { 620 error = config_detach(sc, flags); 621 if (error != 0) 622 goto out; 623 } 624 } 625 626 wdc_kill_pending(chp); 627 } 628 629 out: 630 #ifdef WDCDEBUG 631 if (sc && error != 0) 632 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 633 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 634 #endif 635 return (error); 636 } 637 638 /* 639 * Start I/O on a controller, for the given channel. 640 * The first xfer may be not for our channel if the channel queues 641 * are shared. 642 */ 643 void 644 wdcstart(chp) 645 struct channel_softc *chp; 646 { 647 struct wdc_xfer *xfer; 648 649 #ifdef WDC_DIAGNOSTIC 650 int spl1, spl2; 651 652 spl1 = splbio(); 653 spl2 = splbio(); 654 if (spl2 != spl1) { 655 printf("wdcstart: not at splbio()\n"); 656 panic("wdcstart"); 657 } 658 splx(spl2); 659 splx(spl1); 660 #endif /* WDC_DIAGNOSTIC */ 661 662 /* is there a xfer ? */ 663 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 664 return; 665 666 /* adjust chp, in case we have a shared queue */ 667 chp = xfer->chp; 668 669 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 670 return; /* channel aleady active */ 671 } 672 #ifdef DIAGNOSTIC 673 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 674 panic("wdcstart: channel waiting for irq"); 675 #endif 676 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 677 if (!(*chp->wdc->claim_hw)(chp, 0)) 678 return; 679 680 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 681 chp->channel, xfer->drive), DEBUG_XFERS); 682 chp->ch_flags |= WDCF_ACTIVE; 683 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 684 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 685 chp->ch_drive[xfer->drive].state = 0; 686 } 687 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 688 KASSERT(xfer->c_flags & C_POLL); 689 xfer->c_start(chp, xfer); 690 } 691 692 /* restart an interrupted I/O */ 693 void 694 wdcrestart(v) 695 void *v; 696 { 697 struct channel_softc *chp = v; 698 int s; 699 700 s = splbio(); 701 wdcstart(chp); 702 splx(s); 703 } 704 705 706 /* 707 * Interrupt routine for the controller. Acknowledge the interrupt, check for 708 * errors on the current operation, mark it done if necessary, and start the 709 * next request. Also check for a partially done transfer, and continue with 710 * the next chunk if so. 711 */ 712 int 713 wdcintr(arg) 714 void *arg; 715 { 716 struct channel_softc *chp = arg; 717 struct wdc_xfer *xfer; 718 int ret; 719 720 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 721 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 722 DEBUG_INTR); 723 return (0); 724 } 725 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 726 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 727 /* try to clear the pending interrupt anyway */ 728 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 729 return (0); 730 } 731 732 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 733 xfer = chp->ch_queue->sc_xfer.tqh_first; 734 if (chp->ch_flags & WDCF_DMA_WAIT) { 735 chp->wdc->dma_status = 736 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 737 xfer->drive, 0); 738 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 739 /* IRQ not for us, not detected by DMA engine */ 740 return 0; 741 } 742 chp->ch_flags &= ~WDCF_DMA_WAIT; 743 } 744 chp->ch_flags &= ~WDCF_IRQ_WAIT; 745 ret = xfer->c_intr(chp, xfer, 1); 746 if (ret == 0) /* irq was not for us, still waiting for irq */ 747 chp->ch_flags |= WDCF_IRQ_WAIT; 748 return (ret); 749 } 750 751 /* Put all disk in RESET state */ 752 void wdc_reset_channel(drvp) 753 struct ata_drive_datas *drvp; 754 { 755 struct channel_softc *chp = drvp->chnl_softc; 756 int drive; 757 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 758 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 759 DEBUG_FUNCS); 760 (void) wdcreset(chp, VERBOSE); 761 for (drive = 0; drive < 2; drive++) { 762 chp->ch_drive[drive].state = 0; 763 } 764 } 765 766 int 767 wdcreset(chp, verb) 768 struct channel_softc *chp; 769 int verb; 770 { 771 int drv_mask1, drv_mask2; 772 773 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 774 chp->wdc->select(chp,0); 775 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 776 WDSD_IBM); /* master */ 777 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 778 WDCTL_RST | WDCTL_IDS); 779 delay(1000); 780 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 781 WDCTL_IDS); 782 delay(1000); 783 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 784 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 785 WDCTL_4BIT); 786 787 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 788 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 789 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 790 if (verb && drv_mask2 != drv_mask1) { 791 printf("%s channel %d: reset failed for", 792 chp->wdc->sc_dev.dv_xname, chp->channel); 793 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 794 printf(" drive 0"); 795 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 796 printf(" drive 1"); 797 printf("\n"); 798 } 799 return (drv_mask1 != drv_mask2) ? 1 : 0; 800 } 801 802 static int 803 __wdcwait_reset(chp, drv_mask) 804 struct channel_softc *chp; 805 int drv_mask; 806 { 807 int timeout; 808 u_int8_t st0, st1; 809 #ifdef WDCDEBUG 810 u_int8_t sc0, sn0, cl0, ch0; 811 u_int8_t sc1, sn1, cl1, ch1; 812 #endif 813 /* wait for BSY to deassert */ 814 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 815 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 816 chp->wdc->select(chp,0); 817 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 818 WDSD_IBM); /* master */ 819 delay(10); 820 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 821 #ifdef WDCDEBUG 822 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 823 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 824 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 825 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 826 #endif 827 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 828 chp->wdc->select(chp,1); 829 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 830 WDSD_IBM | 0x10); /* slave */ 831 delay(10); 832 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 833 #ifdef WDCDEBUG 834 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 835 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 836 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 837 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 838 #endif 839 840 if ((drv_mask & 0x01) == 0) { 841 /* no master */ 842 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 843 /* No master, slave is ready, it's done */ 844 goto end; 845 } 846 } else if ((drv_mask & 0x02) == 0) { 847 /* no slave */ 848 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 849 /* No slave, master is ready, it's done */ 850 goto end; 851 } 852 } else { 853 /* Wait for both master and slave to be ready */ 854 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 855 goto end; 856 } 857 } 858 delay(WDCDELAY); 859 } 860 /* Reset timed out. Maybe it's because drv_mask was not right */ 861 if (st0 & WDCS_BSY) 862 drv_mask &= ~0x01; 863 if (st1 & WDCS_BSY) 864 drv_mask &= ~0x02; 865 end: 866 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 867 "cl=0x%x ch=0x%x\n", 868 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 869 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 870 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 871 "cl=0x%x ch=0x%x\n", 872 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 873 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 874 875 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 876 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 877 st0, st1), DEBUG_PROBE); 878 879 return drv_mask; 880 } 881 882 /* 883 * Wait for a drive to be !BSY, and have mask in its status register. 884 * return -1 for a timeout after "timeout" ms. 885 */ 886 int 887 wdcwait(chp, mask, bits, timeout) 888 struct channel_softc *chp; 889 int mask, bits, timeout; 890 { 891 u_char status; 892 int time = 0; 893 894 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 895 :"none", chp->channel), DEBUG_STATUS); 896 chp->ch_error = 0; 897 898 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 899 900 for (;;) { 901 chp->ch_status = status = 902 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 903 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 904 break; 905 if (++time > timeout) { 906 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 907 "status %x error %x (mask 0x%x bits 0x%x)\n", 908 time, status, 909 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 910 wd_error), mask, bits), 911 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 912 return -1; 913 } 914 delay(WDCDELAY); 915 } 916 #ifdef WDCDEBUG 917 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 918 printf("wdcwait: did busy-wait, time=%d\n", time); 919 #endif 920 if (status & WDCS_ERR) 921 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 922 wd_error); 923 #ifdef WDCNDELAY_DEBUG 924 /* After autoconfig, there should be no long delays. */ 925 if (!cold && time > WDCNDELAY_DEBUG) { 926 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 927 if (xfer == NULL) 928 printf("%s channel %d: warning: busy-wait took %dus\n", 929 chp->wdc->sc_dev.dv_xname, chp->channel, 930 WDCDELAY * time); 931 else 932 printf("%s:%d:%d: warning: busy-wait took %dus\n", 933 chp->wdc->sc_dev.dv_xname, chp->channel, 934 xfer->drive, 935 WDCDELAY * time); 936 } 937 #endif 938 return 0; 939 } 940 941 /* 942 * Busy-wait for DMA to complete 943 */ 944 int 945 wdc_dmawait(chp, xfer, timeout) 946 struct channel_softc *chp; 947 struct wdc_xfer *xfer; 948 int timeout; 949 { 950 int time; 951 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 952 chp->wdc->dma_status = 953 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 954 chp->channel, xfer->drive, 0); 955 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 956 return 0; 957 delay(WDCDELAY); 958 } 959 /* timeout, force a DMA halt */ 960 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 961 chp->channel, xfer->drive, 1); 962 return 1; 963 } 964 965 void 966 wdctimeout(arg) 967 void *arg; 968 { 969 struct channel_softc *chp = (struct channel_softc *)arg; 970 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 971 int s; 972 973 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 974 975 s = splbio(); 976 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 977 __wdcerror(chp, "lost interrupt"); 978 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 979 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 980 xfer->c_bcount, 981 xfer->c_skip); 982 if (chp->ch_flags & WDCF_DMA_WAIT) { 983 chp->wdc->dma_status = 984 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 985 chp->channel, xfer->drive, 1); 986 chp->ch_flags &= ~WDCF_DMA_WAIT; 987 } 988 /* 989 * Call the interrupt routine. If we just missed an interrupt, 990 * it will do what's needed. Else, it will take the needed 991 * action (reset the device). 992 * Before that we need to reinstall the timeout callback, 993 * in case it will miss another irq while in this transfer 994 * We arbitray chose it to be 1s 995 */ 996 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 997 xfer->c_flags |= C_TIMEOU; 998 chp->ch_flags &= ~WDCF_IRQ_WAIT; 999 xfer->c_intr(chp, xfer, 1); 1000 } else 1001 __wdcerror(chp, "missing untimeout"); 1002 splx(s); 1003 } 1004 1005 /* 1006 * Probe drive's capabilites, for use by the controller later 1007 * Assumes drvp points to an existing drive. 1008 * XXX this should be a controller-indep function 1009 */ 1010 void 1011 wdc_probe_caps(drvp) 1012 struct ata_drive_datas *drvp; 1013 { 1014 struct ataparams params, params2; 1015 struct channel_softc *chp = drvp->chnl_softc; 1016 struct device *drv_dev = drvp->drv_softc; 1017 struct wdc_softc *wdc = chp->wdc; 1018 int i, printed; 1019 char *sep = ""; 1020 int cf_flags; 1021 1022 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 1023 /* IDENTIFY failed. Can't tell more about the device */ 1024 return; 1025 } 1026 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1027 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1028 /* 1029 * Controller claims 16 and 32 bit transfers. 1030 * Re-do an IDENTIFY with 32-bit transfers, 1031 * and compare results. 1032 */ 1033 drvp->drive_flags |= DRIVE_CAP32; 1034 ata_get_params(drvp, AT_POLL, ¶ms2); 1035 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1036 /* Not good. fall back to 16bits */ 1037 drvp->drive_flags &= ~DRIVE_CAP32; 1038 } else { 1039 printf("%s: 32-bit data port", drv_dev->dv_xname); 1040 } 1041 } 1042 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1043 if (params.atap_ata_major > 0x01 && 1044 params.atap_ata_major != 0xffff) { 1045 for (i = 14; i > 0; i--) { 1046 if (params.atap_ata_major & (1 << i)) { 1047 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1048 printf("%s: ", drv_dev->dv_xname); 1049 else 1050 printf(", "); 1051 printf("ATA version %d\n", i); 1052 drvp->ata_vers = i; 1053 break; 1054 } 1055 } 1056 } else 1057 #endif 1058 if (drvp->drive_flags & DRIVE_CAP32) 1059 printf("\n"); 1060 1061 /* An ATAPI device is at last PIO mode 3 */ 1062 if (drvp->drive_flags & DRIVE_ATAPI) 1063 drvp->PIO_mode = 3; 1064 1065 /* 1066 * It's not in the specs, but it seems that some drive 1067 * returns 0xffff in atap_extensions when this field is invalid 1068 */ 1069 if (params.atap_extensions != 0xffff && 1070 (params.atap_extensions & WDC_EXT_MODES)) { 1071 printed = 0; 1072 /* 1073 * XXX some drives report something wrong here (they claim to 1074 * support PIO mode 8 !). As mode is coded on 3 bits in 1075 * SET FEATURE, limit it to 7 (so limit i to 4). 1076 * If higher mode than 7 is found, abort. 1077 */ 1078 for (i = 7; i >= 0; i--) { 1079 if ((params.atap_piomode_supp & (1 << i)) == 0) 1080 continue; 1081 if (i > 4) 1082 return; 1083 /* 1084 * See if mode is accepted. 1085 * If the controller can't set its PIO mode, 1086 * assume the defaults are good, so don't try 1087 * to set it 1088 */ 1089 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1090 if (ata_set_mode(drvp, 0x08 | (i + 3), 1091 AT_POLL) != CMD_OK) 1092 continue; 1093 if (!printed) { 1094 printf("%s: drive supports PIO mode %d", 1095 drv_dev->dv_xname, i + 3); 1096 sep = ","; 1097 printed = 1; 1098 } 1099 /* 1100 * If controller's driver can't set its PIO mode, 1101 * get the highter one for the drive. 1102 */ 1103 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1104 wdc->PIO_cap >= i + 3) { 1105 drvp->PIO_mode = i + 3; 1106 drvp->PIO_cap = i + 3; 1107 break; 1108 } 1109 } 1110 if (!printed) { 1111 /* 1112 * We didn't find a valid PIO mode. 1113 * Assume the values returned for DMA are buggy too 1114 */ 1115 return; 1116 } 1117 drvp->drive_flags |= DRIVE_MODE; 1118 printed = 0; 1119 for (i = 7; i >= 0; i--) { 1120 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1121 continue; 1122 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1123 (wdc->cap & WDC_CAPABILITY_MODE)) 1124 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1125 != CMD_OK) 1126 continue; 1127 if (!printed) { 1128 printf("%s DMA mode %d", sep, i); 1129 sep = ","; 1130 printed = 1; 1131 } 1132 if (wdc->cap & WDC_CAPABILITY_DMA) { 1133 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1134 wdc->DMA_cap < i) 1135 continue; 1136 drvp->DMA_mode = i; 1137 drvp->DMA_cap = i; 1138 drvp->drive_flags |= DRIVE_DMA; 1139 } 1140 break; 1141 } 1142 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1143 printed = 0; 1144 for (i = 7; i >= 0; i--) { 1145 if ((params.atap_udmamode_supp & (1 << i)) 1146 == 0) 1147 continue; 1148 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1149 (wdc->cap & WDC_CAPABILITY_UDMA)) 1150 if (ata_set_mode(drvp, 0x40 | i, 1151 AT_POLL) != CMD_OK) 1152 continue; 1153 if (!printed) { 1154 printf("%s Ultra-DMA mode %d", sep, i); 1155 if (i == 2) 1156 printf(" (Ultra/33)"); 1157 else if (i == 4) 1158 printf(" (Ultra/66)"); 1159 else if (i == 5) 1160 printf(" (Ultra/100)"); 1161 else if (i == 6) 1162 printf(" (Ultra/133)"); 1163 sep = ","; 1164 printed = 1; 1165 } 1166 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1167 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1168 wdc->UDMA_cap < i) 1169 continue; 1170 drvp->UDMA_mode = i; 1171 drvp->UDMA_cap = i; 1172 drvp->drive_flags |= DRIVE_UDMA; 1173 } 1174 break; 1175 } 1176 } 1177 printf("\n"); 1178 } 1179 1180 /* Try to guess ATA version here, if it didn't get reported */ 1181 if (drvp->ata_vers == 0) { 1182 if (drvp->drive_flags & DRIVE_UDMA) 1183 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1184 else if (drvp->PIO_cap > 2) 1185 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1186 } 1187 cf_flags = drv_dev->dv_cfdata->cf_flags; 1188 if (cf_flags & ATA_CONFIG_PIO_SET) { 1189 drvp->PIO_mode = 1190 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1191 drvp->drive_flags |= DRIVE_MODE; 1192 } 1193 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1194 /* don't care about DMA modes */ 1195 return; 1196 } 1197 if (cf_flags & ATA_CONFIG_DMA_SET) { 1198 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1199 ATA_CONFIG_DMA_DISABLE) { 1200 drvp->drive_flags &= ~DRIVE_DMA; 1201 } else { 1202 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1203 ATA_CONFIG_DMA_OFF; 1204 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1205 } 1206 } 1207 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1208 /* don't care about UDMA modes */ 1209 return; 1210 } 1211 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1212 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1213 ATA_CONFIG_UDMA_DISABLE) { 1214 drvp->drive_flags &= ~DRIVE_UDMA; 1215 } else { 1216 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1217 ATA_CONFIG_UDMA_OFF; 1218 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1219 } 1220 } 1221 } 1222 1223 /* 1224 * downgrade the transfer mode of a drive after an error. return 1 if 1225 * downgrade was possible, 0 otherwise. 1226 */ 1227 int 1228 wdc_downgrade_mode(drvp) 1229 struct ata_drive_datas *drvp; 1230 { 1231 struct channel_softc *chp = drvp->chnl_softc; 1232 struct device *drv_dev = drvp->drv_softc; 1233 struct wdc_softc *wdc = chp->wdc; 1234 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1235 1236 /* if drive or controller don't know its mode, we can't do much */ 1237 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1238 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1239 return 0; 1240 /* current drive mode was set by a config flag, let it this way */ 1241 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1242 (cf_flags & ATA_CONFIG_DMA_SET) || 1243 (cf_flags & ATA_CONFIG_UDMA_SET)) 1244 return 0; 1245 1246 /* 1247 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1248 * Maybe we didn't properly notice the cable type 1249 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1250 * It helps in some cases. 1251 */ 1252 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1253 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1254 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1255 drv_dev->dv_xname, drvp->UDMA_mode); 1256 } 1257 1258 /* 1259 * If we were using ultra-DMA, don't downgrade to multiword DMA 1260 * if we noticed a CRC error. It has been noticed that CRC errors 1261 * in ultra-DMA lead to silent data corruption in multiword DMA. 1262 * Data corruption is less likely to occur in PIO mode. 1263 */ 1264 else if ((drvp->drive_flags & DRIVE_UDMA) && 1265 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1266 drvp->drive_flags &= ~DRIVE_UDMA; 1267 drvp->drive_flags |= DRIVE_DMA; 1268 drvp->DMA_mode = drvp->DMA_cap; 1269 printf("%s: transfer error, downgrading to DMA mode %d\n", 1270 drv_dev->dv_xname, drvp->DMA_mode); 1271 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1272 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1273 drvp->PIO_mode = drvp->PIO_cap; 1274 printf("%s: transfer error, downgrading to PIO mode %d\n", 1275 drv_dev->dv_xname, drvp->PIO_mode); 1276 } else /* already using PIO, can't downgrade */ 1277 return 0; 1278 1279 wdc->set_modes(chp); 1280 /* reset the channel, which will shedule all drives for setup */ 1281 wdc_reset_channel(drvp); 1282 return 1; 1283 } 1284 1285 int 1286 wdc_exec_command(drvp, wdc_c) 1287 struct ata_drive_datas *drvp; 1288 struct wdc_command *wdc_c; 1289 { 1290 struct channel_softc *chp = drvp->chnl_softc; 1291 struct wdc_xfer *xfer; 1292 int s, ret; 1293 1294 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1295 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1296 DEBUG_FUNCS); 1297 1298 /* set up an xfer and queue. Wait for completion */ 1299 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1300 WDC_NOSLEEP); 1301 if (xfer == NULL) { 1302 return WDC_TRY_AGAIN; 1303 } 1304 1305 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1306 wdc_c->flags |= AT_POLL; 1307 if (wdc_c->flags & AT_POLL) 1308 xfer->c_flags |= C_POLL; 1309 xfer->drive = drvp->drive; 1310 xfer->databuf = wdc_c->data; 1311 xfer->c_bcount = wdc_c->bcount; 1312 xfer->cmd = wdc_c; 1313 xfer->c_start = __wdccommand_start; 1314 xfer->c_intr = __wdccommand_intr; 1315 xfer->c_kill_xfer = __wdccommand_done; 1316 1317 s = splbio(); 1318 wdc_exec_xfer(chp, xfer); 1319 #ifdef DIAGNOSTIC 1320 if ((wdc_c->flags & AT_POLL) != 0 && 1321 (wdc_c->flags & AT_DONE) == 0) 1322 panic("wdc_exec_command: polled command not done"); 1323 #endif 1324 if (wdc_c->flags & AT_DONE) { 1325 ret = WDC_COMPLETE; 1326 } else { 1327 if (wdc_c->flags & AT_WAIT) { 1328 while ((wdc_c->flags & AT_DONE) == 0) { 1329 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1330 } 1331 ret = WDC_COMPLETE; 1332 } else { 1333 ret = WDC_QUEUED; 1334 } 1335 } 1336 splx(s); 1337 return ret; 1338 } 1339 1340 void 1341 __wdccommand_start(chp, xfer) 1342 struct channel_softc *chp; 1343 struct wdc_xfer *xfer; 1344 { 1345 int drive = xfer->drive; 1346 struct wdc_command *wdc_c = xfer->cmd; 1347 1348 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1349 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1350 DEBUG_FUNCS); 1351 1352 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1353 chp->wdc->select(chp,drive); 1354 1355 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1356 WDSD_IBM | (drive << 4)); 1357 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1358 wdc_c->timeout) != 0) { 1359 wdc_c->flags |= AT_TIMEOU; 1360 __wdccommand_done(chp, xfer); 1361 return; 1362 } 1363 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1364 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1365 if ((wdc_c->flags & AT_POLL) == 0) { 1366 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1367 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1368 wdctimeout, chp); 1369 return; 1370 } 1371 /* 1372 * Polled command. Wait for drive ready or drq. Done in intr(). 1373 * Wait for at last 400ns for status bit to be valid. 1374 */ 1375 delay(10); 1376 __wdccommand_intr(chp, xfer, 0); 1377 } 1378 1379 int 1380 __wdccommand_intr(chp, xfer, irq) 1381 struct channel_softc *chp; 1382 struct wdc_xfer *xfer; 1383 int irq; 1384 { 1385 struct wdc_command *wdc_c = xfer->cmd; 1386 int bcount = wdc_c->bcount; 1387 char *data = wdc_c->data; 1388 1389 again: 1390 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1391 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1392 if ((wdc_c->flags & AT_XFDONE) != 0) { 1393 /* 1394 * We have completed a data xfer. The drive should now be 1395 * in its initial state 1396 */ 1397 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1398 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0) != 0) { 1399 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1400 return 0; /* IRQ was not for us */ 1401 wdc_c->flags |= AT_TIMEOU; 1402 __wdccommand_done(chp, xfer); 1403 return 1; 1404 } 1405 wdc_c->flags |= AT_DONE; 1406 __wdccommand_done(chp, xfer); 1407 return 1; 1408 } 1409 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1410 (irq == 0) ? wdc_c->timeout : 0)) { 1411 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1412 return 0; /* IRQ was not for us */ 1413 wdc_c->flags |= AT_TIMEOU; 1414 __wdccommand_done(chp, xfer); 1415 return 1; 1416 } 1417 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1418 chp->wdc->irqack(chp); 1419 if (wdc_c->flags & AT_READ) { 1420 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1421 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1422 0, (u_int32_t*)data, bcount >> 2); 1423 data += bcount & 0xfffffffc; 1424 bcount = bcount & 0x03; 1425 } 1426 if (bcount > 0) 1427 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1428 wd_data, (u_int16_t *)data, bcount >> 1); 1429 /* at this point the drive should be in its initial state */ 1430 wdc_c->flags |= AT_XFDONE; 1431 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1432 wdc_c->r_st_bmask, 100) != 0) 1433 wdc_c->flags |= AT_TIMEOU; 1434 } else if (wdc_c->flags & AT_WRITE) { 1435 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1436 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1437 0, (u_int32_t*)data, bcount >> 2); 1438 data += bcount & 0xfffffffc; 1439 bcount = bcount & 0x03; 1440 } 1441 if (bcount > 0) 1442 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1443 wd_data, (u_int16_t *)data, bcount >> 1); 1444 wdc_c->flags |= AT_XFDONE; 1445 if ((wdc_c->flags & AT_POLL) == 0) { 1446 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1447 callout_reset(&chp->ch_callout, 1448 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1449 return 1; 1450 } else { 1451 goto again; 1452 } 1453 } 1454 __wdccommand_done(chp, xfer); 1455 return 1; 1456 } 1457 1458 void 1459 __wdccommand_done(chp, xfer) 1460 struct channel_softc *chp; 1461 struct wdc_xfer *xfer; 1462 { 1463 struct wdc_command *wdc_c = xfer->cmd; 1464 1465 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1466 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1467 1468 callout_stop(&chp->ch_callout); 1469 1470 if (chp->ch_status & WDCS_DWF) 1471 wdc_c->flags |= AT_DF; 1472 if (chp->ch_status & WDCS_ERR) { 1473 wdc_c->flags |= AT_ERROR; 1474 wdc_c->r_error = chp->ch_error; 1475 } 1476 wdc_c->flags |= AT_DONE; 1477 if ((wdc_c->flags & AT_READREG) != 0 && 1478 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1479 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1480 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1481 wd_sdh); 1482 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1483 wd_cyl_hi) << 8; 1484 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1485 wd_cyl_lo); 1486 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1487 wd_sector); 1488 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1489 wd_seccnt); 1490 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1491 wd_error); 1492 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1493 wd_precomp); 1494 } 1495 wdc_free_xfer(chp, xfer); 1496 if (wdc_c->flags & AT_WAIT) 1497 wakeup(wdc_c); 1498 else if (wdc_c->callback) 1499 wdc_c->callback(wdc_c->callback_arg); 1500 wdcstart(chp); 1501 return; 1502 } 1503 1504 /* 1505 * Send a command. The drive should be ready. 1506 * Assumes interrupts are blocked. 1507 */ 1508 void 1509 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1510 struct channel_softc *chp; 1511 u_int8_t drive; 1512 u_int8_t command; 1513 u_int16_t cylin; 1514 u_int8_t head, sector, count, precomp; 1515 { 1516 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1517 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1518 chp->channel, drive, command, cylin, head, sector, count, precomp), 1519 DEBUG_FUNCS); 1520 1521 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1522 chp->wdc->select(chp,drive); 1523 1524 /* Select drive, head, and addressing mode. */ 1525 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1526 WDSD_IBM | (drive << 4) | head); 1527 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1528 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1529 precomp); 1530 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1531 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1532 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1533 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1534 1535 /* Send command. */ 1536 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1537 return; 1538 } 1539 1540 /* 1541 * Send a 48-bit addressing command. The drive should be ready. 1542 * Assumes interrupts are blocked. 1543 */ 1544 void 1545 wdccommandext(chp, drive, command, blkno, count) 1546 struct channel_softc *chp; 1547 u_int8_t drive; 1548 u_int8_t command; 1549 u_int64_t blkno; 1550 u_int16_t count; 1551 { 1552 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1553 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1554 chp->channel, drive, command, (u_int32_t) blkno, count), 1555 DEBUG_FUNCS); 1556 1557 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1558 chp->wdc->select(chp,drive); 1559 1560 /* Select drive, head, and addressing mode. */ 1561 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1562 (drive << 4) | WDSD_LBA); 1563 1564 /* previous */ 1565 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1566 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1567 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1568 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1569 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1570 1571 /* current */ 1572 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1573 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1574 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1575 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1576 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1577 1578 /* Send command. */ 1579 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1580 return; 1581 } 1582 1583 /* 1584 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1585 * tested by the caller. 1586 */ 1587 void 1588 wdccommandshort(chp, drive, command) 1589 struct channel_softc *chp; 1590 int drive; 1591 int command; 1592 { 1593 1594 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1595 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1596 DEBUG_FUNCS); 1597 1598 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1599 chp->wdc->select(chp,drive); 1600 1601 /* Select drive. */ 1602 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1603 WDSD_IBM | (drive << 4)); 1604 1605 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1606 } 1607 1608 /* Add a command to the queue and start controller. Must be called at splbio */ 1609 1610 void 1611 wdc_exec_xfer(chp, xfer) 1612 struct channel_softc *chp; 1613 struct wdc_xfer *xfer; 1614 { 1615 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1616 chp->channel, xfer->drive), DEBUG_XFERS); 1617 1618 /* complete xfer setup */ 1619 xfer->chp = chp; 1620 1621 /* 1622 * If we are a polled command, and the list is not empty, 1623 * we are doing a dump. Drop the list to allow the polled command 1624 * to complete, we're going to reboot soon anyway. 1625 */ 1626 if ((xfer->c_flags & C_POLL) != 0 && 1627 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1628 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1629 } 1630 /* insert at the end of command list */ 1631 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1632 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1633 chp->ch_flags), DEBUG_XFERS); 1634 wdcstart(chp); 1635 } 1636 1637 struct wdc_xfer * 1638 wdc_get_xfer(flags) 1639 int flags; 1640 { 1641 struct wdc_xfer *xfer; 1642 int s; 1643 1644 s = splbio(); 1645 xfer = pool_get(&wdc_xfer_pool, 1646 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1647 splx(s); 1648 if (xfer != NULL) { 1649 memset(xfer, 0, sizeof(struct wdc_xfer)); 1650 } 1651 return xfer; 1652 } 1653 1654 void 1655 wdc_free_xfer(chp, xfer) 1656 struct channel_softc *chp; 1657 struct wdc_xfer *xfer; 1658 { 1659 struct wdc_softc *wdc = chp->wdc; 1660 int s; 1661 1662 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1663 (*wdc->free_hw)(chp); 1664 s = splbio(); 1665 chp->ch_flags &= ~WDCF_ACTIVE; 1666 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1667 pool_put(&wdc_xfer_pool, xfer); 1668 splx(s); 1669 } 1670 1671 /* 1672 * Kill off all pending xfers for a channel_softc. 1673 * 1674 * Must be called at splbio(). 1675 */ 1676 void 1677 wdc_kill_pending(chp) 1678 struct channel_softc *chp; 1679 { 1680 struct wdc_xfer *xfer; 1681 1682 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1683 chp = xfer->chp; 1684 (*xfer->c_kill_xfer)(chp, xfer); 1685 } 1686 } 1687 1688 static void 1689 __wdcerror(chp, msg) 1690 struct channel_softc *chp; 1691 char *msg; 1692 { 1693 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1694 1695 if (xfer == NULL) 1696 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1697 msg); 1698 else 1699 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1700 chp->channel, xfer->drive, msg); 1701 } 1702 1703 /* 1704 * the bit bucket 1705 */ 1706 void 1707 wdcbit_bucket(chp, size) 1708 struct channel_softc *chp; 1709 int size; 1710 { 1711 1712 for (; size >= 2; size -= 2) 1713 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1714 if (size) 1715 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1716 } 1717 1718 int 1719 wdc_addref(chp) 1720 struct channel_softc *chp; 1721 { 1722 struct wdc_softc *wdc = chp->wdc; 1723 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1724 int s, error = 0; 1725 1726 s = splbio(); 1727 if (adapt->adapt_refcnt++ == 0 && 1728 adapt->adapt_enable != NULL) { 1729 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1730 if (error) 1731 adapt->adapt_refcnt--; 1732 } 1733 splx(s); 1734 return (error); 1735 } 1736 1737 void 1738 wdc_delref(chp) 1739 struct channel_softc *chp; 1740 { 1741 struct wdc_softc *wdc = chp->wdc; 1742 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1743 int s; 1744 1745 s = splbio(); 1746 if (adapt->adapt_refcnt-- == 1 && 1747 adapt->adapt_enable != NULL) 1748 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1749 splx(s); 1750 } 1751 1752 void 1753 wdc_print_modes(struct channel_softc *chp) 1754 { 1755 int drive; 1756 struct ata_drive_datas *drvp; 1757 1758 for (drive = 0; drive < 2; drive++) { 1759 drvp = &chp->ch_drive[drive]; 1760 if ((drvp->drive_flags & DRIVE) == 0) 1761 continue; 1762 printf("%s(%s:%d:%d): using PIO mode %d", 1763 drvp->drv_softc->dv_xname, 1764 chp->wdc->sc_dev.dv_xname, 1765 chp->channel, drive, drvp->PIO_mode); 1766 if (drvp->drive_flags & DRIVE_DMA) 1767 printf(", DMA mode %d", drvp->DMA_mode); 1768 if (drvp->drive_flags & DRIVE_UDMA) { 1769 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1770 if (drvp->UDMA_mode == 2) 1771 printf(" (Ultra/33)"); 1772 else if (drvp->UDMA_mode == 4) 1773 printf(" (Ultra/66)"); 1774 else if (drvp->UDMA_mode == 5) 1775 printf(" (Ultra/100)"); 1776 } 1777 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1778 printf(" (using DMA data transfers)"); 1779 printf("\n"); 1780 } 1781 } 1782
Indexes created Tue Sep 23 02:09:52 GMT 2025