wdc.c revision 1.125
1 /* $NetBSD: wdc.c,v 1.125 2003/09/19 21:36:02 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.125 2003/09/19 21:36:02 mycroft Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/wdvar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 struct pool wdc_xfer_pool; 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL 136 }; 137 #endif 138 139 static void __wdcerror __P((struct channel_softc*, char *)); 140 static int __wdcwait_reset __P((struct channel_softc *, int)); 141 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 142 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 143 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 144 int wdprint __P((void *, const char *)); 145 void wdc_channel_attach __P((struct channel_softc *)); 146 147 #define DEBUG_INTR 0x01 148 #define DEBUG_XFERS 0x02 149 #define DEBUG_STATUS 0x04 150 #define DEBUG_FUNCS 0x08 151 #define DEBUG_PROBE 0x10 152 #define DEBUG_DETACH 0x20 153 #define DEBUG_DELAY 0x40 154 #ifdef WDCDEBUG 155 int wdcdebug_mask = 0; 156 int wdc_nxfer = 0; 157 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 158 #else 159 #define WDCDEBUG_PRINT(args, level) 160 #endif 161 162 int 163 wdprint(aux, pnp) 164 void *aux; 165 const char *pnp; 166 { 167 struct ata_device *adev = aux; 168 if (pnp) 169 aprint_normal("wd at %s", pnp); 170 aprint_normal(" channel %d drive %d", adev->adev_channel, 171 adev->adev_drv_data->drive); 172 return (UNCONF); 173 } 174 175 /* Test to see controller with at last one attached drive is there. 176 * Returns a bit for each possible drive found (0x01 for drive 0, 177 * 0x02 for drive 1). 178 * Logic: 179 * - If a status register is at 0xff, assume there is no drive here 180 * (ISA has pull-up resistors). Similarly if the status register has 181 * the value we last wrote to the bus (for IDE interfaces without pullups). 182 * If no drive at all -> return. 183 * - reset the controller, wait for it to complete (may take up to 31s !). 184 * If timeout -> return. 185 * - test ATA/ATAPI signatures. If at last one drive found -> return. 186 * - try an ATA command on the master. 187 */ 188 189 int 190 wdcprobe(chp) 191 struct channel_softc *chp; 192 { 193 u_int8_t st0, st1, sc, sn, cl, ch; 194 u_int8_t ret_value = 0x03; 195 u_int8_t drive; 196 197 /* 198 * Sanity check to see if the wdc channel responds at all. 199 */ 200 201 if (chp->wdc == NULL || 202 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 203 204 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 205 chp->wdc->select(chp,0); 206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 207 WDSD_IBM); 208 delay(10); 209 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 210 211 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 212 chp->wdc->select(chp,1); 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM | 0x10); 215 delay(10); 216 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 217 218 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 219 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 220 chp->channel, st0, st1), DEBUG_PROBE); 221 222 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 223 ret_value &= ~0x01; 224 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 225 ret_value &= ~0x02; 226 227 /* Register writability test, drive 0. */ 228 if (ret_value & 0x01) { 229 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 230 chp->wdc->select(chp,0); 231 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 232 WDSD_IBM); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 234 0x01); 235 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 236 wd_cyl_lo) != 0x01) 237 ret_value &= ~0x01; 238 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 239 0x02); 240 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 241 wd_cyl_lo) != 0x02) 242 ret_value &= ~0x01; 243 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 244 0x01); 245 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 246 wd_sector) != 0x01) 247 ret_value &= ~0x01; 248 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 249 0x02); 250 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 251 wd_sector) != 0x02) 252 ret_value &= ~0x01; 253 } 254 255 /* Register writability test, drive 1. */ 256 if (ret_value & 0x02) { 257 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 258 chp->wdc->select(chp,1); 259 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 260 WDSD_IBM | 0x10); 261 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 262 0x01); 263 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 264 wd_cyl_lo) != 0x01) 265 ret_value &= ~0x02; 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 267 0x02); 268 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 269 wd_cyl_lo) != 0x02) 270 ret_value &= ~0x02; 271 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 272 0x01); 273 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 274 wd_sector) != 0x01) 275 ret_value &= ~0x02; 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 277 0x02); 278 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 279 wd_sector) != 0x02) 280 ret_value &= ~0x02; 281 } 282 283 /* Register ghost test. */ 284 if (ret_value == 0x03) { 285 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 286 chp->wdc->select(chp,1); 287 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 288 WDSD_IBM | 0x10); 289 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 0x01); 290 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 291 chp->wdc->select(chp,0); 292 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 293 WDSD_IBM); 294 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 0x02); 295 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 296 chp->wdc->select(chp,1); 297 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 298 WDSD_IBM | 0x10); 299 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector) == 0x02) { 300 printf("ghost detected\n"); 301 ret_value = 0x01; 302 } 303 } 304 305 if (ret_value == 0) 306 return 0; 307 308 } 309 310 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 311 chp->wdc->select(chp,0); 312 /* assert SRST, wait for reset to complete */ 313 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 314 WDSD_IBM); 315 delay(10); 316 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 317 WDCTL_RST | WDCTL_IDS); 318 DELAY(1000); 319 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 320 WDCTL_IDS); 321 delay(1000); 322 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 323 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 324 delay(10); 325 326 ret_value = __wdcwait_reset(chp, ret_value); 327 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 328 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 329 ret_value), DEBUG_PROBE); 330 331 /* if reset failed, there's nothing here */ 332 if (ret_value == 0) 333 return 0; 334 335 /* 336 * Test presence of drives. First test register signatures looking for 337 * ATAPI devices. If it's not an ATAPI and reset said there may be 338 * something here assume it's ATA or OLD. Ghost will be killed later in 339 * attach routine. 340 */ 341 for (drive = 0; drive < 2; drive++) { 342 if ((ret_value & (0x01 << drive)) == 0) 343 continue; 344 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 345 chp->wdc->select(chp,drive); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 347 WDSD_IBM | (drive << 4)); 348 delay(10); 349 /* Save registers contents */ 350 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 351 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 352 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 353 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 354 355 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 356 "cl=0x%x ch=0x%x\n", 357 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 358 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 359 /* 360 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 361 * we get wrong values here, so ignore it. 362 */ 363 if (cl == 0x14 && ch == 0xeb) { 364 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 365 } else { 366 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 367 if (chp->wdc == NULL || 368 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 369 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 370 } 371 } 372 return (ret_value); 373 } 374 375 void 376 wdcattach(self) 377 struct device *self; 378 { 379 struct wdc_softc *wdc = (void *)self; 380 int i; 381 382 for (i = 0; i < wdc->nchannels; i++) 383 wdc_channel_attach(wdc->channels[i]); 384 } 385 386 void 387 wdc_channel_attach(chp) 388 struct channel_softc *chp; 389 { 390 int ctrl_flags, i, error; 391 struct ataparams params; 392 static int inited = 0; 393 394 if (chp->ch_flags & WDCF_DISABLED) 395 return; 396 397 callout_init(&chp->ch_callout); 398 399 if ((error = wdc_addref(chp)) != 0) { 400 aprint_error("%s: unable to enable controller\n", 401 chp->wdc->sc_dev.dv_xname); 402 return; 403 } 404 405 if (wdcprobe(chp) == 0) 406 /* If no drives, abort attach here. */ 407 goto out; 408 409 /* initialise global data */ 410 if (inited == 0) { 411 /* Initialize the wdc_xfer pool. */ 412 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 413 0, 0, "wdcspl", NULL); 414 inited++; 415 } 416 TAILQ_INIT(&chp->ch_queue->sc_xfer); 417 418 for (i = 0; i < 2; i++) { 419 chp->ch_drive[i].chnl_softc = chp; 420 chp->ch_drive[i].drive = i; 421 /* 422 * Init error counter so that an error withing the first xfers 423 * will trigger a downgrade 424 */ 425 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 426 427 /* If controller can't do 16bit flag the drives as 32bit */ 428 if ((chp->wdc->cap & 429 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 430 WDC_CAPABILITY_DATA32) 431 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 432 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 433 continue; 434 435 /* 436 * Wait a bit, some devices are weird just after a reset. 437 * Then issue a IDENTIFY command, to try to detect slave ghost 438 */ 439 delay(5000); 440 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, ¶ms); 441 if (error != CMD_OK) { 442 delay(1000000); 443 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, 444 ¶ms); 445 } 446 if (error == CMD_OK) { 447 /* If IDENTIFY succeded, this is not an OLD ctrl */ 448 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 449 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 450 } else { 451 chp->ch_drive[i].drive_flags &= 452 ~(DRIVE_ATA | DRIVE_ATAPI); 453 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 454 chp->wdc->sc_dev.dv_xname, 455 chp->channel, i, error), DEBUG_PROBE); 456 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 457 continue; 458 /* 459 * Pre-ATA drive ? 460 * Test registers writability (Error register not 461 * writable, but cyllo is), then try an ATA command. 462 */ 463 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 464 chp->wdc->select(chp,i); 465 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 466 WDSD_IBM | (i << 4)); 467 delay(10); 468 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 469 wd_error, 0x58); 470 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 471 wd_cyl_lo, 0xa5); 472 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 473 wd_error == 0x58) || 474 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 475 wd_cyl_lo) != 0xa5) { 476 WDCDEBUG_PRINT(("%s:%d:%d: register " 477 "writability failed\n", 478 chp->wdc->sc_dev.dv_xname, 479 chp->channel, i), DEBUG_PROBE); 480 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 481 } 482 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 483 chp->wdc->select(chp,i); 484 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 485 WDSD_IBM | (i << 4)); 486 delay(100); 487 if (wait_for_ready(chp, 10000) != 0) { 488 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 489 chp->wdc->sc_dev.dv_xname, 490 chp->channel, i), DEBUG_PROBE); 491 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 492 continue; 493 } 494 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 495 wd_command, WDCC_RECAL); 496 if (wait_for_ready(chp, 10000) != 0) { 497 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 498 chp->wdc->sc_dev.dv_xname, 499 chp->channel, i), DEBUG_PROBE); 500 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 501 } 502 } 503 } 504 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 505 506 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 507 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 508 DEBUG_PROBE); 509 510 /* If no drives, abort here */ 511 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 512 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 513 goto out; 514 515 /* 516 * Attach an ATAPI bus, if needed. 517 */ 518 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 519 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 520 #if NATAPIBUS > 0 521 wdc_atapibus_attach(chp); 522 #else 523 /* 524 * Fake the autoconfig "not configured" message 525 */ 526 aprint_normal("atapibus at %s channel %d not configured\n", 527 chp->wdc->sc_dev.dv_xname, chp->channel); 528 chp->atapibus = NULL; 529 #endif 530 } 531 532 for (i = 0; i < 2; i++) { 533 struct ata_device adev; 534 if ((chp->ch_drive[i].drive_flags & 535 (DRIVE_ATA | DRIVE_OLD)) == 0) { 536 continue; 537 } 538 memset(&adev, 0, sizeof(struct ata_device)); 539 adev.adev_bustype = &wdc_ata_bustype; 540 adev.adev_channel = chp->channel; 541 adev.adev_openings = 1; 542 adev.adev_drv_data = &chp->ch_drive[i]; 543 chp->ata_drives[i] = config_found(&chp->wdc->sc_dev, 544 &adev, wdprint); 545 if (chp->ata_drives[i] != NULL) { 546 wdc_probe_caps(&chp->ch_drive[i]); 547 #if NATARAID > 0 548 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 549 config_interrupts(chp->ata_drives[i], 550 ata_raid_check_component); 551 #endif /* NATARAID > 0 */ 552 } 553 } 554 555 /* 556 * reset drive_flags for unnatached devices, reset state for attached 557 * ones 558 */ 559 for (i = 0; i < 2; i++) { 560 if (chp->ch_drive[i].drv_softc == NULL) 561 chp->ch_drive[i].drive_flags = 0; 562 else 563 chp->ch_drive[i].state = 0; 564 } 565 566 /* 567 * Reset channel. The probe, with some combinations of ATA/ATAPI 568 * devices keep it in a mostly working, but strange state (with busy 569 * led on) 570 */ 571 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 572 delay(50); 573 wdcreset(chp, VERBOSE); 574 /* 575 * Read status registers to avoid spurious interrupts. 576 */ 577 for (i = 1; i >= 0; i--) { 578 if (chp->ch_drive[i].drive_flags & DRIVE) { 579 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 580 chp->wdc->select(chp,i); 581 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 582 wd_sdh, WDSD_IBM | (i << 4)); 583 if (wait_for_unbusy(chp, 10000) < 0) 584 aprint_error("%s:%d:%d: device busy\n", 585 chp->wdc->sc_dev.dv_xname, 586 chp->channel, i); 587 } 588 } 589 } 590 591 if (chp->wdc->cap & WDC_CAPABILITY_MODE) 592 chp->wdc->set_modes(chp); 593 wdc_print_modes(chp); 594 595 out: 596 wdc_delref(chp); 597 } 598 599 /* 600 * Call activate routine of underlying devices. 601 */ 602 int 603 wdcactivate(self, act) 604 struct device *self; 605 enum devact act; 606 { 607 struct wdc_softc *wdc = (struct wdc_softc *)self; 608 struct channel_softc *chp; 609 struct device *sc = 0; 610 int s, i, j, error = 0; 611 612 s = splbio(); 613 switch (act) { 614 case DVACT_ACTIVATE: 615 error = EOPNOTSUPP; 616 break; 617 618 case DVACT_DEACTIVATE: 619 for (i = 0; i < wdc->nchannels; i++) { 620 chp = wdc->channels[i]; 621 622 /* 623 * We might call deactivate routine for 624 * the children of atapibus twice (once via 625 * atapibus, once directly), but since 626 * config_deactivate maintains DVF_ACTIVE flag, 627 * it's safe. 628 */ 629 sc = chp->atapibus; 630 if (sc != NULL) { 631 error = config_deactivate(sc); 632 if (error != 0) 633 goto out; 634 } 635 636 for (j = 0; j < 2; j++) { 637 sc = chp->ch_drive[j].drv_softc; 638 WDCDEBUG_PRINT(("wdcactivate: %s:" 639 " deactivating %s\n", wdc->sc_dev.dv_xname, 640 sc == NULL ? "nodrv" : sc->dv_xname), 641 DEBUG_DETACH); 642 if (sc != NULL) { 643 error = config_deactivate(sc); 644 if (error != 0) 645 goto out; 646 } 647 } 648 } 649 break; 650 } 651 652 out: 653 splx(s); 654 655 #ifdef WDCDEBUG 656 if (sc && error != 0) 657 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 658 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 659 #endif 660 return (error); 661 } 662 663 int 664 wdcdetach(self, flags) 665 struct device *self; 666 int flags; 667 { 668 struct wdc_softc *wdc = (struct wdc_softc *)self; 669 struct channel_softc *chp; 670 struct device *sc = 0; 671 int i, j, error = 0; 672 673 for (i = 0; i < wdc->nchannels; i++) { 674 chp = wdc->channels[i]; 675 676 /* 677 * Detach atapibus and its children. 678 */ 679 sc = chp->atapibus; 680 if (sc != NULL) { 681 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 682 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 683 error = config_detach(sc, flags); 684 if (error != 0) 685 goto out; 686 } 687 688 /* 689 * Detach our other children. 690 */ 691 for (j = 0; j < 2; j++) { 692 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 693 continue; 694 sc = chp->ch_drive[j].drv_softc; 695 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 696 wdc->sc_dev.dv_xname, 697 sc == NULL ? "nodrv" : sc->dv_xname), 698 DEBUG_DETACH); 699 if (sc != NULL) { 700 error = config_detach(sc, flags); 701 if (error != 0) 702 goto out; 703 } 704 } 705 706 wdc_kill_pending(chp); 707 } 708 709 out: 710 #ifdef WDCDEBUG 711 if (sc && error != 0) 712 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 713 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 714 #endif 715 return (error); 716 } 717 718 /* 719 * Start I/O on a controller, for the given channel. 720 * The first xfer may be not for our channel if the channel queues 721 * are shared. 722 */ 723 void 724 wdcstart(chp) 725 struct channel_softc *chp; 726 { 727 struct wdc_xfer *xfer; 728 729 #ifdef WDC_DIAGNOSTIC 730 int spl1, spl2; 731 732 spl1 = splbio(); 733 spl2 = splbio(); 734 if (spl2 != spl1) { 735 printf("wdcstart: not at splbio()\n"); 736 panic("wdcstart"); 737 } 738 splx(spl2); 739 splx(spl1); 740 #endif /* WDC_DIAGNOSTIC */ 741 742 /* is there a xfer ? */ 743 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 744 return; 745 746 /* adjust chp, in case we have a shared queue */ 747 chp = xfer->chp; 748 749 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 750 return; /* channel aleady active */ 751 } 752 #ifdef DIAGNOSTIC 753 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 754 panic("wdcstart: channel waiting for irq"); 755 #endif 756 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 757 if (!(*chp->wdc->claim_hw)(chp, 0)) 758 return; 759 760 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 761 chp->channel, xfer->drive), DEBUG_XFERS); 762 chp->ch_flags |= WDCF_ACTIVE; 763 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 764 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 765 chp->ch_drive[xfer->drive].state = 0; 766 } 767 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 768 KASSERT(xfer->c_flags & C_POLL); 769 xfer->c_start(chp, xfer); 770 } 771 772 /* restart an interrupted I/O */ 773 void 774 wdcrestart(v) 775 void *v; 776 { 777 struct channel_softc *chp = v; 778 int s; 779 780 s = splbio(); 781 wdcstart(chp); 782 splx(s); 783 } 784 785 786 /* 787 * Interrupt routine for the controller. Acknowledge the interrupt, check for 788 * errors on the current operation, mark it done if necessary, and start the 789 * next request. Also check for a partially done transfer, and continue with 790 * the next chunk if so. 791 */ 792 int 793 wdcintr(arg) 794 void *arg; 795 { 796 struct channel_softc *chp = arg; 797 struct wdc_xfer *xfer; 798 int ret; 799 800 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 801 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 802 DEBUG_INTR); 803 return (0); 804 } 805 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 806 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 807 /* try to clear the pending interrupt anyway */ 808 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 809 return (0); 810 } 811 812 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 813 xfer = chp->ch_queue->sc_xfer.tqh_first; 814 if (chp->ch_flags & WDCF_DMA_WAIT) { 815 chp->wdc->dma_status = 816 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 817 xfer->drive, 0); 818 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 819 /* IRQ not for us, not detected by DMA engine */ 820 return 0; 821 } 822 chp->ch_flags &= ~WDCF_DMA_WAIT; 823 } 824 chp->ch_flags &= ~WDCF_IRQ_WAIT; 825 ret = xfer->c_intr(chp, xfer, 1); 826 if (ret == 0) /* irq was not for us, still waiting for irq */ 827 chp->ch_flags |= WDCF_IRQ_WAIT; 828 return (ret); 829 } 830 831 /* Put all disk in RESET state */ 832 void 833 wdc_reset_channel(drvp) 834 struct ata_drive_datas *drvp; 835 { 836 struct channel_softc *chp = drvp->chnl_softc; 837 int drive; 838 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 839 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 840 DEBUG_FUNCS); 841 (void) wdcreset(chp, VERBOSE); 842 for (drive = 0; drive < 2; drive++) { 843 chp->ch_drive[drive].state = 0; 844 } 845 } 846 847 int 848 wdcreset(chp, verb) 849 struct channel_softc *chp; 850 int verb; 851 { 852 int drv_mask1, drv_mask2; 853 854 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 855 chp->wdc->select(chp,0); 856 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 857 WDSD_IBM); /* master */ 858 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 859 WDCTL_RST | WDCTL_IDS); 860 delay(1000); 861 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 862 WDCTL_IDS); 863 delay(1000); 864 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 865 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 866 WDCTL_4BIT); 867 868 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 869 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 870 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 871 if (verb && drv_mask2 != drv_mask1) { 872 printf("%s channel %d: reset failed for", 873 chp->wdc->sc_dev.dv_xname, chp->channel); 874 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 875 printf(" drive 0"); 876 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 877 printf(" drive 1"); 878 printf("\n"); 879 } 880 return (drv_mask1 != drv_mask2) ? 1 : 0; 881 } 882 883 static int 884 __wdcwait_reset(chp, drv_mask) 885 struct channel_softc *chp; 886 int drv_mask; 887 { 888 int timeout; 889 u_int8_t st0, st1; 890 #ifdef WDCDEBUG 891 u_int8_t sc0, sn0, cl0, ch0; 892 u_int8_t sc1, sn1, cl1, ch1; 893 #endif 894 /* wait for BSY to deassert */ 895 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 896 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 897 chp->wdc->select(chp,0); 898 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 899 WDSD_IBM); /* master */ 900 delay(10); 901 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 902 #ifdef WDCDEBUG 903 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 904 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 905 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 906 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 907 #endif 908 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 909 chp->wdc->select(chp,1); 910 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 911 WDSD_IBM | 0x10); /* slave */ 912 delay(10); 913 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 914 #ifdef WDCDEBUG 915 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 916 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 917 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 918 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 919 #endif 920 921 if ((drv_mask & 0x01) == 0) { 922 /* no master */ 923 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 924 /* No master, slave is ready, it's done */ 925 goto end; 926 } 927 } else if ((drv_mask & 0x02) == 0) { 928 /* no slave */ 929 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 930 /* No slave, master is ready, it's done */ 931 goto end; 932 } 933 } else { 934 /* Wait for both master and slave to be ready */ 935 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 936 goto end; 937 } 938 } 939 delay(WDCDELAY); 940 } 941 /* Reset timed out. Maybe it's because drv_mask was not right */ 942 if (st0 & WDCS_BSY) 943 drv_mask &= ~0x01; 944 if (st1 & WDCS_BSY) 945 drv_mask &= ~0x02; 946 end: 947 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 948 "cl=0x%x ch=0x%x\n", 949 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 950 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 951 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 952 "cl=0x%x ch=0x%x\n", 953 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 954 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 955 956 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 957 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 958 st0, st1), DEBUG_PROBE); 959 960 return drv_mask; 961 } 962 963 /* 964 * Wait for a drive to be !BSY, and have mask in its status register. 965 * return -1 for a timeout after "timeout" ms. 966 */ 967 int 968 wdcwait(chp, mask, bits, timeout) 969 struct channel_softc *chp; 970 int mask, bits, timeout; 971 { 972 u_char status; 973 int time = 0; 974 975 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 976 :"none", chp->channel), DEBUG_STATUS); 977 chp->ch_error = 0; 978 979 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 980 981 for (;;) { 982 chp->ch_status = status = 983 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 984 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 985 break; 986 if (++time > timeout) { 987 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 988 "status %x error %x (mask 0x%x bits 0x%x)\n", 989 time, status, 990 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 991 wd_error), mask, bits), 992 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 993 return -1; 994 } 995 delay(WDCDELAY); 996 } 997 #ifdef WDCDEBUG 998 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 999 printf("wdcwait: did busy-wait, time=%d\n", time); 1000 #endif 1001 if (status & WDCS_ERR) 1002 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1003 wd_error); 1004 #ifdef WDCNDELAY_DEBUG 1005 /* After autoconfig, there should be no long delays. */ 1006 if (!cold && time > WDCNDELAY_DEBUG) { 1007 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1008 if (xfer == NULL) 1009 printf("%s channel %d: warning: busy-wait took %dus\n", 1010 chp->wdc->sc_dev.dv_xname, chp->channel, 1011 WDCDELAY * time); 1012 else 1013 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1014 chp->wdc->sc_dev.dv_xname, chp->channel, 1015 xfer->drive, 1016 WDCDELAY * time); 1017 } 1018 #endif 1019 return 0; 1020 } 1021 1022 /* 1023 * Busy-wait for DMA to complete 1024 */ 1025 int 1026 wdc_dmawait(chp, xfer, timeout) 1027 struct channel_softc *chp; 1028 struct wdc_xfer *xfer; 1029 int timeout; 1030 { 1031 int time; 1032 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1033 chp->wdc->dma_status = 1034 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1035 chp->channel, xfer->drive, 0); 1036 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1037 return 0; 1038 delay(WDCDELAY); 1039 } 1040 /* timeout, force a DMA halt */ 1041 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1042 chp->channel, xfer->drive, 1); 1043 return 1; 1044 } 1045 1046 void 1047 wdctimeout(arg) 1048 void *arg; 1049 { 1050 struct channel_softc *chp = (struct channel_softc *)arg; 1051 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1052 int s; 1053 1054 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1055 1056 s = splbio(); 1057 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1058 __wdcerror(chp, "lost interrupt"); 1059 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1060 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1061 xfer->c_bcount, 1062 xfer->c_skip); 1063 if (chp->ch_flags & WDCF_DMA_WAIT) { 1064 chp->wdc->dma_status = 1065 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1066 chp->channel, xfer->drive, 1); 1067 chp->ch_flags &= ~WDCF_DMA_WAIT; 1068 } 1069 /* 1070 * Call the interrupt routine. If we just missed an interrupt, 1071 * it will do what's needed. Else, it will take the needed 1072 * action (reset the device). 1073 * Before that we need to reinstall the timeout callback, 1074 * in case it will miss another irq while in this transfer 1075 * We arbitray chose it to be 1s 1076 */ 1077 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1078 xfer->c_flags |= C_TIMEOU; 1079 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1080 xfer->c_intr(chp, xfer, 1); 1081 } else 1082 __wdcerror(chp, "missing untimeout"); 1083 splx(s); 1084 } 1085 1086 /* 1087 * Probe drive's capabilites, for use by the controller later 1088 * Assumes drvp points to an existing drive. 1089 * XXX this should be a controller-indep function 1090 */ 1091 void 1092 wdc_probe_caps(drvp) 1093 struct ata_drive_datas *drvp; 1094 { 1095 struct ataparams params, params2; 1096 struct channel_softc *chp = drvp->chnl_softc; 1097 struct device *drv_dev = drvp->drv_softc; 1098 struct wdc_softc *wdc = chp->wdc; 1099 int i, printed; 1100 char *sep = ""; 1101 int cf_flags; 1102 1103 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1104 /* IDENTIFY failed. Can't tell more about the device */ 1105 return; 1106 } 1107 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1108 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1109 /* 1110 * Controller claims 16 and 32 bit transfers. 1111 * Re-do an IDENTIFY with 32-bit transfers, 1112 * and compare results. 1113 */ 1114 drvp->drive_flags |= DRIVE_CAP32; 1115 ata_get_params(drvp, AT_WAIT, ¶ms2); 1116 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1117 /* Not good. fall back to 16bits */ 1118 drvp->drive_flags &= ~DRIVE_CAP32; 1119 } else { 1120 aprint_normal("%s: 32-bit data port\n", 1121 drv_dev->dv_xname); 1122 } 1123 } 1124 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1125 if (params.atap_ata_major > 0x01 && 1126 params.atap_ata_major != 0xffff) { 1127 for (i = 14; i > 0; i--) { 1128 if (params.atap_ata_major & (1 << i)) { 1129 aprint_normal("%s: ATA version %d\n", 1130 drv_dev->dv_xname, i); 1131 drvp->ata_vers = i; 1132 break; 1133 } 1134 } 1135 } 1136 #endif 1137 1138 /* An ATAPI device is at last PIO mode 3 */ 1139 if (drvp->drive_flags & DRIVE_ATAPI) 1140 drvp->PIO_mode = 3; 1141 1142 /* 1143 * It's not in the specs, but it seems that some drive 1144 * returns 0xffff in atap_extensions when this field is invalid 1145 */ 1146 if (params.atap_extensions != 0xffff && 1147 (params.atap_extensions & WDC_EXT_MODES)) { 1148 printed = 0; 1149 /* 1150 * XXX some drives report something wrong here (they claim to 1151 * support PIO mode 8 !). As mode is coded on 3 bits in 1152 * SET FEATURE, limit it to 7 (so limit i to 4). 1153 * If higher mode than 7 is found, abort. 1154 */ 1155 for (i = 7; i >= 0; i--) { 1156 if ((params.atap_piomode_supp & (1 << i)) == 0) 1157 continue; 1158 if (i > 4) 1159 return; 1160 /* 1161 * See if mode is accepted. 1162 * If the controller can't set its PIO mode, 1163 * assume the defaults are good, so don't try 1164 * to set it 1165 */ 1166 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1167 if (ata_set_mode(drvp, 0x08 | (i + 3), 1168 AT_WAIT) != CMD_OK) 1169 continue; 1170 if (!printed) { 1171 aprint_normal("%s: drive supports PIO mode %d", 1172 drv_dev->dv_xname, i + 3); 1173 sep = ","; 1174 printed = 1; 1175 } 1176 /* 1177 * If controller's driver can't set its PIO mode, 1178 * get the highter one for the drive. 1179 */ 1180 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1181 wdc->PIO_cap >= i + 3) { 1182 drvp->PIO_mode = i + 3; 1183 drvp->PIO_cap = i + 3; 1184 break; 1185 } 1186 } 1187 if (!printed) { 1188 /* 1189 * We didn't find a valid PIO mode. 1190 * Assume the values returned for DMA are buggy too 1191 */ 1192 return; 1193 } 1194 drvp->drive_flags |= DRIVE_MODE; 1195 printed = 0; 1196 for (i = 7; i >= 0; i--) { 1197 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1198 continue; 1199 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1200 (wdc->cap & WDC_CAPABILITY_MODE)) 1201 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1202 != CMD_OK) 1203 continue; 1204 if (!printed) { 1205 aprint_normal("%s DMA mode %d", sep, i); 1206 sep = ","; 1207 printed = 1; 1208 } 1209 if (wdc->cap & WDC_CAPABILITY_DMA) { 1210 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1211 wdc->DMA_cap < i) 1212 continue; 1213 drvp->DMA_mode = i; 1214 drvp->DMA_cap = i; 1215 drvp->drive_flags |= DRIVE_DMA; 1216 } 1217 break; 1218 } 1219 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1220 printed = 0; 1221 for (i = 7; i >= 0; i--) { 1222 if ((params.atap_udmamode_supp & (1 << i)) 1223 == 0) 1224 continue; 1225 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1226 (wdc->cap & WDC_CAPABILITY_UDMA)) 1227 if (ata_set_mode(drvp, 0x40 | i, 1228 AT_WAIT) != CMD_OK) 1229 continue; 1230 if (!printed) { 1231 aprint_normal("%s Ultra-DMA mode %d", 1232 sep, i); 1233 if (i == 2) 1234 aprint_normal(" (Ultra/33)"); 1235 else if (i == 4) 1236 aprint_normal(" (Ultra/66)"); 1237 else if (i == 5) 1238 aprint_normal(" (Ultra/100)"); 1239 else if (i == 6) 1240 aprint_normal(" (Ultra/133)"); 1241 sep = ","; 1242 printed = 1; 1243 } 1244 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1245 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1246 wdc->UDMA_cap < i) 1247 continue; 1248 drvp->UDMA_mode = i; 1249 drvp->UDMA_cap = i; 1250 drvp->drive_flags |= DRIVE_UDMA; 1251 } 1252 break; 1253 } 1254 } 1255 aprint_normal("\n"); 1256 } 1257 1258 /* Try to guess ATA version here, if it didn't get reported */ 1259 if (drvp->ata_vers == 0) { 1260 if (drvp->drive_flags & DRIVE_UDMA) 1261 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1262 else if (drvp->PIO_cap > 2) 1263 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1264 } 1265 cf_flags = drv_dev->dv_cfdata->cf_flags; 1266 if (cf_flags & ATA_CONFIG_PIO_SET) { 1267 drvp->PIO_mode = 1268 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1269 drvp->drive_flags |= DRIVE_MODE; 1270 } 1271 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1272 /* don't care about DMA modes */ 1273 return; 1274 } 1275 if (cf_flags & ATA_CONFIG_DMA_SET) { 1276 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1277 ATA_CONFIG_DMA_DISABLE) { 1278 drvp->drive_flags &= ~DRIVE_DMA; 1279 } else { 1280 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1281 ATA_CONFIG_DMA_OFF; 1282 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1283 } 1284 } 1285 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1286 /* don't care about UDMA modes */ 1287 return; 1288 } 1289 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1290 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1291 ATA_CONFIG_UDMA_DISABLE) { 1292 drvp->drive_flags &= ~DRIVE_UDMA; 1293 } else { 1294 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1295 ATA_CONFIG_UDMA_OFF; 1296 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1297 } 1298 } 1299 } 1300 1301 /* 1302 * downgrade the transfer mode of a drive after an error. return 1 if 1303 * downgrade was possible, 0 otherwise. 1304 */ 1305 int 1306 wdc_downgrade_mode(drvp) 1307 struct ata_drive_datas *drvp; 1308 { 1309 struct channel_softc *chp = drvp->chnl_softc; 1310 struct device *drv_dev = drvp->drv_softc; 1311 struct wdc_softc *wdc = chp->wdc; 1312 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1313 1314 /* if drive or controller don't know its mode, we can't do much */ 1315 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1316 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1317 return 0; 1318 /* current drive mode was set by a config flag, let it this way */ 1319 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1320 (cf_flags & ATA_CONFIG_DMA_SET) || 1321 (cf_flags & ATA_CONFIG_UDMA_SET)) 1322 return 0; 1323 1324 /* 1325 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1326 * Maybe we didn't properly notice the cable type 1327 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1328 * It helps in some cases. 1329 */ 1330 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1331 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1332 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1333 drv_dev->dv_xname, drvp->UDMA_mode); 1334 } 1335 1336 /* 1337 * If we were using ultra-DMA, don't downgrade to multiword DMA 1338 * if we noticed a CRC error. It has been noticed that CRC errors 1339 * in ultra-DMA lead to silent data corruption in multiword DMA. 1340 * Data corruption is less likely to occur in PIO mode. 1341 */ 1342 else if ((drvp->drive_flags & DRIVE_UDMA) && 1343 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1344 drvp->drive_flags &= ~DRIVE_UDMA; 1345 drvp->drive_flags |= DRIVE_DMA; 1346 drvp->DMA_mode = drvp->DMA_cap; 1347 printf("%s: transfer error, downgrading to DMA mode %d\n", 1348 drv_dev->dv_xname, drvp->DMA_mode); 1349 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1350 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1351 drvp->PIO_mode = drvp->PIO_cap; 1352 printf("%s: transfer error, downgrading to PIO mode %d\n", 1353 drv_dev->dv_xname, drvp->PIO_mode); 1354 } else /* already using PIO, can't downgrade */ 1355 return 0; 1356 1357 wdc->set_modes(chp); 1358 /* reset the channel, which will schedule all drives for setup */ 1359 wdc_reset_channel(drvp); 1360 return 1; 1361 } 1362 1363 int 1364 wdc_exec_command(drvp, wdc_c) 1365 struct ata_drive_datas *drvp; 1366 struct wdc_command *wdc_c; 1367 { 1368 struct channel_softc *chp = drvp->chnl_softc; 1369 struct wdc_xfer *xfer; 1370 int s, ret; 1371 1372 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1373 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1374 DEBUG_FUNCS); 1375 1376 /* set up an xfer and queue. Wait for completion */ 1377 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1378 WDC_NOSLEEP); 1379 if (xfer == NULL) { 1380 return WDC_TRY_AGAIN; 1381 } 1382 1383 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1384 wdc_c->flags |= AT_POLL; 1385 if (wdc_c->flags & AT_POLL) 1386 xfer->c_flags |= C_POLL; 1387 xfer->drive = drvp->drive; 1388 xfer->databuf = wdc_c->data; 1389 xfer->c_bcount = wdc_c->bcount; 1390 xfer->cmd = wdc_c; 1391 xfer->c_start = __wdccommand_start; 1392 xfer->c_intr = __wdccommand_intr; 1393 xfer->c_kill_xfer = __wdccommand_done; 1394 1395 s = splbio(); 1396 wdc_exec_xfer(chp, xfer); 1397 #ifdef DIAGNOSTIC 1398 if ((wdc_c->flags & AT_POLL) != 0 && 1399 (wdc_c->flags & AT_DONE) == 0) 1400 panic("wdc_exec_command: polled command not done"); 1401 #endif 1402 if (wdc_c->flags & AT_DONE) { 1403 ret = WDC_COMPLETE; 1404 } else { 1405 if (wdc_c->flags & AT_WAIT) { 1406 while ((wdc_c->flags & AT_DONE) == 0) { 1407 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1408 } 1409 ret = WDC_COMPLETE; 1410 } else { 1411 ret = WDC_QUEUED; 1412 } 1413 } 1414 splx(s); 1415 return ret; 1416 } 1417 1418 void 1419 __wdccommand_start(chp, xfer) 1420 struct channel_softc *chp; 1421 struct wdc_xfer *xfer; 1422 { 1423 int drive = xfer->drive; 1424 struct wdc_command *wdc_c = xfer->cmd; 1425 1426 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1427 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1428 DEBUG_FUNCS); 1429 1430 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1431 chp->wdc->select(chp,drive); 1432 1433 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1434 WDSD_IBM | (drive << 4)); 1435 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1436 wdc_c->timeout) != 0) { 1437 wdc_c->flags |= AT_TIMEOU; 1438 __wdccommand_done(chp, xfer); 1439 return; 1440 } 1441 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1442 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1443 if ((wdc_c->flags & AT_POLL) == 0) { 1444 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1445 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1446 wdctimeout, chp); 1447 return; 1448 } 1449 /* 1450 * Polled command. Wait for drive ready or drq. Done in intr(). 1451 * Wait for at last 400ns for status bit to be valid. 1452 */ 1453 delay(10); 1454 __wdccommand_intr(chp, xfer, 0); 1455 } 1456 1457 int 1458 __wdccommand_intr(chp, xfer, irq) 1459 struct channel_softc *chp; 1460 struct wdc_xfer *xfer; 1461 int irq; 1462 { 1463 struct wdc_command *wdc_c = xfer->cmd; 1464 int bcount = wdc_c->bcount; 1465 char *data = wdc_c->data; 1466 1467 again: 1468 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1469 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1470 if ((wdc_c->flags & AT_XFDONE) != 0) { 1471 /* 1472 * We have completed a data xfer. The drive should now be 1473 * in its initial state 1474 */ 1475 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1476 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0) != 0) { 1477 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1478 return 0; /* IRQ was not for us */ 1479 wdc_c->flags |= AT_TIMEOU; 1480 __wdccommand_done(chp, xfer); 1481 return 1; 1482 } 1483 wdc_c->flags |= AT_DONE; 1484 __wdccommand_done(chp, xfer); 1485 return 1; 1486 } 1487 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1488 (irq == 0) ? wdc_c->timeout : 0)) { 1489 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1490 return 0; /* IRQ was not for us */ 1491 wdc_c->flags |= AT_TIMEOU; 1492 __wdccommand_done(chp, xfer); 1493 return 1; 1494 } 1495 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1496 chp->wdc->irqack(chp); 1497 if (wdc_c->flags & AT_READ) { 1498 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1499 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1500 0, (u_int32_t*)data, bcount >> 2); 1501 data += bcount & 0xfffffffc; 1502 bcount = bcount & 0x03; 1503 } 1504 if (bcount > 0) 1505 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1506 wd_data, (u_int16_t *)data, bcount >> 1); 1507 /* at this point the drive should be in its initial state */ 1508 wdc_c->flags |= AT_XFDONE; 1509 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1510 wdc_c->r_st_bmask, 100) != 0) 1511 wdc_c->flags |= AT_TIMEOU; 1512 } else if (wdc_c->flags & AT_WRITE) { 1513 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1514 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1515 0, (u_int32_t*)data, bcount >> 2); 1516 data += bcount & 0xfffffffc; 1517 bcount = bcount & 0x03; 1518 } 1519 if (bcount > 0) 1520 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1521 wd_data, (u_int16_t *)data, bcount >> 1); 1522 wdc_c->flags |= AT_XFDONE; 1523 if ((wdc_c->flags & AT_POLL) == 0) { 1524 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1525 callout_reset(&chp->ch_callout, 1526 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1527 return 1; 1528 } else { 1529 goto again; 1530 } 1531 } 1532 __wdccommand_done(chp, xfer); 1533 return 1; 1534 } 1535 1536 void 1537 __wdccommand_done(chp, xfer) 1538 struct channel_softc *chp; 1539 struct wdc_xfer *xfer; 1540 { 1541 struct wdc_command *wdc_c = xfer->cmd; 1542 1543 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1544 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1545 1546 callout_stop(&chp->ch_callout); 1547 1548 if (chp->ch_status & WDCS_DWF) 1549 wdc_c->flags |= AT_DF; 1550 if (chp->ch_status & WDCS_ERR) { 1551 wdc_c->flags |= AT_ERROR; 1552 wdc_c->r_error = chp->ch_error; 1553 } 1554 wdc_c->flags |= AT_DONE; 1555 if ((wdc_c->flags & AT_READREG) != 0 && 1556 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1557 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1558 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1559 wd_sdh); 1560 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1561 wd_cyl_hi) << 8; 1562 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1563 wd_cyl_lo); 1564 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1565 wd_sector); 1566 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1567 wd_seccnt); 1568 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1569 wd_error); 1570 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1571 wd_precomp); 1572 } 1573 wdc_free_xfer(chp, xfer); 1574 if (wdc_c->flags & AT_WAIT) 1575 wakeup(wdc_c); 1576 else if (wdc_c->callback) 1577 wdc_c->callback(wdc_c->callback_arg); 1578 wdcstart(chp); 1579 return; 1580 } 1581 1582 /* 1583 * Send a command. The drive should be ready. 1584 * Assumes interrupts are blocked. 1585 */ 1586 void 1587 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1588 struct channel_softc *chp; 1589 u_int8_t drive; 1590 u_int8_t command; 1591 u_int16_t cylin; 1592 u_int8_t head, sector, count, precomp; 1593 { 1594 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1595 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1596 chp->channel, drive, command, cylin, head, sector, count, precomp), 1597 DEBUG_FUNCS); 1598 1599 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1600 chp->wdc->select(chp,drive); 1601 1602 /* Select drive, head, and addressing mode. */ 1603 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1604 WDSD_IBM | (drive << 4) | head); 1605 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1606 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1607 precomp); 1608 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1609 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1610 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1611 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1612 1613 /* Send command. */ 1614 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1615 return; 1616 } 1617 1618 /* 1619 * Send a 48-bit addressing command. The drive should be ready. 1620 * Assumes interrupts are blocked. 1621 */ 1622 void 1623 wdccommandext(chp, drive, command, blkno, count) 1624 struct channel_softc *chp; 1625 u_int8_t drive; 1626 u_int8_t command; 1627 u_int64_t blkno; 1628 u_int16_t count; 1629 { 1630 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1631 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1632 chp->channel, drive, command, (u_int32_t) blkno, count), 1633 DEBUG_FUNCS); 1634 1635 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1636 chp->wdc->select(chp,drive); 1637 1638 /* Select drive, head, and addressing mode. */ 1639 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1640 (drive << 4) | WDSD_LBA); 1641 1642 /* previous */ 1643 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1644 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1645 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1646 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1647 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1648 1649 /* current */ 1650 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1651 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1652 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1654 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1655 1656 /* Send command. */ 1657 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1658 return; 1659 } 1660 1661 /* 1662 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1663 * tested by the caller. 1664 */ 1665 void 1666 wdccommandshort(chp, drive, command) 1667 struct channel_softc *chp; 1668 int drive; 1669 int command; 1670 { 1671 1672 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1673 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1674 DEBUG_FUNCS); 1675 1676 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1677 chp->wdc->select(chp,drive); 1678 1679 /* Select drive. */ 1680 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1681 WDSD_IBM | (drive << 4)); 1682 1683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1684 } 1685 1686 /* Add a command to the queue and start controller. Must be called at splbio */ 1687 1688 void 1689 wdc_exec_xfer(chp, xfer) 1690 struct channel_softc *chp; 1691 struct wdc_xfer *xfer; 1692 { 1693 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1694 chp->channel, xfer->drive), DEBUG_XFERS); 1695 1696 /* complete xfer setup */ 1697 xfer->chp = chp; 1698 1699 /* 1700 * If we are a polled command, and the list is not empty, 1701 * we are doing a dump. Drop the list to allow the polled command 1702 * to complete, we're going to reboot soon anyway. 1703 */ 1704 if ((xfer->c_flags & C_POLL) != 0 && 1705 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1706 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1707 } 1708 /* insert at the end of command list */ 1709 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1710 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1711 chp->ch_flags), DEBUG_XFERS); 1712 wdcstart(chp); 1713 } 1714 1715 struct wdc_xfer * 1716 wdc_get_xfer(flags) 1717 int flags; 1718 { 1719 struct wdc_xfer *xfer; 1720 int s; 1721 1722 s = splbio(); 1723 xfer = pool_get(&wdc_xfer_pool, 1724 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1725 splx(s); 1726 if (xfer != NULL) { 1727 memset(xfer, 0, sizeof(struct wdc_xfer)); 1728 } 1729 return xfer; 1730 } 1731 1732 void 1733 wdc_free_xfer(chp, xfer) 1734 struct channel_softc *chp; 1735 struct wdc_xfer *xfer; 1736 { 1737 struct wdc_softc *wdc = chp->wdc; 1738 int s; 1739 1740 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1741 (*wdc->free_hw)(chp); 1742 s = splbio(); 1743 chp->ch_flags &= ~WDCF_ACTIVE; 1744 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1745 pool_put(&wdc_xfer_pool, xfer); 1746 splx(s); 1747 } 1748 1749 /* 1750 * Kill off all pending xfers for a channel_softc. 1751 * 1752 * Must be called at splbio(). 1753 */ 1754 void 1755 wdc_kill_pending(chp) 1756 struct channel_softc *chp; 1757 { 1758 struct wdc_xfer *xfer; 1759 1760 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1761 chp = xfer->chp; 1762 (*xfer->c_kill_xfer)(chp, xfer); 1763 } 1764 } 1765 1766 static void 1767 __wdcerror(chp, msg) 1768 struct channel_softc *chp; 1769 char *msg; 1770 { 1771 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1772 1773 if (xfer == NULL) 1774 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1775 msg); 1776 else 1777 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1778 chp->channel, xfer->drive, msg); 1779 } 1780 1781 /* 1782 * the bit bucket 1783 */ 1784 void 1785 wdcbit_bucket(chp, size) 1786 struct channel_softc *chp; 1787 int size; 1788 { 1789 1790 for (; size >= 2; size -= 2) 1791 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1792 if (size) 1793 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1794 } 1795 1796 int 1797 wdc_addref(chp) 1798 struct channel_softc *chp; 1799 { 1800 struct wdc_softc *wdc = chp->wdc; 1801 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1802 int s, error = 0; 1803 1804 s = splbio(); 1805 if (adapt->adapt_refcnt++ == 0 && 1806 adapt->adapt_enable != NULL) { 1807 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1808 if (error) 1809 adapt->adapt_refcnt--; 1810 } 1811 splx(s); 1812 return (error); 1813 } 1814 1815 void 1816 wdc_delref(chp) 1817 struct channel_softc *chp; 1818 { 1819 struct wdc_softc *wdc = chp->wdc; 1820 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1821 int s; 1822 1823 s = splbio(); 1824 if (adapt->adapt_refcnt-- == 1 && 1825 adapt->adapt_enable != NULL) 1826 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1827 splx(s); 1828 } 1829 1830 void 1831 wdc_print_modes(struct channel_softc *chp) 1832 { 1833 int drive; 1834 struct ata_drive_datas *drvp; 1835 1836 for (drive = 0; drive < 2; drive++) { 1837 drvp = &chp->ch_drive[drive]; 1838 if ((drvp->drive_flags & DRIVE) == 0) 1839 continue; 1840 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1841 drvp->drv_softc->dv_xname, 1842 chp->wdc->sc_dev.dv_xname, 1843 chp->channel, drive, drvp->PIO_mode); 1844 if (drvp->drive_flags & DRIVE_DMA) 1845 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1846 if (drvp->drive_flags & DRIVE_UDMA) { 1847 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1848 if (drvp->UDMA_mode == 2) 1849 aprint_normal(" (Ultra/33)"); 1850 else if (drvp->UDMA_mode == 4) 1851 aprint_normal(" (Ultra/66)"); 1852 else if (drvp->UDMA_mode == 5) 1853 aprint_normal(" (Ultra/100)"); 1854 else if (drvp->UDMA_mode == 6) 1855 aprint_normal(" (Ultra/133)"); 1856 } 1857 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1858 aprint_normal(" (using DMA data transfers)"); 1859 aprint_normal("\n"); 1860 } 1861 } 1862
Indexes created Sat Sep 27 22:09:54 GMT 2025