wdc.c revision 1.126
1 /* $NetBSD: wdc.c,v 1.126 2003/09/20 02:19:36 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.126 2003/09/20 02:19:36 enami Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/wdvar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 struct pool wdc_xfer_pool; 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL 136 }; 137 #endif 138 139 static void __wdcerror __P((struct channel_softc*, char *)); 140 static int __wdcwait_reset __P((struct channel_softc *, int)); 141 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 142 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 143 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 144 int wdprint __P((void *, const char *)); 145 void wdc_channel_attach __P((struct channel_softc *)); 146 147 #define DEBUG_INTR 0x01 148 #define DEBUG_XFERS 0x02 149 #define DEBUG_STATUS 0x04 150 #define DEBUG_FUNCS 0x08 151 #define DEBUG_PROBE 0x10 152 #define DEBUG_DETACH 0x20 153 #define DEBUG_DELAY 0x40 154 #ifdef WDCDEBUG 155 int wdcdebug_mask = 0; 156 int wdc_nxfer = 0; 157 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 158 #else 159 #define WDCDEBUG_PRINT(args, level) 160 #endif 161 162 int 163 wdprint(aux, pnp) 164 void *aux; 165 const char *pnp; 166 { 167 struct ata_device *adev = aux; 168 if (pnp) 169 aprint_normal("wd at %s", pnp); 170 aprint_normal(" channel %d drive %d", adev->adev_channel, 171 adev->adev_drv_data->drive); 172 return (UNCONF); 173 } 174 175 /* Test to see controller with at last one attached drive is there. 176 * Returns a bit for each possible drive found (0x01 for drive 0, 177 * 0x02 for drive 1). 178 * Logic: 179 * - If a status register is at 0xff, assume there is no drive here 180 * (ISA has pull-up resistors). Similarly if the status register has 181 * the value we last wrote to the bus (for IDE interfaces without pullups). 182 * If no drive at all -> return. 183 * - reset the controller, wait for it to complete (may take up to 31s !). 184 * If timeout -> return. 185 * - test ATA/ATAPI signatures. If at last one drive found -> return. 186 * - try an ATA command on the master. 187 */ 188 189 int 190 wdcprobe(chp) 191 struct channel_softc *chp; 192 { 193 u_int8_t st0, st1, sc, sn, cl, ch; 194 u_int8_t ret_value = 0x03; 195 u_int8_t drive; 196 197 /* 198 * Sanity check to see if the wdc channel responds at all. 199 */ 200 201 if (chp->wdc == NULL || 202 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 203 204 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 205 chp->wdc->select(chp,0); 206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 207 WDSD_IBM); 208 delay(10); 209 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 210 211 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 212 chp->wdc->select(chp,1); 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM | 0x10); 215 delay(10); 216 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 217 218 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 219 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 220 chp->channel, st0, st1), DEBUG_PROBE); 221 222 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 223 ret_value &= ~0x01; 224 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 225 ret_value &= ~0x02; 226 227 /* Register writability test, drive 0. */ 228 if (ret_value & 0x01) { 229 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 230 chp->wdc->select(chp,0); 231 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 232 WDSD_IBM); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 234 0x01); 235 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 236 wd_cyl_lo) != 0x01) 237 ret_value &= ~0x01; 238 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 239 0x02); 240 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 241 wd_cyl_lo) != 0x02) 242 ret_value &= ~0x01; 243 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 244 0x01); 245 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 246 wd_sector) != 0x01) 247 ret_value &= ~0x01; 248 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 249 0x02); 250 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 251 wd_sector) != 0x02) 252 ret_value &= ~0x01; 253 } 254 255 /* Register writability test, drive 1. */ 256 if (ret_value & 0x02) { 257 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 258 chp->wdc->select(chp,1); 259 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 260 WDSD_IBM | 0x10); 261 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 262 0x01); 263 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 264 wd_cyl_lo) != 0x01) 265 ret_value &= ~0x02; 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 267 0x02); 268 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 269 wd_cyl_lo) != 0x02) 270 ret_value &= ~0x02; 271 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 272 0x01); 273 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 274 wd_sector) != 0x01) 275 ret_value &= ~0x02; 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 277 0x02); 278 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 279 wd_sector) != 0x02) 280 ret_value &= ~0x02; 281 } 282 283 /* Register ghost test. */ 284 if (ret_value == 0x03) { 285 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 286 chp->wdc->select(chp,1); 287 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 288 WDSD_IBM | 0x10); 289 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 0x01); 290 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 291 chp->wdc->select(chp,0); 292 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 293 WDSD_IBM); 294 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 0x02); 295 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 296 chp->wdc->select(chp,1); 297 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 298 WDSD_IBM | 0x10); 299 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector) == 0x02) { 300 printf("ghost detected\n"); 301 ret_value = 0x01; 302 } 303 } 304 305 if (ret_value == 0) 306 return 0; 307 308 } 309 310 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 311 chp->wdc->select(chp,0); 312 /* assert SRST, wait for reset to complete */ 313 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 314 WDSD_IBM); 315 delay(10); 316 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 317 WDCTL_RST | WDCTL_IDS); 318 DELAY(1000); 319 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 320 WDCTL_IDS); 321 delay(1000); 322 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 323 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 324 delay(10); 325 326 ret_value = __wdcwait_reset(chp, ret_value); 327 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 328 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 329 ret_value), DEBUG_PROBE); 330 331 /* if reset failed, there's nothing here */ 332 if (ret_value == 0) 333 return 0; 334 335 /* 336 * Test presence of drives. First test register signatures looking for 337 * ATAPI devices. If it's not an ATAPI and reset said there may be 338 * something here assume it's ATA or OLD. Ghost will be killed later in 339 * attach routine. 340 */ 341 for (drive = 0; drive < 2; drive++) { 342 if ((ret_value & (0x01 << drive)) == 0) 343 continue; 344 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 345 chp->wdc->select(chp,drive); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 347 WDSD_IBM | (drive << 4)); 348 delay(10); 349 /* Save registers contents */ 350 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 351 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 352 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 353 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 354 355 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 356 "cl=0x%x ch=0x%x\n", 357 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 358 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 359 /* 360 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 361 * we get wrong values here, so ignore it. 362 */ 363 if (cl == 0x14 && ch == 0xeb) { 364 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 365 } else { 366 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 367 if (chp->wdc == NULL || 368 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 369 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 370 } 371 } 372 return (ret_value); 373 } 374 375 void 376 wdcattach(self) 377 struct device *self; 378 { 379 struct wdc_softc *wdc = (void *)self; 380 int i; 381 382 for (i = 0; i < wdc->nchannels; i++) 383 wdc_channel_attach(wdc->channels[i]); 384 } 385 386 void 387 wdc_channel_attach(chp) 388 struct channel_softc *chp; 389 { 390 int ctrl_flags, i, error; 391 struct ataparams params; 392 static int inited = 0; 393 394 if (chp->ch_flags & WDCF_DISABLED) 395 return; 396 397 callout_init(&chp->ch_callout); 398 399 if ((error = wdc_addref(chp)) != 0) { 400 aprint_error("%s: unable to enable controller\n", 401 chp->wdc->sc_dev.dv_xname); 402 return; 403 } 404 405 if (wdcprobe(chp) == 0) 406 /* If no drives, abort attach here. */ 407 goto out; 408 409 /* initialise global data */ 410 if (inited == 0) { 411 /* Initialize the wdc_xfer pool. */ 412 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 413 0, 0, "wdcspl", NULL); 414 inited++; 415 } 416 TAILQ_INIT(&chp->ch_queue->sc_xfer); 417 418 for (i = 0; i < 2; i++) { 419 chp->ch_drive[i].chnl_softc = chp; 420 chp->ch_drive[i].drive = i; 421 /* 422 * Init error counter so that an error withing the first xfers 423 * will trigger a downgrade 424 */ 425 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 426 427 /* If controller can't do 16bit flag the drives as 32bit */ 428 if ((chp->wdc->cap & 429 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 430 WDC_CAPABILITY_DATA32) 431 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 432 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 433 continue; 434 435 /* 436 * Wait a bit, some devices are weird just after a reset. 437 * Then issue a IDENTIFY command, to try to detect slave ghost 438 */ 439 delay(5000); 440 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, ¶ms); 441 if (error != CMD_OK) { 442 delay(1000000); 443 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, 444 ¶ms); 445 } 446 if (error == CMD_OK) { 447 /* If IDENTIFY succeded, this is not an OLD ctrl */ 448 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 449 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 450 } else { 451 chp->ch_drive[i].drive_flags &= 452 ~(DRIVE_ATA | DRIVE_ATAPI); 453 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 454 chp->wdc->sc_dev.dv_xname, 455 chp->channel, i, error), DEBUG_PROBE); 456 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 457 continue; 458 /* 459 * Pre-ATA drive ? 460 * Test registers writability (Error register not 461 * writable, but cyllo is), then try an ATA command. 462 */ 463 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 464 chp->wdc->select(chp,i); 465 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 466 WDSD_IBM | (i << 4)); 467 delay(10); 468 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 469 wd_error, 0x58); 470 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 471 wd_cyl_lo, 0xa5); 472 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 473 wd_error == 0x58) || 474 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 475 wd_cyl_lo) != 0xa5) { 476 WDCDEBUG_PRINT(("%s:%d:%d: register " 477 "writability failed\n", 478 chp->wdc->sc_dev.dv_xname, 479 chp->channel, i), DEBUG_PROBE); 480 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 481 } 482 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 483 chp->wdc->select(chp,i); 484 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 485 WDSD_IBM | (i << 4)); 486 delay(100); 487 if (wait_for_ready(chp, 10000) != 0) { 488 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 489 chp->wdc->sc_dev.dv_xname, 490 chp->channel, i), DEBUG_PROBE); 491 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 492 continue; 493 } 494 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 495 wd_command, WDCC_RECAL); 496 if (wait_for_ready(chp, 10000) != 0) { 497 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 498 chp->wdc->sc_dev.dv_xname, 499 chp->channel, i), DEBUG_PROBE); 500 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 501 } 502 } 503 } 504 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 505 506 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 507 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 508 DEBUG_PROBE); 509 510 /* If no drives, abort here */ 511 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 512 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 513 goto out; 514 515 /* 516 * Attach an ATAPI bus, if needed. 517 */ 518 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 519 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 520 #if NATAPIBUS > 0 521 wdc_atapibus_attach(chp); 522 #else 523 /* 524 * Fake the autoconfig "not configured" message 525 */ 526 aprint_normal("atapibus at %s channel %d not configured\n", 527 chp->wdc->sc_dev.dv_xname, chp->channel); 528 chp->atapibus = NULL; 529 #endif 530 } 531 532 for (i = 0; i < 2; i++) { 533 struct ata_device adev; 534 if ((chp->ch_drive[i].drive_flags & 535 (DRIVE_ATA | DRIVE_OLD)) == 0) { 536 continue; 537 } 538 memset(&adev, 0, sizeof(struct ata_device)); 539 adev.adev_bustype = &wdc_ata_bustype; 540 adev.adev_channel = chp->channel; 541 adev.adev_openings = 1; 542 adev.adev_drv_data = &chp->ch_drive[i]; 543 chp->ata_drives[i] = config_found(&chp->wdc->sc_dev, 544 &adev, wdprint); 545 if (chp->ata_drives[i] != NULL) 546 wdc_probe_caps(&chp->ch_drive[i]); 547 } 548 549 /* 550 * reset drive_flags for unnatached devices, reset state for attached 551 * ones 552 */ 553 for (i = 0; i < 2; i++) { 554 if (chp->ch_drive[i].drv_softc == NULL) 555 chp->ch_drive[i].drive_flags = 0; 556 else 557 chp->ch_drive[i].state = 0; 558 } 559 560 /* 561 * Reset channel. The probe, with some combinations of ATA/ATAPI 562 * devices keep it in a mostly working, but strange state (with busy 563 * led on) 564 */ 565 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 566 delay(50); 567 wdcreset(chp, VERBOSE); 568 /* 569 * Read status registers to avoid spurious interrupts. 570 */ 571 for (i = 1; i >= 0; i--) { 572 if (chp->ch_drive[i].drive_flags & DRIVE) { 573 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 574 chp->wdc->select(chp,i); 575 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 576 wd_sdh, WDSD_IBM | (i << 4)); 577 if (wait_for_unbusy(chp, 10000) < 0) 578 aprint_error("%s:%d:%d: device busy\n", 579 chp->wdc->sc_dev.dv_xname, 580 chp->channel, i); 581 } 582 } 583 } 584 585 if (chp->wdc->cap & WDC_CAPABILITY_MODE) 586 chp->wdc->set_modes(chp); 587 wdc_print_modes(chp); 588 589 #if NATARAID > 0 590 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 591 for (i = 0; i < 2; i++) 592 if (chp->ata_drives[i] != NULL) 593 ata_raid_check_component(chp->ata_drives[i]); 594 #endif /* NATARAID > 0 */ 595 596 out: 597 wdc_delref(chp); 598 } 599 600 /* 601 * Call activate routine of underlying devices. 602 */ 603 int 604 wdcactivate(self, act) 605 struct device *self; 606 enum devact act; 607 { 608 struct wdc_softc *wdc = (struct wdc_softc *)self; 609 struct channel_softc *chp; 610 struct device *sc = 0; 611 int s, i, j, error = 0; 612 613 s = splbio(); 614 switch (act) { 615 case DVACT_ACTIVATE: 616 error = EOPNOTSUPP; 617 break; 618 619 case DVACT_DEACTIVATE: 620 for (i = 0; i < wdc->nchannels; i++) { 621 chp = wdc->channels[i]; 622 623 /* 624 * We might call deactivate routine for 625 * the children of atapibus twice (once via 626 * atapibus, once directly), but since 627 * config_deactivate maintains DVF_ACTIVE flag, 628 * it's safe. 629 */ 630 sc = chp->atapibus; 631 if (sc != NULL) { 632 error = config_deactivate(sc); 633 if (error != 0) 634 goto out; 635 } 636 637 for (j = 0; j < 2; j++) { 638 sc = chp->ch_drive[j].drv_softc; 639 WDCDEBUG_PRINT(("wdcactivate: %s:" 640 " deactivating %s\n", wdc->sc_dev.dv_xname, 641 sc == NULL ? "nodrv" : sc->dv_xname), 642 DEBUG_DETACH); 643 if (sc != NULL) { 644 error = config_deactivate(sc); 645 if (error != 0) 646 goto out; 647 } 648 } 649 } 650 break; 651 } 652 653 out: 654 splx(s); 655 656 #ifdef WDCDEBUG 657 if (sc && error != 0) 658 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 659 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 660 #endif 661 return (error); 662 } 663 664 int 665 wdcdetach(self, flags) 666 struct device *self; 667 int flags; 668 { 669 struct wdc_softc *wdc = (struct wdc_softc *)self; 670 struct channel_softc *chp; 671 struct device *sc = 0; 672 int i, j, error = 0; 673 674 for (i = 0; i < wdc->nchannels; i++) { 675 chp = wdc->channels[i]; 676 677 /* 678 * Detach atapibus and its children. 679 */ 680 sc = chp->atapibus; 681 if (sc != NULL) { 682 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 683 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 684 error = config_detach(sc, flags); 685 if (error != 0) 686 goto out; 687 } 688 689 /* 690 * Detach our other children. 691 */ 692 for (j = 0; j < 2; j++) { 693 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 694 continue; 695 sc = chp->ch_drive[j].drv_softc; 696 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 697 wdc->sc_dev.dv_xname, 698 sc == NULL ? "nodrv" : sc->dv_xname), 699 DEBUG_DETACH); 700 if (sc != NULL) { 701 error = config_detach(sc, flags); 702 if (error != 0) 703 goto out; 704 } 705 } 706 707 wdc_kill_pending(chp); 708 } 709 710 out: 711 #ifdef WDCDEBUG 712 if (sc && error != 0) 713 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 714 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 715 #endif 716 return (error); 717 } 718 719 /* 720 * Start I/O on a controller, for the given channel. 721 * The first xfer may be not for our channel if the channel queues 722 * are shared. 723 */ 724 void 725 wdcstart(chp) 726 struct channel_softc *chp; 727 { 728 struct wdc_xfer *xfer; 729 730 #ifdef WDC_DIAGNOSTIC 731 int spl1, spl2; 732 733 spl1 = splbio(); 734 spl2 = splbio(); 735 if (spl2 != spl1) { 736 printf("wdcstart: not at splbio()\n"); 737 panic("wdcstart"); 738 } 739 splx(spl2); 740 splx(spl1); 741 #endif /* WDC_DIAGNOSTIC */ 742 743 /* is there a xfer ? */ 744 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 745 return; 746 747 /* adjust chp, in case we have a shared queue */ 748 chp = xfer->chp; 749 750 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 751 return; /* channel aleady active */ 752 } 753 #ifdef DIAGNOSTIC 754 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 755 panic("wdcstart: channel waiting for irq"); 756 #endif 757 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 758 if (!(*chp->wdc->claim_hw)(chp, 0)) 759 return; 760 761 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 762 chp->channel, xfer->drive), DEBUG_XFERS); 763 chp->ch_flags |= WDCF_ACTIVE; 764 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 765 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 766 chp->ch_drive[xfer->drive].state = 0; 767 } 768 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 769 KASSERT(xfer->c_flags & C_POLL); 770 xfer->c_start(chp, xfer); 771 } 772 773 /* restart an interrupted I/O */ 774 void 775 wdcrestart(v) 776 void *v; 777 { 778 struct channel_softc *chp = v; 779 int s; 780 781 s = splbio(); 782 wdcstart(chp); 783 splx(s); 784 } 785 786 787 /* 788 * Interrupt routine for the controller. Acknowledge the interrupt, check for 789 * errors on the current operation, mark it done if necessary, and start the 790 * next request. Also check for a partially done transfer, and continue with 791 * the next chunk if so. 792 */ 793 int 794 wdcintr(arg) 795 void *arg; 796 { 797 struct channel_softc *chp = arg; 798 struct wdc_xfer *xfer; 799 int ret; 800 801 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 802 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 803 DEBUG_INTR); 804 return (0); 805 } 806 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 807 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 808 /* try to clear the pending interrupt anyway */ 809 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 810 return (0); 811 } 812 813 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 814 xfer = chp->ch_queue->sc_xfer.tqh_first; 815 if (chp->ch_flags & WDCF_DMA_WAIT) { 816 chp->wdc->dma_status = 817 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 818 xfer->drive, 0); 819 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 820 /* IRQ not for us, not detected by DMA engine */ 821 return 0; 822 } 823 chp->ch_flags &= ~WDCF_DMA_WAIT; 824 } 825 chp->ch_flags &= ~WDCF_IRQ_WAIT; 826 ret = xfer->c_intr(chp, xfer, 1); 827 if (ret == 0) /* irq was not for us, still waiting for irq */ 828 chp->ch_flags |= WDCF_IRQ_WAIT; 829 return (ret); 830 } 831 832 /* Put all disk in RESET state */ 833 void 834 wdc_reset_channel(drvp) 835 struct ata_drive_datas *drvp; 836 { 837 struct channel_softc *chp = drvp->chnl_softc; 838 int drive; 839 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 840 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 841 DEBUG_FUNCS); 842 (void) wdcreset(chp, VERBOSE); 843 for (drive = 0; drive < 2; drive++) { 844 chp->ch_drive[drive].state = 0; 845 } 846 } 847 848 int 849 wdcreset(chp, verb) 850 struct channel_softc *chp; 851 int verb; 852 { 853 int drv_mask1, drv_mask2; 854 855 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 856 chp->wdc->select(chp,0); 857 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 858 WDSD_IBM); /* master */ 859 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 860 WDCTL_RST | WDCTL_IDS); 861 delay(1000); 862 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 863 WDCTL_IDS); 864 delay(1000); 865 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 866 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 867 WDCTL_4BIT); 868 869 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 870 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 871 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 872 if (verb && drv_mask2 != drv_mask1) { 873 printf("%s channel %d: reset failed for", 874 chp->wdc->sc_dev.dv_xname, chp->channel); 875 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 876 printf(" drive 0"); 877 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 878 printf(" drive 1"); 879 printf("\n"); 880 } 881 return (drv_mask1 != drv_mask2) ? 1 : 0; 882 } 883 884 static int 885 __wdcwait_reset(chp, drv_mask) 886 struct channel_softc *chp; 887 int drv_mask; 888 { 889 int timeout; 890 u_int8_t st0, st1; 891 #ifdef WDCDEBUG 892 u_int8_t sc0, sn0, cl0, ch0; 893 u_int8_t sc1, sn1, cl1, ch1; 894 #endif 895 /* wait for BSY to deassert */ 896 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 897 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 898 chp->wdc->select(chp,0); 899 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 900 WDSD_IBM); /* master */ 901 delay(10); 902 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 903 #ifdef WDCDEBUG 904 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 905 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 906 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 907 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 908 #endif 909 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 910 chp->wdc->select(chp,1); 911 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 912 WDSD_IBM | 0x10); /* slave */ 913 delay(10); 914 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 915 #ifdef WDCDEBUG 916 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 917 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 918 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 919 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 920 #endif 921 922 if ((drv_mask & 0x01) == 0) { 923 /* no master */ 924 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 925 /* No master, slave is ready, it's done */ 926 goto end; 927 } 928 } else if ((drv_mask & 0x02) == 0) { 929 /* no slave */ 930 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 931 /* No slave, master is ready, it's done */ 932 goto end; 933 } 934 } else { 935 /* Wait for both master and slave to be ready */ 936 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 937 goto end; 938 } 939 } 940 delay(WDCDELAY); 941 } 942 /* Reset timed out. Maybe it's because drv_mask was not right */ 943 if (st0 & WDCS_BSY) 944 drv_mask &= ~0x01; 945 if (st1 & WDCS_BSY) 946 drv_mask &= ~0x02; 947 end: 948 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 949 "cl=0x%x ch=0x%x\n", 950 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 951 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 952 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 953 "cl=0x%x ch=0x%x\n", 954 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 955 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 956 957 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 958 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 959 st0, st1), DEBUG_PROBE); 960 961 return drv_mask; 962 } 963 964 /* 965 * Wait for a drive to be !BSY, and have mask in its status register. 966 * return -1 for a timeout after "timeout" ms. 967 */ 968 int 969 wdcwait(chp, mask, bits, timeout) 970 struct channel_softc *chp; 971 int mask, bits, timeout; 972 { 973 u_char status; 974 int time = 0; 975 976 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 977 :"none", chp->channel), DEBUG_STATUS); 978 chp->ch_error = 0; 979 980 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 981 982 for (;;) { 983 chp->ch_status = status = 984 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 985 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 986 break; 987 if (++time > timeout) { 988 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 989 "status %x error %x (mask 0x%x bits 0x%x)\n", 990 time, status, 991 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 992 wd_error), mask, bits), 993 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 994 return -1; 995 } 996 delay(WDCDELAY); 997 } 998 #ifdef WDCDEBUG 999 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1000 printf("wdcwait: did busy-wait, time=%d\n", time); 1001 #endif 1002 if (status & WDCS_ERR) 1003 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1004 wd_error); 1005 #ifdef WDCNDELAY_DEBUG 1006 /* After autoconfig, there should be no long delays. */ 1007 if (!cold && time > WDCNDELAY_DEBUG) { 1008 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1009 if (xfer == NULL) 1010 printf("%s channel %d: warning: busy-wait took %dus\n", 1011 chp->wdc->sc_dev.dv_xname, chp->channel, 1012 WDCDELAY * time); 1013 else 1014 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1015 chp->wdc->sc_dev.dv_xname, chp->channel, 1016 xfer->drive, 1017 WDCDELAY * time); 1018 } 1019 #endif 1020 return 0; 1021 } 1022 1023 /* 1024 * Busy-wait for DMA to complete 1025 */ 1026 int 1027 wdc_dmawait(chp, xfer, timeout) 1028 struct channel_softc *chp; 1029 struct wdc_xfer *xfer; 1030 int timeout; 1031 { 1032 int time; 1033 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1034 chp->wdc->dma_status = 1035 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1036 chp->channel, xfer->drive, 0); 1037 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1038 return 0; 1039 delay(WDCDELAY); 1040 } 1041 /* timeout, force a DMA halt */ 1042 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1043 chp->channel, xfer->drive, 1); 1044 return 1; 1045 } 1046 1047 void 1048 wdctimeout(arg) 1049 void *arg; 1050 { 1051 struct channel_softc *chp = (struct channel_softc *)arg; 1052 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1053 int s; 1054 1055 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1056 1057 s = splbio(); 1058 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1059 __wdcerror(chp, "lost interrupt"); 1060 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1061 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1062 xfer->c_bcount, 1063 xfer->c_skip); 1064 if (chp->ch_flags & WDCF_DMA_WAIT) { 1065 chp->wdc->dma_status = 1066 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1067 chp->channel, xfer->drive, 1); 1068 chp->ch_flags &= ~WDCF_DMA_WAIT; 1069 } 1070 /* 1071 * Call the interrupt routine. If we just missed an interrupt, 1072 * it will do what's needed. Else, it will take the needed 1073 * action (reset the device). 1074 * Before that we need to reinstall the timeout callback, 1075 * in case it will miss another irq while in this transfer 1076 * We arbitray chose it to be 1s 1077 */ 1078 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1079 xfer->c_flags |= C_TIMEOU; 1080 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1081 xfer->c_intr(chp, xfer, 1); 1082 } else 1083 __wdcerror(chp, "missing untimeout"); 1084 splx(s); 1085 } 1086 1087 /* 1088 * Probe drive's capabilites, for use by the controller later 1089 * Assumes drvp points to an existing drive. 1090 * XXX this should be a controller-indep function 1091 */ 1092 void 1093 wdc_probe_caps(drvp) 1094 struct ata_drive_datas *drvp; 1095 { 1096 struct ataparams params, params2; 1097 struct channel_softc *chp = drvp->chnl_softc; 1098 struct device *drv_dev = drvp->drv_softc; 1099 struct wdc_softc *wdc = chp->wdc; 1100 int i, printed; 1101 char *sep = ""; 1102 int cf_flags; 1103 1104 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1105 /* IDENTIFY failed. Can't tell more about the device */ 1106 return; 1107 } 1108 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1109 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1110 /* 1111 * Controller claims 16 and 32 bit transfers. 1112 * Re-do an IDENTIFY with 32-bit transfers, 1113 * and compare results. 1114 */ 1115 drvp->drive_flags |= DRIVE_CAP32; 1116 ata_get_params(drvp, AT_WAIT, ¶ms2); 1117 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1118 /* Not good. fall back to 16bits */ 1119 drvp->drive_flags &= ~DRIVE_CAP32; 1120 } else { 1121 aprint_normal("%s: 32-bit data port\n", 1122 drv_dev->dv_xname); 1123 } 1124 } 1125 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1126 if (params.atap_ata_major > 0x01 && 1127 params.atap_ata_major != 0xffff) { 1128 for (i = 14; i > 0; i--) { 1129 if (params.atap_ata_major & (1 << i)) { 1130 aprint_normal("%s: ATA version %d\n", 1131 drv_dev->dv_xname, i); 1132 drvp->ata_vers = i; 1133 break; 1134 } 1135 } 1136 } 1137 #endif 1138 1139 /* An ATAPI device is at last PIO mode 3 */ 1140 if (drvp->drive_flags & DRIVE_ATAPI) 1141 drvp->PIO_mode = 3; 1142 1143 /* 1144 * It's not in the specs, but it seems that some drive 1145 * returns 0xffff in atap_extensions when this field is invalid 1146 */ 1147 if (params.atap_extensions != 0xffff && 1148 (params.atap_extensions & WDC_EXT_MODES)) { 1149 printed = 0; 1150 /* 1151 * XXX some drives report something wrong here (they claim to 1152 * support PIO mode 8 !). As mode is coded on 3 bits in 1153 * SET FEATURE, limit it to 7 (so limit i to 4). 1154 * If higher mode than 7 is found, abort. 1155 */ 1156 for (i = 7; i >= 0; i--) { 1157 if ((params.atap_piomode_supp & (1 << i)) == 0) 1158 continue; 1159 if (i > 4) 1160 return; 1161 /* 1162 * See if mode is accepted. 1163 * If the controller can't set its PIO mode, 1164 * assume the defaults are good, so don't try 1165 * to set it 1166 */ 1167 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1168 if (ata_set_mode(drvp, 0x08 | (i + 3), 1169 AT_WAIT) != CMD_OK) 1170 continue; 1171 if (!printed) { 1172 aprint_normal("%s: drive supports PIO mode %d", 1173 drv_dev->dv_xname, i + 3); 1174 sep = ","; 1175 printed = 1; 1176 } 1177 /* 1178 * If controller's driver can't set its PIO mode, 1179 * get the highter one for the drive. 1180 */ 1181 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1182 wdc->PIO_cap >= i + 3) { 1183 drvp->PIO_mode = i + 3; 1184 drvp->PIO_cap = i + 3; 1185 break; 1186 } 1187 } 1188 if (!printed) { 1189 /* 1190 * We didn't find a valid PIO mode. 1191 * Assume the values returned for DMA are buggy too 1192 */ 1193 return; 1194 } 1195 drvp->drive_flags |= DRIVE_MODE; 1196 printed = 0; 1197 for (i = 7; i >= 0; i--) { 1198 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1199 continue; 1200 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1201 (wdc->cap & WDC_CAPABILITY_MODE)) 1202 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1203 != CMD_OK) 1204 continue; 1205 if (!printed) { 1206 aprint_normal("%s DMA mode %d", sep, i); 1207 sep = ","; 1208 printed = 1; 1209 } 1210 if (wdc->cap & WDC_CAPABILITY_DMA) { 1211 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1212 wdc->DMA_cap < i) 1213 continue; 1214 drvp->DMA_mode = i; 1215 drvp->DMA_cap = i; 1216 drvp->drive_flags |= DRIVE_DMA; 1217 } 1218 break; 1219 } 1220 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1221 printed = 0; 1222 for (i = 7; i >= 0; i--) { 1223 if ((params.atap_udmamode_supp & (1 << i)) 1224 == 0) 1225 continue; 1226 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1227 (wdc->cap & WDC_CAPABILITY_UDMA)) 1228 if (ata_set_mode(drvp, 0x40 | i, 1229 AT_WAIT) != CMD_OK) 1230 continue; 1231 if (!printed) { 1232 aprint_normal("%s Ultra-DMA mode %d", 1233 sep, i); 1234 if (i == 2) 1235 aprint_normal(" (Ultra/33)"); 1236 else if (i == 4) 1237 aprint_normal(" (Ultra/66)"); 1238 else if (i == 5) 1239 aprint_normal(" (Ultra/100)"); 1240 else if (i == 6) 1241 aprint_normal(" (Ultra/133)"); 1242 sep = ","; 1243 printed = 1; 1244 } 1245 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1246 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1247 wdc->UDMA_cap < i) 1248 continue; 1249 drvp->UDMA_mode = i; 1250 drvp->UDMA_cap = i; 1251 drvp->drive_flags |= DRIVE_UDMA; 1252 } 1253 break; 1254 } 1255 } 1256 aprint_normal("\n"); 1257 } 1258 1259 /* Try to guess ATA version here, if it didn't get reported */ 1260 if (drvp->ata_vers == 0) { 1261 if (drvp->drive_flags & DRIVE_UDMA) 1262 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1263 else if (drvp->PIO_cap > 2) 1264 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1265 } 1266 cf_flags = drv_dev->dv_cfdata->cf_flags; 1267 if (cf_flags & ATA_CONFIG_PIO_SET) { 1268 drvp->PIO_mode = 1269 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1270 drvp->drive_flags |= DRIVE_MODE; 1271 } 1272 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1273 /* don't care about DMA modes */ 1274 return; 1275 } 1276 if (cf_flags & ATA_CONFIG_DMA_SET) { 1277 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1278 ATA_CONFIG_DMA_DISABLE) { 1279 drvp->drive_flags &= ~DRIVE_DMA; 1280 } else { 1281 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1282 ATA_CONFIG_DMA_OFF; 1283 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1284 } 1285 } 1286 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1287 /* don't care about UDMA modes */ 1288 return; 1289 } 1290 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1291 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1292 ATA_CONFIG_UDMA_DISABLE) { 1293 drvp->drive_flags &= ~DRIVE_UDMA; 1294 } else { 1295 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1296 ATA_CONFIG_UDMA_OFF; 1297 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1298 } 1299 } 1300 } 1301 1302 /* 1303 * downgrade the transfer mode of a drive after an error. return 1 if 1304 * downgrade was possible, 0 otherwise. 1305 */ 1306 int 1307 wdc_downgrade_mode(drvp) 1308 struct ata_drive_datas *drvp; 1309 { 1310 struct channel_softc *chp = drvp->chnl_softc; 1311 struct device *drv_dev = drvp->drv_softc; 1312 struct wdc_softc *wdc = chp->wdc; 1313 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1314 1315 /* if drive or controller don't know its mode, we can't do much */ 1316 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1317 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1318 return 0; 1319 /* current drive mode was set by a config flag, let it this way */ 1320 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1321 (cf_flags & ATA_CONFIG_DMA_SET) || 1322 (cf_flags & ATA_CONFIG_UDMA_SET)) 1323 return 0; 1324 1325 /* 1326 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1327 * Maybe we didn't properly notice the cable type 1328 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1329 * It helps in some cases. 1330 */ 1331 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1332 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1333 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1334 drv_dev->dv_xname, drvp->UDMA_mode); 1335 } 1336 1337 /* 1338 * If we were using ultra-DMA, don't downgrade to multiword DMA 1339 * if we noticed a CRC error. It has been noticed that CRC errors 1340 * in ultra-DMA lead to silent data corruption in multiword DMA. 1341 * Data corruption is less likely to occur in PIO mode. 1342 */ 1343 else if ((drvp->drive_flags & DRIVE_UDMA) && 1344 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1345 drvp->drive_flags &= ~DRIVE_UDMA; 1346 drvp->drive_flags |= DRIVE_DMA; 1347 drvp->DMA_mode = drvp->DMA_cap; 1348 printf("%s: transfer error, downgrading to DMA mode %d\n", 1349 drv_dev->dv_xname, drvp->DMA_mode); 1350 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1351 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1352 drvp->PIO_mode = drvp->PIO_cap; 1353 printf("%s: transfer error, downgrading to PIO mode %d\n", 1354 drv_dev->dv_xname, drvp->PIO_mode); 1355 } else /* already using PIO, can't downgrade */ 1356 return 0; 1357 1358 wdc->set_modes(chp); 1359 /* reset the channel, which will schedule all drives for setup */ 1360 wdc_reset_channel(drvp); 1361 return 1; 1362 } 1363 1364 int 1365 wdc_exec_command(drvp, wdc_c) 1366 struct ata_drive_datas *drvp; 1367 struct wdc_command *wdc_c; 1368 { 1369 struct channel_softc *chp = drvp->chnl_softc; 1370 struct wdc_xfer *xfer; 1371 int s, ret; 1372 1373 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1374 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1375 DEBUG_FUNCS); 1376 1377 /* set up an xfer and queue. Wait for completion */ 1378 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1379 WDC_NOSLEEP); 1380 if (xfer == NULL) { 1381 return WDC_TRY_AGAIN; 1382 } 1383 1384 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1385 wdc_c->flags |= AT_POLL; 1386 if (wdc_c->flags & AT_POLL) 1387 xfer->c_flags |= C_POLL; 1388 xfer->drive = drvp->drive; 1389 xfer->databuf = wdc_c->data; 1390 xfer->c_bcount = wdc_c->bcount; 1391 xfer->cmd = wdc_c; 1392 xfer->c_start = __wdccommand_start; 1393 xfer->c_intr = __wdccommand_intr; 1394 xfer->c_kill_xfer = __wdccommand_done; 1395 1396 s = splbio(); 1397 wdc_exec_xfer(chp, xfer); 1398 #ifdef DIAGNOSTIC 1399 if ((wdc_c->flags & AT_POLL) != 0 && 1400 (wdc_c->flags & AT_DONE) == 0) 1401 panic("wdc_exec_command: polled command not done"); 1402 #endif 1403 if (wdc_c->flags & AT_DONE) { 1404 ret = WDC_COMPLETE; 1405 } else { 1406 if (wdc_c->flags & AT_WAIT) { 1407 while ((wdc_c->flags & AT_DONE) == 0) { 1408 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1409 } 1410 ret = WDC_COMPLETE; 1411 } else { 1412 ret = WDC_QUEUED; 1413 } 1414 } 1415 splx(s); 1416 return ret; 1417 } 1418 1419 void 1420 __wdccommand_start(chp, xfer) 1421 struct channel_softc *chp; 1422 struct wdc_xfer *xfer; 1423 { 1424 int drive = xfer->drive; 1425 struct wdc_command *wdc_c = xfer->cmd; 1426 1427 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1428 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1429 DEBUG_FUNCS); 1430 1431 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1432 chp->wdc->select(chp,drive); 1433 1434 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1435 WDSD_IBM | (drive << 4)); 1436 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1437 wdc_c->timeout) != 0) { 1438 wdc_c->flags |= AT_TIMEOU; 1439 __wdccommand_done(chp, xfer); 1440 return; 1441 } 1442 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1443 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1444 if ((wdc_c->flags & AT_POLL) == 0) { 1445 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1446 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1447 wdctimeout, chp); 1448 return; 1449 } 1450 /* 1451 * Polled command. Wait for drive ready or drq. Done in intr(). 1452 * Wait for at last 400ns for status bit to be valid. 1453 */ 1454 delay(10); 1455 __wdccommand_intr(chp, xfer, 0); 1456 } 1457 1458 int 1459 __wdccommand_intr(chp, xfer, irq) 1460 struct channel_softc *chp; 1461 struct wdc_xfer *xfer; 1462 int irq; 1463 { 1464 struct wdc_command *wdc_c = xfer->cmd; 1465 int bcount = wdc_c->bcount; 1466 char *data = wdc_c->data; 1467 1468 again: 1469 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1470 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1471 if ((wdc_c->flags & AT_XFDONE) != 0) { 1472 /* 1473 * We have completed a data xfer. The drive should now be 1474 * in its initial state 1475 */ 1476 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1477 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0) != 0) { 1478 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1479 return 0; /* IRQ was not for us */ 1480 wdc_c->flags |= AT_TIMEOU; 1481 __wdccommand_done(chp, xfer); 1482 return 1; 1483 } 1484 wdc_c->flags |= AT_DONE; 1485 __wdccommand_done(chp, xfer); 1486 return 1; 1487 } 1488 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1489 (irq == 0) ? wdc_c->timeout : 0)) { 1490 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1491 return 0; /* IRQ was not for us */ 1492 wdc_c->flags |= AT_TIMEOU; 1493 __wdccommand_done(chp, xfer); 1494 return 1; 1495 } 1496 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1497 chp->wdc->irqack(chp); 1498 if (wdc_c->flags & AT_READ) { 1499 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1500 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1501 0, (u_int32_t*)data, bcount >> 2); 1502 data += bcount & 0xfffffffc; 1503 bcount = bcount & 0x03; 1504 } 1505 if (bcount > 0) 1506 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1507 wd_data, (u_int16_t *)data, bcount >> 1); 1508 /* at this point the drive should be in its initial state */ 1509 wdc_c->flags |= AT_XFDONE; 1510 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1511 wdc_c->r_st_bmask, 100) != 0) 1512 wdc_c->flags |= AT_TIMEOU; 1513 } else if (wdc_c->flags & AT_WRITE) { 1514 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1515 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1516 0, (u_int32_t*)data, bcount >> 2); 1517 data += bcount & 0xfffffffc; 1518 bcount = bcount & 0x03; 1519 } 1520 if (bcount > 0) 1521 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1522 wd_data, (u_int16_t *)data, bcount >> 1); 1523 wdc_c->flags |= AT_XFDONE; 1524 if ((wdc_c->flags & AT_POLL) == 0) { 1525 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1526 callout_reset(&chp->ch_callout, 1527 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1528 return 1; 1529 } else { 1530 goto again; 1531 } 1532 } 1533 __wdccommand_done(chp, xfer); 1534 return 1; 1535 } 1536 1537 void 1538 __wdccommand_done(chp, xfer) 1539 struct channel_softc *chp; 1540 struct wdc_xfer *xfer; 1541 { 1542 struct wdc_command *wdc_c = xfer->cmd; 1543 1544 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1545 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1546 1547 callout_stop(&chp->ch_callout); 1548 1549 if (chp->ch_status & WDCS_DWF) 1550 wdc_c->flags |= AT_DF; 1551 if (chp->ch_status & WDCS_ERR) { 1552 wdc_c->flags |= AT_ERROR; 1553 wdc_c->r_error = chp->ch_error; 1554 } 1555 wdc_c->flags |= AT_DONE; 1556 if ((wdc_c->flags & AT_READREG) != 0 && 1557 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1558 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1559 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1560 wd_sdh); 1561 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1562 wd_cyl_hi) << 8; 1563 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1564 wd_cyl_lo); 1565 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1566 wd_sector); 1567 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1568 wd_seccnt); 1569 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1570 wd_error); 1571 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1572 wd_precomp); 1573 } 1574 wdc_free_xfer(chp, xfer); 1575 if (wdc_c->flags & AT_WAIT) 1576 wakeup(wdc_c); 1577 else if (wdc_c->callback) 1578 wdc_c->callback(wdc_c->callback_arg); 1579 wdcstart(chp); 1580 return; 1581 } 1582 1583 /* 1584 * Send a command. The drive should be ready. 1585 * Assumes interrupts are blocked. 1586 */ 1587 void 1588 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1589 struct channel_softc *chp; 1590 u_int8_t drive; 1591 u_int8_t command; 1592 u_int16_t cylin; 1593 u_int8_t head, sector, count, precomp; 1594 { 1595 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1596 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1597 chp->channel, drive, command, cylin, head, sector, count, precomp), 1598 DEBUG_FUNCS); 1599 1600 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1601 chp->wdc->select(chp,drive); 1602 1603 /* Select drive, head, and addressing mode. */ 1604 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1605 WDSD_IBM | (drive << 4) | head); 1606 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1607 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1608 precomp); 1609 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1610 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1611 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1612 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1613 1614 /* Send command. */ 1615 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1616 return; 1617 } 1618 1619 /* 1620 * Send a 48-bit addressing command. The drive should be ready. 1621 * Assumes interrupts are blocked. 1622 */ 1623 void 1624 wdccommandext(chp, drive, command, blkno, count) 1625 struct channel_softc *chp; 1626 u_int8_t drive; 1627 u_int8_t command; 1628 u_int64_t blkno; 1629 u_int16_t count; 1630 { 1631 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1632 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1633 chp->channel, drive, command, (u_int32_t) blkno, count), 1634 DEBUG_FUNCS); 1635 1636 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1637 chp->wdc->select(chp,drive); 1638 1639 /* Select drive, head, and addressing mode. */ 1640 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1641 (drive << 4) | WDSD_LBA); 1642 1643 /* previous */ 1644 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1645 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1646 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1647 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1648 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1649 1650 /* current */ 1651 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1652 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1654 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1655 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1656 1657 /* Send command. */ 1658 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1659 return; 1660 } 1661 1662 /* 1663 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1664 * tested by the caller. 1665 */ 1666 void 1667 wdccommandshort(chp, drive, command) 1668 struct channel_softc *chp; 1669 int drive; 1670 int command; 1671 { 1672 1673 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1674 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1675 DEBUG_FUNCS); 1676 1677 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1678 chp->wdc->select(chp,drive); 1679 1680 /* Select drive. */ 1681 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1682 WDSD_IBM | (drive << 4)); 1683 1684 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1685 } 1686 1687 /* Add a command to the queue and start controller. Must be called at splbio */ 1688 1689 void 1690 wdc_exec_xfer(chp, xfer) 1691 struct channel_softc *chp; 1692 struct wdc_xfer *xfer; 1693 { 1694 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1695 chp->channel, xfer->drive), DEBUG_XFERS); 1696 1697 /* complete xfer setup */ 1698 xfer->chp = chp; 1699 1700 /* 1701 * If we are a polled command, and the list is not empty, 1702 * we are doing a dump. Drop the list to allow the polled command 1703 * to complete, we're going to reboot soon anyway. 1704 */ 1705 if ((xfer->c_flags & C_POLL) != 0 && 1706 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1707 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1708 } 1709 /* insert at the end of command list */ 1710 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1711 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1712 chp->ch_flags), DEBUG_XFERS); 1713 wdcstart(chp); 1714 } 1715 1716 struct wdc_xfer * 1717 wdc_get_xfer(flags) 1718 int flags; 1719 { 1720 struct wdc_xfer *xfer; 1721 int s; 1722 1723 s = splbio(); 1724 xfer = pool_get(&wdc_xfer_pool, 1725 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1726 splx(s); 1727 if (xfer != NULL) { 1728 memset(xfer, 0, sizeof(struct wdc_xfer)); 1729 } 1730 return xfer; 1731 } 1732 1733 void 1734 wdc_free_xfer(chp, xfer) 1735 struct channel_softc *chp; 1736 struct wdc_xfer *xfer; 1737 { 1738 struct wdc_softc *wdc = chp->wdc; 1739 int s; 1740 1741 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1742 (*wdc->free_hw)(chp); 1743 s = splbio(); 1744 chp->ch_flags &= ~WDCF_ACTIVE; 1745 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1746 pool_put(&wdc_xfer_pool, xfer); 1747 splx(s); 1748 } 1749 1750 /* 1751 * Kill off all pending xfers for a channel_softc. 1752 * 1753 * Must be called at splbio(). 1754 */ 1755 void 1756 wdc_kill_pending(chp) 1757 struct channel_softc *chp; 1758 { 1759 struct wdc_xfer *xfer; 1760 1761 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1762 chp = xfer->chp; 1763 (*xfer->c_kill_xfer)(chp, xfer); 1764 } 1765 } 1766 1767 static void 1768 __wdcerror(chp, msg) 1769 struct channel_softc *chp; 1770 char *msg; 1771 { 1772 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1773 1774 if (xfer == NULL) 1775 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1776 msg); 1777 else 1778 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1779 chp->channel, xfer->drive, msg); 1780 } 1781 1782 /* 1783 * the bit bucket 1784 */ 1785 void 1786 wdcbit_bucket(chp, size) 1787 struct channel_softc *chp; 1788 int size; 1789 { 1790 1791 for (; size >= 2; size -= 2) 1792 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1793 if (size) 1794 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1795 } 1796 1797 int 1798 wdc_addref(chp) 1799 struct channel_softc *chp; 1800 { 1801 struct wdc_softc *wdc = chp->wdc; 1802 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1803 int s, error = 0; 1804 1805 s = splbio(); 1806 if (adapt->adapt_refcnt++ == 0 && 1807 adapt->adapt_enable != NULL) { 1808 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1809 if (error) 1810 adapt->adapt_refcnt--; 1811 } 1812 splx(s); 1813 return (error); 1814 } 1815 1816 void 1817 wdc_delref(chp) 1818 struct channel_softc *chp; 1819 { 1820 struct wdc_softc *wdc = chp->wdc; 1821 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1822 int s; 1823 1824 s = splbio(); 1825 if (adapt->adapt_refcnt-- == 1 && 1826 adapt->adapt_enable != NULL) 1827 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1828 splx(s); 1829 } 1830 1831 void 1832 wdc_print_modes(struct channel_softc *chp) 1833 { 1834 int drive; 1835 struct ata_drive_datas *drvp; 1836 1837 for (drive = 0; drive < 2; drive++) { 1838 drvp = &chp->ch_drive[drive]; 1839 if ((drvp->drive_flags & DRIVE) == 0) 1840 continue; 1841 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1842 drvp->drv_softc->dv_xname, 1843 chp->wdc->sc_dev.dv_xname, 1844 chp->channel, drive, drvp->PIO_mode); 1845 if (drvp->drive_flags & DRIVE_DMA) 1846 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1847 if (drvp->drive_flags & DRIVE_UDMA) { 1848 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1849 if (drvp->UDMA_mode == 2) 1850 aprint_normal(" (Ultra/33)"); 1851 else if (drvp->UDMA_mode == 4) 1852 aprint_normal(" (Ultra/66)"); 1853 else if (drvp->UDMA_mode == 5) 1854 aprint_normal(" (Ultra/100)"); 1855 else if (drvp->UDMA_mode == 6) 1856 aprint_normal(" (Ultra/133)"); 1857 } 1858 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1859 aprint_normal(" (using DMA data transfers)"); 1860 aprint_normal("\n"); 1861 } 1862 } 1863
Indexes created Thu Sep 25 16:09:42 GMT 2025