wdc.c revision 1.132
1 /* $NetBSD: wdc.c,v 1.132 2003/09/23 16:27:10 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.132 2003/09/23 16:27:10 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/wdvar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 struct pool wdc_xfer_pool; 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL 136 }; 137 #endif 138 139 static void __wdcerror __P((struct channel_softc*, char *)); 140 static int __wdcwait_reset __P((struct channel_softc *, int)); 141 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 142 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 143 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 144 int wdprint __P((void *, const char *)); 145 void wdc_channel_attach __P((struct channel_softc *)); 146 147 #define DEBUG_INTR 0x01 148 #define DEBUG_XFERS 0x02 149 #define DEBUG_STATUS 0x04 150 #define DEBUG_FUNCS 0x08 151 #define DEBUG_PROBE 0x10 152 #define DEBUG_DETACH 0x20 153 #define DEBUG_DELAY 0x40 154 #ifdef WDCDEBUG 155 int wdcdebug_mask = 0; 156 int wdc_nxfer = 0; 157 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 158 #else 159 #define WDCDEBUG_PRINT(args, level) 160 #endif 161 162 int 163 wdprint(aux, pnp) 164 void *aux; 165 const char *pnp; 166 { 167 struct ata_device *adev = aux; 168 if (pnp) 169 aprint_normal("wd at %s", pnp); 170 aprint_normal(" channel %d drive %d", adev->adev_channel, 171 adev->adev_drv_data->drive); 172 return (UNCONF); 173 } 174 175 /* Test to see controller with at last one attached drive is there. 176 * Returns a bit for each possible drive found (0x01 for drive 0, 177 * 0x02 for drive 1). 178 * Logic: 179 * - If a status register is at 0xff, assume there is no drive here 180 * (ISA has pull-up resistors). Similarly if the status register has 181 * the value we last wrote to the bus (for IDE interfaces without pullups). 182 * If no drive at all -> return. 183 * - reset the controller, wait for it to complete (may take up to 31s !). 184 * If timeout -> return. 185 * - test ATA/ATAPI signatures. If at last one drive found -> return. 186 * - try an ATA command on the master. 187 */ 188 189 int 190 wdcprobe(chp) 191 struct channel_softc *chp; 192 { 193 u_int8_t st0, st1, sc, sn, cl, ch; 194 u_int8_t ret_value = 0x03; 195 u_int8_t drive; 196 197 /* 198 * Sanity check to see if the wdc channel responds at all. 199 */ 200 201 if (chp->wdc == NULL || 202 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 203 204 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 205 chp->wdc->select(chp,0); 206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 207 WDSD_IBM); 208 delay(10); /* 400ns delay */ 209 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 210 211 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 212 chp->wdc->select(chp,1); 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM | 0x10); 215 delay(10); /* 400ns delay */ 216 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 217 218 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 219 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 220 chp->channel, st0, st1), DEBUG_PROBE); 221 222 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 223 ret_value &= ~0x01; 224 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 225 ret_value &= ~0x02; 226 227 /* Register writability test, drive 0. */ 228 if (ret_value & 0x01) { 229 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 230 chp->wdc->select(chp,0); 231 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 232 WDSD_IBM); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 234 0x02); 235 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 236 wd_cyl_lo) != 0x02) 237 ret_value &= ~0x01; 238 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 239 0x01); 240 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 241 wd_cyl_lo) != 0x01) 242 ret_value &= ~0x01; 243 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 244 0x01); 245 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 246 wd_sector) != 0x01) 247 ret_value &= ~0x01; 248 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 249 0x02); 250 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 251 wd_sector) != 0x02) 252 ret_value &= ~0x01; 253 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 254 wd_cyl_lo) != 0x01) 255 ret_value &= ~0x01; 256 } 257 258 /* Register writability test, drive 1. */ 259 if (ret_value & 0x02) { 260 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 261 chp->wdc->select(chp,1); 262 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 263 WDSD_IBM | 0x10); 264 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 265 0x02); 266 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 267 wd_cyl_lo) != 0x02) 268 ret_value &= ~0x02; 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 270 0x01); 271 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 272 wd_cyl_lo) != 0x01) 273 ret_value &= ~0x02; 274 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 275 0x01); 276 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 277 wd_sector) != 0x01) 278 ret_value &= ~0x02; 279 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 280 0x02); 281 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 282 wd_sector) != 0x02) 283 ret_value &= ~0x02; 284 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 285 wd_cyl_lo) != 0x01) 286 ret_value &= ~0x02; 287 } 288 289 if (ret_value == 0) 290 return 0; 291 292 } 293 294 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 295 chp->wdc->select(chp,0); 296 /* assert SRST, wait for reset to complete */ 297 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 298 WDSD_IBM); 299 delay(10); /* 400ns delay */ 300 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 301 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 302 delay(2000); 303 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 304 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 305 delay(10); /* 400ns delay */ 306 307 ret_value = __wdcwait_reset(chp, ret_value); 308 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 309 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 310 ret_value), DEBUG_PROBE); 311 312 /* if reset failed, there's nothing here */ 313 if (ret_value == 0) 314 return 0; 315 316 /* 317 * Test presence of drives. First test register signatures looking for 318 * ATAPI devices. If it's not an ATAPI and reset said there may be 319 * something here assume it's ATA or OLD. Ghost will be killed later in 320 * attach routine. 321 */ 322 for (drive = 0; drive < 2; drive++) { 323 if ((ret_value & (0x01 << drive)) == 0) 324 continue; 325 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 326 chp->wdc->select(chp,drive); 327 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 328 WDSD_IBM | (drive << 4)); 329 delay(10); /* 400ns delay */ 330 /* Save registers contents */ 331 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 332 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 333 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 334 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 335 336 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 337 "cl=0x%x ch=0x%x\n", 338 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 339 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 340 /* 341 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 342 * we get wrong values here, so ignore it. 343 */ 344 if (cl == 0x14 && ch == 0xeb) { 345 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 346 } else { 347 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 348 if (chp->wdc == NULL || 349 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 350 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 351 } 352 } 353 return (ret_value); 354 } 355 356 void 357 wdcattach(self) 358 struct device *self; 359 { 360 struct wdc_softc *wdc = (void *)self; 361 int i; 362 363 for (i = 0; i < wdc->nchannels; i++) 364 wdc_channel_attach(wdc->channels[i]); 365 } 366 367 void 368 wdc_channel_attach(chp) 369 struct channel_softc *chp; 370 { 371 int ctrl_flags, i, error; 372 struct ataparams params; 373 static int inited = 0; 374 375 if (chp->ch_flags & WDCF_DISABLED) 376 return; 377 378 callout_init(&chp->ch_callout); 379 380 if ((error = wdc_addref(chp)) != 0) { 381 aprint_error("%s: unable to enable controller\n", 382 chp->wdc->sc_dev.dv_xname); 383 return; 384 } 385 386 if (wdcprobe(chp) == 0) 387 /* If no drives, abort attach here. */ 388 goto out; 389 390 /* initialise global data */ 391 if (inited == 0) { 392 /* Initialize the wdc_xfer pool. */ 393 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 394 0, 0, "wdcspl", NULL); 395 inited++; 396 } 397 TAILQ_INIT(&chp->ch_queue->sc_xfer); 398 399 for (i = 0; i < 2; i++) { 400 chp->ch_drive[i].chnl_softc = chp; 401 chp->ch_drive[i].drive = i; 402 /* 403 * Init error counter so that an error withing the first xfers 404 * will trigger a downgrade 405 */ 406 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 407 408 /* If controller can't do 16bit flag the drives as 32bit */ 409 if ((chp->wdc->cap & 410 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 411 WDC_CAPABILITY_DATA32) 412 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 413 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 414 continue; 415 416 /* 417 * Wait a bit, some devices are weird just after a reset. 418 * Then issue a IDENTIFY command, to try to detect slave ghost 419 */ 420 delay(5000); 421 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, ¶ms); 422 if (error != CMD_OK) { 423 delay(1000000); 424 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, 425 ¶ms); 426 } 427 if (error == CMD_OK) { 428 /* If IDENTIFY succeded, this is not an OLD ctrl */ 429 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 430 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 431 } else { 432 chp->ch_drive[i].drive_flags &= 433 ~(DRIVE_ATA | DRIVE_ATAPI); 434 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 435 chp->wdc->sc_dev.dv_xname, 436 chp->channel, i, error), DEBUG_PROBE); 437 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 438 continue; 439 /* 440 * Pre-ATA drive ? 441 * Test registers writability (Error register not 442 * writable, but cyllo is), then try an ATA command. 443 */ 444 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 445 chp->wdc->select(chp,i); 446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 447 WDSD_IBM | (i << 4)); 448 delay(10); /* 400ns delay */ 449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 450 wd_error, 0x58); 451 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 452 wd_cyl_lo, 0xa5); 453 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 454 wd_error) == 0x58 || 455 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 456 wd_cyl_lo) != 0xa5) { 457 WDCDEBUG_PRINT(("%s:%d:%d: register " 458 "writability failed\n", 459 chp->wdc->sc_dev.dv_xname, 460 chp->channel, i), DEBUG_PROBE); 461 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 462 } 463 if (wait_for_ready(chp, 10000) != 0) { 464 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 465 chp->wdc->sc_dev.dv_xname, 466 chp->channel, i), DEBUG_PROBE); 467 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 468 continue; 469 } 470 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 471 wd_command, WDCC_RECAL); 472 delay(10); /* 400ns delay */ 473 if (wait_for_ready(chp, 10000) != 0) { 474 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 475 chp->wdc->sc_dev.dv_xname, 476 chp->channel, i), DEBUG_PROBE); 477 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 478 } 479 } 480 } 481 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 482 483 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 484 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 485 DEBUG_PROBE); 486 487 /* If no drives, abort here */ 488 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 489 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 490 goto out; 491 492 /* 493 * Attach an ATAPI bus, if needed. 494 */ 495 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 496 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 497 #if NATAPIBUS > 0 498 wdc_atapibus_attach(chp); 499 #else 500 /* 501 * Fake the autoconfig "not configured" message 502 */ 503 aprint_normal("atapibus at %s channel %d not configured\n", 504 chp->wdc->sc_dev.dv_xname, chp->channel); 505 chp->atapibus = NULL; 506 #endif 507 } 508 509 for (i = 0; i < 2; i++) { 510 struct ata_device adev; 511 if ((chp->ch_drive[i].drive_flags & 512 (DRIVE_ATA | DRIVE_OLD)) == 0) { 513 continue; 514 } 515 memset(&adev, 0, sizeof(struct ata_device)); 516 adev.adev_bustype = &wdc_ata_bustype; 517 adev.adev_channel = chp->channel; 518 adev.adev_openings = 1; 519 adev.adev_drv_data = &chp->ch_drive[i]; 520 chp->ata_drives[i] = config_found(&chp->wdc->sc_dev, 521 &adev, wdprint); 522 if (chp->ata_drives[i] != NULL) 523 wdc_probe_caps(&chp->ch_drive[i]); 524 } 525 526 /* 527 * reset drive_flags for unnatached devices, reset state for attached 528 * ones 529 */ 530 for (i = 0; i < 2; i++) { 531 if (chp->ch_drive[i].drv_softc == NULL) 532 chp->ch_drive[i].drive_flags = 0; 533 else 534 chp->ch_drive[i].state = 0; 535 } 536 537 /* 538 * Reset channel. The probe, with some combinations of ATA/ATAPI 539 * devices keep it in a mostly working, but strange state (with busy 540 * led on) 541 */ 542 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 543 delay(50); 544 wdcreset(chp, VERBOSE); 545 /* 546 * Read status registers to avoid spurious interrupts. 547 */ 548 for (i = 1; i >= 0; i--) { 549 if (chp->ch_drive[i].drive_flags & DRIVE) { 550 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 551 chp->wdc->select(chp,i); 552 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 553 wd_sdh, WDSD_IBM | (i << 4)); 554 if (wait_for_unbusy(chp, 10000) < 0) 555 aprint_error("%s:%d:%d: device busy\n", 556 chp->wdc->sc_dev.dv_xname, 557 chp->channel, i); 558 } 559 } 560 } 561 562 if (chp->wdc->cap & WDC_CAPABILITY_MODE) 563 chp->wdc->set_modes(chp); 564 wdc_print_modes(chp); 565 566 #if NATARAID > 0 567 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 568 for (i = 0; i < 2; i++) 569 if (chp->ata_drives[i] != NULL) 570 ata_raid_check_component(chp->ata_drives[i]); 571 #endif /* NATARAID > 0 */ 572 573 out: 574 wdc_delref(chp); 575 } 576 577 /* 578 * Call activate routine of underlying devices. 579 */ 580 int 581 wdcactivate(self, act) 582 struct device *self; 583 enum devact act; 584 { 585 struct wdc_softc *wdc = (struct wdc_softc *)self; 586 struct channel_softc *chp; 587 struct device *sc = 0; 588 int s, i, j, error = 0; 589 590 s = splbio(); 591 switch (act) { 592 case DVACT_ACTIVATE: 593 error = EOPNOTSUPP; 594 break; 595 596 case DVACT_DEACTIVATE: 597 for (i = 0; i < wdc->nchannels; i++) { 598 chp = wdc->channels[i]; 599 600 /* 601 * We might call deactivate routine for 602 * the children of atapibus twice (once via 603 * atapibus, once directly), but since 604 * config_deactivate maintains DVF_ACTIVE flag, 605 * it's safe. 606 */ 607 sc = chp->atapibus; 608 if (sc != NULL) { 609 error = config_deactivate(sc); 610 if (error != 0) 611 goto out; 612 } 613 614 for (j = 0; j < 2; j++) { 615 sc = chp->ch_drive[j].drv_softc; 616 WDCDEBUG_PRINT(("wdcactivate: %s:" 617 " deactivating %s\n", wdc->sc_dev.dv_xname, 618 sc == NULL ? "nodrv" : sc->dv_xname), 619 DEBUG_DETACH); 620 if (sc != NULL) { 621 error = config_deactivate(sc); 622 if (error != 0) 623 goto out; 624 } 625 } 626 } 627 break; 628 } 629 630 out: 631 splx(s); 632 633 #ifdef WDCDEBUG 634 if (sc && error != 0) 635 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 636 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 637 #endif 638 return (error); 639 } 640 641 int 642 wdcdetach(self, flags) 643 struct device *self; 644 int flags; 645 { 646 struct wdc_softc *wdc = (struct wdc_softc *)self; 647 struct channel_softc *chp; 648 struct device *sc = 0; 649 int i, j, error = 0; 650 651 for (i = 0; i < wdc->nchannels; i++) { 652 chp = wdc->channels[i]; 653 654 /* 655 * Detach atapibus and its children. 656 */ 657 sc = chp->atapibus; 658 if (sc != NULL) { 659 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 660 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 661 error = config_detach(sc, flags); 662 if (error != 0) 663 goto out; 664 } 665 666 /* 667 * Detach our other children. 668 */ 669 for (j = 0; j < 2; j++) { 670 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 671 continue; 672 sc = chp->ch_drive[j].drv_softc; 673 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 674 wdc->sc_dev.dv_xname, 675 sc == NULL ? "nodrv" : sc->dv_xname), 676 DEBUG_DETACH); 677 if (sc != NULL) { 678 error = config_detach(sc, flags); 679 if (error != 0) 680 goto out; 681 } 682 } 683 684 wdc_kill_pending(chp); 685 } 686 687 out: 688 #ifdef WDCDEBUG 689 if (sc && error != 0) 690 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 691 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 692 #endif 693 return (error); 694 } 695 696 /* 697 * Start I/O on a controller, for the given channel. 698 * The first xfer may be not for our channel if the channel queues 699 * are shared. 700 */ 701 void 702 wdcstart(chp) 703 struct channel_softc *chp; 704 { 705 struct wdc_xfer *xfer; 706 707 #ifdef WDC_DIAGNOSTIC 708 int spl1, spl2; 709 710 spl1 = splbio(); 711 spl2 = splbio(); 712 if (spl2 != spl1) { 713 printf("wdcstart: not at splbio()\n"); 714 panic("wdcstart"); 715 } 716 splx(spl2); 717 splx(spl1); 718 #endif /* WDC_DIAGNOSTIC */ 719 720 /* is there a xfer ? */ 721 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 722 return; 723 724 /* adjust chp, in case we have a shared queue */ 725 chp = xfer->chp; 726 727 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 728 return; /* channel aleady active */ 729 } 730 #ifdef DIAGNOSTIC 731 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 732 panic("wdcstart: channel waiting for irq"); 733 #endif 734 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 735 if (!(*chp->wdc->claim_hw)(chp, 0)) 736 return; 737 738 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 739 chp->channel, xfer->drive), DEBUG_XFERS); 740 chp->ch_flags |= WDCF_ACTIVE; 741 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 742 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 743 chp->ch_drive[xfer->drive].state = 0; 744 } 745 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 746 KASSERT(xfer->c_flags & C_POLL); 747 xfer->c_start(chp, xfer); 748 } 749 750 /* restart an interrupted I/O */ 751 void 752 wdcrestart(v) 753 void *v; 754 { 755 struct channel_softc *chp = v; 756 int s; 757 758 s = splbio(); 759 wdcstart(chp); 760 splx(s); 761 } 762 763 764 /* 765 * Interrupt routine for the controller. Acknowledge the interrupt, check for 766 * errors on the current operation, mark it done if necessary, and start the 767 * next request. Also check for a partially done transfer, and continue with 768 * the next chunk if so. 769 */ 770 int 771 wdcintr(arg) 772 void *arg; 773 { 774 struct channel_softc *chp = arg; 775 struct wdc_xfer *xfer; 776 int ret; 777 778 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 779 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 780 DEBUG_INTR); 781 return (0); 782 } 783 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 784 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 785 /* try to clear the pending interrupt anyway */ 786 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 787 return (0); 788 } 789 790 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 791 xfer = chp->ch_queue->sc_xfer.tqh_first; 792 if (chp->ch_flags & WDCF_DMA_WAIT) { 793 chp->wdc->dma_status = 794 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 795 xfer->drive, 0); 796 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 797 /* IRQ not for us, not detected by DMA engine */ 798 return 0; 799 } 800 chp->ch_flags &= ~WDCF_DMA_WAIT; 801 } 802 chp->ch_flags &= ~WDCF_IRQ_WAIT; 803 ret = xfer->c_intr(chp, xfer, 1); 804 if (ret == 0) /* irq was not for us, still waiting for irq */ 805 chp->ch_flags |= WDCF_IRQ_WAIT; 806 return (ret); 807 } 808 809 /* Put all disk in RESET state */ 810 void 811 wdc_reset_channel(drvp) 812 struct ata_drive_datas *drvp; 813 { 814 struct channel_softc *chp = drvp->chnl_softc; 815 int drive; 816 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 817 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 818 DEBUG_FUNCS); 819 (void) wdcreset(chp, VERBOSE); 820 for (drive = 0; drive < 2; drive++) { 821 chp->ch_drive[drive].state = 0; 822 } 823 } 824 825 int 826 wdcreset(chp, verb) 827 struct channel_softc *chp; 828 int verb; 829 { 830 int drv_mask1, drv_mask2; 831 832 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 833 chp->wdc->select(chp,0); 834 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 835 WDSD_IBM); /* master */ 836 delay(10); /* 400ns delay */ 837 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 838 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 839 delay(2000); 840 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 841 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 842 delay(10); /* 400ns delay */ 843 844 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 845 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 846 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 847 if (verb && drv_mask2 != drv_mask1) { 848 printf("%s channel %d: reset failed for", 849 chp->wdc->sc_dev.dv_xname, chp->channel); 850 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 851 printf(" drive 0"); 852 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 853 printf(" drive 1"); 854 printf("\n"); 855 } 856 return (drv_mask1 != drv_mask2) ? 1 : 0; 857 } 858 859 static int 860 __wdcwait_reset(chp, drv_mask) 861 struct channel_softc *chp; 862 int drv_mask; 863 { 864 int timeout; 865 u_int8_t st0, er0, st1, er1; 866 #ifdef WDCDEBUG 867 u_int8_t sc0, sn0, cl0, ch0; 868 u_int8_t sc1, sn1, cl1, ch1; 869 #endif 870 /* wait for BSY to deassert */ 871 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 872 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 873 chp->wdc->select(chp,0); 874 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 875 WDSD_IBM); /* master */ 876 delay(10); 877 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 878 er0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 879 #ifdef WDCDEBUG 880 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 881 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 882 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 883 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 884 #endif 885 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 886 chp->wdc->select(chp,1); 887 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 888 WDSD_IBM | 0x10); /* slave */ 889 delay(10); 890 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 891 er1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 892 #ifdef WDCDEBUG 893 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 894 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 895 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 896 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 897 #endif 898 899 if ((drv_mask & 0x01) == 0) { 900 /* no master */ 901 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 902 /* No master, slave is ready, it's done */ 903 goto end; 904 } 905 } else if ((drv_mask & 0x02) == 0) { 906 /* no slave */ 907 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 908 /* No slave, master is ready, it's done */ 909 goto end; 910 } 911 } else { 912 /* Wait for both master and slave to be ready */ 913 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 914 goto end; 915 } 916 } 917 delay(WDCDELAY); 918 } 919 /* Reset timed out. Maybe it's because drv_mask was not right */ 920 if (st0 & WDCS_BSY) 921 drv_mask &= ~0x01; 922 if (st1 & WDCS_BSY) 923 drv_mask &= ~0x02; 924 end: 925 if (er0 != 0x01 && er0 != 0x81) 926 drv_mask &= ~0x01; 927 if (er1 != 0x01) 928 drv_mask &= ~0x02; 929 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 930 "cl=0x%x ch=0x%x\n", 931 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 932 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 933 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 934 "cl=0x%x ch=0x%x\n", 935 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 936 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 937 938 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x er0=0x%x, st1=0x%x er1=0x%x\n", 939 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 940 st0, er0, st1, er1), DEBUG_PROBE); 941 942 return drv_mask; 943 } 944 945 /* 946 * Wait for a drive to be !BSY, and have mask in its status register. 947 * return -1 for a timeout after "timeout" ms. 948 */ 949 int 950 wdcwait(chp, mask, bits, timeout) 951 struct channel_softc *chp; 952 int mask, bits, timeout; 953 { 954 u_char status; 955 int time = 0; 956 957 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 958 :"none", chp->channel), DEBUG_STATUS); 959 chp->ch_error = 0; 960 961 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 962 963 for (;;) { 964 chp->ch_status = status = 965 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 966 if ((status & (WDCS_BSY | mask)) == bits) 967 break; 968 if (++time > timeout) { 969 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 970 "status %x error %x (mask 0x%x bits 0x%x)\n", 971 time, status, 972 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 973 wd_error), mask, bits), 974 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 975 return -1; 976 } 977 delay(WDCDELAY); 978 } 979 #ifdef WDCDEBUG 980 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 981 printf("wdcwait: did busy-wait, time=%d\n", time); 982 #endif 983 if (status & WDCS_ERR) 984 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 985 wd_error); 986 #ifdef WDCNDELAY_DEBUG 987 /* After autoconfig, there should be no long delays. */ 988 if (!cold && time > WDCNDELAY_DEBUG) { 989 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 990 if (xfer == NULL) 991 printf("%s channel %d: warning: busy-wait took %dus\n", 992 chp->wdc->sc_dev.dv_xname, chp->channel, 993 WDCDELAY * time); 994 else 995 printf("%s:%d:%d: warning: busy-wait took %dus\n", 996 chp->wdc->sc_dev.dv_xname, chp->channel, 997 xfer->drive, 998 WDCDELAY * time); 999 } 1000 #endif 1001 return 0; 1002 } 1003 1004 /* 1005 * Busy-wait for DMA to complete 1006 */ 1007 int 1008 wdc_dmawait(chp, xfer, timeout) 1009 struct channel_softc *chp; 1010 struct wdc_xfer *xfer; 1011 int timeout; 1012 { 1013 int time; 1014 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1015 chp->wdc->dma_status = 1016 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1017 chp->channel, xfer->drive, 0); 1018 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1019 return 0; 1020 delay(WDCDELAY); 1021 } 1022 /* timeout, force a DMA halt */ 1023 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1024 chp->channel, xfer->drive, 1); 1025 return 1; 1026 } 1027 1028 void 1029 wdctimeout(arg) 1030 void *arg; 1031 { 1032 struct channel_softc *chp = (struct channel_softc *)arg; 1033 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1034 int s; 1035 1036 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1037 1038 s = splbio(); 1039 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1040 __wdcerror(chp, "lost interrupt"); 1041 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1042 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1043 xfer->c_bcount, 1044 xfer->c_skip); 1045 if (chp->ch_flags & WDCF_DMA_WAIT) { 1046 chp->wdc->dma_status = 1047 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1048 chp->channel, xfer->drive, 1); 1049 chp->ch_flags &= ~WDCF_DMA_WAIT; 1050 } 1051 /* 1052 * Call the interrupt routine. If we just missed an interrupt, 1053 * it will do what's needed. Else, it will take the needed 1054 * action (reset the device). 1055 * Before that we need to reinstall the timeout callback, 1056 * in case it will miss another irq while in this transfer 1057 * We arbitray chose it to be 1s 1058 */ 1059 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1060 xfer->c_flags |= C_TIMEOU; 1061 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1062 xfer->c_intr(chp, xfer, 1); 1063 } else 1064 __wdcerror(chp, "missing untimeout"); 1065 splx(s); 1066 } 1067 1068 /* 1069 * Probe drive's capabilites, for use by the controller later 1070 * Assumes drvp points to an existing drive. 1071 * XXX this should be a controller-indep function 1072 */ 1073 void 1074 wdc_probe_caps(drvp) 1075 struct ata_drive_datas *drvp; 1076 { 1077 struct ataparams params, params2; 1078 struct channel_softc *chp = drvp->chnl_softc; 1079 struct device *drv_dev = drvp->drv_softc; 1080 struct wdc_softc *wdc = chp->wdc; 1081 int i, printed; 1082 char *sep = ""; 1083 int cf_flags; 1084 1085 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1086 /* IDENTIFY failed. Can't tell more about the device */ 1087 return; 1088 } 1089 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1090 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1091 /* 1092 * Controller claims 16 and 32 bit transfers. 1093 * Re-do an IDENTIFY with 32-bit transfers, 1094 * and compare results. 1095 */ 1096 drvp->drive_flags |= DRIVE_CAP32; 1097 ata_get_params(drvp, AT_WAIT, ¶ms2); 1098 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1099 /* Not good. fall back to 16bits */ 1100 drvp->drive_flags &= ~DRIVE_CAP32; 1101 } else { 1102 aprint_normal("%s: 32-bit data port\n", 1103 drv_dev->dv_xname); 1104 } 1105 } 1106 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1107 if (params.atap_ata_major > 0x01 && 1108 params.atap_ata_major != 0xffff) { 1109 for (i = 14; i > 0; i--) { 1110 if (params.atap_ata_major & (1 << i)) { 1111 aprint_normal("%s: ATA version %d\n", 1112 drv_dev->dv_xname, i); 1113 drvp->ata_vers = i; 1114 break; 1115 } 1116 } 1117 } 1118 #endif 1119 1120 /* An ATAPI device is at last PIO mode 3 */ 1121 if (drvp->drive_flags & DRIVE_ATAPI) 1122 drvp->PIO_mode = 3; 1123 1124 /* 1125 * It's not in the specs, but it seems that some drive 1126 * returns 0xffff in atap_extensions when this field is invalid 1127 */ 1128 if (params.atap_extensions != 0xffff && 1129 (params.atap_extensions & WDC_EXT_MODES)) { 1130 printed = 0; 1131 /* 1132 * XXX some drives report something wrong here (they claim to 1133 * support PIO mode 8 !). As mode is coded on 3 bits in 1134 * SET FEATURE, limit it to 7 (so limit i to 4). 1135 * If higher mode than 7 is found, abort. 1136 */ 1137 for (i = 7; i >= 0; i--) { 1138 if ((params.atap_piomode_supp & (1 << i)) == 0) 1139 continue; 1140 if (i > 4) 1141 return; 1142 /* 1143 * See if mode is accepted. 1144 * If the controller can't set its PIO mode, 1145 * assume the defaults are good, so don't try 1146 * to set it 1147 */ 1148 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1149 if (ata_set_mode(drvp, 0x08 | (i + 3), 1150 AT_WAIT) != CMD_OK) 1151 continue; 1152 if (!printed) { 1153 aprint_normal("%s: drive supports PIO mode %d", 1154 drv_dev->dv_xname, i + 3); 1155 sep = ","; 1156 printed = 1; 1157 } 1158 /* 1159 * If controller's driver can't set its PIO mode, 1160 * get the highter one for the drive. 1161 */ 1162 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1163 wdc->PIO_cap >= i + 3) { 1164 drvp->PIO_mode = i + 3; 1165 drvp->PIO_cap = i + 3; 1166 break; 1167 } 1168 } 1169 if (!printed) { 1170 /* 1171 * We didn't find a valid PIO mode. 1172 * Assume the values returned for DMA are buggy too 1173 */ 1174 return; 1175 } 1176 drvp->drive_flags |= DRIVE_MODE; 1177 printed = 0; 1178 for (i = 7; i >= 0; i--) { 1179 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1180 continue; 1181 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1182 (wdc->cap & WDC_CAPABILITY_MODE)) 1183 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1184 != CMD_OK) 1185 continue; 1186 if (!printed) { 1187 aprint_normal("%s DMA mode %d", sep, i); 1188 sep = ","; 1189 printed = 1; 1190 } 1191 if (wdc->cap & WDC_CAPABILITY_DMA) { 1192 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1193 wdc->DMA_cap < i) 1194 continue; 1195 drvp->DMA_mode = i; 1196 drvp->DMA_cap = i; 1197 drvp->drive_flags |= DRIVE_DMA; 1198 } 1199 break; 1200 } 1201 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1202 printed = 0; 1203 for (i = 7; i >= 0; i--) { 1204 if ((params.atap_udmamode_supp & (1 << i)) 1205 == 0) 1206 continue; 1207 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1208 (wdc->cap & WDC_CAPABILITY_UDMA)) 1209 if (ata_set_mode(drvp, 0x40 | i, 1210 AT_WAIT) != CMD_OK) 1211 continue; 1212 if (!printed) { 1213 aprint_normal("%s Ultra-DMA mode %d", 1214 sep, i); 1215 if (i == 2) 1216 aprint_normal(" (Ultra/33)"); 1217 else if (i == 4) 1218 aprint_normal(" (Ultra/66)"); 1219 else if (i == 5) 1220 aprint_normal(" (Ultra/100)"); 1221 else if (i == 6) 1222 aprint_normal(" (Ultra/133)"); 1223 sep = ","; 1224 printed = 1; 1225 } 1226 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1227 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1228 wdc->UDMA_cap < i) 1229 continue; 1230 drvp->UDMA_mode = i; 1231 drvp->UDMA_cap = i; 1232 drvp->drive_flags |= DRIVE_UDMA; 1233 } 1234 break; 1235 } 1236 } 1237 aprint_normal("\n"); 1238 } 1239 1240 /* Try to guess ATA version here, if it didn't get reported */ 1241 if (drvp->ata_vers == 0) { 1242 if (drvp->drive_flags & DRIVE_UDMA) 1243 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1244 else if (drvp->PIO_cap > 2) 1245 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1246 } 1247 cf_flags = drv_dev->dv_cfdata->cf_flags; 1248 if (cf_flags & ATA_CONFIG_PIO_SET) { 1249 drvp->PIO_mode = 1250 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1251 drvp->drive_flags |= DRIVE_MODE; 1252 } 1253 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1254 /* don't care about DMA modes */ 1255 return; 1256 } 1257 if (cf_flags & ATA_CONFIG_DMA_SET) { 1258 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1259 ATA_CONFIG_DMA_DISABLE) { 1260 drvp->drive_flags &= ~DRIVE_DMA; 1261 } else { 1262 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1263 ATA_CONFIG_DMA_OFF; 1264 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1265 } 1266 } 1267 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1268 /* don't care about UDMA modes */ 1269 return; 1270 } 1271 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1272 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1273 ATA_CONFIG_UDMA_DISABLE) { 1274 drvp->drive_flags &= ~DRIVE_UDMA; 1275 } else { 1276 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1277 ATA_CONFIG_UDMA_OFF; 1278 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1279 } 1280 } 1281 } 1282 1283 /* 1284 * downgrade the transfer mode of a drive after an error. return 1 if 1285 * downgrade was possible, 0 otherwise. 1286 */ 1287 int 1288 wdc_downgrade_mode(drvp) 1289 struct ata_drive_datas *drvp; 1290 { 1291 struct channel_softc *chp = drvp->chnl_softc; 1292 struct device *drv_dev = drvp->drv_softc; 1293 struct wdc_softc *wdc = chp->wdc; 1294 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1295 1296 /* if drive or controller don't know its mode, we can't do much */ 1297 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1298 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1299 return 0; 1300 /* current drive mode was set by a config flag, let it this way */ 1301 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1302 (cf_flags & ATA_CONFIG_DMA_SET) || 1303 (cf_flags & ATA_CONFIG_UDMA_SET)) 1304 return 0; 1305 1306 /* 1307 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1308 * Maybe we didn't properly notice the cable type 1309 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1310 * It helps in some cases. 1311 */ 1312 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1313 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1314 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1315 drv_dev->dv_xname, drvp->UDMA_mode); 1316 } 1317 1318 /* 1319 * If we were using ultra-DMA, don't downgrade to multiword DMA 1320 * if we noticed a CRC error. It has been noticed that CRC errors 1321 * in ultra-DMA lead to silent data corruption in multiword DMA. 1322 * Data corruption is less likely to occur in PIO mode. 1323 */ 1324 else if ((drvp->drive_flags & DRIVE_UDMA) && 1325 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1326 drvp->drive_flags &= ~DRIVE_UDMA; 1327 drvp->drive_flags |= DRIVE_DMA; 1328 drvp->DMA_mode = drvp->DMA_cap; 1329 printf("%s: transfer error, downgrading to DMA mode %d\n", 1330 drv_dev->dv_xname, drvp->DMA_mode); 1331 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1332 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1333 drvp->PIO_mode = drvp->PIO_cap; 1334 printf("%s: transfer error, downgrading to PIO mode %d\n", 1335 drv_dev->dv_xname, drvp->PIO_mode); 1336 } else /* already using PIO, can't downgrade */ 1337 return 0; 1338 1339 wdc->set_modes(chp); 1340 /* reset the channel, which will schedule all drives for setup */ 1341 wdc_reset_channel(drvp); 1342 return 1; 1343 } 1344 1345 int 1346 wdc_exec_command(drvp, wdc_c) 1347 struct ata_drive_datas *drvp; 1348 struct wdc_command *wdc_c; 1349 { 1350 struct channel_softc *chp = drvp->chnl_softc; 1351 struct wdc_xfer *xfer; 1352 int s, ret; 1353 1354 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1355 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1356 DEBUG_FUNCS); 1357 1358 /* set up an xfer and queue. Wait for completion */ 1359 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1360 WDC_NOSLEEP); 1361 if (xfer == NULL) { 1362 return WDC_TRY_AGAIN; 1363 } 1364 1365 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1366 wdc_c->flags |= AT_POLL; 1367 if (wdc_c->flags & AT_POLL) 1368 xfer->c_flags |= C_POLL; 1369 xfer->drive = drvp->drive; 1370 xfer->databuf = wdc_c->data; 1371 xfer->c_bcount = wdc_c->bcount; 1372 xfer->cmd = wdc_c; 1373 xfer->c_start = __wdccommand_start; 1374 xfer->c_intr = __wdccommand_intr; 1375 xfer->c_kill_xfer = __wdccommand_done; 1376 1377 s = splbio(); 1378 wdc_exec_xfer(chp, xfer); 1379 #ifdef DIAGNOSTIC 1380 if ((wdc_c->flags & AT_POLL) != 0 && 1381 (wdc_c->flags & AT_DONE) == 0) 1382 panic("wdc_exec_command: polled command not done"); 1383 #endif 1384 if (wdc_c->flags & AT_DONE) { 1385 ret = WDC_COMPLETE; 1386 } else { 1387 if (wdc_c->flags & AT_WAIT) { 1388 while ((wdc_c->flags & AT_DONE) == 0) { 1389 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1390 } 1391 ret = WDC_COMPLETE; 1392 } else { 1393 ret = WDC_QUEUED; 1394 } 1395 } 1396 splx(s); 1397 return ret; 1398 } 1399 1400 void 1401 __wdccommand_start(chp, xfer) 1402 struct channel_softc *chp; 1403 struct wdc_xfer *xfer; 1404 { 1405 int drive = xfer->drive; 1406 struct wdc_command *wdc_c = xfer->cmd; 1407 1408 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1409 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1410 DEBUG_FUNCS); 1411 1412 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1413 chp->wdc->select(chp,drive); 1414 1415 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1416 WDSD_IBM | (drive << 4)); 1417 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1418 wdc_c->timeout) != 0) { 1419 wdc_c->flags |= AT_TIMEOU; 1420 __wdccommand_done(chp, xfer); 1421 return; 1422 } 1423 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1424 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1425 if ((wdc_c->flags & AT_POLL) == 0) { 1426 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1427 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1428 wdctimeout, chp); 1429 return; 1430 } 1431 /* 1432 * Polled command. Wait for drive ready or drq. Done in intr(). 1433 * Wait for at last 400ns for status bit to be valid. 1434 */ 1435 delay(10); 1436 __wdccommand_intr(chp, xfer, 0); 1437 } 1438 1439 int 1440 __wdccommand_intr(chp, xfer, irq) 1441 struct channel_softc *chp; 1442 struct wdc_xfer *xfer; 1443 int irq; 1444 { 1445 struct wdc_command *wdc_c = xfer->cmd; 1446 int bcount = wdc_c->bcount; 1447 char *data = wdc_c->data; 1448 1449 again: 1450 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1451 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1452 if ((wdc_c->flags & AT_XFDONE) != 0) { 1453 /* 1454 * We have completed a data xfer. The drive should now be 1455 * in its initial state 1456 */ 1457 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1458 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0)) { 1459 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1460 return 0; /* IRQ was not for us */ 1461 wdc_c->flags |= AT_TIMEOU; 1462 } 1463 goto out; 1464 } 1465 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1466 (irq == 0) ? wdc_c->timeout : 0)) { 1467 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1468 return 0; /* IRQ was not for us */ 1469 wdc_c->flags |= AT_TIMEOU; 1470 goto out; 1471 } 1472 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1473 chp->wdc->irqack(chp); 1474 if (wdc_c->flags & AT_READ) { 1475 if ((chp->ch_status & WDCS_DRQ) == 0) { 1476 wdc_c->flags |= AT_TIMEOU; 1477 goto out; 1478 } 1479 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1480 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1481 0, (u_int32_t*)data, bcount >> 2); 1482 data += bcount & 0xfffffffc; 1483 bcount = bcount & 0x03; 1484 } 1485 if (bcount > 0) 1486 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1487 wd_data, (u_int16_t *)data, bcount >> 1); 1488 /* at this point the drive should be in its initial state */ 1489 wdc_c->flags |= AT_XFDONE; 1490 } else if (wdc_c->flags & AT_WRITE) { 1491 if ((chp->ch_status & WDCS_DRQ) == 0) { 1492 wdc_c->flags |= AT_TIMEOU; 1493 goto out; 1494 } 1495 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1496 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1497 0, (u_int32_t*)data, bcount >> 2); 1498 data += bcount & 0xfffffffc; 1499 bcount = bcount & 0x03; 1500 } 1501 if (bcount > 0) 1502 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1503 wd_data, (u_int16_t *)data, bcount >> 1); 1504 wdc_c->flags |= AT_XFDONE; 1505 if ((wdc_c->flags & AT_POLL) == 0) { 1506 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1507 callout_reset(&chp->ch_callout, 1508 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1509 return 1; 1510 } else { 1511 goto again; 1512 } 1513 } 1514 out: 1515 __wdccommand_done(chp, xfer); 1516 return 1; 1517 } 1518 1519 void 1520 __wdccommand_done(chp, xfer) 1521 struct channel_softc *chp; 1522 struct wdc_xfer *xfer; 1523 { 1524 struct wdc_command *wdc_c = xfer->cmd; 1525 1526 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1527 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1528 1529 callout_stop(&chp->ch_callout); 1530 1531 if (chp->ch_status & WDCS_DWF) 1532 wdc_c->flags |= AT_DF; 1533 if (chp->ch_status & WDCS_ERR) { 1534 wdc_c->flags |= AT_ERROR; 1535 wdc_c->r_error = chp->ch_error; 1536 } 1537 wdc_c->flags |= AT_DONE; 1538 if ((wdc_c->flags & AT_READREG) != 0 && 1539 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1540 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1541 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1542 wd_sdh); 1543 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1544 wd_cyl_hi) << 8; 1545 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1546 wd_cyl_lo); 1547 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1548 wd_sector); 1549 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1550 wd_seccnt); 1551 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1552 wd_error); 1553 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1554 wd_precomp); 1555 } 1556 wdc_free_xfer(chp, xfer); 1557 if (wdc_c->flags & AT_WAIT) 1558 wakeup(wdc_c); 1559 else if (wdc_c->callback) 1560 wdc_c->callback(wdc_c->callback_arg); 1561 wdcstart(chp); 1562 return; 1563 } 1564 1565 /* 1566 * Send a command. The drive should be ready. 1567 * Assumes interrupts are blocked. 1568 */ 1569 void 1570 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1571 struct channel_softc *chp; 1572 u_int8_t drive; 1573 u_int8_t command; 1574 u_int16_t cylin; 1575 u_int8_t head, sector, count, precomp; 1576 { 1577 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1578 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1579 chp->channel, drive, command, cylin, head, sector, count, precomp), 1580 DEBUG_FUNCS); 1581 1582 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1583 chp->wdc->select(chp,drive); 1584 1585 /* Select drive, head, and addressing mode. */ 1586 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1587 WDSD_IBM | (drive << 4) | head); 1588 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1589 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1590 precomp); 1591 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1592 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1593 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1594 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1595 1596 /* Send command. */ 1597 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1598 return; 1599 } 1600 1601 /* 1602 * Send a 48-bit addressing command. The drive should be ready. 1603 * Assumes interrupts are blocked. 1604 */ 1605 void 1606 wdccommandext(chp, drive, command, blkno, count) 1607 struct channel_softc *chp; 1608 u_int8_t drive; 1609 u_int8_t command; 1610 u_int64_t blkno; 1611 u_int16_t count; 1612 { 1613 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1614 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1615 chp->channel, drive, command, (u_int32_t) blkno, count), 1616 DEBUG_FUNCS); 1617 1618 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1619 chp->wdc->select(chp,drive); 1620 1621 /* Select drive, head, and addressing mode. */ 1622 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1623 (drive << 4) | WDSD_LBA); 1624 1625 /* previous */ 1626 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1627 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1628 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1629 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1630 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1631 1632 /* current */ 1633 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1634 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1635 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1636 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1637 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1638 1639 /* Send command. */ 1640 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1641 return; 1642 } 1643 1644 /* 1645 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1646 * tested by the caller. 1647 */ 1648 void 1649 wdccommandshort(chp, drive, command) 1650 struct channel_softc *chp; 1651 int drive; 1652 int command; 1653 { 1654 1655 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1656 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1657 DEBUG_FUNCS); 1658 1659 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1660 chp->wdc->select(chp,drive); 1661 1662 /* Select drive. */ 1663 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1664 WDSD_IBM | (drive << 4)); 1665 1666 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1667 } 1668 1669 /* Add a command to the queue and start controller. Must be called at splbio */ 1670 1671 void 1672 wdc_exec_xfer(chp, xfer) 1673 struct channel_softc *chp; 1674 struct wdc_xfer *xfer; 1675 { 1676 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1677 chp->channel, xfer->drive), DEBUG_XFERS); 1678 1679 /* complete xfer setup */ 1680 xfer->chp = chp; 1681 1682 /* 1683 * If we are a polled command, and the list is not empty, 1684 * we are doing a dump. Drop the list to allow the polled command 1685 * to complete, we're going to reboot soon anyway. 1686 */ 1687 if ((xfer->c_flags & C_POLL) != 0 && 1688 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1689 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1690 } 1691 /* insert at the end of command list */ 1692 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1693 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1694 chp->ch_flags), DEBUG_XFERS); 1695 wdcstart(chp); 1696 } 1697 1698 struct wdc_xfer * 1699 wdc_get_xfer(flags) 1700 int flags; 1701 { 1702 struct wdc_xfer *xfer; 1703 int s; 1704 1705 s = splbio(); 1706 xfer = pool_get(&wdc_xfer_pool, 1707 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1708 splx(s); 1709 if (xfer != NULL) { 1710 memset(xfer, 0, sizeof(struct wdc_xfer)); 1711 } 1712 return xfer; 1713 } 1714 1715 void 1716 wdc_free_xfer(chp, xfer) 1717 struct channel_softc *chp; 1718 struct wdc_xfer *xfer; 1719 { 1720 struct wdc_softc *wdc = chp->wdc; 1721 int s; 1722 1723 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1724 (*wdc->free_hw)(chp); 1725 s = splbio(); 1726 chp->ch_flags &= ~WDCF_ACTIVE; 1727 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1728 pool_put(&wdc_xfer_pool, xfer); 1729 splx(s); 1730 } 1731 1732 /* 1733 * Kill off all pending xfers for a channel_softc. 1734 * 1735 * Must be called at splbio(). 1736 */ 1737 void 1738 wdc_kill_pending(chp) 1739 struct channel_softc *chp; 1740 { 1741 struct wdc_xfer *xfer; 1742 1743 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1744 chp = xfer->chp; 1745 (*xfer->c_kill_xfer)(chp, xfer); 1746 } 1747 } 1748 1749 static void 1750 __wdcerror(chp, msg) 1751 struct channel_softc *chp; 1752 char *msg; 1753 { 1754 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1755 1756 if (xfer == NULL) 1757 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1758 msg); 1759 else 1760 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1761 chp->channel, xfer->drive, msg); 1762 } 1763 1764 /* 1765 * the bit bucket 1766 */ 1767 void 1768 wdcbit_bucket(chp, size) 1769 struct channel_softc *chp; 1770 int size; 1771 { 1772 1773 for (; size >= 2; size -= 2) 1774 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1775 if (size) 1776 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1777 } 1778 1779 int 1780 wdc_addref(chp) 1781 struct channel_softc *chp; 1782 { 1783 struct wdc_softc *wdc = chp->wdc; 1784 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1785 int s, error = 0; 1786 1787 s = splbio(); 1788 if (adapt->adapt_refcnt++ == 0 && 1789 adapt->adapt_enable != NULL) { 1790 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1791 if (error) 1792 adapt->adapt_refcnt--; 1793 } 1794 splx(s); 1795 return (error); 1796 } 1797 1798 void 1799 wdc_delref(chp) 1800 struct channel_softc *chp; 1801 { 1802 struct wdc_softc *wdc = chp->wdc; 1803 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1804 int s; 1805 1806 s = splbio(); 1807 if (adapt->adapt_refcnt-- == 1 && 1808 adapt->adapt_enable != NULL) 1809 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1810 splx(s); 1811 } 1812 1813 void 1814 wdc_print_modes(struct channel_softc *chp) 1815 { 1816 int drive; 1817 struct ata_drive_datas *drvp; 1818 1819 for (drive = 0; drive < 2; drive++) { 1820 drvp = &chp->ch_drive[drive]; 1821 if ((drvp->drive_flags & DRIVE) == 0) 1822 continue; 1823 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1824 drvp->drv_softc->dv_xname, 1825 chp->wdc->sc_dev.dv_xname, 1826 chp->channel, drive, drvp->PIO_mode); 1827 if (drvp->drive_flags & DRIVE_DMA) 1828 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1829 if (drvp->drive_flags & DRIVE_UDMA) { 1830 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1831 if (drvp->UDMA_mode == 2) 1832 aprint_normal(" (Ultra/33)"); 1833 else if (drvp->UDMA_mode == 4) 1834 aprint_normal(" (Ultra/66)"); 1835 else if (drvp->UDMA_mode == 5) 1836 aprint_normal(" (Ultra/100)"); 1837 else if (drvp->UDMA_mode == 6) 1838 aprint_normal(" (Ultra/133)"); 1839 } 1840 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1841 aprint_normal(" (using DMA data transfers)"); 1842 aprint_normal("\n"); 1843 } 1844 } 1845
Indexes created Wed Sep 24 05:09:52 GMT 2025