wdc.c revision 1.134
1 /* $NetBSD: wdc.c,v 1.134 2003/09/25 19:29:49 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.134 2003/09/25 19:29:49 mycroft Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/wdvar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 struct pool wdc_xfer_pool; 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL 136 }; 137 #endif 138 139 static void __wdcerror __P((struct channel_softc*, char *)); 140 static int __wdcwait_reset __P((struct channel_softc *, int)); 141 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 142 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 143 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 144 int wdprint __P((void *, const char *)); 145 void wdc_finish_attach __P((struct device *)); 146 void wdc_channel_attach __P((struct channel_softc *)); 147 148 #define DEBUG_INTR 0x01 149 #define DEBUG_XFERS 0x02 150 #define DEBUG_STATUS 0x04 151 #define DEBUG_FUNCS 0x08 152 #define DEBUG_PROBE 0x10 153 #define DEBUG_DETACH 0x20 154 #define DEBUG_DELAY 0x40 155 #ifdef WDCDEBUG 156 int wdcdebug_mask = 0; 157 int wdc_nxfer = 0; 158 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 159 #else 160 #define WDCDEBUG_PRINT(args, level) 161 #endif 162 163 int 164 wdprint(aux, pnp) 165 void *aux; 166 const char *pnp; 167 { 168 struct ata_device *adev = aux; 169 if (pnp) 170 aprint_normal("wd at %s", pnp); 171 aprint_normal(" channel %d drive %d", adev->adev_channel, 172 adev->adev_drv_data->drive); 173 return (UNCONF); 174 } 175 176 /* Test to see controller with at last one attached drive is there. 177 * Returns a bit for each possible drive found (0x01 for drive 0, 178 * 0x02 for drive 1). 179 * Logic: 180 * - If a status register is at 0xff, assume there is no drive here 181 * (ISA has pull-up resistors). Similarly if the status register has 182 * the value we last wrote to the bus (for IDE interfaces without pullups). 183 * If no drive at all -> return. 184 * - reset the controller, wait for it to complete (may take up to 31s !). 185 * If timeout -> return. 186 * - test ATA/ATAPI signatures. If at last one drive found -> return. 187 * - try an ATA command on the master. 188 */ 189 190 int 191 wdcprobe(chp) 192 struct channel_softc *chp; 193 { 194 u_int8_t st0, st1, sc, sn, cl, ch; 195 u_int8_t ret_value = 0x03; 196 u_int8_t drive; 197 198 /* 199 * Sanity check to see if the wdc channel responds at all. 200 */ 201 202 if (chp->wdc == NULL || 203 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 204 205 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 206 chp->wdc->select(chp,0); 207 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 208 WDSD_IBM); 209 delay(10); /* 400ns delay */ 210 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 211 212 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 213 chp->wdc->select(chp,1); 214 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 215 WDSD_IBM | 0x10); 216 delay(10); /* 400ns delay */ 217 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 218 219 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 221 chp->channel, st0, st1), DEBUG_PROBE); 222 223 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 224 ret_value &= ~0x01; 225 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 226 ret_value &= ~0x02; 227 228 /* Register writability test, drive 0. */ 229 if (ret_value & 0x01) { 230 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 231 chp->wdc->select(chp,0); 232 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 233 WDSD_IBM); 234 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 235 0x02); 236 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 237 wd_cyl_lo) != 0x02) 238 ret_value &= ~0x01; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 240 0x01); 241 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 242 wd_cyl_lo) != 0x01) 243 ret_value &= ~0x01; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 245 0x01); 246 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 247 wd_sector) != 0x01) 248 ret_value &= ~0x01; 249 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 250 0x02); 251 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 252 wd_sector) != 0x02) 253 ret_value &= ~0x01; 254 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 255 wd_cyl_lo) != 0x01) 256 ret_value &= ~0x01; 257 } 258 259 /* Register writability test, drive 1. */ 260 if (ret_value & 0x02) { 261 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 262 chp->wdc->select(chp,1); 263 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 264 WDSD_IBM | 0x10); 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 266 0x02); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 268 wd_cyl_lo) != 0x02) 269 ret_value &= ~0x02; 270 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 271 0x01); 272 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 273 wd_cyl_lo) != 0x01) 274 ret_value &= ~0x02; 275 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 276 0x01); 277 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 278 wd_sector) != 0x01) 279 ret_value &= ~0x02; 280 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 281 0x02); 282 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 283 wd_sector) != 0x02) 284 ret_value &= ~0x02; 285 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 286 wd_cyl_lo) != 0x01) 287 ret_value &= ~0x02; 288 } 289 290 if (ret_value == 0) 291 return 0; 292 293 } 294 295 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 296 chp->wdc->select(chp,0); 297 /* assert SRST, wait for reset to complete */ 298 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 299 WDSD_IBM); 300 delay(10); /* 400ns delay */ 301 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 302 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 303 delay(2000); 304 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 305 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 306 delay(10); /* 400ns delay */ 307 308 ret_value = __wdcwait_reset(chp, ret_value); 309 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 310 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 311 ret_value), DEBUG_PROBE); 312 313 /* if reset failed, there's nothing here */ 314 if (ret_value == 0) 315 return 0; 316 317 /* 318 * Test presence of drives. First test register signatures looking for 319 * ATAPI devices. If it's not an ATAPI and reset said there may be 320 * something here assume it's ATA or OLD. Ghost will be killed later in 321 * attach routine. 322 */ 323 for (drive = 0; drive < 2; drive++) { 324 if ((ret_value & (0x01 << drive)) == 0) 325 continue; 326 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 327 chp->wdc->select(chp,drive); 328 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 329 WDSD_IBM | (drive << 4)); 330 delay(10); /* 400ns delay */ 331 /* Save registers contents */ 332 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 333 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 334 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 335 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 336 337 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 338 "cl=0x%x ch=0x%x\n", 339 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 340 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 341 /* 342 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 343 * we get wrong values here, so ignore it. 344 */ 345 if (cl == 0x14 && ch == 0xeb) { 346 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 347 } else { 348 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 349 if (chp->wdc == NULL || 350 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 351 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 352 } 353 } 354 return (ret_value); 355 } 356 357 void 358 wdcattach(wdc) 359 struct wdc_softc *wdc; 360 { 361 362 config_interrupts(&wdc->sc_dev, wdc_finish_attach); 363 } 364 365 void 366 wdc_finish_attach(self) 367 struct device *self; 368 { 369 struct wdc_softc *wdc = (void *)self; 370 int i; 371 372 for (i = 0; i < wdc->nchannels; i++) 373 wdc_channel_attach(wdc->channels[i]); 374 } 375 376 void 377 wdc_channel_attach(chp) 378 struct channel_softc *chp; 379 { 380 int ctrl_flags, i, error; 381 struct ataparams params; 382 static int inited = 0; 383 384 if (chp->ch_flags & WDCF_DISABLED) 385 return; 386 387 callout_init(&chp->ch_callout); 388 389 if ((error = wdc_addref(chp)) != 0) { 390 aprint_error("%s: unable to enable controller\n", 391 chp->wdc->sc_dev.dv_xname); 392 return; 393 } 394 395 if (wdcprobe(chp) == 0) 396 /* If no drives, abort attach here. */ 397 goto out; 398 399 /* initialise global data */ 400 if (inited == 0) { 401 /* Initialize the wdc_xfer pool. */ 402 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 403 0, 0, "wdcspl", NULL); 404 inited++; 405 } 406 TAILQ_INIT(&chp->ch_queue->sc_xfer); 407 408 for (i = 0; i < 2; i++) { 409 chp->ch_drive[i].chnl_softc = chp; 410 chp->ch_drive[i].drive = i; 411 /* 412 * Init error counter so that an error withing the first xfers 413 * will trigger a downgrade 414 */ 415 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 416 417 /* If controller can't do 16bit flag the drives as 32bit */ 418 if ((chp->wdc->cap & 419 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 420 WDC_CAPABILITY_DATA32) 421 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 422 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 423 continue; 424 425 /* 426 * Wait a bit, some devices are weird just after a reset. 427 * Then issue a IDENTIFY command, to try to detect slave ghost 428 */ 429 delay(5000); 430 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, ¶ms); 431 if (error != CMD_OK) { 432 delay(1000000); 433 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, 434 ¶ms); 435 } 436 if (error == CMD_OK) { 437 /* If IDENTIFY succeded, this is not an OLD ctrl */ 438 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 439 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 440 } else { 441 chp->ch_drive[i].drive_flags &= 442 ~(DRIVE_ATA | DRIVE_ATAPI); 443 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 444 chp->wdc->sc_dev.dv_xname, 445 chp->channel, i, error), DEBUG_PROBE); 446 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 447 continue; 448 /* 449 * Pre-ATA drive ? 450 * Test registers writability (Error register not 451 * writable, but cyllo is), then try an ATA command. 452 */ 453 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 454 chp->wdc->select(chp,i); 455 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 456 WDSD_IBM | (i << 4)); 457 delay(10); /* 400ns delay */ 458 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 459 wd_error, 0x58); 460 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 461 wd_cyl_lo, 0xa5); 462 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 463 wd_error) == 0x58 || 464 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 465 wd_cyl_lo) != 0xa5) { 466 WDCDEBUG_PRINT(("%s:%d:%d: register " 467 "writability failed\n", 468 chp->wdc->sc_dev.dv_xname, 469 chp->channel, i), DEBUG_PROBE); 470 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 471 } 472 if (wait_for_ready(chp, 10000) != 0) { 473 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 474 chp->wdc->sc_dev.dv_xname, 475 chp->channel, i), DEBUG_PROBE); 476 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 477 continue; 478 } 479 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 480 wd_command, WDCC_RECAL); 481 delay(10); /* 400ns delay */ 482 if (wait_for_ready(chp, 10000) != 0) { 483 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 484 chp->wdc->sc_dev.dv_xname, 485 chp->channel, i), DEBUG_PROBE); 486 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 487 } 488 } 489 } 490 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 491 492 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 493 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 494 DEBUG_PROBE); 495 496 /* If no drives, abort here */ 497 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 498 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 499 goto out; 500 501 /* 502 * Attach an ATAPI bus, if needed. 503 */ 504 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 505 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 506 #if NATAPIBUS > 0 507 wdc_atapibus_attach(chp); 508 #else 509 /* 510 * Fake the autoconfig "not configured" message 511 */ 512 aprint_normal("atapibus at %s channel %d not configured\n", 513 chp->wdc->sc_dev.dv_xname, chp->channel); 514 chp->atapibus = NULL; 515 #endif 516 } 517 518 for (i = 0; i < 2; i++) { 519 struct ata_device adev; 520 if ((chp->ch_drive[i].drive_flags & 521 (DRIVE_ATA | DRIVE_OLD)) == 0) { 522 continue; 523 } 524 memset(&adev, 0, sizeof(struct ata_device)); 525 adev.adev_bustype = &wdc_ata_bustype; 526 adev.adev_channel = chp->channel; 527 adev.adev_openings = 1; 528 adev.adev_drv_data = &chp->ch_drive[i]; 529 chp->ata_drives[i] = config_found(&chp->wdc->sc_dev, 530 &adev, wdprint); 531 if (chp->ata_drives[i] != NULL) 532 wdc_probe_caps(&chp->ch_drive[i]); 533 } 534 535 /* 536 * reset drive_flags for unnatached devices, reset state for attached 537 * ones 538 */ 539 for (i = 0; i < 2; i++) { 540 if (chp->ch_drive[i].drv_softc == NULL) 541 chp->ch_drive[i].drive_flags = 0; 542 else 543 chp->ch_drive[i].state = 0; 544 } 545 546 /* 547 * Reset channel. The probe, with some combinations of ATA/ATAPI 548 * devices keep it in a mostly working, but strange state (with busy 549 * led on) 550 */ 551 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 552 delay(50); 553 wdcreset(chp, VERBOSE); 554 /* 555 * Read status registers to avoid spurious interrupts. 556 */ 557 for (i = 1; i >= 0; i--) { 558 if (chp->ch_drive[i].drive_flags & DRIVE) { 559 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 560 chp->wdc->select(chp,i); 561 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 562 wd_sdh, WDSD_IBM | (i << 4)); 563 if (wait_for_unbusy(chp, 10000) < 0) 564 aprint_error("%s:%d:%d: device busy\n", 565 chp->wdc->sc_dev.dv_xname, 566 chp->channel, i); 567 } 568 } 569 } 570 571 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 572 chp->wdc->set_modes(chp); 573 wdc_print_modes(chp); 574 } 575 576 #if NATARAID > 0 577 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 578 for (i = 0; i < 2; i++) 579 if (chp->ata_drives[i] != NULL) 580 ata_raid_check_component(chp->ata_drives[i]); 581 #endif /* NATARAID > 0 */ 582 583 out: 584 wdc_delref(chp); 585 } 586 587 /* 588 * Call activate routine of underlying devices. 589 */ 590 int 591 wdcactivate(self, act) 592 struct device *self; 593 enum devact act; 594 { 595 struct wdc_softc *wdc = (struct wdc_softc *)self; 596 struct channel_softc *chp; 597 struct device *sc = 0; 598 int s, i, j, error = 0; 599 600 s = splbio(); 601 switch (act) { 602 case DVACT_ACTIVATE: 603 error = EOPNOTSUPP; 604 break; 605 606 case DVACT_DEACTIVATE: 607 for (i = 0; i < wdc->nchannels; i++) { 608 chp = wdc->channels[i]; 609 610 /* 611 * We might call deactivate routine for 612 * the children of atapibus twice (once via 613 * atapibus, once directly), but since 614 * config_deactivate maintains DVF_ACTIVE flag, 615 * it's safe. 616 */ 617 sc = chp->atapibus; 618 if (sc != NULL) { 619 error = config_deactivate(sc); 620 if (error != 0) 621 goto out; 622 } 623 624 for (j = 0; j < 2; j++) { 625 sc = chp->ch_drive[j].drv_softc; 626 WDCDEBUG_PRINT(("wdcactivate: %s:" 627 " deactivating %s\n", wdc->sc_dev.dv_xname, 628 sc == NULL ? "nodrv" : sc->dv_xname), 629 DEBUG_DETACH); 630 if (sc != NULL) { 631 error = config_deactivate(sc); 632 if (error != 0) 633 goto out; 634 } 635 } 636 } 637 break; 638 } 639 640 out: 641 splx(s); 642 643 #ifdef WDCDEBUG 644 if (sc && error != 0) 645 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 646 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 647 #endif 648 return (error); 649 } 650 651 int 652 wdcdetach(self, flags) 653 struct device *self; 654 int flags; 655 { 656 struct wdc_softc *wdc = (struct wdc_softc *)self; 657 struct channel_softc *chp; 658 struct device *sc = 0; 659 int i, j, error = 0; 660 661 for (i = 0; i < wdc->nchannels; i++) { 662 chp = wdc->channels[i]; 663 664 /* 665 * Detach atapibus and its children. 666 */ 667 sc = chp->atapibus; 668 if (sc != NULL) { 669 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 670 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 671 error = config_detach(sc, flags); 672 if (error != 0) 673 goto out; 674 } 675 676 /* 677 * Detach our other children. 678 */ 679 for (j = 0; j < 2; j++) { 680 if (chp->ch_drive[j].drive_flags & DRIVE_ATAPI) 681 continue; 682 sc = chp->ch_drive[j].drv_softc; 683 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 684 wdc->sc_dev.dv_xname, 685 sc == NULL ? "nodrv" : sc->dv_xname), 686 DEBUG_DETACH); 687 if (sc != NULL) { 688 error = config_detach(sc, flags); 689 if (error != 0) 690 goto out; 691 } 692 } 693 694 wdc_kill_pending(chp); 695 } 696 697 out: 698 #ifdef WDCDEBUG 699 if (sc && error != 0) 700 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 701 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 702 #endif 703 return (error); 704 } 705 706 /* 707 * Start I/O on a controller, for the given channel. 708 * The first xfer may be not for our channel if the channel queues 709 * are shared. 710 */ 711 void 712 wdcstart(chp) 713 struct channel_softc *chp; 714 { 715 struct wdc_xfer *xfer; 716 717 #ifdef WDC_DIAGNOSTIC 718 int spl1, spl2; 719 720 spl1 = splbio(); 721 spl2 = splbio(); 722 if (spl2 != spl1) { 723 printf("wdcstart: not at splbio()\n"); 724 panic("wdcstart"); 725 } 726 splx(spl2); 727 splx(spl1); 728 #endif /* WDC_DIAGNOSTIC */ 729 730 /* is there a xfer ? */ 731 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 732 return; 733 734 /* adjust chp, in case we have a shared queue */ 735 chp = xfer->chp; 736 737 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 738 return; /* channel aleady active */ 739 } 740 #ifdef DIAGNOSTIC 741 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 742 panic("wdcstart: channel waiting for irq"); 743 #endif 744 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 745 if (!(*chp->wdc->claim_hw)(chp, 0)) 746 return; 747 748 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 749 chp->channel, xfer->drive), DEBUG_XFERS); 750 chp->ch_flags |= WDCF_ACTIVE; 751 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 752 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 753 chp->ch_drive[xfer->drive].state = 0; 754 } 755 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 756 KASSERT(xfer->c_flags & C_POLL); 757 xfer->c_start(chp, xfer); 758 } 759 760 /* restart an interrupted I/O */ 761 void 762 wdcrestart(v) 763 void *v; 764 { 765 struct channel_softc *chp = v; 766 int s; 767 768 s = splbio(); 769 wdcstart(chp); 770 splx(s); 771 } 772 773 774 /* 775 * Interrupt routine for the controller. Acknowledge the interrupt, check for 776 * errors on the current operation, mark it done if necessary, and start the 777 * next request. Also check for a partially done transfer, and continue with 778 * the next chunk if so. 779 */ 780 int 781 wdcintr(arg) 782 void *arg; 783 { 784 struct channel_softc *chp = arg; 785 struct wdc_xfer *xfer; 786 int ret; 787 788 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 789 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 790 DEBUG_INTR); 791 return (0); 792 } 793 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 794 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 795 /* try to clear the pending interrupt anyway */ 796 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 797 return (0); 798 } 799 800 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 801 xfer = chp->ch_queue->sc_xfer.tqh_first; 802 if (chp->ch_flags & WDCF_DMA_WAIT) { 803 chp->wdc->dma_status = 804 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 805 xfer->drive, 0); 806 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 807 /* IRQ not for us, not detected by DMA engine */ 808 return 0; 809 } 810 chp->ch_flags &= ~WDCF_DMA_WAIT; 811 } 812 chp->ch_flags &= ~WDCF_IRQ_WAIT; 813 ret = xfer->c_intr(chp, xfer, 1); 814 if (ret == 0) /* irq was not for us, still waiting for irq */ 815 chp->ch_flags |= WDCF_IRQ_WAIT; 816 return (ret); 817 } 818 819 /* Put all disk in RESET state */ 820 void 821 wdc_reset_channel(drvp) 822 struct ata_drive_datas *drvp; 823 { 824 struct channel_softc *chp = drvp->chnl_softc; 825 int drive; 826 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 827 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 828 DEBUG_FUNCS); 829 (void) wdcreset(chp, VERBOSE); 830 for (drive = 0; drive < 2; drive++) { 831 chp->ch_drive[drive].state = 0; 832 } 833 } 834 835 int 836 wdcreset(chp, verb) 837 struct channel_softc *chp; 838 int verb; 839 { 840 int drv_mask1, drv_mask2; 841 842 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 843 chp->wdc->select(chp,0); 844 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 845 WDSD_IBM); /* master */ 846 delay(10); /* 400ns delay */ 847 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 848 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 849 delay(2000); 850 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 851 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 852 delay(10); /* 400ns delay */ 853 854 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 855 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 856 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 857 if (verb && drv_mask2 != drv_mask1) { 858 printf("%s channel %d: reset failed for", 859 chp->wdc->sc_dev.dv_xname, chp->channel); 860 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 861 printf(" drive 0"); 862 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 863 printf(" drive 1"); 864 printf("\n"); 865 } 866 return (drv_mask1 != drv_mask2) ? 1 : 0; 867 } 868 869 static int 870 __wdcwait_reset(chp, drv_mask) 871 struct channel_softc *chp; 872 int drv_mask; 873 { 874 int timeout; 875 u_int8_t st0, er0, st1, er1; 876 #ifdef WDCDEBUG 877 u_int8_t sc0, sn0, cl0, ch0; 878 u_int8_t sc1, sn1, cl1, ch1; 879 #endif 880 /* wait for BSY to deassert */ 881 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 882 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 883 chp->wdc->select(chp,0); 884 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 885 WDSD_IBM); /* master */ 886 delay(10); 887 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 888 er0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 889 #ifdef WDCDEBUG 890 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 891 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 892 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 893 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 894 #endif 895 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 896 chp->wdc->select(chp,1); 897 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 898 WDSD_IBM | 0x10); /* slave */ 899 delay(10); 900 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 901 er1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 902 #ifdef WDCDEBUG 903 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 904 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 905 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 906 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 907 #endif 908 909 if ((drv_mask & 0x01) == 0) { 910 /* no master */ 911 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 912 /* No master, slave is ready, it's done */ 913 goto end; 914 } 915 } else if ((drv_mask & 0x02) == 0) { 916 /* no slave */ 917 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 918 /* No slave, master is ready, it's done */ 919 goto end; 920 } 921 } else { 922 /* Wait for both master and slave to be ready */ 923 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 924 goto end; 925 } 926 } 927 delay(WDCDELAY); 928 } 929 /* Reset timed out. Maybe it's because drv_mask was not right */ 930 if (st0 & WDCS_BSY) 931 drv_mask &= ~0x01; 932 if (st1 & WDCS_BSY) 933 drv_mask &= ~0x02; 934 end: 935 if (er0 != 0x01 && er0 != 0x81) 936 drv_mask &= ~0x01; 937 if (er1 != 0x01) 938 drv_mask &= ~0x02; 939 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 940 "cl=0x%x ch=0x%x\n", 941 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 942 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 943 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 944 "cl=0x%x ch=0x%x\n", 945 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 946 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 947 948 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x er0=0x%x, st1=0x%x er1=0x%x\n", 949 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 950 st0, er0, st1, er1), DEBUG_PROBE); 951 952 return drv_mask; 953 } 954 955 /* 956 * Wait for a drive to be !BSY, and have mask in its status register. 957 * return -1 for a timeout after "timeout" ms. 958 */ 959 int 960 wdcwait(chp, mask, bits, timeout) 961 struct channel_softc *chp; 962 int mask, bits, timeout; 963 { 964 u_char status; 965 int time = 0; 966 967 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 968 :"none", chp->channel), DEBUG_STATUS); 969 chp->ch_error = 0; 970 971 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 972 973 for (;;) { 974 chp->ch_status = status = 975 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 976 if ((status & (WDCS_BSY | mask)) == bits) 977 break; 978 if (++time > timeout) { 979 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 980 "status %x error %x (mask 0x%x bits 0x%x)\n", 981 time, status, 982 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 983 wd_error), mask, bits), 984 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 985 return -1; 986 } 987 delay(WDCDELAY); 988 } 989 #ifdef WDCDEBUG 990 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 991 printf("wdcwait: did busy-wait, time=%d\n", time); 992 #endif 993 if (status & WDCS_ERR) 994 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 995 wd_error); 996 #ifdef WDCNDELAY_DEBUG 997 /* After autoconfig, there should be no long delays. */ 998 if (!cold && time > WDCNDELAY_DEBUG) { 999 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1000 if (xfer == NULL) 1001 printf("%s channel %d: warning: busy-wait took %dus\n", 1002 chp->wdc->sc_dev.dv_xname, chp->channel, 1003 WDCDELAY * time); 1004 else 1005 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1006 chp->wdc->sc_dev.dv_xname, chp->channel, 1007 xfer->drive, 1008 WDCDELAY * time); 1009 } 1010 #endif 1011 return 0; 1012 } 1013 1014 /* 1015 * Busy-wait for DMA to complete 1016 */ 1017 int 1018 wdc_dmawait(chp, xfer, timeout) 1019 struct channel_softc *chp; 1020 struct wdc_xfer *xfer; 1021 int timeout; 1022 { 1023 int time; 1024 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1025 chp->wdc->dma_status = 1026 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1027 chp->channel, xfer->drive, 0); 1028 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1029 return 0; 1030 delay(WDCDELAY); 1031 } 1032 /* timeout, force a DMA halt */ 1033 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1034 chp->channel, xfer->drive, 1); 1035 return 1; 1036 } 1037 1038 void 1039 wdctimeout(arg) 1040 void *arg; 1041 { 1042 struct channel_softc *chp = (struct channel_softc *)arg; 1043 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1044 int s; 1045 1046 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1047 1048 s = splbio(); 1049 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1050 __wdcerror(chp, "lost interrupt"); 1051 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1052 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1053 xfer->c_bcount, 1054 xfer->c_skip); 1055 if (chp->ch_flags & WDCF_DMA_WAIT) { 1056 chp->wdc->dma_status = 1057 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1058 chp->channel, xfer->drive, 1); 1059 chp->ch_flags &= ~WDCF_DMA_WAIT; 1060 } 1061 /* 1062 * Call the interrupt routine. If we just missed an interrupt, 1063 * it will do what's needed. Else, it will take the needed 1064 * action (reset the device). 1065 * Before that we need to reinstall the timeout callback, 1066 * in case it will miss another irq while in this transfer 1067 * We arbitray chose it to be 1s 1068 */ 1069 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1070 xfer->c_flags |= C_TIMEOU; 1071 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1072 xfer->c_intr(chp, xfer, 1); 1073 } else 1074 __wdcerror(chp, "missing untimeout"); 1075 splx(s); 1076 } 1077 1078 /* 1079 * Probe drive's capabilites, for use by the controller later 1080 * Assumes drvp points to an existing drive. 1081 * XXX this should be a controller-indep function 1082 */ 1083 void 1084 wdc_probe_caps(drvp) 1085 struct ata_drive_datas *drvp; 1086 { 1087 struct ataparams params, params2; 1088 struct channel_softc *chp = drvp->chnl_softc; 1089 struct device *drv_dev = drvp->drv_softc; 1090 struct wdc_softc *wdc = chp->wdc; 1091 int i, printed; 1092 char *sep = ""; 1093 int cf_flags; 1094 1095 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1096 /* IDENTIFY failed. Can't tell more about the device */ 1097 return; 1098 } 1099 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1100 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1101 /* 1102 * Controller claims 16 and 32 bit transfers. 1103 * Re-do an IDENTIFY with 32-bit transfers, 1104 * and compare results. 1105 */ 1106 drvp->drive_flags |= DRIVE_CAP32; 1107 ata_get_params(drvp, AT_WAIT, ¶ms2); 1108 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1109 /* Not good. fall back to 16bits */ 1110 drvp->drive_flags &= ~DRIVE_CAP32; 1111 } else { 1112 aprint_normal("%s: 32-bit data port\n", 1113 drv_dev->dv_xname); 1114 } 1115 } 1116 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1117 if (params.atap_ata_major > 0x01 && 1118 params.atap_ata_major != 0xffff) { 1119 for (i = 14; i > 0; i--) { 1120 if (params.atap_ata_major & (1 << i)) { 1121 aprint_normal("%s: ATA version %d\n", 1122 drv_dev->dv_xname, i); 1123 drvp->ata_vers = i; 1124 break; 1125 } 1126 } 1127 } 1128 #endif 1129 1130 /* An ATAPI device is at last PIO mode 3 */ 1131 if (drvp->drive_flags & DRIVE_ATAPI) 1132 drvp->PIO_mode = 3; 1133 1134 /* 1135 * It's not in the specs, but it seems that some drive 1136 * returns 0xffff in atap_extensions when this field is invalid 1137 */ 1138 if (params.atap_extensions != 0xffff && 1139 (params.atap_extensions & WDC_EXT_MODES)) { 1140 printed = 0; 1141 /* 1142 * XXX some drives report something wrong here (they claim to 1143 * support PIO mode 8 !). As mode is coded on 3 bits in 1144 * SET FEATURE, limit it to 7 (so limit i to 4). 1145 * If higher mode than 7 is found, abort. 1146 */ 1147 for (i = 7; i >= 0; i--) { 1148 if ((params.atap_piomode_supp & (1 << i)) == 0) 1149 continue; 1150 if (i > 4) 1151 return; 1152 /* 1153 * See if mode is accepted. 1154 * If the controller can't set its PIO mode, 1155 * assume the defaults are good, so don't try 1156 * to set it 1157 */ 1158 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1159 if (ata_set_mode(drvp, 0x08 | (i + 3), 1160 AT_WAIT) != CMD_OK) 1161 continue; 1162 if (!printed) { 1163 aprint_normal("%s: drive supports PIO mode %d", 1164 drv_dev->dv_xname, i + 3); 1165 sep = ","; 1166 printed = 1; 1167 } 1168 /* 1169 * If controller's driver can't set its PIO mode, 1170 * get the highter one for the drive. 1171 */ 1172 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1173 wdc->PIO_cap >= i + 3) { 1174 drvp->PIO_mode = i + 3; 1175 drvp->PIO_cap = i + 3; 1176 break; 1177 } 1178 } 1179 if (!printed) { 1180 /* 1181 * We didn't find a valid PIO mode. 1182 * Assume the values returned for DMA are buggy too 1183 */ 1184 return; 1185 } 1186 drvp->drive_flags |= DRIVE_MODE; 1187 printed = 0; 1188 for (i = 7; i >= 0; i--) { 1189 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1190 continue; 1191 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1192 (wdc->cap & WDC_CAPABILITY_MODE)) 1193 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1194 != CMD_OK) 1195 continue; 1196 if (!printed) { 1197 aprint_normal("%s DMA mode %d", sep, i); 1198 sep = ","; 1199 printed = 1; 1200 } 1201 if (wdc->cap & WDC_CAPABILITY_DMA) { 1202 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1203 wdc->DMA_cap < i) 1204 continue; 1205 drvp->DMA_mode = i; 1206 drvp->DMA_cap = i; 1207 drvp->drive_flags |= DRIVE_DMA; 1208 } 1209 break; 1210 } 1211 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1212 printed = 0; 1213 for (i = 7; i >= 0; i--) { 1214 if ((params.atap_udmamode_supp & (1 << i)) 1215 == 0) 1216 continue; 1217 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1218 (wdc->cap & WDC_CAPABILITY_UDMA)) 1219 if (ata_set_mode(drvp, 0x40 | i, 1220 AT_WAIT) != CMD_OK) 1221 continue; 1222 if (!printed) { 1223 aprint_normal("%s Ultra-DMA mode %d", 1224 sep, i); 1225 if (i == 2) 1226 aprint_normal(" (Ultra/33)"); 1227 else if (i == 4) 1228 aprint_normal(" (Ultra/66)"); 1229 else if (i == 5) 1230 aprint_normal(" (Ultra/100)"); 1231 else if (i == 6) 1232 aprint_normal(" (Ultra/133)"); 1233 sep = ","; 1234 printed = 1; 1235 } 1236 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1237 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1238 wdc->UDMA_cap < i) 1239 continue; 1240 drvp->UDMA_mode = i; 1241 drvp->UDMA_cap = i; 1242 drvp->drive_flags |= DRIVE_UDMA; 1243 } 1244 break; 1245 } 1246 } 1247 aprint_normal("\n"); 1248 } 1249 1250 /* Try to guess ATA version here, if it didn't get reported */ 1251 if (drvp->ata_vers == 0) { 1252 if (drvp->drive_flags & DRIVE_UDMA) 1253 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1254 else if (drvp->PIO_cap > 2) 1255 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1256 } 1257 cf_flags = drv_dev->dv_cfdata->cf_flags; 1258 if (cf_flags & ATA_CONFIG_PIO_SET) { 1259 drvp->PIO_mode = 1260 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1261 drvp->drive_flags |= DRIVE_MODE; 1262 } 1263 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1264 /* don't care about DMA modes */ 1265 return; 1266 } 1267 if (cf_flags & ATA_CONFIG_DMA_SET) { 1268 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1269 ATA_CONFIG_DMA_DISABLE) { 1270 drvp->drive_flags &= ~DRIVE_DMA; 1271 } else { 1272 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1273 ATA_CONFIG_DMA_OFF; 1274 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1275 } 1276 } 1277 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1278 /* don't care about UDMA modes */ 1279 return; 1280 } 1281 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1282 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1283 ATA_CONFIG_UDMA_DISABLE) { 1284 drvp->drive_flags &= ~DRIVE_UDMA; 1285 } else { 1286 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1287 ATA_CONFIG_UDMA_OFF; 1288 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1289 } 1290 } 1291 } 1292 1293 /* 1294 * downgrade the transfer mode of a drive after an error. return 1 if 1295 * downgrade was possible, 0 otherwise. 1296 */ 1297 int 1298 wdc_downgrade_mode(drvp) 1299 struct ata_drive_datas *drvp; 1300 { 1301 struct channel_softc *chp = drvp->chnl_softc; 1302 struct device *drv_dev = drvp->drv_softc; 1303 struct wdc_softc *wdc = chp->wdc; 1304 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1305 1306 /* if drive or controller don't know its mode, we can't do much */ 1307 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1308 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1309 return 0; 1310 /* current drive mode was set by a config flag, let it this way */ 1311 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1312 (cf_flags & ATA_CONFIG_DMA_SET) || 1313 (cf_flags & ATA_CONFIG_UDMA_SET)) 1314 return 0; 1315 1316 /* 1317 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1318 * Maybe we didn't properly notice the cable type 1319 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1320 * It helps in some cases. 1321 */ 1322 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1323 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1324 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1325 drv_dev->dv_xname, drvp->UDMA_mode); 1326 } 1327 1328 /* 1329 * If we were using ultra-DMA, don't downgrade to multiword DMA 1330 * if we noticed a CRC error. It has been noticed that CRC errors 1331 * in ultra-DMA lead to silent data corruption in multiword DMA. 1332 * Data corruption is less likely to occur in PIO mode. 1333 */ 1334 else if ((drvp->drive_flags & DRIVE_UDMA) && 1335 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1336 drvp->drive_flags &= ~DRIVE_UDMA; 1337 drvp->drive_flags |= DRIVE_DMA; 1338 drvp->DMA_mode = drvp->DMA_cap; 1339 printf("%s: transfer error, downgrading to DMA mode %d\n", 1340 drv_dev->dv_xname, drvp->DMA_mode); 1341 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1342 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1343 drvp->PIO_mode = drvp->PIO_cap; 1344 printf("%s: transfer error, downgrading to PIO mode %d\n", 1345 drv_dev->dv_xname, drvp->PIO_mode); 1346 } else /* already using PIO, can't downgrade */ 1347 return 0; 1348 1349 wdc->set_modes(chp); 1350 /* reset the channel, which will schedule all drives for setup */ 1351 wdc_reset_channel(drvp); 1352 return 1; 1353 } 1354 1355 int 1356 wdc_exec_command(drvp, wdc_c) 1357 struct ata_drive_datas *drvp; 1358 struct wdc_command *wdc_c; 1359 { 1360 struct channel_softc *chp = drvp->chnl_softc; 1361 struct wdc_xfer *xfer; 1362 int s, ret; 1363 1364 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1365 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1366 DEBUG_FUNCS); 1367 1368 /* set up an xfer and queue. Wait for completion */ 1369 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1370 WDC_NOSLEEP); 1371 if (xfer == NULL) { 1372 return WDC_TRY_AGAIN; 1373 } 1374 1375 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1376 wdc_c->flags |= AT_POLL; 1377 if (wdc_c->flags & AT_POLL) 1378 xfer->c_flags |= C_POLL; 1379 xfer->drive = drvp->drive; 1380 xfer->databuf = wdc_c->data; 1381 xfer->c_bcount = wdc_c->bcount; 1382 xfer->cmd = wdc_c; 1383 xfer->c_start = __wdccommand_start; 1384 xfer->c_intr = __wdccommand_intr; 1385 xfer->c_kill_xfer = __wdccommand_done; 1386 1387 s = splbio(); 1388 wdc_exec_xfer(chp, xfer); 1389 #ifdef DIAGNOSTIC 1390 if ((wdc_c->flags & AT_POLL) != 0 && 1391 (wdc_c->flags & AT_DONE) == 0) 1392 panic("wdc_exec_command: polled command not done"); 1393 #endif 1394 if (wdc_c->flags & AT_DONE) { 1395 ret = WDC_COMPLETE; 1396 } else { 1397 if (wdc_c->flags & AT_WAIT) { 1398 while ((wdc_c->flags & AT_DONE) == 0) { 1399 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1400 } 1401 ret = WDC_COMPLETE; 1402 } else { 1403 ret = WDC_QUEUED; 1404 } 1405 } 1406 splx(s); 1407 return ret; 1408 } 1409 1410 void 1411 __wdccommand_start(chp, xfer) 1412 struct channel_softc *chp; 1413 struct wdc_xfer *xfer; 1414 { 1415 int drive = xfer->drive; 1416 struct wdc_command *wdc_c = xfer->cmd; 1417 1418 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1419 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1420 DEBUG_FUNCS); 1421 1422 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1423 chp->wdc->select(chp,drive); 1424 1425 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1426 WDSD_IBM | (drive << 4)); 1427 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1428 wdc_c->timeout) != 0) { 1429 wdc_c->flags |= AT_TIMEOU; 1430 __wdccommand_done(chp, xfer); 1431 return; 1432 } 1433 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1434 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1435 #if 0 1436 if (wdc_c->r_command == WDCC_IDENTIFY) { 1437 /* 1438 * This is an IDENTIFY command. Do an immediate poll of the 1439 * status to try to determine if there's actually a device 1440 * there. Since this is a data-bearing command, it should go 1441 * to either BSY or DRQ within 400ns. 1442 */ 1443 delay(10); /* 400ns delay */ 1444 if ((bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_altsts) & 1445 (WDCS_BSY | WDCS_DRQ | WDCS_ERR)) == 0) { 1446 __wdccommand_intr(chp, xfer, 0); 1447 return; 1448 } 1449 } 1450 #endif 1451 if ((wdc_c->flags & AT_POLL) == 0) { 1452 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1453 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1454 wdctimeout, chp); 1455 return; 1456 } 1457 /* 1458 * Polled command. Wait for drive ready or drq. Done in intr(). 1459 * Wait for at last 400ns for status bit to be valid. 1460 */ 1461 delay(10); /* 400ns delay */ 1462 __wdccommand_intr(chp, xfer, 0); 1463 } 1464 1465 int 1466 __wdccommand_intr(chp, xfer, irq) 1467 struct channel_softc *chp; 1468 struct wdc_xfer *xfer; 1469 int irq; 1470 { 1471 struct wdc_command *wdc_c = xfer->cmd; 1472 int bcount = wdc_c->bcount; 1473 char *data = wdc_c->data; 1474 1475 again: 1476 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1477 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1478 if ((wdc_c->flags & AT_XFDONE) != 0) { 1479 /* 1480 * We have completed a data xfer. The drive should now be 1481 * in its initial state 1482 */ 1483 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1484 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0)) { 1485 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1486 return 0; /* IRQ was not for us */ 1487 wdc_c->flags |= AT_TIMEOU; 1488 } 1489 goto out; 1490 } 1491 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1492 (irq == 0) ? wdc_c->timeout : 0)) { 1493 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1494 return 0; /* IRQ was not for us */ 1495 wdc_c->flags |= AT_TIMEOU; 1496 goto out; 1497 } 1498 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1499 chp->wdc->irqack(chp); 1500 if (wdc_c->flags & AT_READ) { 1501 if ((chp->ch_status & WDCS_DRQ) == 0) { 1502 wdc_c->flags |= AT_TIMEOU; 1503 goto out; 1504 } 1505 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1506 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1507 0, (u_int32_t*)data, bcount >> 2); 1508 data += bcount & 0xfffffffc; 1509 bcount = bcount & 0x03; 1510 } 1511 if (bcount > 0) 1512 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1513 wd_data, (u_int16_t *)data, bcount >> 1); 1514 /* at this point the drive should be in its initial state */ 1515 wdc_c->flags |= AT_XFDONE; 1516 } else if (wdc_c->flags & AT_WRITE) { 1517 if ((chp->ch_status & WDCS_DRQ) == 0) { 1518 wdc_c->flags |= AT_TIMEOU; 1519 goto out; 1520 } 1521 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1522 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1523 0, (u_int32_t*)data, bcount >> 2); 1524 data += bcount & 0xfffffffc; 1525 bcount = bcount & 0x03; 1526 } 1527 if (bcount > 0) 1528 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1529 wd_data, (u_int16_t *)data, bcount >> 1); 1530 wdc_c->flags |= AT_XFDONE; 1531 if ((wdc_c->flags & AT_POLL) == 0) { 1532 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1533 callout_reset(&chp->ch_callout, 1534 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1535 return 1; 1536 } else { 1537 goto again; 1538 } 1539 } 1540 out: 1541 __wdccommand_done(chp, xfer); 1542 return 1; 1543 } 1544 1545 void 1546 __wdccommand_done(chp, xfer) 1547 struct channel_softc *chp; 1548 struct wdc_xfer *xfer; 1549 { 1550 struct wdc_command *wdc_c = xfer->cmd; 1551 1552 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1553 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1554 1555 callout_stop(&chp->ch_callout); 1556 1557 if (chp->ch_status & WDCS_DWF) 1558 wdc_c->flags |= AT_DF; 1559 if (chp->ch_status & WDCS_ERR) { 1560 wdc_c->flags |= AT_ERROR; 1561 wdc_c->r_error = chp->ch_error; 1562 } 1563 wdc_c->flags |= AT_DONE; 1564 if ((wdc_c->flags & AT_READREG) != 0 && 1565 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1566 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1567 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1568 wd_sdh); 1569 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1570 wd_cyl_hi) << 8; 1571 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1572 wd_cyl_lo); 1573 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1574 wd_sector); 1575 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1576 wd_seccnt); 1577 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1578 wd_error); 1579 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1580 wd_precomp); 1581 } 1582 wdc_free_xfer(chp, xfer); 1583 if (wdc_c->flags & AT_WAIT) 1584 wakeup(wdc_c); 1585 else if (wdc_c->callback) 1586 wdc_c->callback(wdc_c->callback_arg); 1587 wdcstart(chp); 1588 return; 1589 } 1590 1591 /* 1592 * Send a command. The drive should be ready. 1593 * Assumes interrupts are blocked. 1594 */ 1595 void 1596 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1597 struct channel_softc *chp; 1598 u_int8_t drive; 1599 u_int8_t command; 1600 u_int16_t cylin; 1601 u_int8_t head, sector, count, precomp; 1602 { 1603 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1604 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1605 chp->channel, drive, command, cylin, head, sector, count, precomp), 1606 DEBUG_FUNCS); 1607 1608 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1609 chp->wdc->select(chp,drive); 1610 1611 /* Select drive, head, and addressing mode. */ 1612 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1613 WDSD_IBM | (drive << 4) | head); 1614 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1615 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1616 precomp); 1617 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1618 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1619 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1620 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1621 1622 /* Send command. */ 1623 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1624 return; 1625 } 1626 1627 /* 1628 * Send a 48-bit addressing command. The drive should be ready. 1629 * Assumes interrupts are blocked. 1630 */ 1631 void 1632 wdccommandext(chp, drive, command, blkno, count) 1633 struct channel_softc *chp; 1634 u_int8_t drive; 1635 u_int8_t command; 1636 u_int64_t blkno; 1637 u_int16_t count; 1638 { 1639 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1640 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1641 chp->channel, drive, command, (u_int32_t) blkno, count), 1642 DEBUG_FUNCS); 1643 1644 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1645 chp->wdc->select(chp,drive); 1646 1647 /* Select drive, head, and addressing mode. */ 1648 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1649 (drive << 4) | WDSD_LBA); 1650 1651 /* previous */ 1652 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1654 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1655 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1656 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1657 1658 /* current */ 1659 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1660 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1661 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1662 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1663 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1664 1665 /* Send command. */ 1666 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1667 return; 1668 } 1669 1670 /* 1671 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1672 * tested by the caller. 1673 */ 1674 void 1675 wdccommandshort(chp, drive, command) 1676 struct channel_softc *chp; 1677 int drive; 1678 int command; 1679 { 1680 1681 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1682 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1683 DEBUG_FUNCS); 1684 1685 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1686 chp->wdc->select(chp,drive); 1687 1688 /* Select drive. */ 1689 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1690 WDSD_IBM | (drive << 4)); 1691 1692 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1693 } 1694 1695 /* Add a command to the queue and start controller. Must be called at splbio */ 1696 1697 void 1698 wdc_exec_xfer(chp, xfer) 1699 struct channel_softc *chp; 1700 struct wdc_xfer *xfer; 1701 { 1702 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1703 chp->channel, xfer->drive), DEBUG_XFERS); 1704 1705 /* complete xfer setup */ 1706 xfer->chp = chp; 1707 1708 /* 1709 * If we are a polled command, and the list is not empty, 1710 * we are doing a dump. Drop the list to allow the polled command 1711 * to complete, we're going to reboot soon anyway. 1712 */ 1713 if ((xfer->c_flags & C_POLL) != 0 && 1714 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1715 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1716 } 1717 /* insert at the end of command list */ 1718 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1719 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1720 chp->ch_flags), DEBUG_XFERS); 1721 wdcstart(chp); 1722 } 1723 1724 struct wdc_xfer * 1725 wdc_get_xfer(flags) 1726 int flags; 1727 { 1728 struct wdc_xfer *xfer; 1729 int s; 1730 1731 s = splbio(); 1732 xfer = pool_get(&wdc_xfer_pool, 1733 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1734 splx(s); 1735 if (xfer != NULL) { 1736 memset(xfer, 0, sizeof(struct wdc_xfer)); 1737 } 1738 return xfer; 1739 } 1740 1741 void 1742 wdc_free_xfer(chp, xfer) 1743 struct channel_softc *chp; 1744 struct wdc_xfer *xfer; 1745 { 1746 struct wdc_softc *wdc = chp->wdc; 1747 int s; 1748 1749 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1750 (*wdc->free_hw)(chp); 1751 s = splbio(); 1752 chp->ch_flags &= ~WDCF_ACTIVE; 1753 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1754 pool_put(&wdc_xfer_pool, xfer); 1755 splx(s); 1756 } 1757 1758 /* 1759 * Kill off all pending xfers for a channel_softc. 1760 * 1761 * Must be called at splbio(). 1762 */ 1763 void 1764 wdc_kill_pending(chp) 1765 struct channel_softc *chp; 1766 { 1767 struct wdc_xfer *xfer; 1768 1769 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1770 chp = xfer->chp; 1771 (*xfer->c_kill_xfer)(chp, xfer); 1772 } 1773 } 1774 1775 static void 1776 __wdcerror(chp, msg) 1777 struct channel_softc *chp; 1778 char *msg; 1779 { 1780 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1781 1782 if (xfer == NULL) 1783 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1784 msg); 1785 else 1786 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1787 chp->channel, xfer->drive, msg); 1788 } 1789 1790 /* 1791 * the bit bucket 1792 */ 1793 void 1794 wdcbit_bucket(chp, size) 1795 struct channel_softc *chp; 1796 int size; 1797 { 1798 1799 for (; size >= 2; size -= 2) 1800 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1801 if (size) 1802 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1803 } 1804 1805 int 1806 wdc_addref(chp) 1807 struct channel_softc *chp; 1808 { 1809 struct wdc_softc *wdc = chp->wdc; 1810 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1811 int s, error = 0; 1812 1813 s = splbio(); 1814 if (adapt->adapt_refcnt++ == 0 && 1815 adapt->adapt_enable != NULL) { 1816 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1817 if (error) 1818 adapt->adapt_refcnt--; 1819 } 1820 splx(s); 1821 return (error); 1822 } 1823 1824 void 1825 wdc_delref(chp) 1826 struct channel_softc *chp; 1827 { 1828 struct wdc_softc *wdc = chp->wdc; 1829 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1830 int s; 1831 1832 s = splbio(); 1833 if (adapt->adapt_refcnt-- == 1 && 1834 adapt->adapt_enable != NULL) 1835 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1836 splx(s); 1837 } 1838 1839 void 1840 wdc_print_modes(struct channel_softc *chp) 1841 { 1842 int drive; 1843 struct ata_drive_datas *drvp; 1844 1845 for (drive = 0; drive < 2; drive++) { 1846 drvp = &chp->ch_drive[drive]; 1847 if ((drvp->drive_flags & DRIVE) == 0) 1848 continue; 1849 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1850 drvp->drv_softc->dv_xname, 1851 chp->wdc->sc_dev.dv_xname, 1852 chp->channel, drive, drvp->PIO_mode); 1853 if (drvp->drive_flags & DRIVE_DMA) 1854 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1855 if (drvp->drive_flags & DRIVE_UDMA) { 1856 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1857 if (drvp->UDMA_mode == 2) 1858 aprint_normal(" (Ultra/33)"); 1859 else if (drvp->UDMA_mode == 4) 1860 aprint_normal(" (Ultra/66)"); 1861 else if (drvp->UDMA_mode == 5) 1862 aprint_normal(" (Ultra/100)"); 1863 else if (drvp->UDMA_mode == 6) 1864 aprint_normal(" (Ultra/133)"); 1865 } 1866 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1867 aprint_normal(" (using DMA data transfers)"); 1868 aprint_normal("\n"); 1869 } 1870 } 1871
Indexes created Wed Sep 24 05:09:52 GMT 2025