wdc.c revision 1.138
1 /* $NetBSD: wdc.c,v 1.138 2003/10/08 20:58:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.138 2003/10/08 20:58:00 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 printf("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) 272 { 273 s = splbio(); 274 chp->ch_flags &= ~WDCF_TH_RUN; 275 tsleep(&chp->thread, PRIBIO, "atath", 0); 276 chp->ch_flags |= WDCF_TH_RUN; 277 splx(s); 278 if (chp->ch_flags & WDCF_SHUTDOWN) 279 break; 280 s = splbio(); 281 if (chp->ch_flags & WDCF_TH_RESET) { 282 int drive; 283 (void) wdcreset(chp, RESET_SLEEP); 284 for (drive = 0; drive < 2; drive++) { 285 chp->ch_drive[drive].state = 0; 286 } 287 chp->ch_flags &= ~WDCF_TH_RESET; 288 wdcstart(chp); 289 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 290 chp->ch_queue->queue_freese == 1) { 291 /* 292 * caller has bumped queue_freese, decrease it 293 */ 294 chp->ch_queue->queue_freese--; 295 xfer = chp->ch_queue->sc_xfer.tqh_first; 296 #ifdef DIAGNOSTIC 297 if (xfer == NULL) 298 panic("channel active with no xfer ?"); 299 #endif 300 xfer->c_start(chp, xfer); 301 } else if (chp->ch_queue->queue_freese > 1) { 302 panic("queue_freese"); 303 } 304 splx(s); 305 } 306 chp->thread = NULL; 307 wakeup(&chp->ch_flags); 308 kthread_exit(0); 309 } 310 311 void 312 atabusconfig(atabus_sc) 313 struct atabus_softc *atabus_sc; 314 { 315 struct channel_softc *chp = atabus_sc->sc_chan; 316 int ctrl_flags, i, error; 317 struct ataparams params; 318 struct atabus_initq *atabus_initq = NULL; 319 u_int8_t st0, st1; 320 321 if ((error = wdc_addref(chp)) != 0) { 322 aprint_error("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 config_pending_decr(); 325 return; 326 } 327 328 if (__wdcprobe(chp, 0) == 0) 329 /* If no drives, abort attach here. */ 330 goto out; 331 332 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 333 for (i = 0; i < mstohz(3000); i++) { 334 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 335 chp->wdc->select(chp,0); 336 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 337 WDSD_IBM); 338 delay(10); /* 400ns delay */ 339 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 340 341 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 342 chp->wdc->select(chp,1); 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 344 WDSD_IBM | 0x10); 345 delay(10); /* 400ns delay */ 346 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 347 348 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 349 == 0 || 350 (st0 & WDCS_DRDY)) && 351 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 352 == 0 || 353 (st1 & WDCS_DRDY))) 354 break; 355 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 356 } 357 if ((st0 & WDCS_DRDY) == 0) 358 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 359 if ((st1 & WDCS_DRDY) == 0) 360 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 361 362 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 363 chp->wdc->sc_dev.dv_xname, 364 chp->channel, st0, st1), DEBUG_PROBE); 365 366 /* Wait a bit, some devices are weird just after a reset. */ 367 delay(5000); 368 369 for (i = 0; i < 2; i++) { 370 chp->ch_drive[i].chnl_softc = chp; 371 chp->ch_drive[i].drive = i; 372 /* 373 * Init error counter so that an error withing the first xfers 374 * will trigger a downgrade 375 */ 376 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 377 378 /* If controller can't do 16bit flag the drives as 32bit */ 379 if ((chp->wdc->cap & 380 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 381 WDC_CAPABILITY_DATA32) 382 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 383 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 384 continue; 385 386 /* issue an identify, to try to detect ghosts */ 387 error = ata_get_params(&chp->ch_drive[i], 388 AT_WAIT | AT_POLL, ¶ms); 389 if (error != CMD_OK) { 390 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 391 error = ata_get_params(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL, ¶ms); 393 } 394 if (error == CMD_OK) { 395 /* If IDENTIFY succeded, this is not an OLD ctrl */ 396 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 397 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 398 } else { 399 chp->ch_drive[i].drive_flags &= 400 ~(DRIVE_ATA | DRIVE_ATAPI); 401 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 402 chp->wdc->sc_dev.dv_xname, 403 chp->channel, i, error), DEBUG_PROBE); 404 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 405 continue; 406 /* 407 * Pre-ATA drive ? 408 * Test registers writability (Error register not 409 * writable, but cyllo is), then try an ATA command. 410 */ 411 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 412 chp->wdc->select(chp,i); 413 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 414 WDSD_IBM | (i << 4)); 415 delay(10); /* 400ns delay */ 416 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 417 wd_error, 0x58); 418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 419 wd_cyl_lo, 0xa5); 420 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 421 wd_error) == 0x58 || 422 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 423 wd_cyl_lo) != 0xa5) { 424 WDCDEBUG_PRINT(("%s:%d:%d: register " 425 "writability failed\n", 426 chp->wdc->sc_dev.dv_xname, 427 chp->channel, i), DEBUG_PROBE); 428 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 429 } 430 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 431 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 432 chp->wdc->sc_dev.dv_xname, 433 chp->channel, i), DEBUG_PROBE); 434 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 435 continue; 436 } 437 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 438 wd_command, WDCC_RECAL); 439 delay(10); /* 400ns delay */ 440 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 441 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 442 chp->wdc->sc_dev.dv_xname, 443 chp->channel, i), DEBUG_PROBE); 444 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 445 } 446 } 447 } 448 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 449 450 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 451 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 452 DEBUG_PROBE); 453 454 /* If no drives, abort here */ 455 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 456 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 457 goto out; 458 459 /* Make sure the devices probe in atabus order to avoid jitter. */ 460 simple_lock(&atabus_interlock); 461 while(1) { 462 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 463 if (atabus_initq->atabus_sc == atabus_sc) 464 break; 465 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 466 &atabus_interlock); 467 } 468 simple_unlock(&atabus_interlock); 469 470 /* 471 * Attach an ATAPI bus, if needed. 472 */ 473 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 474 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 475 #if NATAPIBUS > 0 476 wdc_atapibus_attach(atabus_sc); 477 #else 478 /* 479 * Fake the autoconfig "not configured" message 480 */ 481 aprint_normal("atapibus at %s not configured\n", 482 chp->wdc->sc_dev.dv_xname); 483 chp->atapibus = NULL; 484 #endif 485 } 486 487 for (i = 0; i < 2; i++) { 488 struct ata_device adev; 489 if ((chp->ch_drive[i].drive_flags & 490 (DRIVE_ATA | DRIVE_OLD)) == 0) { 491 continue; 492 } 493 memset(&adev, 0, sizeof(struct ata_device)); 494 adev.adev_bustype = &wdc_ata_bustype; 495 adev.adev_channel = chp->channel; 496 adev.adev_openings = 1; 497 adev.adev_drv_data = &chp->ch_drive[i]; 498 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 499 &adev, wdprint); 500 if (chp->ata_drives[i] != NULL) { 501 wdc_probe_caps(&chp->ch_drive[i]); 502 } 503 } 504 505 /* now that we know the drives, the controller can set its modes */ 506 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 507 chp->wdc->set_modes(chp); 508 wdc_print_modes(chp); 509 } 510 #if NATARAID > 0 511 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 512 for (i = 0; i < 2; i++) 513 if (chp->ata_drives[i] != NULL) 514 ata_raid_check_component(chp->ata_drives[i]); 515 #endif /* NATARAID > 0 */ 516 517 /* 518 * reset drive_flags for unnatached devices, reset state for attached 519 * ones 520 */ 521 for (i = 0; i < 2; i++) { 522 if (chp->ch_drive[i].drv_softc == NULL) 523 chp->ch_drive[i].drive_flags = 0; 524 else 525 chp->ch_drive[i].state = 0; 526 } 527 528 out: 529 if (atabus_initq == NULL) { 530 simple_lock(&atabus_interlock); 531 while(1) { 532 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 533 if (atabus_initq->atabus_sc == atabus_sc) 534 break; 535 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 536 &atabus_interlock); 537 } 538 simple_unlock(&atabus_interlock); 539 } 540 simple_lock(&atabus_interlock); 541 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 542 simple_unlock(&atabus_interlock); 543 544 free(atabus_initq, M_DEVBUF); 545 wakeup(&atabus_initq_head); 546 547 config_pending_decr(); 548 wdc_delref(chp); 549 } 550 551 552 int 553 wdprint(aux, pnp) 554 void *aux; 555 const char *pnp; 556 { 557 struct ata_device *adev = aux; 558 if (pnp) 559 aprint_normal("wd at %s", pnp); 560 aprint_normal(" drive %d", adev->adev_drv_data->drive); 561 return (UNCONF); 562 } 563 564 /* Test to see controller with at last one attached drive is there. 565 * Returns a bit for each possible drive found (0x01 for drive 0, 566 * 0x02 for drive 1). 567 * Logic: 568 * - If a status register is at 0xff, assume there is no drive here 569 * (ISA has pull-up resistors). Similarly if the status register has 570 * the value we last wrote to the bus (for IDE interfaces without pullups). 571 * If no drive at all -> return. 572 * - reset the controller, wait for it to complete (may take up to 31s !). 573 * If timeout -> return. 574 * - test ATA/ATAPI signatures. If at last one drive found -> return. 575 * - try an ATA command on the master. 576 */ 577 578 int 579 wdcprobe(chp) 580 struct channel_softc *chp; 581 { 582 return __wdcprobe(chp, 1); 583 } 584 585 int 586 __wdcprobe(chp, poll) 587 struct channel_softc *chp; 588 int poll; 589 { 590 u_int8_t st0, st1, sc, sn, cl, ch; 591 u_int8_t ret_value = 0x03; 592 u_int8_t drive; 593 594 /* 595 * Sanity check to see if the wdc channel responds at all. 596 */ 597 598 if (chp->wdc == NULL || 599 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 600 601 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 602 chp->wdc->select(chp,0); 603 604 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 605 WDSD_IBM); 606 delay(10); /* 400ns delay */ 607 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 608 609 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 610 chp->wdc->select(chp,1); 611 612 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 613 WDSD_IBM | 0x10); 614 delay(10); /* 400ns delay */ 615 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 616 617 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 618 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 619 chp->channel, st0, st1), DEBUG_PROBE); 620 621 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM) 622 ret_value &= ~0x01; 623 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10)) 624 ret_value &= ~0x02; 625 /* Register writability test, drive 0. */ 626 if (ret_value & 0x01) { 627 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 628 chp->wdc->select(chp,0); 629 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 630 WDSD_IBM); 631 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 632 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 633 wd_cyl_lo) != 0x02) 634 ret_value &= ~0x01; 635 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 636 0x01); 637 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 638 wd_cyl_lo) != 0x01) 639 ret_value &= ~0x01; 640 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 641 0x01); 642 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 643 wd_sector) != 0x01) 644 ret_value &= ~0x01; 645 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 646 0x02); 647 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 648 wd_sector) != 0x02) 649 ret_value &= ~0x01; 650 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_cyl_lo) != 0x01) 652 ret_value &= ~0x01; 653 } 654 /* Register writability test, drive 1. */ 655 if (ret_value & 0x02) { 656 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 657 chp->wdc->select(chp,1); 658 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 659 WDSD_IBM | 0x10); 660 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 661 0x02); 662 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 663 wd_cyl_lo) != 0x02) 664 ret_value &= ~0x02; 665 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 666 0x01); 667 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 668 wd_cyl_lo) != 0x01) 669 ret_value &= ~0x02; 670 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 671 0x01); 672 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 673 wd_sector) != 0x01) 674 ret_value &= ~0x02; 675 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 676 0x02); 677 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 678 wd_sector) != 0x02) 679 ret_value &= ~0x02; 680 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 681 wd_cyl_lo) != 0x01) 682 ret_value &= ~0x02; 683 } 684 685 if (ret_value == 0) 686 return 0; 687 } 688 689 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 690 chp->wdc->select(chp,0); 691 /* assert SRST, wait for reset to complete */ 692 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 693 WDSD_IBM); 694 delay(10); /* 400ns delay */ 695 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 696 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 697 DELAY(2000); 698 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 699 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 700 delay(10); /* 400ns delay */ 701 702 ret_value = __wdcwait_reset(chp, ret_value, poll); 703 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 704 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 705 ret_value), DEBUG_PROBE); 706 707 /* if reset failed, there's nothing here */ 708 if (ret_value == 0) 709 return 0; 710 711 /* 712 * Test presence of drives. First test register signatures looking for 713 * ATAPI devices. If it's not an ATAPI and reset said there may be 714 * something here assume it's ATA or OLD. Ghost will be killed later in 715 * attach routine. 716 */ 717 for (drive = 0; drive < 2; drive++) { 718 if ((ret_value & (0x01 << drive)) == 0) 719 continue; 720 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 721 chp->wdc->select(chp,drive); 722 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 723 WDSD_IBM | (drive << 4)); 724 delay(10); /* 400ns delay */ 725 /* Save registers contents */ 726 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 727 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 728 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 729 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 730 731 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 732 "cl=0x%x ch=0x%x\n", 733 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 734 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 735 /* 736 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 737 * we get wrong values here, so ignore it. 738 */ 739 if (cl == 0x14 && ch == 0xeb) { 740 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 741 } else { 742 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 743 if (chp->wdc == NULL || 744 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 745 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 746 } 747 } 748 return (ret_value); 749 } 750 751 void 752 wdcattach(chp) 753 struct channel_softc *chp; 754 { 755 static int inited = 0; 756 757 if (chp->ch_flags & WDCF_DISABLED) 758 return; 759 760 /* initialise global data */ 761 callout_init(&chp->ch_callout); 762 if (inited == 0) { 763 /* Initialize the wdc_xfer pool. */ 764 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 765 0, 0, "wdcspl", NULL); 766 inited++; 767 } 768 TAILQ_INIT(&chp->ch_queue->sc_xfer); 769 chp->ch_queue->queue_freese = 0; 770 771 config_found(&chp->wdc->sc_dev, chp, atabusprint); 772 } 773 774 /* 775 * Call activate routine of underlying devices. 776 */ 777 int 778 atabusactivate(self, act) 779 struct device *self; 780 enum devact act; 781 { 782 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 783 struct channel_softc *chp = atabus_sc->sc_chan; 784 struct device *sc = 0; 785 int s, i, error = 0; 786 787 s = splbio(); 788 switch (act) { 789 case DVACT_ACTIVATE: 790 error = EOPNOTSUPP; 791 break; 792 793 case DVACT_DEACTIVATE: 794 /* 795 * We might call deactivate routine for 796 * the children of atapibus twice (once via 797 * atapibus, once directly), but since 798 * config_deactivate maintains DVF_ACTIVE flag, 799 * it's safe. 800 */ 801 sc = chp->atapibus; 802 if (sc != NULL) { 803 error = config_deactivate(sc); 804 if (error != 0) 805 goto out; 806 } 807 808 for (i = 0; i < 2; i++) { 809 sc = chp->ch_drive[i].drv_softc; 810 WDCDEBUG_PRINT(("atabusactivate: %s:" 811 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 812 sc == NULL ? "nodrv" : sc->dv_xname), 813 DEBUG_DETACH); 814 if (sc != NULL) { 815 error = config_deactivate(sc); 816 if (error != 0) 817 goto out; 818 } 819 } 820 break; 821 } 822 823 out: 824 splx(s); 825 826 #ifdef WDCDEBUG 827 if (sc && error != 0) 828 WDCDEBUG_PRINT(("atabusactivate: %s: " 829 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 830 error, sc->dv_xname), DEBUG_DETACH); 831 #endif 832 return (error); 833 } 834 835 int wdcactivate(self, act) 836 struct device *self; 837 enum devact act; 838 { 839 struct wdc_softc *wdc = (struct wdc_softc *)self; 840 int s, i, error = 0; 841 842 s = splbio(); 843 switch (act) { 844 case DVACT_ACTIVATE: 845 error = EOPNOTSUPP; 846 break; 847 848 case DVACT_DEACTIVATE: 849 for (i = 0; i < wdc->nchannels; i++) { 850 error = config_deactivate(wdc->channels[i]->atabus); 851 if (error) 852 break; 853 } 854 break; 855 } 856 splx(s); 857 return (error); 858 } 859 860 861 int 862 atabusdetach(self, flags) 863 struct device *self; 864 int flags; 865 { 866 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 867 struct channel_softc *chp = atabus_sc->sc_chan; 868 struct device *sc = 0; 869 int i, error = 0; 870 871 /* shutdown channel */ 872 chp->ch_flags |= WDCF_SHUTDOWN; 873 wakeup(&chp); 874 while (chp->thread != NULL) 875 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 876 877 /* 878 * Detach atapibus and its children. 879 */ 880 sc = chp->atapibus; 881 if (sc != NULL) { 882 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 883 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 884 error = config_detach(sc, flags); 885 if (error != 0) 886 goto out; 887 } 888 889 /* 890 * Detach our other children. 891 */ 892 for (i = 0; i < 2; i++) { 893 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 894 continue; 895 sc = chp->ch_drive[i].drv_softc; 896 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 897 atabus_sc->sc_dev.dv_xname, 898 sc == NULL ? "nodrv" : sc->dv_xname), 899 DEBUG_DETACH); 900 if (sc != NULL) { 901 error = config_detach(sc, flags); 902 if (error != 0) 903 goto out; 904 } 905 } 906 907 wdc_kill_pending(chp); 908 909 out: 910 #ifdef WDCDEBUG 911 if (sc && error != 0) 912 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 913 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 914 DEBUG_DETACH); 915 #endif 916 return (error); 917 } 918 919 int 920 wdcdetach(self, flags) 921 struct device *self; 922 int flags; 923 { 924 struct wdc_softc *wdc = (struct wdc_softc *)self; 925 struct channel_softc *chp; 926 int i, error = 0; 927 928 for (i = 0; i < wdc->nchannels; i++) { 929 chp = wdc->channels[i]; 930 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 931 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 932 error = config_detach(chp->atabus, flags); 933 if (error) 934 break; 935 } 936 return (error); 937 } 938 939 /* 940 * Start I/O on a controller, for the given channel. 941 * The first xfer may be not for our channel if the channel queues 942 * are shared. 943 */ 944 void 945 wdcstart(chp) 946 struct channel_softc *chp; 947 { 948 struct wdc_xfer *xfer; 949 950 #ifdef WDC_DIAGNOSTIC 951 int spl1, spl2; 952 953 spl1 = splbio(); 954 spl2 = splbio(); 955 if (spl2 != spl1) { 956 printf("wdcstart: not at splbio()\n"); 957 panic("wdcstart"); 958 } 959 splx(spl2); 960 splx(spl1); 961 #endif /* WDC_DIAGNOSTIC */ 962 963 /* is there a xfer ? */ 964 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 965 return; 966 967 /* adjust chp, in case we have a shared queue */ 968 chp = xfer->chp; 969 970 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 971 return; /* channel aleady active */ 972 } 973 if ((chp->ch_flags & WDCF_TH_RESET) != 0) { 974 return; /* a channel reset is pending */ 975 } 976 #ifdef DIAGNOSTIC 977 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 978 panic("wdcstart: channel waiting for irq"); 979 #endif 980 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 981 if (!(*chp->wdc->claim_hw)(chp, 0)) 982 return; 983 984 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 985 chp->channel, xfer->drive), DEBUG_XFERS); 986 chp->ch_flags |= WDCF_ACTIVE; 987 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 988 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 989 chp->ch_drive[xfer->drive].state = 0; 990 } 991 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 992 KASSERT(xfer->c_flags & C_POLL); 993 xfer->c_start(chp, xfer); 994 } 995 996 /* restart an interrupted I/O */ 997 void 998 wdcrestart(v) 999 void *v; 1000 { 1001 struct channel_softc *chp = v; 1002 int s; 1003 1004 s = splbio(); 1005 wdcstart(chp); 1006 splx(s); 1007 } 1008 1009 1010 /* 1011 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1012 * errors on the current operation, mark it done if necessary, and start the 1013 * next request. Also check for a partially done transfer, and continue with 1014 * the next chunk if so. 1015 */ 1016 int 1017 wdcintr(arg) 1018 void *arg; 1019 { 1020 struct channel_softc *chp = arg; 1021 struct wdc_xfer *xfer; 1022 int ret; 1023 1024 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1025 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1026 DEBUG_INTR); 1027 return (0); 1028 } 1029 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1030 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1031 /* try to clear the pending interrupt anyway */ 1032 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1033 return (0); 1034 } 1035 1036 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1037 xfer = chp->ch_queue->sc_xfer.tqh_first; 1038 if (chp->ch_flags & WDCF_DMA_WAIT) { 1039 chp->wdc->dma_status = 1040 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1041 xfer->drive, 0); 1042 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1043 /* IRQ not for us, not detected by DMA engine */ 1044 return 0; 1045 } 1046 chp->ch_flags &= ~WDCF_DMA_WAIT; 1047 } 1048 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1049 ret = xfer->c_intr(chp, xfer, 1); 1050 if (ret == 0) /* irq was not for us, still waiting for irq */ 1051 chp->ch_flags |= WDCF_IRQ_WAIT; 1052 return (ret); 1053 } 1054 1055 /* Put all disk in RESET state */ 1056 void 1057 wdc_reset_channel(drvp, flags) 1058 struct ata_drive_datas *drvp; 1059 int flags; 1060 { 1061 struct channel_softc *chp = drvp->chnl_softc; 1062 int drive; 1063 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1064 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1065 DEBUG_FUNCS); 1066 if ((chp->ch_flags & WDCF_TH_RUN) == 0 && 1067 (flags & AT_POLL) == 0) { 1068 chp->ch_flags |= WDCF_TH_RESET; 1069 wakeup(&chp->thread); 1070 return; 1071 } 1072 (void) wdcreset(chp, (flags & AT_POLL) ? RESET_POLL : RESET_SLEEP); 1073 for (drive = 0; drive < 2; drive++) { 1074 chp->ch_drive[drive].state = 0; 1075 } 1076 } 1077 1078 int 1079 wdcreset(chp, poll) 1080 struct channel_softc *chp; 1081 int poll; 1082 { 1083 int drv_mask1, drv_mask2; 1084 1085 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1086 chp->wdc->select(chp,0); 1087 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1088 WDSD_IBM); /* master */ 1089 delay(10); /* 400ns delay */ 1090 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1091 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1092 delay(2000); 1093 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1094 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1095 WDCTL_4BIT | WDCTL_IDS); 1096 delay(10); /* 400ns delay */ 1097 1098 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1099 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1100 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1101 (poll == RESET_SLEEP) ? 0 : 1); 1102 if (drv_mask2 != drv_mask1) { 1103 printf("%s channel %d: reset failed for", 1104 chp->wdc->sc_dev.dv_xname, chp->channel); 1105 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1106 printf(" drive 0"); 1107 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1108 printf(" drive 1"); 1109 printf("\n"); 1110 } 1111 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1112 return (drv_mask1 != drv_mask2) ? 1 : 0; 1113 } 1114 1115 static int 1116 __wdcwait_reset(chp, drv_mask, poll) 1117 struct channel_softc *chp; 1118 int drv_mask; 1119 { 1120 int timeout, nloop; 1121 u_int8_t st0, er0, st1, er1; 1122 #ifdef WDCDEBUG 1123 u_int8_t sc0, sn0, cl0, ch0; 1124 u_int8_t sc1, sn1, cl1, ch1; 1125 #endif 1126 1127 if (poll) 1128 nloop = WDCNDELAY_RST; 1129 else 1130 nloop = WDC_RESET_WAIT * hz / 1000; 1131 /* wait for BSY to deassert */ 1132 for (timeout = 0; timeout < nloop; timeout++) { 1133 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1134 chp->wdc->select(chp,0); 1135 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1136 WDSD_IBM); /* master */ 1137 delay(10); 1138 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1139 er0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1140 #ifdef WDCDEBUG 1141 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1142 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1143 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1144 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1145 #endif 1146 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1147 chp->wdc->select(chp,1); 1148 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1149 WDSD_IBM | 0x10); /* slave */ 1150 delay(10); 1151 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1152 er1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1153 #ifdef WDCDEBUG 1154 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1155 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1156 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1157 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1158 #endif 1159 1160 if ((drv_mask & 0x01) == 0) { 1161 /* no master */ 1162 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1163 /* No master, slave is ready, it's done */ 1164 goto end; 1165 } 1166 } else if ((drv_mask & 0x02) == 0) { 1167 /* no slave */ 1168 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1169 /* No slave, master is ready, it's done */ 1170 goto end; 1171 } 1172 } else { 1173 /* Wait for both master and slave to be ready */ 1174 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1175 goto end; 1176 } 1177 } 1178 if (poll) 1179 delay(WDCDELAY); 1180 else 1181 tsleep(&nloop, PRIBIO, "atarst", 1); 1182 } 1183 /* Reset timed out. Maybe it's because drv_mask was not right */ 1184 if (st0 & WDCS_BSY) 1185 drv_mask &= ~0x01; 1186 if (st1 & WDCS_BSY) 1187 drv_mask &= ~0x02; 1188 end: 1189 if (er0 != 0x01 && er0 != 0x81) 1190 drv_mask &= ~0x01; 1191 if (er1 != 0x01) 1192 drv_mask &= ~0x02; 1193 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1194 "cl=0x%x ch=0x%x\n", 1195 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1196 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1197 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1198 "cl=0x%x ch=0x%x\n", 1199 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1200 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1201 1202 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, " 1203 "st0=0x%x er0=0x%x, st1=0x%x er1=0x%x\n", 1204 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1205 st0, er0, st1, er1), DEBUG_PROBE); 1206 1207 return drv_mask; 1208 } 1209 1210 /* 1211 * Wait for a drive to be !BSY, and have mask in its status register. 1212 * return -1 for a timeout after "timeout" ms. 1213 */ 1214 int 1215 __wdcwait(chp, mask, bits, timeout) 1216 struct channel_softc *chp; 1217 int mask, bits, timeout; 1218 { 1219 u_char status; 1220 int time = 0; 1221 1222 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1223 :"none", chp->channel), DEBUG_STATUS); 1224 chp->ch_error = 0; 1225 1226 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1227 1228 for (;;) { 1229 chp->ch_status = status = 1230 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1231 if ((status & (WDCS_BSY | mask)) == bits) 1232 break; 1233 if (++time > timeout) { 1234 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1235 "status %x error %x (mask 0x%x bits 0x%x)\n", 1236 time, status, 1237 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1238 wd_error), mask, bits), 1239 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1240 return(WDCWAIT_TOUT); 1241 } 1242 delay(WDCDELAY); 1243 } 1244 #ifdef WDCDEBUG 1245 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1246 printf("__wdcwait: did busy-wait, time=%d\n", time); 1247 #endif 1248 if (status & WDCS_ERR) 1249 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1250 wd_error); 1251 #ifdef WDCNDELAY_DEBUG 1252 /* After autoconfig, there should be no long delays. */ 1253 if (!cold && time > WDCNDELAY_DEBUG) { 1254 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1255 if (xfer == NULL) 1256 printf("%s channel %d: warning: busy-wait took %dus\n", 1257 chp->wdc->sc_dev.dv_xname, chp->channel, 1258 WDCDELAY * time); 1259 else 1260 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1261 chp->wdc->sc_dev.dv_xname, chp->channel, 1262 xfer->drive, 1263 WDCDELAY * time); 1264 } 1265 #endif 1266 return(WDCWAIT_OK); 1267 } 1268 1269 /* 1270 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1271 * thread if possible 1272 */ 1273 int 1274 wdcwait(chp, mask, bits, timeout, flags) 1275 struct channel_softc *chp; 1276 int mask, bits, timeout, flags; 1277 { 1278 int error, i, timeout_hz = mstohz(timeout); 1279 1280 if (timeout_hz == 0 || 1281 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1282 error = __wdcwait(chp, mask, bits, timeout); 1283 else { 1284 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1285 if (error != 0) { 1286 if (chp->ch_flags & WDCF_TH_RUN) { 1287 /* 1288 * we're running in the channel thread context 1289 */ 1290 for (i = 0; i < timeout_hz; i++) { 1291 if (__wdcwait(chp, mask, bits, 1292 WDCDELAY_POLL) == 0) { 1293 error = 0; 1294 break; 1295 } 1296 tsleep(&chp, PRIBIO, "atapoll", 1); 1297 } 1298 } else { 1299 /* 1300 * we're probably in interrupt context, 1301 * ask the thread to come back here 1302 */ 1303 chp->ch_queue->queue_freese++; 1304 wakeup(&chp->thread); 1305 return(WDCWAIT_THR); 1306 } 1307 } 1308 } 1309 return(error); 1310 } 1311 1312 1313 /* 1314 * Busy-wait for DMA to complete 1315 */ 1316 int 1317 wdc_dmawait(chp, xfer, timeout) 1318 struct channel_softc *chp; 1319 struct wdc_xfer *xfer; 1320 int timeout; 1321 { 1322 int time; 1323 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1324 chp->wdc->dma_status = 1325 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1326 chp->channel, xfer->drive, 0); 1327 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1328 return 0; 1329 delay(WDCDELAY); 1330 } 1331 /* timeout, force a DMA halt */ 1332 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1333 chp->channel, xfer->drive, 1); 1334 return 1; 1335 } 1336 1337 void 1338 wdctimeout(arg) 1339 void *arg; 1340 { 1341 struct channel_softc *chp = (struct channel_softc *)arg; 1342 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1343 int s; 1344 1345 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1346 1347 s = splbio(); 1348 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1349 __wdcerror(chp, "lost interrupt"); 1350 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1351 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1352 xfer->c_bcount, 1353 xfer->c_skip); 1354 if (chp->ch_flags & WDCF_DMA_WAIT) { 1355 chp->wdc->dma_status = 1356 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1357 chp->channel, xfer->drive, 1); 1358 chp->ch_flags &= ~WDCF_DMA_WAIT; 1359 } 1360 /* 1361 * Call the interrupt routine. If we just missed an interrupt, 1362 * it will do what's needed. Else, it will take the needed 1363 * action (reset the device). 1364 * Before that we need to reinstall the timeout callback, 1365 * in case it will miss another irq while in this transfer 1366 * We arbitray chose it to be 1s 1367 */ 1368 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1369 xfer->c_flags |= C_TIMEOU; 1370 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1371 xfer->c_intr(chp, xfer, 1); 1372 } else 1373 __wdcerror(chp, "missing untimeout"); 1374 splx(s); 1375 } 1376 1377 /* 1378 * Probe drive's capabilites, for use by the controller later 1379 * Assumes drvp points to an existing drive. 1380 * XXX this should be a controller-indep function 1381 */ 1382 void 1383 wdc_probe_caps(drvp) 1384 struct ata_drive_datas *drvp; 1385 { 1386 struct ataparams params, params2; 1387 struct channel_softc *chp = drvp->chnl_softc; 1388 struct device *drv_dev = drvp->drv_softc; 1389 struct wdc_softc *wdc = chp->wdc; 1390 int i, printed; 1391 char *sep = ""; 1392 int cf_flags; 1393 1394 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1395 /* IDENTIFY failed. Can't tell more about the device */ 1396 return; 1397 } 1398 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1399 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1400 /* 1401 * Controller claims 16 and 32 bit transfers. 1402 * Re-do an IDENTIFY with 32-bit transfers, 1403 * and compare results. 1404 */ 1405 drvp->drive_flags |= DRIVE_CAP32; 1406 ata_get_params(drvp, AT_WAIT, ¶ms2); 1407 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1408 /* Not good. fall back to 16bits */ 1409 drvp->drive_flags &= ~DRIVE_CAP32; 1410 } else { 1411 aprint_normal("%s: 32-bit data port\n", 1412 drv_dev->dv_xname); 1413 } 1414 } 1415 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1416 if (params.atap_ata_major > 0x01 && 1417 params.atap_ata_major != 0xffff) { 1418 for (i = 14; i > 0; i--) { 1419 if (params.atap_ata_major & (1 << i)) { 1420 aprint_normal("%s: ATA version %d\n", 1421 drv_dev->dv_xname, i); 1422 drvp->ata_vers = i; 1423 break; 1424 } 1425 } 1426 } 1427 #endif 1428 1429 /* An ATAPI device is at last PIO mode 3 */ 1430 if (drvp->drive_flags & DRIVE_ATAPI) 1431 drvp->PIO_mode = 3; 1432 1433 /* 1434 * It's not in the specs, but it seems that some drive 1435 * returns 0xffff in atap_extensions when this field is invalid 1436 */ 1437 if (params.atap_extensions != 0xffff && 1438 (params.atap_extensions & WDC_EXT_MODES)) { 1439 printed = 0; 1440 /* 1441 * XXX some drives report something wrong here (they claim to 1442 * support PIO mode 8 !). As mode is coded on 3 bits in 1443 * SET FEATURE, limit it to 7 (so limit i to 4). 1444 * If higher mode than 7 is found, abort. 1445 */ 1446 for (i = 7; i >= 0; i--) { 1447 if ((params.atap_piomode_supp & (1 << i)) == 0) 1448 continue; 1449 if (i > 4) 1450 return; 1451 /* 1452 * See if mode is accepted. 1453 * If the controller can't set its PIO mode, 1454 * assume the defaults are good, so don't try 1455 * to set it 1456 */ 1457 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1458 /* 1459 * It's OK to pool here, it's fast enouth 1460 * to not bother waiting for interrupt 1461 */ 1462 if (ata_set_mode(drvp, 0x08 | (i + 3), 1463 AT_WAIT) != CMD_OK) 1464 continue; 1465 if (!printed) { 1466 aprint_normal("%s: drive supports PIO mode %d", 1467 drv_dev->dv_xname, i + 3); 1468 sep = ","; 1469 printed = 1; 1470 } 1471 /* 1472 * If controller's driver can't set its PIO mode, 1473 * get the highter one for the drive. 1474 */ 1475 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1476 wdc->PIO_cap >= i + 3) { 1477 drvp->PIO_mode = i + 3; 1478 drvp->PIO_cap = i + 3; 1479 break; 1480 } 1481 } 1482 if (!printed) { 1483 /* 1484 * We didn't find a valid PIO mode. 1485 * Assume the values returned for DMA are buggy too 1486 */ 1487 return; 1488 } 1489 drvp->drive_flags |= DRIVE_MODE; 1490 printed = 0; 1491 for (i = 7; i >= 0; i--) { 1492 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1493 continue; 1494 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1495 (wdc->cap & WDC_CAPABILITY_MODE)) 1496 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1497 != CMD_OK) 1498 continue; 1499 if (!printed) { 1500 aprint_normal("%s DMA mode %d", sep, i); 1501 sep = ","; 1502 printed = 1; 1503 } 1504 if (wdc->cap & WDC_CAPABILITY_DMA) { 1505 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1506 wdc->DMA_cap < i) 1507 continue; 1508 drvp->DMA_mode = i; 1509 drvp->DMA_cap = i; 1510 drvp->drive_flags |= DRIVE_DMA; 1511 } 1512 break; 1513 } 1514 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1515 printed = 0; 1516 for (i = 7; i >= 0; i--) { 1517 if ((params.atap_udmamode_supp & (1 << i)) 1518 == 0) 1519 continue; 1520 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1521 (wdc->cap & WDC_CAPABILITY_UDMA)) 1522 if (ata_set_mode(drvp, 0x40 | i, 1523 AT_WAIT) != CMD_OK) 1524 continue; 1525 if (!printed) { 1526 aprint_normal("%s Ultra-DMA mode %d", 1527 sep, i); 1528 if (i == 2) 1529 aprint_normal(" (Ultra/33)"); 1530 else if (i == 4) 1531 aprint_normal(" (Ultra/66)"); 1532 else if (i == 5) 1533 aprint_normal(" (Ultra/100)"); 1534 else if (i == 6) 1535 aprint_normal(" (Ultra/133)"); 1536 sep = ","; 1537 printed = 1; 1538 } 1539 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1540 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1541 wdc->UDMA_cap < i) 1542 continue; 1543 drvp->UDMA_mode = i; 1544 drvp->UDMA_cap = i; 1545 drvp->drive_flags |= DRIVE_UDMA; 1546 } 1547 break; 1548 } 1549 } 1550 aprint_normal("\n"); 1551 } 1552 1553 /* Try to guess ATA version here, if it didn't get reported */ 1554 if (drvp->ata_vers == 0) { 1555 if (drvp->drive_flags & DRIVE_UDMA) 1556 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1557 else if (drvp->PIO_cap > 2) 1558 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1559 } 1560 cf_flags = drv_dev->dv_cfdata->cf_flags; 1561 if (cf_flags & ATA_CONFIG_PIO_SET) { 1562 drvp->PIO_mode = 1563 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1564 drvp->drive_flags |= DRIVE_MODE; 1565 } 1566 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1567 /* don't care about DMA modes */ 1568 return; 1569 } 1570 if (cf_flags & ATA_CONFIG_DMA_SET) { 1571 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1572 ATA_CONFIG_DMA_DISABLE) { 1573 drvp->drive_flags &= ~DRIVE_DMA; 1574 } else { 1575 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1576 ATA_CONFIG_DMA_OFF; 1577 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1578 } 1579 } 1580 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1581 /* don't care about UDMA modes */ 1582 return; 1583 } 1584 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1585 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1586 ATA_CONFIG_UDMA_DISABLE) { 1587 drvp->drive_flags &= ~DRIVE_UDMA; 1588 } else { 1589 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1590 ATA_CONFIG_UDMA_OFF; 1591 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1592 } 1593 } 1594 } 1595 1596 /* 1597 * downgrade the transfer mode of a drive after an error. return 1 if 1598 * downgrade was possible, 0 otherwise. 1599 */ 1600 int 1601 wdc_downgrade_mode(drvp, flags) 1602 struct ata_drive_datas *drvp; 1603 { 1604 struct channel_softc *chp = drvp->chnl_softc; 1605 struct device *drv_dev = drvp->drv_softc; 1606 struct wdc_softc *wdc = chp->wdc; 1607 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1608 1609 /* if drive or controller don't know its mode, we can't do much */ 1610 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1611 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1612 return 0; 1613 /* current drive mode was set by a config flag, let it this way */ 1614 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1615 (cf_flags & ATA_CONFIG_DMA_SET) || 1616 (cf_flags & ATA_CONFIG_UDMA_SET)) 1617 return 0; 1618 1619 /* 1620 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1621 * Maybe we didn't properly notice the cable type 1622 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1623 * It helps in some cases. 1624 */ 1625 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1626 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1627 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1628 drv_dev->dv_xname, drvp->UDMA_mode); 1629 } 1630 1631 /* 1632 * If we were using ultra-DMA, don't downgrade to multiword DMA 1633 * if we noticed a CRC error. It has been noticed that CRC errors 1634 * in ultra-DMA lead to silent data corruption in multiword DMA. 1635 * Data corruption is less likely to occur in PIO mode. 1636 */ 1637 else if ((drvp->drive_flags & DRIVE_UDMA) && 1638 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1639 drvp->drive_flags &= ~DRIVE_UDMA; 1640 drvp->drive_flags |= DRIVE_DMA; 1641 drvp->DMA_mode = drvp->DMA_cap; 1642 printf("%s: transfer error, downgrading to DMA mode %d\n", 1643 drv_dev->dv_xname, drvp->DMA_mode); 1644 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1645 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1646 drvp->PIO_mode = drvp->PIO_cap; 1647 printf("%s: transfer error, downgrading to PIO mode %d\n", 1648 drv_dev->dv_xname, drvp->PIO_mode); 1649 } else /* already using PIO, can't downgrade */ 1650 return 0; 1651 1652 wdc->set_modes(chp); 1653 wdc_print_modes(chp); 1654 /* reset the channel, which will shedule all drives for setup */ 1655 wdc_reset_channel(drvp, flags); 1656 return 1; 1657 } 1658 1659 int 1660 wdc_exec_command(drvp, wdc_c) 1661 struct ata_drive_datas *drvp; 1662 struct wdc_command *wdc_c; 1663 { 1664 struct channel_softc *chp = drvp->chnl_softc; 1665 struct wdc_xfer *xfer; 1666 int s, ret; 1667 1668 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1669 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1670 DEBUG_FUNCS); 1671 1672 /* set up an xfer and queue. Wait for completion */ 1673 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1674 WDC_NOSLEEP); 1675 if (xfer == NULL) { 1676 return WDC_TRY_AGAIN; 1677 } 1678 1679 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1680 wdc_c->flags |= AT_POLL; 1681 if (wdc_c->flags & AT_POLL) 1682 xfer->c_flags |= C_POLL; 1683 xfer->drive = drvp->drive; 1684 xfer->databuf = wdc_c->data; 1685 xfer->c_bcount = wdc_c->bcount; 1686 xfer->cmd = wdc_c; 1687 xfer->c_start = __wdccommand_start; 1688 xfer->c_intr = __wdccommand_intr; 1689 xfer->c_kill_xfer = __wdccommand_done; 1690 1691 s = splbio(); 1692 wdc_exec_xfer(chp, xfer); 1693 #ifdef DIAGNOSTIC 1694 if ((wdc_c->flags & AT_POLL) != 0 && 1695 (wdc_c->flags & AT_DONE) == 0) 1696 panic("wdc_exec_command: polled command not done"); 1697 #endif 1698 if (wdc_c->flags & AT_DONE) { 1699 ret = WDC_COMPLETE; 1700 } else { 1701 if (wdc_c->flags & AT_WAIT) { 1702 while ((wdc_c->flags & AT_DONE) == 0) { 1703 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1704 } 1705 ret = WDC_COMPLETE; 1706 } else { 1707 ret = WDC_QUEUED; 1708 } 1709 } 1710 splx(s); 1711 return ret; 1712 } 1713 1714 void 1715 __wdccommand_start(chp, xfer) 1716 struct channel_softc *chp; 1717 struct wdc_xfer *xfer; 1718 { 1719 int drive = xfer->drive; 1720 struct wdc_command *wdc_c = xfer->cmd; 1721 int st; 1722 1723 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1724 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1725 DEBUG_FUNCS); 1726 1727 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1728 chp->wdc->select(chp,drive); 1729 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1730 WDSD_IBM | (drive << 4)); 1731 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1732 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1733 case WDCWAIT_OK: 1734 break; 1735 case WDCWAIT_TOUT: 1736 wdc_c->flags |= AT_TIMEOU; 1737 __wdccommand_done(chp, xfer); 1738 return; 1739 case WDCWAIT_THR: 1740 return; 1741 } 1742 if (wdc_c->flags & AT_POLL) { 1743 /* polled command, disable interrupts */ 1744 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1745 WDCTL_4BIT | WDCTL_IDS); 1746 } 1747 if (wdc_c->flags & AT_POLL) { 1748 /* polled command, disable interrupts */ 1749 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1750 WDCTL_4BIT | WDCTL_IDS); 1751 } 1752 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1753 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1754 if ((wdc_c->flags & (AT_WAIT | AT_POLL | AT_READ)) == 1755 (AT_WAIT | AT_POLL | AT_READ)) { 1756 /* 1757 * This is a data in command, so we should have either 1758 * BSY or DRQ in 400ns, or error. 1759 */ 1760 delay(10); /* 400ns delay */ 1761 st = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1762 if (st == 0) { 1763 wdc_c->flags |= AT_TIMEOU; 1764 __wdccommand_done(chp, xfer); 1765 return; 1766 } 1767 } 1768 if ((wdc_c->flags & AT_POLL) == 0) { 1769 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1770 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1771 wdctimeout, chp); 1772 return; 1773 } 1774 /* 1775 * Polled command. Wait for drive ready or drq. Done in intr(). 1776 * Wait for at last 400ns for status bit to be valid. 1777 */ 1778 delay(10); /* 400ns delay */ 1779 __wdccommand_intr(chp, xfer, 0); 1780 } 1781 1782 int 1783 __wdccommand_intr(chp, xfer, irq) 1784 struct channel_softc *chp; 1785 struct wdc_xfer *xfer; 1786 int irq; 1787 { 1788 struct wdc_command *wdc_c = xfer->cmd; 1789 int bcount = wdc_c->bcount; 1790 char *data = wdc_c->data; 1791 int wflags; 1792 1793 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1794 /* both wait and poll, we can tsleep here */ 1795 wflags = 0; 1796 } else { 1797 wflags = AT_POLL; 1798 } 1799 1800 again: 1801 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1802 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1803 /* 1804 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1805 * Reselect again, it doesn't hurt for others commands, and the time 1806 * penalty for the extra regiter write is acceptable, 1807 * wdc_exec_command() isn't called often (mosly for autoconfig) 1808 */ 1809 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1810 WDSD_IBM | (xfer->drive << 4)); 1811 if ((wdc_c->flags & AT_XFDONE) != 0) { 1812 /* 1813 * We have completed a data xfer. The drive should now be 1814 * in its initial state 1815 */ 1816 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1817 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1818 wflags) == WDCWAIT_TOUT) { 1819 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1820 return 0; /* IRQ was not for us */ 1821 wdc_c->flags |= AT_TIMEOU; 1822 } 1823 goto out; 1824 } 1825 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1826 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1827 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1828 return 0; /* IRQ was not for us */ 1829 wdc_c->flags |= AT_TIMEOU; 1830 goto out; 1831 } 1832 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1833 chp->wdc->irqack(chp); 1834 if (wdc_c->flags & AT_READ) { 1835 if ((chp->ch_status & WDCS_DRQ) == 0) { 1836 wdc_c->flags |= AT_TIMEOU; 1837 goto out; 1838 } 1839 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1840 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1841 0, (u_int32_t*)data, bcount >> 2); 1842 data += bcount & 0xfffffffc; 1843 bcount = bcount & 0x03; 1844 } 1845 if (bcount > 0) 1846 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1847 wd_data, (u_int16_t *)data, bcount >> 1); 1848 /* at this point the drive should be in its initial state */ 1849 wdc_c->flags |= AT_XFDONE; 1850 /* XXX should read status register here ? */ 1851 } else if (wdc_c->flags & AT_WRITE) { 1852 if ((chp->ch_status & WDCS_DRQ) == 0) { 1853 wdc_c->flags |= AT_TIMEOU; 1854 goto out; 1855 } 1856 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1857 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1858 0, (u_int32_t*)data, bcount >> 2); 1859 data += bcount & 0xfffffffc; 1860 bcount = bcount & 0x03; 1861 } 1862 if (bcount > 0) 1863 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1864 wd_data, (u_int16_t *)data, bcount >> 1); 1865 wdc_c->flags |= AT_XFDONE; 1866 if ((wdc_c->flags & AT_POLL) == 0) { 1867 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1868 callout_reset(&chp->ch_callout, 1869 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1870 return 1; 1871 } else { 1872 goto again; 1873 } 1874 } 1875 out: 1876 __wdccommand_done(chp, xfer); 1877 return 1; 1878 } 1879 1880 void 1881 __wdccommand_done(chp, xfer) 1882 struct channel_softc *chp; 1883 struct wdc_xfer *xfer; 1884 { 1885 struct wdc_command *wdc_c = xfer->cmd; 1886 1887 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1888 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1889 1890 callout_stop(&chp->ch_callout); 1891 1892 if (chp->ch_status & WDCS_DWF) 1893 wdc_c->flags |= AT_DF; 1894 if (chp->ch_status & WDCS_ERR) { 1895 wdc_c->flags |= AT_ERROR; 1896 wdc_c->r_error = chp->ch_error; 1897 } 1898 wdc_c->flags |= AT_DONE; 1899 if ((wdc_c->flags & AT_READREG) != 0 && 1900 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1901 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1902 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1903 wd_sdh); 1904 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1905 wd_cyl_hi) << 8; 1906 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1907 wd_cyl_lo); 1908 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1909 wd_sector); 1910 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1911 wd_seccnt); 1912 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1913 wd_error); 1914 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1915 wd_precomp); 1916 } 1917 1918 if (wdc_c->flags & AT_POLL) { 1919 /* enable interrupts */ 1920 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1921 WDCTL_4BIT); 1922 } 1923 wdc_free_xfer(chp, xfer); 1924 if (wdc_c->flags & AT_WAIT) 1925 wakeup(wdc_c); 1926 else if (wdc_c->callback) 1927 wdc_c->callback(wdc_c->callback_arg); 1928 wdcstart(chp); 1929 return; 1930 } 1931 1932 /* 1933 * Send a command. The drive should be ready. 1934 * Assumes interrupts are blocked. 1935 */ 1936 void 1937 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1938 struct channel_softc *chp; 1939 u_int8_t drive; 1940 u_int8_t command; 1941 u_int16_t cylin; 1942 u_int8_t head, sector, count, precomp; 1943 { 1944 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1945 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1946 chp->channel, drive, command, cylin, head, sector, count, precomp), 1947 DEBUG_FUNCS); 1948 1949 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1950 chp->wdc->select(chp,drive); 1951 1952 /* Select drive, head, and addressing mode. */ 1953 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1954 WDSD_IBM | (drive << 4) | head); 1955 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1956 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1957 precomp); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1959 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1960 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1961 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1962 1963 /* Send command. */ 1964 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1965 return; 1966 } 1967 1968 /* 1969 * Send a 48-bit addressing command. The drive should be ready. 1970 * Assumes interrupts are blocked. 1971 */ 1972 void 1973 wdccommandext(chp, drive, command, blkno, count) 1974 struct channel_softc *chp; 1975 u_int8_t drive; 1976 u_int8_t command; 1977 u_int64_t blkno; 1978 u_int16_t count; 1979 { 1980 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1981 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1982 chp->channel, drive, command, (u_int32_t) blkno, count), 1983 DEBUG_FUNCS); 1984 1985 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1986 chp->wdc->select(chp,drive); 1987 1988 /* Select drive, head, and addressing mode. */ 1989 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1990 (drive << 4) | WDSD_LBA); 1991 1992 /* previous */ 1993 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1995 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1996 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1997 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1998 1999 /* current */ 2000 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 2001 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 2003 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 2004 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 2005 2006 /* Send command. */ 2007 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2008 return; 2009 } 2010 2011 /* 2012 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2013 * tested by the caller. 2014 */ 2015 void 2016 wdccommandshort(chp, drive, command) 2017 struct channel_softc *chp; 2018 int drive; 2019 int command; 2020 { 2021 2022 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2023 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2024 DEBUG_FUNCS); 2025 2026 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2027 chp->wdc->select(chp,drive); 2028 2029 /* Select drive. */ 2030 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2031 WDSD_IBM | (drive << 4)); 2032 2033 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2034 } 2035 2036 /* Add a command to the queue and start controller. Must be called at splbio */ 2037 2038 void 2039 wdc_exec_xfer(chp, xfer) 2040 struct channel_softc *chp; 2041 struct wdc_xfer *xfer; 2042 { 2043 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2044 chp->channel, xfer->drive), DEBUG_XFERS); 2045 2046 /* complete xfer setup */ 2047 xfer->chp = chp; 2048 2049 /* 2050 * If we are a polled command, and the list is not empty, 2051 * we are doing a dump. Drop the list to allow the polled command 2052 * to complete, we're going to reboot soon anyway. 2053 */ 2054 if ((xfer->c_flags & C_POLL) != 0 && 2055 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2056 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2057 } 2058 /* insert at the end of command list */ 2059 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2060 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2061 chp->ch_flags), DEBUG_XFERS); 2062 wdcstart(chp); 2063 } 2064 2065 struct wdc_xfer * 2066 wdc_get_xfer(flags) 2067 int flags; 2068 { 2069 struct wdc_xfer *xfer; 2070 int s; 2071 2072 s = splbio(); 2073 xfer = pool_get(&wdc_xfer_pool, 2074 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2075 splx(s); 2076 if (xfer != NULL) { 2077 memset(xfer, 0, sizeof(struct wdc_xfer)); 2078 } 2079 return xfer; 2080 } 2081 2082 void 2083 wdc_free_xfer(chp, xfer) 2084 struct channel_softc *chp; 2085 struct wdc_xfer *xfer; 2086 { 2087 struct wdc_softc *wdc = chp->wdc; 2088 int s; 2089 2090 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2091 (*wdc->free_hw)(chp); 2092 s = splbio(); 2093 chp->ch_flags &= ~WDCF_ACTIVE; 2094 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2095 pool_put(&wdc_xfer_pool, xfer); 2096 splx(s); 2097 } 2098 2099 /* 2100 * Kill off all pending xfers for a channel_softc. 2101 * 2102 * Must be called at splbio(). 2103 */ 2104 void 2105 wdc_kill_pending(chp) 2106 struct channel_softc *chp; 2107 { 2108 struct wdc_xfer *xfer; 2109 2110 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2111 chp = xfer->chp; 2112 (*xfer->c_kill_xfer)(chp, xfer); 2113 } 2114 } 2115 2116 static void 2117 __wdcerror(chp, msg) 2118 struct channel_softc *chp; 2119 char *msg; 2120 { 2121 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2122 2123 if (xfer == NULL) 2124 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2125 msg); 2126 else 2127 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2128 chp->channel, xfer->drive, msg); 2129 } 2130 2131 /* 2132 * the bit bucket 2133 */ 2134 void 2135 wdcbit_bucket(chp, size) 2136 struct channel_softc *chp; 2137 int size; 2138 { 2139 2140 for (; size >= 2; size -= 2) 2141 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2142 if (size) 2143 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2144 } 2145 2146 int 2147 wdc_addref(chp) 2148 struct channel_softc *chp; 2149 { 2150 struct wdc_softc *wdc = chp->wdc; 2151 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2152 int s, error = 0; 2153 2154 s = splbio(); 2155 if (adapt->adapt_refcnt++ == 0 && 2156 adapt->adapt_enable != NULL) { 2157 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2158 if (error) 2159 adapt->adapt_refcnt--; 2160 } 2161 splx(s); 2162 return (error); 2163 } 2164 2165 void 2166 wdc_delref(chp) 2167 struct channel_softc *chp; 2168 { 2169 struct wdc_softc *wdc = chp->wdc; 2170 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2171 int s; 2172 2173 s = splbio(); 2174 if (adapt->adapt_refcnt-- == 1 && 2175 adapt->adapt_enable != NULL) 2176 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2177 splx(s); 2178 } 2179 2180 void 2181 wdc_print_modes(struct channel_softc *chp) 2182 { 2183 int drive; 2184 struct ata_drive_datas *drvp; 2185 2186 for (drive = 0; drive < 2; drive++) { 2187 drvp = &chp->ch_drive[drive]; 2188 if ((drvp->drive_flags & DRIVE) == 0) 2189 continue; 2190 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2191 drvp->drv_softc->dv_xname, 2192 chp->wdc->sc_dev.dv_xname, 2193 chp->channel, drive, drvp->PIO_mode); 2194 if (drvp->drive_flags & DRIVE_DMA) 2195 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2196 if (drvp->drive_flags & DRIVE_UDMA) { 2197 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2198 if (drvp->UDMA_mode == 2) 2199 aprint_normal(" (Ultra/33)"); 2200 else if (drvp->UDMA_mode == 4) 2201 aprint_normal(" (Ultra/66)"); 2202 else if (drvp->UDMA_mode == 5) 2203 aprint_normal(" (Ultra/100)"); 2204 else if (drvp->UDMA_mode == 6) 2205 aprint_normal(" (Ultra/133)"); 2206 } 2207 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2208 aprint_normal(" (using DMA data transfers)"); 2209 aprint_normal("\n"); 2210 } 2211 } 2212
Indexes created Thu Sep 25 16:09:42 GMT 2025