wdc.c revision 1.143
1 /* $NetBSD: wdc.c,v 1.143 2003/10/15 20:29:26 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.143 2003/10/15 20:29:26 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 printf("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) 272 { 273 s = splbio(); 274 chp->ch_flags &= ~WDCF_TH_RUN; 275 tsleep(&chp->thread, PRIBIO, "atath", 0); 276 chp->ch_flags |= WDCF_TH_RUN; 277 splx(s); 278 if (chp->ch_flags & WDCF_SHUTDOWN) 279 break; 280 s = splbio(); 281 if (chp->ch_flags & WDCF_TH_RESET) { 282 int drive; 283 (void) wdcreset(chp, RESET_SLEEP); 284 for (drive = 0; drive < 2; drive++) { 285 chp->ch_drive[drive].state = 0; 286 } 287 chp->ch_flags &= ~WDCF_TH_RESET; 288 wdcstart(chp); 289 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 290 chp->ch_queue->queue_freese == 1) { 291 /* 292 * caller has bumped queue_freese, decrease it 293 */ 294 chp->ch_queue->queue_freese--; 295 xfer = chp->ch_queue->sc_xfer.tqh_first; 296 #ifdef DIAGNOSTIC 297 if (xfer == NULL) 298 panic("channel active with no xfer ?"); 299 #endif 300 xfer->c_start(chp, xfer); 301 } else if (chp->ch_queue->queue_freese > 1) { 302 panic("queue_freese"); 303 } 304 splx(s); 305 } 306 chp->thread = NULL; 307 wakeup(&chp->ch_flags); 308 kthread_exit(0); 309 } 310 311 void 312 atabusconfig(atabus_sc) 313 struct atabus_softc *atabus_sc; 314 { 315 struct channel_softc *chp = atabus_sc->sc_chan; 316 int ctrl_flags, i, error; 317 struct ataparams params; 318 struct atabus_initq *atabus_initq = NULL; 319 u_int8_t st0, st1; 320 321 if ((error = wdc_addref(chp)) != 0) { 322 aprint_error("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 config_pending_decr(); 325 return; 326 } 327 328 if (__wdcprobe(chp, 0) == 0) 329 /* If no drives, abort attach here. */ 330 goto out; 331 332 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 333 for (i = 0; i < mstohz(3000); i++) { 334 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 335 chp->wdc->select(chp,0); 336 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 337 WDSD_IBM); 338 delay(10); /* 400ns delay */ 339 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 340 341 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 342 chp->wdc->select(chp,1); 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 344 WDSD_IBM | 0x10); 345 delay(10); /* 400ns delay */ 346 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 347 348 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 349 == 0 || 350 (st0 & WDCS_DRDY)) && 351 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 352 == 0 || 353 (st1 & WDCS_DRDY))) 354 break; 355 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 356 } 357 if ((st0 & WDCS_DRDY) == 0) 358 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 359 if ((st1 & WDCS_DRDY) == 0) 360 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 361 362 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 363 chp->wdc->sc_dev.dv_xname, 364 chp->channel, st0, st1), DEBUG_PROBE); 365 366 /* Wait a bit, some devices are weird just after a reset. */ 367 delay(5000); 368 369 for (i = 0; i < 2; i++) { 370 chp->ch_drive[i].chnl_softc = chp; 371 chp->ch_drive[i].drive = i; 372 /* 373 * Init error counter so that an error withing the first xfers 374 * will trigger a downgrade 375 */ 376 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 377 378 /* If controller can't do 16bit flag the drives as 32bit */ 379 if ((chp->wdc->cap & 380 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 381 WDC_CAPABILITY_DATA32) 382 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 383 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 384 continue; 385 386 /* issue an identify, to try to detect ghosts */ 387 error = ata_get_params(&chp->ch_drive[i], 388 AT_WAIT | AT_POLL, ¶ms); 389 if (error != CMD_OK) { 390 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 391 error = ata_get_params(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL, ¶ms); 393 } 394 if (error == CMD_OK) { 395 /* If IDENTIFY succeded, this is not an OLD ctrl */ 396 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 397 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 398 } else { 399 chp->ch_drive[i].drive_flags &= 400 ~(DRIVE_ATA | DRIVE_ATAPI); 401 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 402 chp->wdc->sc_dev.dv_xname, 403 chp->channel, i, error), DEBUG_PROBE); 404 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 405 continue; 406 /* 407 * Pre-ATA drive ? 408 * Test registers writability (Error register not 409 * writable, but cyllo is), then try an ATA command. 410 */ 411 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 412 chp->wdc->select(chp,i); 413 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 414 WDSD_IBM | (i << 4)); 415 delay(10); /* 400ns delay */ 416 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 417 wd_error, 0x58); 418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 419 wd_cyl_lo, 0xa5); 420 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 421 wd_error) == 0x58 || 422 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 423 wd_cyl_lo) != 0xa5) { 424 WDCDEBUG_PRINT(("%s:%d:%d: register " 425 "writability failed\n", 426 chp->wdc->sc_dev.dv_xname, 427 chp->channel, i), DEBUG_PROBE); 428 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 429 } 430 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 431 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 432 chp->wdc->sc_dev.dv_xname, 433 chp->channel, i), DEBUG_PROBE); 434 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 435 continue; 436 } 437 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 438 wd_command, WDCC_RECAL); 439 delay(10); /* 400ns delay */ 440 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 441 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 442 chp->wdc->sc_dev.dv_xname, 443 chp->channel, i), DEBUG_PROBE); 444 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 445 } 446 } 447 } 448 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 449 450 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 451 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 452 DEBUG_PROBE); 453 454 /* If no drives, abort here */ 455 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 456 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 457 goto out; 458 459 /* Make sure the devices probe in atabus order to avoid jitter. */ 460 simple_lock(&atabus_interlock); 461 while(1) { 462 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 463 if (atabus_initq->atabus_sc == atabus_sc) 464 break; 465 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 466 &atabus_interlock); 467 } 468 simple_unlock(&atabus_interlock); 469 470 /* 471 * Attach an ATAPI bus, if needed. 472 */ 473 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 474 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 475 #if NATAPIBUS > 0 476 wdc_atapibus_attach(atabus_sc); 477 #else 478 /* 479 * Fake the autoconfig "not configured" message 480 */ 481 aprint_normal("atapibus at %s not configured\n", 482 chp->wdc->sc_dev.dv_xname); 483 chp->atapibus = NULL; 484 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 485 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 486 #endif 487 } 488 489 for (i = 0; i < 2; i++) { 490 struct ata_device adev; 491 if ((chp->ch_drive[i].drive_flags & 492 (DRIVE_ATA | DRIVE_OLD)) == 0) { 493 continue; 494 } 495 memset(&adev, 0, sizeof(struct ata_device)); 496 adev.adev_bustype = &wdc_ata_bustype; 497 adev.adev_channel = chp->channel; 498 adev.adev_openings = 1; 499 adev.adev_drv_data = &chp->ch_drive[i]; 500 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 501 &adev, wdprint); 502 if (chp->ata_drives[i] != NULL) 503 wdc_probe_caps(&chp->ch_drive[i]); 504 else 505 chp->ch_drive[i].drive_flags &= 506 ~(DRIVE_ATA | DRIVE_OLD); 507 } 508 509 /* now that we know the drives, the controller can set its modes */ 510 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 511 chp->wdc->set_modes(chp); 512 wdc_print_modes(chp); 513 } 514 #if NATARAID > 0 515 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 516 for (i = 0; i < 2; i++) 517 if (chp->ata_drives[i] != NULL) 518 ata_raid_check_component(chp->ata_drives[i]); 519 #endif /* NATARAID > 0 */ 520 521 /* 522 * reset drive_flags for unnatached devices, reset state for attached 523 * ones 524 */ 525 for (i = 0; i < 2; i++) { 526 if (chp->ch_drive[i].drv_softc == NULL) 527 chp->ch_drive[i].drive_flags = 0; 528 else 529 chp->ch_drive[i].state = 0; 530 } 531 532 out: 533 if (atabus_initq == NULL) { 534 simple_lock(&atabus_interlock); 535 while(1) { 536 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 537 if (atabus_initq->atabus_sc == atabus_sc) 538 break; 539 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 540 &atabus_interlock); 541 } 542 simple_unlock(&atabus_interlock); 543 } 544 simple_lock(&atabus_interlock); 545 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 546 simple_unlock(&atabus_interlock); 547 548 free(atabus_initq, M_DEVBUF); 549 wakeup(&atabus_initq_head); 550 551 config_pending_decr(); 552 wdc_delref(chp); 553 } 554 555 556 int 557 wdprint(aux, pnp) 558 void *aux; 559 const char *pnp; 560 { 561 struct ata_device *adev = aux; 562 if (pnp) 563 aprint_normal("wd at %s", pnp); 564 aprint_normal(" drive %d", adev->adev_drv_data->drive); 565 return (UNCONF); 566 } 567 568 /* Test to see controller with at last one attached drive is there. 569 * Returns a bit for each possible drive found (0x01 for drive 0, 570 * 0x02 for drive 1). 571 * Logic: 572 * - If a status register is at 0xff, assume there is no drive here 573 * (ISA has pull-up resistors). Similarly if the status register has 574 * the value we last wrote to the bus (for IDE interfaces without pullups). 575 * If no drive at all -> return. 576 * - reset the controller, wait for it to complete (may take up to 31s !). 577 * If timeout -> return. 578 * - test ATA/ATAPI signatures. If at last one drive found -> return. 579 * - try an ATA command on the master. 580 */ 581 582 int 583 wdcprobe(chp) 584 struct channel_softc *chp; 585 { 586 return __wdcprobe(chp, 1); 587 } 588 589 int 590 __wdcprobe(chp, poll) 591 struct channel_softc *chp; 592 int poll; 593 { 594 u_int8_t st0, st1, sc, sn, cl, ch; 595 u_int8_t ret_value = 0x03; 596 u_int8_t drive; 597 598 /* 599 * Sanity check to see if the wdc channel responds at all. 600 */ 601 602 if (chp->wdc == NULL || 603 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 604 605 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 606 chp->wdc->select(chp,0); 607 608 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 609 WDSD_IBM); 610 delay(10); /* 400ns delay */ 611 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 612 613 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 614 chp->wdc->select(chp,1); 615 616 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 617 WDSD_IBM | 0x10); 618 delay(10); /* 400ns delay */ 619 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 620 621 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 622 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 623 chp->channel, st0, st1), DEBUG_PROBE); 624 625 if (st0 == 0xff || st0 == WDSD_IBM) 626 ret_value &= ~0x01; 627 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 628 ret_value &= ~0x02; 629 /* Register writability test, drive 0. */ 630 if (ret_value & 0x01) { 631 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 632 chp->wdc->select(chp,0); 633 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 634 WDSD_IBM); 635 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 636 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 637 wd_cyl_lo) != 0x02) 638 ret_value &= ~0x01; 639 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 640 0x01); 641 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 642 wd_cyl_lo) != 0x01) 643 ret_value &= ~0x01; 644 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 645 0x01); 646 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 647 wd_sector) != 0x01) 648 ret_value &= ~0x01; 649 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 650 0x02); 651 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 652 wd_sector) != 0x02) 653 ret_value &= ~0x01; 654 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 655 wd_cyl_lo) != 0x01) 656 ret_value &= ~0x01; 657 } 658 /* Register writability test, drive 1. */ 659 if (ret_value & 0x02) { 660 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 661 chp->wdc->select(chp,1); 662 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 663 WDSD_IBM | 0x10); 664 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 665 0x02); 666 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 667 wd_cyl_lo) != 0x02) 668 ret_value &= ~0x02; 669 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 670 0x01); 671 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 672 wd_cyl_lo) != 0x01) 673 ret_value &= ~0x02; 674 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 675 0x01); 676 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 677 wd_sector) != 0x01) 678 ret_value &= ~0x02; 679 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 680 0x02); 681 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 682 wd_sector) != 0x02) 683 ret_value &= ~0x02; 684 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 685 wd_cyl_lo) != 0x01) 686 ret_value &= ~0x02; 687 } 688 689 if (ret_value == 0) 690 return 0; 691 } 692 693 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 694 chp->wdc->select(chp,0); 695 /* assert SRST, wait for reset to complete */ 696 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 697 WDSD_IBM); 698 delay(10); /* 400ns delay */ 699 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 700 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 701 DELAY(2000); 702 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 703 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 704 delay(10); /* 400ns delay */ 705 706 ret_value = __wdcwait_reset(chp, ret_value, poll); 707 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 708 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 709 ret_value), DEBUG_PROBE); 710 711 /* if reset failed, there's nothing here */ 712 if (ret_value == 0) 713 return 0; 714 715 /* 716 * Test presence of drives. First test register signatures looking for 717 * ATAPI devices. If it's not an ATAPI and reset said there may be 718 * something here assume it's ATA or OLD. Ghost will be killed later in 719 * attach routine. 720 */ 721 for (drive = 0; drive < 2; drive++) { 722 if ((ret_value & (0x01 << drive)) == 0) 723 continue; 724 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 725 chp->wdc->select(chp,drive); 726 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 727 WDSD_IBM | (drive << 4)); 728 delay(10); /* 400ns delay */ 729 /* Save registers contents */ 730 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 731 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 732 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 733 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 734 735 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 736 "cl=0x%x ch=0x%x\n", 737 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 738 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 739 /* 740 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 741 * we get wrong values here, so ignore it. 742 */ 743 if (cl == 0x14 && ch == 0xeb) { 744 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 745 } else { 746 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 747 if (chp->wdc == NULL || 748 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 749 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 750 } 751 } 752 return (ret_value); 753 } 754 755 void 756 wdcattach(chp) 757 struct channel_softc *chp; 758 { 759 static int inited = 0; 760 761 if (chp->ch_flags & WDCF_DISABLED) 762 return; 763 764 /* initialise global data */ 765 callout_init(&chp->ch_callout); 766 if (inited == 0) { 767 /* Initialize the wdc_xfer pool. */ 768 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 769 0, 0, "wdcspl", NULL); 770 inited++; 771 } 772 TAILQ_INIT(&chp->ch_queue->sc_xfer); 773 chp->ch_queue->queue_freese = 0; 774 775 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 776 } 777 778 /* 779 * Call activate routine of underlying devices. 780 */ 781 int 782 atabusactivate(self, act) 783 struct device *self; 784 enum devact act; 785 { 786 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 787 struct channel_softc *chp = atabus_sc->sc_chan; 788 struct device *sc = 0; 789 int s, i, error = 0; 790 791 s = splbio(); 792 switch (act) { 793 case DVACT_ACTIVATE: 794 error = EOPNOTSUPP; 795 break; 796 797 case DVACT_DEACTIVATE: 798 /* 799 * We might call deactivate routine for 800 * the children of atapibus twice (once via 801 * atapibus, once directly), but since 802 * config_deactivate maintains DVF_ACTIVE flag, 803 * it's safe. 804 */ 805 sc = chp->atapibus; 806 if (sc != NULL) { 807 error = config_deactivate(sc); 808 if (error != 0) 809 goto out; 810 } 811 812 for (i = 0; i < 2; i++) { 813 sc = chp->ch_drive[i].drv_softc; 814 WDCDEBUG_PRINT(("atabusactivate: %s:" 815 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 816 sc == NULL ? "nodrv" : sc->dv_xname), 817 DEBUG_DETACH); 818 if (sc != NULL) { 819 error = config_deactivate(sc); 820 if (error != 0) 821 goto out; 822 } 823 } 824 break; 825 } 826 827 out: 828 splx(s); 829 830 #ifdef WDCDEBUG 831 if (sc && error != 0) 832 WDCDEBUG_PRINT(("atabusactivate: %s: " 833 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 834 error, sc->dv_xname), DEBUG_DETACH); 835 #endif 836 return (error); 837 } 838 839 int wdcactivate(self, act) 840 struct device *self; 841 enum devact act; 842 { 843 struct wdc_softc *wdc = (struct wdc_softc *)self; 844 int s, i, error = 0; 845 846 s = splbio(); 847 switch (act) { 848 case DVACT_ACTIVATE: 849 error = EOPNOTSUPP; 850 break; 851 852 case DVACT_DEACTIVATE: 853 for (i = 0; i < wdc->nchannels; i++) { 854 error = config_deactivate(wdc->channels[i]->atabus); 855 if (error) 856 break; 857 } 858 break; 859 } 860 splx(s); 861 return (error); 862 } 863 864 865 int 866 atabusdetach(self, flags) 867 struct device *self; 868 int flags; 869 { 870 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 871 struct channel_softc *chp = atabus_sc->sc_chan; 872 struct device *sc = 0; 873 int i, error = 0; 874 875 /* shutdown channel */ 876 chp->ch_flags |= WDCF_SHUTDOWN; 877 wakeup(&chp->thread); 878 while (chp->thread != NULL) 879 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 880 881 /* 882 * Detach atapibus and its children. 883 */ 884 sc = chp->atapibus; 885 if (sc != NULL) { 886 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 887 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 888 error = config_detach(sc, flags); 889 if (error != 0) 890 goto out; 891 } 892 893 /* 894 * Detach our other children. 895 */ 896 for (i = 0; i < 2; i++) { 897 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 898 continue; 899 sc = chp->ch_drive[i].drv_softc; 900 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 901 atabus_sc->sc_dev.dv_xname, 902 sc == NULL ? "nodrv" : sc->dv_xname), 903 DEBUG_DETACH); 904 if (sc != NULL) { 905 error = config_detach(sc, flags); 906 if (error != 0) 907 goto out; 908 } 909 } 910 911 wdc_kill_pending(chp); 912 913 out: 914 #ifdef WDCDEBUG 915 if (sc && error != 0) 916 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 917 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 918 DEBUG_DETACH); 919 #endif 920 return (error); 921 } 922 923 int 924 wdcdetach(self, flags) 925 struct device *self; 926 int flags; 927 { 928 struct wdc_softc *wdc = (struct wdc_softc *)self; 929 struct channel_softc *chp; 930 int i, error = 0; 931 932 for (i = 0; i < wdc->nchannels; i++) { 933 chp = wdc->channels[i]; 934 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 935 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 936 error = config_detach(chp->atabus, flags); 937 if (error) 938 break; 939 } 940 return (error); 941 } 942 943 /* 944 * Start I/O on a controller, for the given channel. 945 * The first xfer may be not for our channel if the channel queues 946 * are shared. 947 */ 948 void 949 wdcstart(chp) 950 struct channel_softc *chp; 951 { 952 struct wdc_xfer *xfer; 953 954 #ifdef WDC_DIAGNOSTIC 955 int spl1, spl2; 956 957 spl1 = splbio(); 958 spl2 = splbio(); 959 if (spl2 != spl1) { 960 printf("wdcstart: not at splbio()\n"); 961 panic("wdcstart"); 962 } 963 splx(spl2); 964 splx(spl1); 965 #endif /* WDC_DIAGNOSTIC */ 966 967 /* is there a xfer ? */ 968 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 969 return; 970 971 /* adjust chp, in case we have a shared queue */ 972 chp = xfer->chp; 973 974 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 975 return; /* channel aleady active */ 976 } 977 if ((chp->ch_flags & WDCF_TH_RESET) != 0) { 978 return; /* a channel reset is pending */ 979 } 980 #ifdef DIAGNOSTIC 981 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 982 panic("wdcstart: channel waiting for irq"); 983 #endif 984 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 985 if (!(*chp->wdc->claim_hw)(chp, 0)) 986 return; 987 988 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 989 chp->channel, xfer->drive), DEBUG_XFERS); 990 chp->ch_flags |= WDCF_ACTIVE; 991 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 992 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 993 chp->ch_drive[xfer->drive].state = 0; 994 } 995 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 996 KASSERT(xfer->c_flags & C_POLL); 997 xfer->c_start(chp, xfer); 998 } 999 1000 /* restart an interrupted I/O */ 1001 void 1002 wdcrestart(v) 1003 void *v; 1004 { 1005 struct channel_softc *chp = v; 1006 int s; 1007 1008 s = splbio(); 1009 wdcstart(chp); 1010 splx(s); 1011 } 1012 1013 1014 /* 1015 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1016 * errors on the current operation, mark it done if necessary, and start the 1017 * next request. Also check for a partially done transfer, and continue with 1018 * the next chunk if so. 1019 */ 1020 int 1021 wdcintr(arg) 1022 void *arg; 1023 { 1024 struct channel_softc *chp = arg; 1025 struct wdc_xfer *xfer; 1026 int ret; 1027 1028 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1029 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1030 DEBUG_INTR); 1031 return (0); 1032 } 1033 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1034 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1035 /* try to clear the pending interrupt anyway */ 1036 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1037 return (0); 1038 } 1039 1040 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1041 xfer = chp->ch_queue->sc_xfer.tqh_first; 1042 if (chp->ch_flags & WDCF_DMA_WAIT) { 1043 chp->wdc->dma_status = 1044 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1045 xfer->drive, 0); 1046 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1047 /* IRQ not for us, not detected by DMA engine */ 1048 return 0; 1049 } 1050 chp->ch_flags &= ~WDCF_DMA_WAIT; 1051 } 1052 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1053 ret = xfer->c_intr(chp, xfer, 1); 1054 if (ret == 0) /* irq was not for us, still waiting for irq */ 1055 chp->ch_flags |= WDCF_IRQ_WAIT; 1056 return (ret); 1057 } 1058 1059 /* Put all disk in RESET state */ 1060 void 1061 wdc_reset_channel(drvp, flags) 1062 struct ata_drive_datas *drvp; 1063 int flags; 1064 { 1065 struct channel_softc *chp = drvp->chnl_softc; 1066 int drive; 1067 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1068 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1069 DEBUG_FUNCS); 1070 if ((chp->ch_flags & WDCF_TH_RUN) == 0 && 1071 (flags & AT_POLL) == 0) { 1072 chp->ch_flags |= WDCF_TH_RESET; 1073 wakeup(&chp->thread); 1074 return; 1075 } 1076 (void) wdcreset(chp, (flags & AT_POLL) ? RESET_POLL : RESET_SLEEP); 1077 for (drive = 0; drive < 2; drive++) { 1078 chp->ch_drive[drive].state = 0; 1079 } 1080 } 1081 1082 int 1083 wdcreset(chp, poll) 1084 struct channel_softc *chp; 1085 int poll; 1086 { 1087 int drv_mask1, drv_mask2; 1088 1089 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1090 chp->wdc->select(chp,0); 1091 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1092 WDSD_IBM); /* master */ 1093 delay(10); /* 400ns delay */ 1094 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1095 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1096 delay(2000); 1097 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1098 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1099 WDCTL_4BIT | WDCTL_IDS); 1100 delay(10); /* 400ns delay */ 1101 1102 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1103 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1104 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1105 (poll == RESET_SLEEP) ? 0 : 1); 1106 if (drv_mask2 != drv_mask1) { 1107 printf("%s channel %d: reset failed for", 1108 chp->wdc->sc_dev.dv_xname, chp->channel); 1109 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1110 printf(" drive 0"); 1111 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1112 printf(" drive 1"); 1113 printf("\n"); 1114 } 1115 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1116 return (drv_mask1 != drv_mask2) ? 1 : 0; 1117 } 1118 1119 static int 1120 __wdcwait_reset(chp, drv_mask, poll) 1121 struct channel_softc *chp; 1122 int drv_mask; 1123 { 1124 int timeout, nloop; 1125 u_int8_t st0, er0, st1, er1; 1126 #ifdef WDCDEBUG 1127 u_int8_t sc0, sn0, cl0, ch0; 1128 u_int8_t sc1, sn1, cl1, ch1; 1129 #endif 1130 1131 if (poll) 1132 nloop = WDCNDELAY_RST; 1133 else 1134 nloop = WDC_RESET_WAIT * hz / 1000; 1135 /* wait for BSY to deassert */ 1136 for (timeout = 0; timeout < nloop; timeout++) { 1137 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1138 chp->wdc->select(chp,0); 1139 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1140 WDSD_IBM); /* master */ 1141 delay(10); 1142 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1143 er0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1144 #ifdef WDCDEBUG 1145 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1146 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1147 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1148 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1149 #endif 1150 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1151 chp->wdc->select(chp,1); 1152 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1153 WDSD_IBM | 0x10); /* slave */ 1154 delay(10); 1155 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1156 er1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1157 #ifdef WDCDEBUG 1158 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1159 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1160 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1161 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1162 #endif 1163 1164 if ((drv_mask & 0x01) == 0) { 1165 /* no master */ 1166 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1167 /* No master, slave is ready, it's done */ 1168 goto end; 1169 } 1170 } else if ((drv_mask & 0x02) == 0) { 1171 /* no slave */ 1172 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1173 /* No slave, master is ready, it's done */ 1174 goto end; 1175 } 1176 } else { 1177 /* Wait for both master and slave to be ready */ 1178 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1179 goto end; 1180 } 1181 } 1182 if (poll) 1183 delay(WDCDELAY); 1184 else 1185 tsleep(&nloop, PRIBIO, "atarst", 1); 1186 } 1187 /* Reset timed out. Maybe it's because drv_mask was not right */ 1188 if (st0 & WDCS_BSY) 1189 drv_mask &= ~0x01; 1190 if (st1 & WDCS_BSY) 1191 drv_mask &= ~0x02; 1192 end: 1193 if (er0 != 0x01 && er0 != 0x81) 1194 drv_mask &= ~0x01; 1195 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1196 "cl=0x%x ch=0x%x\n", 1197 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1198 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1199 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1200 "cl=0x%x ch=0x%x\n", 1201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1202 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1203 1204 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, " 1205 "st0=0x%x er0=0x%x, st1=0x%x er1=0x%x\n", 1206 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1207 st0, er0, st1, er1), DEBUG_PROBE); 1208 1209 return drv_mask; 1210 } 1211 1212 /* 1213 * Wait for a drive to be !BSY, and have mask in its status register. 1214 * return -1 for a timeout after "timeout" ms. 1215 */ 1216 int 1217 __wdcwait(chp, mask, bits, timeout) 1218 struct channel_softc *chp; 1219 int mask, bits, timeout; 1220 { 1221 u_char status; 1222 int time = 0; 1223 1224 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1225 :"none", chp->channel), DEBUG_STATUS); 1226 chp->ch_error = 0; 1227 1228 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1229 1230 for (;;) { 1231 chp->ch_status = status = 1232 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1233 if ((status & (WDCS_BSY | mask)) == bits) 1234 break; 1235 if (++time > timeout) { 1236 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1237 "status %x error %x (mask 0x%x bits 0x%x)\n", 1238 time, status, 1239 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1240 wd_error), mask, bits), 1241 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1242 return(WDCWAIT_TOUT); 1243 } 1244 delay(WDCDELAY); 1245 } 1246 #ifdef WDCDEBUG 1247 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1248 printf("__wdcwait: did busy-wait, time=%d\n", time); 1249 #endif 1250 if (status & WDCS_ERR) 1251 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1252 wd_error); 1253 #ifdef WDCNDELAY_DEBUG 1254 /* After autoconfig, there should be no long delays. */ 1255 if (!cold && time > WDCNDELAY_DEBUG) { 1256 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1257 if (xfer == NULL) 1258 printf("%s channel %d: warning: busy-wait took %dus\n", 1259 chp->wdc->sc_dev.dv_xname, chp->channel, 1260 WDCDELAY * time); 1261 else 1262 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1263 chp->wdc->sc_dev.dv_xname, chp->channel, 1264 xfer->drive, 1265 WDCDELAY * time); 1266 } 1267 #endif 1268 return(WDCWAIT_OK); 1269 } 1270 1271 /* 1272 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1273 * thread if possible 1274 */ 1275 int 1276 wdcwait(chp, mask, bits, timeout, flags) 1277 struct channel_softc *chp; 1278 int mask, bits, timeout, flags; 1279 { 1280 int error, i, timeout_hz = mstohz(timeout); 1281 1282 if (timeout_hz == 0 || 1283 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1284 error = __wdcwait(chp, mask, bits, timeout); 1285 else { 1286 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1287 if (error != 0) { 1288 if (chp->ch_flags & WDCF_TH_RUN) { 1289 /* 1290 * we're running in the channel thread context 1291 */ 1292 for (i = 0; i < timeout_hz; i++) { 1293 if (__wdcwait(chp, mask, bits, 1294 WDCDELAY_POLL) == 0) { 1295 error = 0; 1296 break; 1297 } 1298 tsleep(&chp, PRIBIO, "atapoll", 1); 1299 } 1300 } else { 1301 /* 1302 * we're probably in interrupt context, 1303 * ask the thread to come back here 1304 */ 1305 chp->ch_queue->queue_freese++; 1306 wakeup(&chp->thread); 1307 return(WDCWAIT_THR); 1308 } 1309 } 1310 } 1311 return(error); 1312 } 1313 1314 1315 /* 1316 * Busy-wait for DMA to complete 1317 */ 1318 int 1319 wdc_dmawait(chp, xfer, timeout) 1320 struct channel_softc *chp; 1321 struct wdc_xfer *xfer; 1322 int timeout; 1323 { 1324 int time; 1325 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1326 chp->wdc->dma_status = 1327 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1328 chp->channel, xfer->drive, 0); 1329 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1330 return 0; 1331 delay(WDCDELAY); 1332 } 1333 /* timeout, force a DMA halt */ 1334 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1335 chp->channel, xfer->drive, 1); 1336 return 1; 1337 } 1338 1339 void 1340 wdctimeout(arg) 1341 void *arg; 1342 { 1343 struct channel_softc *chp = (struct channel_softc *)arg; 1344 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1345 int s; 1346 1347 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1348 1349 s = splbio(); 1350 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1351 __wdcerror(chp, "lost interrupt"); 1352 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1353 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1354 xfer->c_bcount, 1355 xfer->c_skip); 1356 if (chp->ch_flags & WDCF_DMA_WAIT) { 1357 chp->wdc->dma_status = 1358 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1359 chp->channel, xfer->drive, 1); 1360 chp->ch_flags &= ~WDCF_DMA_WAIT; 1361 } 1362 /* 1363 * Call the interrupt routine. If we just missed an interrupt, 1364 * it will do what's needed. Else, it will take the needed 1365 * action (reset the device). 1366 * Before that we need to reinstall the timeout callback, 1367 * in case it will miss another irq while in this transfer 1368 * We arbitray chose it to be 1s 1369 */ 1370 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1371 xfer->c_flags |= C_TIMEOU; 1372 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1373 xfer->c_intr(chp, xfer, 1); 1374 } else 1375 __wdcerror(chp, "missing untimeout"); 1376 splx(s); 1377 } 1378 1379 /* 1380 * Probe drive's capabilites, for use by the controller later 1381 * Assumes drvp points to an existing drive. 1382 * XXX this should be a controller-indep function 1383 */ 1384 void 1385 wdc_probe_caps(drvp) 1386 struct ata_drive_datas *drvp; 1387 { 1388 struct ataparams params, params2; 1389 struct channel_softc *chp = drvp->chnl_softc; 1390 struct device *drv_dev = drvp->drv_softc; 1391 struct wdc_softc *wdc = chp->wdc; 1392 int i, printed; 1393 char *sep = ""; 1394 int cf_flags; 1395 1396 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1397 /* IDENTIFY failed. Can't tell more about the device */ 1398 return; 1399 } 1400 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1401 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1402 /* 1403 * Controller claims 16 and 32 bit transfers. 1404 * Re-do an IDENTIFY with 32-bit transfers, 1405 * and compare results. 1406 */ 1407 drvp->drive_flags |= DRIVE_CAP32; 1408 ata_get_params(drvp, AT_WAIT, ¶ms2); 1409 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1410 /* Not good. fall back to 16bits */ 1411 drvp->drive_flags &= ~DRIVE_CAP32; 1412 } else { 1413 aprint_normal("%s: 32-bit data port\n", 1414 drv_dev->dv_xname); 1415 } 1416 } 1417 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1418 if (params.atap_ata_major > 0x01 && 1419 params.atap_ata_major != 0xffff) { 1420 for (i = 14; i > 0; i--) { 1421 if (params.atap_ata_major & (1 << i)) { 1422 aprint_normal("%s: ATA version %d\n", 1423 drv_dev->dv_xname, i); 1424 drvp->ata_vers = i; 1425 break; 1426 } 1427 } 1428 } 1429 #endif 1430 1431 /* An ATAPI device is at last PIO mode 3 */ 1432 if (drvp->drive_flags & DRIVE_ATAPI) 1433 drvp->PIO_mode = 3; 1434 1435 /* 1436 * It's not in the specs, but it seems that some drive 1437 * returns 0xffff in atap_extensions when this field is invalid 1438 */ 1439 if (params.atap_extensions != 0xffff && 1440 (params.atap_extensions & WDC_EXT_MODES)) { 1441 printed = 0; 1442 /* 1443 * XXX some drives report something wrong here (they claim to 1444 * support PIO mode 8 !). As mode is coded on 3 bits in 1445 * SET FEATURE, limit it to 7 (so limit i to 4). 1446 * If higher mode than 7 is found, abort. 1447 */ 1448 for (i = 7; i >= 0; i--) { 1449 if ((params.atap_piomode_supp & (1 << i)) == 0) 1450 continue; 1451 if (i > 4) 1452 return; 1453 /* 1454 * See if mode is accepted. 1455 * If the controller can't set its PIO mode, 1456 * assume the defaults are good, so don't try 1457 * to set it 1458 */ 1459 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1460 /* 1461 * It's OK to pool here, it's fast enouth 1462 * to not bother waiting for interrupt 1463 */ 1464 if (ata_set_mode(drvp, 0x08 | (i + 3), 1465 AT_WAIT) != CMD_OK) 1466 continue; 1467 if (!printed) { 1468 aprint_normal("%s: drive supports PIO mode %d", 1469 drv_dev->dv_xname, i + 3); 1470 sep = ","; 1471 printed = 1; 1472 } 1473 /* 1474 * If controller's driver can't set its PIO mode, 1475 * get the highter one for the drive. 1476 */ 1477 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1478 wdc->PIO_cap >= i + 3) { 1479 drvp->PIO_mode = i + 3; 1480 drvp->PIO_cap = i + 3; 1481 break; 1482 } 1483 } 1484 if (!printed) { 1485 /* 1486 * We didn't find a valid PIO mode. 1487 * Assume the values returned for DMA are buggy too 1488 */ 1489 return; 1490 } 1491 drvp->drive_flags |= DRIVE_MODE; 1492 printed = 0; 1493 for (i = 7; i >= 0; i--) { 1494 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1495 continue; 1496 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1497 (wdc->cap & WDC_CAPABILITY_MODE)) 1498 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1499 != CMD_OK) 1500 continue; 1501 if (!printed) { 1502 aprint_normal("%s DMA mode %d", sep, i); 1503 sep = ","; 1504 printed = 1; 1505 } 1506 if (wdc->cap & WDC_CAPABILITY_DMA) { 1507 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1508 wdc->DMA_cap < i) 1509 continue; 1510 drvp->DMA_mode = i; 1511 drvp->DMA_cap = i; 1512 drvp->drive_flags |= DRIVE_DMA; 1513 } 1514 break; 1515 } 1516 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1517 printed = 0; 1518 for (i = 7; i >= 0; i--) { 1519 if ((params.atap_udmamode_supp & (1 << i)) 1520 == 0) 1521 continue; 1522 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1523 (wdc->cap & WDC_CAPABILITY_UDMA)) 1524 if (ata_set_mode(drvp, 0x40 | i, 1525 AT_WAIT) != CMD_OK) 1526 continue; 1527 if (!printed) { 1528 aprint_normal("%s Ultra-DMA mode %d", 1529 sep, i); 1530 if (i == 2) 1531 aprint_normal(" (Ultra/33)"); 1532 else if (i == 4) 1533 aprint_normal(" (Ultra/66)"); 1534 else if (i == 5) 1535 aprint_normal(" (Ultra/100)"); 1536 else if (i == 6) 1537 aprint_normal(" (Ultra/133)"); 1538 sep = ","; 1539 printed = 1; 1540 } 1541 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1542 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1543 wdc->UDMA_cap < i) 1544 continue; 1545 drvp->UDMA_mode = i; 1546 drvp->UDMA_cap = i; 1547 drvp->drive_flags |= DRIVE_UDMA; 1548 } 1549 break; 1550 } 1551 } 1552 aprint_normal("\n"); 1553 } 1554 1555 /* Try to guess ATA version here, if it didn't get reported */ 1556 if (drvp->ata_vers == 0) { 1557 if (drvp->drive_flags & DRIVE_UDMA) 1558 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1559 else if (drvp->PIO_cap > 2) 1560 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1561 } 1562 cf_flags = drv_dev->dv_cfdata->cf_flags; 1563 if (cf_flags & ATA_CONFIG_PIO_SET) { 1564 drvp->PIO_mode = 1565 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1566 drvp->drive_flags |= DRIVE_MODE; 1567 } 1568 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1569 /* don't care about DMA modes */ 1570 return; 1571 } 1572 if (cf_flags & ATA_CONFIG_DMA_SET) { 1573 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1574 ATA_CONFIG_DMA_DISABLE) { 1575 drvp->drive_flags &= ~DRIVE_DMA; 1576 } else { 1577 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1578 ATA_CONFIG_DMA_OFF; 1579 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1580 } 1581 } 1582 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1583 /* don't care about UDMA modes */ 1584 return; 1585 } 1586 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1587 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1588 ATA_CONFIG_UDMA_DISABLE) { 1589 drvp->drive_flags &= ~DRIVE_UDMA; 1590 } else { 1591 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1592 ATA_CONFIG_UDMA_OFF; 1593 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1594 } 1595 } 1596 } 1597 1598 /* 1599 * downgrade the transfer mode of a drive after an error. return 1 if 1600 * downgrade was possible, 0 otherwise. 1601 */ 1602 int 1603 wdc_downgrade_mode(drvp, flags) 1604 struct ata_drive_datas *drvp; 1605 { 1606 struct channel_softc *chp = drvp->chnl_softc; 1607 struct device *drv_dev = drvp->drv_softc; 1608 struct wdc_softc *wdc = chp->wdc; 1609 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1610 1611 /* if drive or controller don't know its mode, we can't do much */ 1612 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1613 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1614 return 0; 1615 /* current drive mode was set by a config flag, let it this way */ 1616 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1617 (cf_flags & ATA_CONFIG_DMA_SET) || 1618 (cf_flags & ATA_CONFIG_UDMA_SET)) 1619 return 0; 1620 1621 /* 1622 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1623 * Maybe we didn't properly notice the cable type 1624 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1625 * It helps in some cases. 1626 */ 1627 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1628 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1629 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1630 drv_dev->dv_xname, drvp->UDMA_mode); 1631 } 1632 1633 /* 1634 * If we were using ultra-DMA, don't downgrade to multiword DMA 1635 * if we noticed a CRC error. It has been noticed that CRC errors 1636 * in ultra-DMA lead to silent data corruption in multiword DMA. 1637 * Data corruption is less likely to occur in PIO mode. 1638 */ 1639 else if ((drvp->drive_flags & DRIVE_UDMA) && 1640 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1641 drvp->drive_flags &= ~DRIVE_UDMA; 1642 drvp->drive_flags |= DRIVE_DMA; 1643 drvp->DMA_mode = drvp->DMA_cap; 1644 printf("%s: transfer error, downgrading to DMA mode %d\n", 1645 drv_dev->dv_xname, drvp->DMA_mode); 1646 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1647 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1648 drvp->PIO_mode = drvp->PIO_cap; 1649 printf("%s: transfer error, downgrading to PIO mode %d\n", 1650 drv_dev->dv_xname, drvp->PIO_mode); 1651 } else /* already using PIO, can't downgrade */ 1652 return 0; 1653 1654 wdc->set_modes(chp); 1655 wdc_print_modes(chp); 1656 /* reset the channel, which will shedule all drives for setup */ 1657 wdc_reset_channel(drvp, flags); 1658 return 1; 1659 } 1660 1661 int 1662 wdc_exec_command(drvp, wdc_c) 1663 struct ata_drive_datas *drvp; 1664 struct wdc_command *wdc_c; 1665 { 1666 struct channel_softc *chp = drvp->chnl_softc; 1667 struct wdc_xfer *xfer; 1668 int s, ret; 1669 1670 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1671 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1672 DEBUG_FUNCS); 1673 1674 /* set up an xfer and queue. Wait for completion */ 1675 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1676 WDC_NOSLEEP); 1677 if (xfer == NULL) { 1678 return WDC_TRY_AGAIN; 1679 } 1680 1681 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1682 wdc_c->flags |= AT_POLL; 1683 if (wdc_c->flags & AT_POLL) 1684 xfer->c_flags |= C_POLL; 1685 xfer->drive = drvp->drive; 1686 xfer->databuf = wdc_c->data; 1687 xfer->c_bcount = wdc_c->bcount; 1688 xfer->cmd = wdc_c; 1689 xfer->c_start = __wdccommand_start; 1690 xfer->c_intr = __wdccommand_intr; 1691 xfer->c_kill_xfer = __wdccommand_done; 1692 1693 s = splbio(); 1694 wdc_exec_xfer(chp, xfer); 1695 #ifdef DIAGNOSTIC 1696 if ((wdc_c->flags & AT_POLL) != 0 && 1697 (wdc_c->flags & AT_DONE) == 0) 1698 panic("wdc_exec_command: polled command not done"); 1699 #endif 1700 if (wdc_c->flags & AT_DONE) { 1701 ret = WDC_COMPLETE; 1702 } else { 1703 if (wdc_c->flags & AT_WAIT) { 1704 while ((wdc_c->flags & AT_DONE) == 0) { 1705 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1706 } 1707 ret = WDC_COMPLETE; 1708 } else { 1709 ret = WDC_QUEUED; 1710 } 1711 } 1712 splx(s); 1713 return ret; 1714 } 1715 1716 void 1717 __wdccommand_start(chp, xfer) 1718 struct channel_softc *chp; 1719 struct wdc_xfer *xfer; 1720 { 1721 int drive = xfer->drive; 1722 struct wdc_command *wdc_c = xfer->cmd; 1723 1724 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1725 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1726 DEBUG_FUNCS); 1727 1728 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1729 chp->wdc->select(chp,drive); 1730 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1731 WDSD_IBM | (drive << 4)); 1732 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1733 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1734 case WDCWAIT_OK: 1735 break; 1736 case WDCWAIT_TOUT: 1737 wdc_c->flags |= AT_TIMEOU; 1738 __wdccommand_done(chp, xfer); 1739 return; 1740 case WDCWAIT_THR: 1741 return; 1742 } 1743 if (wdc_c->flags & AT_POLL) { 1744 /* polled command, disable interrupts */ 1745 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1746 WDCTL_4BIT | WDCTL_IDS); 1747 } 1748 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1749 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1750 1751 if ((wdc_c->flags & AT_POLL) == 0) { 1752 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1753 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1754 wdctimeout, chp); 1755 return; 1756 } 1757 /* 1758 * Polled command. Wait for drive ready or drq. Done in intr(). 1759 * Wait for at last 400ns for status bit to be valid. 1760 */ 1761 delay(10); /* 400ns delay */ 1762 __wdccommand_intr(chp, xfer, 0); 1763 } 1764 1765 int 1766 __wdccommand_intr(chp, xfer, irq) 1767 struct channel_softc *chp; 1768 struct wdc_xfer *xfer; 1769 int irq; 1770 { 1771 struct wdc_command *wdc_c = xfer->cmd; 1772 int bcount = wdc_c->bcount; 1773 char *data = wdc_c->data; 1774 int wflags; 1775 1776 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1777 /* both wait and poll, we can tsleep here */ 1778 wflags = 0; 1779 } else { 1780 wflags = AT_POLL; 1781 } 1782 1783 again: 1784 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1785 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1786 /* 1787 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1788 * Reselect again, it doesn't hurt for others commands, and the time 1789 * penalty for the extra regiter write is acceptable, 1790 * wdc_exec_command() isn't called often (mosly for autoconfig) 1791 */ 1792 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1793 WDSD_IBM | (xfer->drive << 4)); 1794 if ((wdc_c->flags & AT_XFDONE) != 0) { 1795 /* 1796 * We have completed a data xfer. The drive should now be 1797 * in its initial state 1798 */ 1799 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1800 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1801 wflags) == WDCWAIT_TOUT) { 1802 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1803 return 0; /* IRQ was not for us */ 1804 wdc_c->flags |= AT_TIMEOU; 1805 } 1806 goto out; 1807 } 1808 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1809 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1810 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1811 return 0; /* IRQ was not for us */ 1812 wdc_c->flags |= AT_TIMEOU; 1813 goto out; 1814 } 1815 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1816 chp->wdc->irqack(chp); 1817 if (wdc_c->flags & AT_READ) { 1818 if ((chp->ch_status & WDCS_DRQ) == 0) { 1819 wdc_c->flags |= AT_TIMEOU; 1820 goto out; 1821 } 1822 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1823 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1824 0, (u_int32_t*)data, bcount >> 2); 1825 data += bcount & 0xfffffffc; 1826 bcount = bcount & 0x03; 1827 } 1828 if (bcount > 0) 1829 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1830 wd_data, (u_int16_t *)data, bcount >> 1); 1831 /* at this point the drive should be in its initial state */ 1832 wdc_c->flags |= AT_XFDONE; 1833 /* XXX should read status register here ? */ 1834 } else if (wdc_c->flags & AT_WRITE) { 1835 if ((chp->ch_status & WDCS_DRQ) == 0) { 1836 wdc_c->flags |= AT_TIMEOU; 1837 goto out; 1838 } 1839 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1840 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1841 0, (u_int32_t*)data, bcount >> 2); 1842 data += bcount & 0xfffffffc; 1843 bcount = bcount & 0x03; 1844 } 1845 if (bcount > 0) 1846 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1847 wd_data, (u_int16_t *)data, bcount >> 1); 1848 wdc_c->flags |= AT_XFDONE; 1849 if ((wdc_c->flags & AT_POLL) == 0) { 1850 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1851 callout_reset(&chp->ch_callout, 1852 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1853 return 1; 1854 } else { 1855 goto again; 1856 } 1857 } 1858 out: 1859 __wdccommand_done(chp, xfer); 1860 return 1; 1861 } 1862 1863 void 1864 __wdccommand_done(chp, xfer) 1865 struct channel_softc *chp; 1866 struct wdc_xfer *xfer; 1867 { 1868 struct wdc_command *wdc_c = xfer->cmd; 1869 1870 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1871 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1872 1873 callout_stop(&chp->ch_callout); 1874 1875 if (chp->ch_status & WDCS_DWF) 1876 wdc_c->flags |= AT_DF; 1877 if (chp->ch_status & WDCS_ERR) { 1878 wdc_c->flags |= AT_ERROR; 1879 wdc_c->r_error = chp->ch_error; 1880 } 1881 wdc_c->flags |= AT_DONE; 1882 if ((wdc_c->flags & AT_READREG) != 0 && 1883 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1884 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1885 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1886 wd_sdh); 1887 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1888 wd_cyl_hi) << 8; 1889 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1890 wd_cyl_lo); 1891 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1892 wd_sector); 1893 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1894 wd_seccnt); 1895 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1896 wd_error); 1897 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1898 wd_precomp); 1899 } 1900 1901 if (wdc_c->flags & AT_POLL) { 1902 /* enable interrupts */ 1903 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1904 WDCTL_4BIT); 1905 } 1906 wdc_free_xfer(chp, xfer); 1907 if (wdc_c->flags & AT_WAIT) 1908 wakeup(wdc_c); 1909 else if (wdc_c->callback) 1910 wdc_c->callback(wdc_c->callback_arg); 1911 wdcstart(chp); 1912 return; 1913 } 1914 1915 /* 1916 * Send a command. The drive should be ready. 1917 * Assumes interrupts are blocked. 1918 */ 1919 void 1920 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1921 struct channel_softc *chp; 1922 u_int8_t drive; 1923 u_int8_t command; 1924 u_int16_t cylin; 1925 u_int8_t head, sector, count, precomp; 1926 { 1927 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1928 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1929 chp->channel, drive, command, cylin, head, sector, count, precomp), 1930 DEBUG_FUNCS); 1931 1932 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1933 chp->wdc->select(chp,drive); 1934 1935 /* Select drive, head, and addressing mode. */ 1936 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1937 WDSD_IBM | (drive << 4) | head); 1938 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1939 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1940 precomp); 1941 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1942 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1943 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1944 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1945 1946 /* Send command. */ 1947 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1948 return; 1949 } 1950 1951 /* 1952 * Send a 48-bit addressing command. The drive should be ready. 1953 * Assumes interrupts are blocked. 1954 */ 1955 void 1956 wdccommandext(chp, drive, command, blkno, count) 1957 struct channel_softc *chp; 1958 u_int8_t drive; 1959 u_int8_t command; 1960 u_int64_t blkno; 1961 u_int16_t count; 1962 { 1963 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1964 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1965 chp->channel, drive, command, (u_int32_t) blkno, count), 1966 DEBUG_FUNCS); 1967 1968 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1969 chp->wdc->select(chp,drive); 1970 1971 /* Select drive, head, and addressing mode. */ 1972 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1973 (drive << 4) | WDSD_LBA); 1974 1975 /* previous */ 1976 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1977 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1978 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1979 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1980 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1981 1982 /* current */ 1983 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1984 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1985 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1986 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1987 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1988 1989 /* Send command. */ 1990 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1991 return; 1992 } 1993 1994 /* 1995 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1996 * tested by the caller. 1997 */ 1998 void 1999 wdccommandshort(chp, drive, command) 2000 struct channel_softc *chp; 2001 int drive; 2002 int command; 2003 { 2004 2005 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2006 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2007 DEBUG_FUNCS); 2008 2009 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2010 chp->wdc->select(chp,drive); 2011 2012 /* Select drive. */ 2013 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2014 WDSD_IBM | (drive << 4)); 2015 2016 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2017 } 2018 2019 /* Add a command to the queue and start controller. Must be called at splbio */ 2020 2021 void 2022 wdc_exec_xfer(chp, xfer) 2023 struct channel_softc *chp; 2024 struct wdc_xfer *xfer; 2025 { 2026 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2027 chp->channel, xfer->drive), DEBUG_XFERS); 2028 2029 /* complete xfer setup */ 2030 xfer->chp = chp; 2031 2032 /* 2033 * If we are a polled command, and the list is not empty, 2034 * we are doing a dump. Drop the list to allow the polled command 2035 * to complete, we're going to reboot soon anyway. 2036 */ 2037 if ((xfer->c_flags & C_POLL) != 0 && 2038 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2039 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2040 } 2041 /* insert at the end of command list */ 2042 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2043 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2044 chp->ch_flags), DEBUG_XFERS); 2045 wdcstart(chp); 2046 } 2047 2048 struct wdc_xfer * 2049 wdc_get_xfer(flags) 2050 int flags; 2051 { 2052 struct wdc_xfer *xfer; 2053 int s; 2054 2055 s = splbio(); 2056 xfer = pool_get(&wdc_xfer_pool, 2057 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2058 splx(s); 2059 if (xfer != NULL) { 2060 memset(xfer, 0, sizeof(struct wdc_xfer)); 2061 } 2062 return xfer; 2063 } 2064 2065 void 2066 wdc_free_xfer(chp, xfer) 2067 struct channel_softc *chp; 2068 struct wdc_xfer *xfer; 2069 { 2070 struct wdc_softc *wdc = chp->wdc; 2071 int s; 2072 2073 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2074 (*wdc->free_hw)(chp); 2075 s = splbio(); 2076 chp->ch_flags &= ~WDCF_ACTIVE; 2077 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2078 pool_put(&wdc_xfer_pool, xfer); 2079 splx(s); 2080 } 2081 2082 /* 2083 * Kill off all pending xfers for a channel_softc. 2084 * 2085 * Must be called at splbio(). 2086 */ 2087 void 2088 wdc_kill_pending(chp) 2089 struct channel_softc *chp; 2090 { 2091 struct wdc_xfer *xfer; 2092 2093 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2094 chp = xfer->chp; 2095 (*xfer->c_kill_xfer)(chp, xfer); 2096 } 2097 } 2098 2099 static void 2100 __wdcerror(chp, msg) 2101 struct channel_softc *chp; 2102 char *msg; 2103 { 2104 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2105 2106 if (xfer == NULL) 2107 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2108 msg); 2109 else 2110 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2111 chp->channel, xfer->drive, msg); 2112 } 2113 2114 /* 2115 * the bit bucket 2116 */ 2117 void 2118 wdcbit_bucket(chp, size) 2119 struct channel_softc *chp; 2120 int size; 2121 { 2122 2123 for (; size >= 2; size -= 2) 2124 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2125 if (size) 2126 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2127 } 2128 2129 int 2130 wdc_addref(chp) 2131 struct channel_softc *chp; 2132 { 2133 struct wdc_softc *wdc = chp->wdc; 2134 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2135 int s, error = 0; 2136 2137 s = splbio(); 2138 if (adapt->adapt_refcnt++ == 0 && 2139 adapt->adapt_enable != NULL) { 2140 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2141 if (error) 2142 adapt->adapt_refcnt--; 2143 } 2144 splx(s); 2145 return (error); 2146 } 2147 2148 void 2149 wdc_delref(chp) 2150 struct channel_softc *chp; 2151 { 2152 struct wdc_softc *wdc = chp->wdc; 2153 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2154 int s; 2155 2156 s = splbio(); 2157 if (adapt->adapt_refcnt-- == 1 && 2158 adapt->adapt_enable != NULL) 2159 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2160 splx(s); 2161 } 2162 2163 void 2164 wdc_print_modes(struct channel_softc *chp) 2165 { 2166 int drive; 2167 struct ata_drive_datas *drvp; 2168 2169 for (drive = 0; drive < 2; drive++) { 2170 drvp = &chp->ch_drive[drive]; 2171 if ((drvp->drive_flags & DRIVE) == 0) 2172 continue; 2173 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2174 drvp->drv_softc->dv_xname, 2175 chp->wdc->sc_dev.dv_xname, 2176 chp->channel, drive, drvp->PIO_mode); 2177 if (drvp->drive_flags & DRIVE_DMA) 2178 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2179 if (drvp->drive_flags & DRIVE_UDMA) { 2180 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2181 if (drvp->UDMA_mode == 2) 2182 aprint_normal(" (Ultra/33)"); 2183 else if (drvp->UDMA_mode == 4) 2184 aprint_normal(" (Ultra/66)"); 2185 else if (drvp->UDMA_mode == 5) 2186 aprint_normal(" (Ultra/100)"); 2187 else if (drvp->UDMA_mode == 6) 2188 aprint_normal(" (Ultra/133)"); 2189 } 2190 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2191 aprint_normal(" (using DMA data transfers)"); 2192 aprint_normal("\n"); 2193 } 2194 } 2195
Indexes created Tue Sep 23 14:10:03 GMT 2025