wdc.c revision 1.145
1 /* $NetBSD: wdc.c,v 1.145 2003/10/25 08:30:46 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.145 2003/10/25 08:30:46 christos Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 printf("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 while (!(chp->ch_flags & WDCF_SHUTDOWN)) { 272 s = splbio(); 273 chp->ch_flags &= ~WDCF_TH_RUN; 274 tsleep(&chp->thread, PRIBIO, "atath", 0); 275 chp->ch_flags |= WDCF_TH_RUN; 276 splx(s); 277 if (chp->ch_flags & WDCF_SHUTDOWN) 278 break; 279 s = splbio(); 280 if (chp->ch_flags & WDCF_TH_RESET) { 281 int drive; 282 (void) wdcreset(chp, RESET_SLEEP); 283 for (drive = 0; drive < 2; drive++) { 284 chp->ch_drive[drive].state = 0; 285 } 286 chp->ch_flags &= ~WDCF_TH_RESET; 287 wdcstart(chp); 288 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 289 chp->ch_queue->queue_freese == 1) { 290 /* 291 * caller has bumped queue_freese, decrease it 292 */ 293 chp->ch_queue->queue_freese--; 294 xfer = chp->ch_queue->sc_xfer.tqh_first; 295 #ifdef DIAGNOSTIC 296 if (xfer == NULL) 297 panic("channel active with no xfer ?"); 298 #endif 299 xfer->c_start(chp, xfer); 300 } else if (chp->ch_queue->queue_freese > 1) { 301 panic("queue_freese"); 302 } 303 splx(s); 304 } 305 chp->thread = NULL; 306 wakeup(&chp->ch_flags); 307 kthread_exit(0); 308 } 309 310 void 311 atabusconfig(atabus_sc) 312 struct atabus_softc *atabus_sc; 313 { 314 struct channel_softc *chp = atabus_sc->sc_chan; 315 int ctrl_flags, i, error, need_delref = 0; 316 struct ataparams params; 317 struct atabus_initq *atabus_initq = NULL; 318 u_int8_t st0 = 0, st1 = 0; 319 320 if ((error = wdc_addref(chp)) != 0) { 321 aprint_error("%s: unable to enable controller\n", 322 chp->wdc->sc_dev.dv_xname); 323 goto out; 324 } 325 need_delref = 1; 326 327 if (__wdcprobe(chp, 0) == 0) 328 /* If no drives, abort attach here. */ 329 goto out; 330 331 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 332 for (i = 0; i < mstohz(3000); i++) { 333 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 334 chp->wdc->select(chp,0); 335 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 336 WDSD_IBM); 337 delay(10); /* 400ns delay */ 338 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 339 340 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 341 chp->wdc->select(chp,1); 342 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 343 WDSD_IBM | 0x10); 344 delay(10); /* 400ns delay */ 345 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 346 347 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 348 == 0 || 349 (st0 & WDCS_DRDY)) && 350 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 351 == 0 || 352 (st1 & WDCS_DRDY))) 353 break; 354 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 355 } 356 if ((st0 & WDCS_DRDY) == 0) 357 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 358 if ((st1 & WDCS_DRDY) == 0) 359 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 360 361 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 362 chp->wdc->sc_dev.dv_xname, 363 chp->channel, st0, st1), DEBUG_PROBE); 364 365 /* Wait a bit, some devices are weird just after a reset. */ 366 delay(5000); 367 368 for (i = 0; i < 2; i++) { 369 chp->ch_drive[i].chnl_softc = chp; 370 chp->ch_drive[i].drive = i; 371 /* 372 * Init error counter so that an error withing the first xfers 373 * will trigger a downgrade 374 */ 375 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 376 377 /* If controller can't do 16bit flag the drives as 32bit */ 378 if ((chp->wdc->cap & 379 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 380 WDC_CAPABILITY_DATA32) 381 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 382 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 383 continue; 384 385 /* Shortcut in case we've been shutdown */ 386 if (chp->ch_flags & WDCF_SHUTDOWN) 387 goto out; 388 389 /* issue an identify, to try to detect ghosts */ 390 error = ata_get_params(&chp->ch_drive[i], 391 AT_WAIT | AT_POLL, ¶ms); 392 if (error != CMD_OK) { 393 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 394 395 /* Shortcut in case we've been shutdown */ 396 if (chp->ch_flags & WDCF_SHUTDOWN) 397 goto out; 398 399 error = ata_get_params(&chp->ch_drive[i], 400 AT_WAIT | AT_POLL, ¶ms); 401 } 402 if (error == CMD_OK) { 403 /* If IDENTIFY succeded, this is not an OLD ctrl */ 404 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 405 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 406 } else { 407 chp->ch_drive[i].drive_flags &= 408 ~(DRIVE_ATA | DRIVE_ATAPI); 409 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 410 chp->wdc->sc_dev.dv_xname, 411 chp->channel, i, error), DEBUG_PROBE); 412 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 413 continue; 414 /* 415 * Pre-ATA drive ? 416 * Test registers writability (Error register not 417 * writable, but cyllo is), then try an ATA command. 418 */ 419 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 420 chp->wdc->select(chp,i); 421 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 422 WDSD_IBM | (i << 4)); 423 delay(10); /* 400ns delay */ 424 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 425 wd_error, 0x58); 426 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 427 wd_cyl_lo, 0xa5); 428 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 429 wd_error) == 0x58 || 430 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 431 wd_cyl_lo) != 0xa5) { 432 WDCDEBUG_PRINT(("%s:%d:%d: register " 433 "writability failed\n", 434 chp->wdc->sc_dev.dv_xname, 435 chp->channel, i), DEBUG_PROBE); 436 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 437 } 438 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 439 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 440 chp->wdc->sc_dev.dv_xname, 441 chp->channel, i), DEBUG_PROBE); 442 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 443 continue; 444 } 445 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 446 wd_command, WDCC_RECAL); 447 delay(10); /* 400ns delay */ 448 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 449 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 450 chp->wdc->sc_dev.dv_xname, 451 chp->channel, i), DEBUG_PROBE); 452 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 453 } 454 } 455 } 456 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 457 458 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 459 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 460 DEBUG_PROBE); 461 462 /* If no drives, abort here */ 463 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 464 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 465 goto out; 466 467 /* Make sure the devices probe in atabus order to avoid jitter. */ 468 simple_lock(&atabus_interlock); 469 while(1) { 470 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 471 if (atabus_initq->atabus_sc == atabus_sc) 472 break; 473 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 474 &atabus_interlock); 475 } 476 simple_unlock(&atabus_interlock); 477 478 /* 479 * Attach an ATAPI bus, if needed. 480 */ 481 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 482 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 483 #if NATAPIBUS > 0 484 wdc_atapibus_attach(atabus_sc); 485 #else 486 /* 487 * Fake the autoconfig "not configured" message 488 */ 489 aprint_normal("atapibus at %s not configured\n", 490 chp->wdc->sc_dev.dv_xname); 491 chp->atapibus = NULL; 492 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 493 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 494 #endif 495 } 496 497 for (i = 0; i < 2; i++) { 498 struct ata_device adev; 499 if ((chp->ch_drive[i].drive_flags & 500 (DRIVE_ATA | DRIVE_OLD)) == 0) { 501 continue; 502 } 503 memset(&adev, 0, sizeof(struct ata_device)); 504 adev.adev_bustype = &wdc_ata_bustype; 505 adev.adev_channel = chp->channel; 506 adev.adev_openings = 1; 507 adev.adev_drv_data = &chp->ch_drive[i]; 508 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 509 &adev, wdprint); 510 if (chp->ata_drives[i] != NULL) 511 wdc_probe_caps(&chp->ch_drive[i]); 512 else 513 chp->ch_drive[i].drive_flags &= 514 ~(DRIVE_ATA | DRIVE_OLD); 515 } 516 517 /* now that we know the drives, the controller can set its modes */ 518 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 519 chp->wdc->set_modes(chp); 520 wdc_print_modes(chp); 521 } 522 #if NATARAID > 0 523 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 524 for (i = 0; i < 2; i++) 525 if (chp->ata_drives[i] != NULL) 526 ata_raid_check_component(chp->ata_drives[i]); 527 #endif /* NATARAID > 0 */ 528 529 /* 530 * reset drive_flags for unnatached devices, reset state for attached 531 * ones 532 */ 533 for (i = 0; i < 2; i++) { 534 if (chp->ch_drive[i].drv_softc == NULL) 535 chp->ch_drive[i].drive_flags = 0; 536 else 537 chp->ch_drive[i].state = 0; 538 } 539 540 out: 541 if (atabus_initq == NULL) { 542 simple_lock(&atabus_interlock); 543 while(1) { 544 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 545 if (atabus_initq->atabus_sc == atabus_sc) 546 break; 547 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 548 &atabus_interlock); 549 } 550 simple_unlock(&atabus_interlock); 551 } 552 simple_lock(&atabus_interlock); 553 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 554 simple_unlock(&atabus_interlock); 555 556 free(atabus_initq, M_DEVBUF); 557 wakeup(&atabus_initq_head); 558 559 config_pending_decr(); 560 if (need_delref) 561 wdc_delref(chp); 562 } 563 564 565 int 566 wdprint(aux, pnp) 567 void *aux; 568 const char *pnp; 569 { 570 struct ata_device *adev = aux; 571 if (pnp) 572 aprint_normal("wd at %s", pnp); 573 aprint_normal(" drive %d", adev->adev_drv_data->drive); 574 return (UNCONF); 575 } 576 577 /* Test to see controller with at last one attached drive is there. 578 * Returns a bit for each possible drive found (0x01 for drive 0, 579 * 0x02 for drive 1). 580 * Logic: 581 * - If a status register is at 0xff, assume there is no drive here 582 * (ISA has pull-up resistors). Similarly if the status register has 583 * the value we last wrote to the bus (for IDE interfaces without pullups). 584 * If no drive at all -> return. 585 * - reset the controller, wait for it to complete (may take up to 31s !). 586 * If timeout -> return. 587 * - test ATA/ATAPI signatures. If at last one drive found -> return. 588 * - try an ATA command on the master. 589 */ 590 591 int 592 wdcprobe(chp) 593 struct channel_softc *chp; 594 { 595 return __wdcprobe(chp, 1); 596 } 597 598 int 599 __wdcprobe(chp, poll) 600 struct channel_softc *chp; 601 int poll; 602 { 603 u_int8_t st0, st1, sc, sn, cl, ch; 604 u_int8_t ret_value = 0x03; 605 u_int8_t drive; 606 607 /* 608 * Sanity check to see if the wdc channel responds at all. 609 */ 610 611 if (chp->wdc == NULL || 612 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 613 614 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 615 chp->wdc->select(chp,0); 616 617 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 618 WDSD_IBM); 619 delay(10); /* 400ns delay */ 620 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 621 622 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 623 chp->wdc->select(chp,1); 624 625 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 626 WDSD_IBM | 0x10); 627 delay(10); /* 400ns delay */ 628 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 629 630 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 631 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 632 chp->channel, st0, st1), DEBUG_PROBE); 633 634 if (st0 == 0xff || st0 == WDSD_IBM) 635 ret_value &= ~0x01; 636 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 637 ret_value &= ~0x02; 638 /* Register writability test, drive 0. */ 639 if (ret_value & 0x01) { 640 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 641 chp->wdc->select(chp,0); 642 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 643 WDSD_IBM); 644 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 645 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 646 wd_cyl_lo) != 0x02) 647 ret_value &= ~0x01; 648 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 649 0x01); 650 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_cyl_lo) != 0x01) 652 ret_value &= ~0x01; 653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 654 0x01); 655 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 656 wd_sector) != 0x01) 657 ret_value &= ~0x01; 658 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 659 0x02); 660 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 661 wd_sector) != 0x02) 662 ret_value &= ~0x01; 663 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 664 wd_cyl_lo) != 0x01) 665 ret_value &= ~0x01; 666 } 667 /* Register writability test, drive 1. */ 668 if (ret_value & 0x02) { 669 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 670 chp->wdc->select(chp,1); 671 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 672 WDSD_IBM | 0x10); 673 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 674 0x02); 675 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 676 wd_cyl_lo) != 0x02) 677 ret_value &= ~0x02; 678 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 679 0x01); 680 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 681 wd_cyl_lo) != 0x01) 682 ret_value &= ~0x02; 683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 684 0x01); 685 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 686 wd_sector) != 0x01) 687 ret_value &= ~0x02; 688 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 689 0x02); 690 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 691 wd_sector) != 0x02) 692 ret_value &= ~0x02; 693 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 694 wd_cyl_lo) != 0x01) 695 ret_value &= ~0x02; 696 } 697 698 if (ret_value == 0) 699 return 0; 700 } 701 702 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 703 chp->wdc->select(chp,0); 704 /* assert SRST, wait for reset to complete */ 705 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 706 WDSD_IBM); 707 delay(10); /* 400ns delay */ 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 710 DELAY(2000); 711 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 712 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 713 delay(10); /* 400ns delay */ 714 715 ret_value = __wdcwait_reset(chp, ret_value, poll); 716 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 717 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 718 ret_value), DEBUG_PROBE); 719 720 /* if reset failed, there's nothing here */ 721 if (ret_value == 0) 722 return 0; 723 724 /* 725 * Test presence of drives. First test register signatures looking for 726 * ATAPI devices. If it's not an ATAPI and reset said there may be 727 * something here assume it's ATA or OLD. Ghost will be killed later in 728 * attach routine. 729 */ 730 for (drive = 0; drive < 2; drive++) { 731 if ((ret_value & (0x01 << drive)) == 0) 732 continue; 733 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 734 chp->wdc->select(chp,drive); 735 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 736 WDSD_IBM | (drive << 4)); 737 delay(10); /* 400ns delay */ 738 /* Save registers contents */ 739 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 740 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 741 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 742 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 743 744 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 745 "cl=0x%x ch=0x%x\n", 746 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 747 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 748 /* 749 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 750 * we get wrong values here, so ignore it. 751 */ 752 if (cl == 0x14 && ch == 0xeb) { 753 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 754 } else { 755 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 756 if (chp->wdc == NULL || 757 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 758 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 759 } 760 } 761 return (ret_value); 762 } 763 764 void 765 wdcattach(chp) 766 struct channel_softc *chp; 767 { 768 static int inited = 0; 769 770 if (chp->ch_flags & WDCF_DISABLED) 771 return; 772 773 /* initialise global data */ 774 callout_init(&chp->ch_callout); 775 if (inited == 0) { 776 /* Initialize the wdc_xfer pool. */ 777 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 778 0, 0, "wdcspl", NULL); 779 inited++; 780 } 781 TAILQ_INIT(&chp->ch_queue->sc_xfer); 782 chp->ch_queue->queue_freese = 0; 783 784 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 785 } 786 787 /* 788 * Call activate routine of underlying devices. 789 */ 790 int 791 atabusactivate(self, act) 792 struct device *self; 793 enum devact act; 794 { 795 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 796 struct channel_softc *chp = atabus_sc->sc_chan; 797 struct device *sc = 0; 798 int s, i, error = 0; 799 800 s = splbio(); 801 switch (act) { 802 case DVACT_ACTIVATE: 803 error = EOPNOTSUPP; 804 break; 805 806 case DVACT_DEACTIVATE: 807 /* 808 * We might call deactivate routine for 809 * the children of atapibus twice (once via 810 * atapibus, once directly), but since 811 * config_deactivate maintains DVF_ACTIVE flag, 812 * it's safe. 813 */ 814 sc = chp->atapibus; 815 if (sc != NULL) { 816 error = config_deactivate(sc); 817 if (error != 0) 818 goto out; 819 } 820 821 for (i = 0; i < 2; i++) { 822 sc = chp->ch_drive[i].drv_softc; 823 WDCDEBUG_PRINT(("atabusactivate: %s:" 824 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 825 sc == NULL ? "nodrv" : sc->dv_xname), 826 DEBUG_DETACH); 827 if (sc != NULL) { 828 error = config_deactivate(sc); 829 if (error != 0) 830 goto out; 831 } 832 } 833 break; 834 } 835 836 out: 837 splx(s); 838 839 #ifdef WDCDEBUG 840 if (sc && error != 0) 841 WDCDEBUG_PRINT(("atabusactivate: %s: " 842 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 843 error, sc->dv_xname), DEBUG_DETACH); 844 #endif 845 return (error); 846 } 847 848 int wdcactivate(self, act) 849 struct device *self; 850 enum devact act; 851 { 852 struct wdc_softc *wdc = (struct wdc_softc *)self; 853 int s, i, error = 0; 854 855 s = splbio(); 856 switch (act) { 857 case DVACT_ACTIVATE: 858 error = EOPNOTSUPP; 859 break; 860 861 case DVACT_DEACTIVATE: 862 for (i = 0; i < wdc->nchannels; i++) { 863 error = config_deactivate(wdc->channels[i]->atabus); 864 if (error) 865 break; 866 } 867 break; 868 } 869 splx(s); 870 return (error); 871 } 872 873 874 int 875 atabusdetach(self, flags) 876 struct device *self; 877 int flags; 878 { 879 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 880 struct channel_softc *chp = atabus_sc->sc_chan; 881 struct device *sc = 0; 882 int i, error = 0; 883 884 /* shutdown channel */ 885 chp->ch_flags |= WDCF_SHUTDOWN; 886 wakeup(&chp->thread); 887 while (chp->thread != NULL) 888 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 889 890 /* 891 * Detach atapibus and its children. 892 */ 893 sc = chp->atapibus; 894 if (sc != NULL) { 895 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 896 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 897 error = config_detach(sc, flags); 898 if (error != 0) 899 goto out; 900 } 901 902 /* 903 * Detach our other children. 904 */ 905 for (i = 0; i < 2; i++) { 906 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 907 continue; 908 sc = chp->ch_drive[i].drv_softc; 909 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 910 atabus_sc->sc_dev.dv_xname, 911 sc == NULL ? "nodrv" : sc->dv_xname), 912 DEBUG_DETACH); 913 if (sc != NULL) { 914 error = config_detach(sc, flags); 915 if (error != 0) 916 goto out; 917 } 918 } 919 920 wdc_kill_pending(chp); 921 922 out: 923 #ifdef WDCDEBUG 924 if (sc && error != 0) 925 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 926 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 927 DEBUG_DETACH); 928 #endif 929 return (error); 930 } 931 932 int 933 wdcdetach(self, flags) 934 struct device *self; 935 int flags; 936 { 937 struct wdc_softc *wdc = (struct wdc_softc *)self; 938 struct channel_softc *chp; 939 int i, error = 0; 940 941 for (i = 0; i < wdc->nchannels; i++) { 942 chp = wdc->channels[i]; 943 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 944 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 945 error = config_detach(chp->atabus, flags); 946 if (error) 947 break; 948 } 949 return (error); 950 } 951 952 /* 953 * Start I/O on a controller, for the given channel. 954 * The first xfer may be not for our channel if the channel queues 955 * are shared. 956 */ 957 void 958 wdcstart(chp) 959 struct channel_softc *chp; 960 { 961 struct wdc_xfer *xfer; 962 963 #ifdef WDC_DIAGNOSTIC 964 int spl1, spl2; 965 966 spl1 = splbio(); 967 spl2 = splbio(); 968 if (spl2 != spl1) { 969 printf("wdcstart: not at splbio()\n"); 970 panic("wdcstart"); 971 } 972 splx(spl2); 973 splx(spl1); 974 #endif /* WDC_DIAGNOSTIC */ 975 976 /* is there a xfer ? */ 977 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 978 return; 979 980 /* adjust chp, in case we have a shared queue */ 981 chp = xfer->chp; 982 983 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 984 return; /* channel aleady active */ 985 } 986 if ((chp->ch_flags & WDCF_TH_RESET) != 0) { 987 return; /* a channel reset is pending */ 988 } 989 #ifdef DIAGNOSTIC 990 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 991 panic("wdcstart: channel waiting for irq"); 992 #endif 993 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 994 if (!(*chp->wdc->claim_hw)(chp, 0)) 995 return; 996 997 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 998 chp->channel, xfer->drive), DEBUG_XFERS); 999 chp->ch_flags |= WDCF_ACTIVE; 1000 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1001 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1002 chp->ch_drive[xfer->drive].state = 0; 1003 } 1004 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1005 KASSERT(xfer->c_flags & C_POLL); 1006 xfer->c_start(chp, xfer); 1007 } 1008 1009 /* restart an interrupted I/O */ 1010 void 1011 wdcrestart(v) 1012 void *v; 1013 { 1014 struct channel_softc *chp = v; 1015 int s; 1016 1017 s = splbio(); 1018 wdcstart(chp); 1019 splx(s); 1020 } 1021 1022 1023 /* 1024 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1025 * errors on the current operation, mark it done if necessary, and start the 1026 * next request. Also check for a partially done transfer, and continue with 1027 * the next chunk if so. 1028 */ 1029 int 1030 wdcintr(arg) 1031 void *arg; 1032 { 1033 struct channel_softc *chp = arg; 1034 struct wdc_xfer *xfer; 1035 int ret; 1036 1037 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1038 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1039 DEBUG_INTR); 1040 return (0); 1041 } 1042 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1043 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1044 /* try to clear the pending interrupt anyway */ 1045 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1046 return (0); 1047 } 1048 1049 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1050 xfer = chp->ch_queue->sc_xfer.tqh_first; 1051 if (chp->ch_flags & WDCF_DMA_WAIT) { 1052 chp->wdc->dma_status = 1053 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1054 xfer->drive, 0); 1055 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1056 /* IRQ not for us, not detected by DMA engine */ 1057 return 0; 1058 } 1059 chp->ch_flags &= ~WDCF_DMA_WAIT; 1060 } 1061 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1062 ret = xfer->c_intr(chp, xfer, 1); 1063 if (ret == 0) /* irq was not for us, still waiting for irq */ 1064 chp->ch_flags |= WDCF_IRQ_WAIT; 1065 return (ret); 1066 } 1067 1068 /* Put all disk in RESET state */ 1069 void 1070 wdc_reset_channel(drvp, flags) 1071 struct ata_drive_datas *drvp; 1072 int flags; 1073 { 1074 struct channel_softc *chp = drvp->chnl_softc; 1075 int drive; 1076 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1077 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1078 DEBUG_FUNCS); 1079 if ((chp->ch_flags & WDCF_TH_RUN) == 0 && 1080 (flags & AT_POLL) == 0) { 1081 chp->ch_flags |= WDCF_TH_RESET; 1082 wakeup(&chp->thread); 1083 return; 1084 } 1085 (void) wdcreset(chp, (flags & AT_POLL) ? RESET_POLL : RESET_SLEEP); 1086 for (drive = 0; drive < 2; drive++) { 1087 chp->ch_drive[drive].state = 0; 1088 } 1089 } 1090 1091 int 1092 wdcreset(chp, poll) 1093 struct channel_softc *chp; 1094 int poll; 1095 { 1096 int drv_mask1, drv_mask2; 1097 1098 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1099 chp->wdc->select(chp,0); 1100 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1101 WDSD_IBM); /* master */ 1102 delay(10); /* 400ns delay */ 1103 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1104 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1105 delay(2000); 1106 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1107 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1108 WDCTL_4BIT | WDCTL_IDS); 1109 delay(10); /* 400ns delay */ 1110 1111 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1112 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1113 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1114 (poll == RESET_SLEEP) ? 0 : 1); 1115 if (drv_mask2 != drv_mask1) { 1116 printf("%s channel %d: reset failed for", 1117 chp->wdc->sc_dev.dv_xname, chp->channel); 1118 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1119 printf(" drive 0"); 1120 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1121 printf(" drive 1"); 1122 printf("\n"); 1123 } 1124 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1125 return (drv_mask1 != drv_mask2) ? 1 : 0; 1126 } 1127 1128 static int 1129 __wdcwait_reset(chp, drv_mask, poll) 1130 struct channel_softc *chp; 1131 int drv_mask; 1132 { 1133 int timeout, nloop; 1134 u_int8_t st0, er0, st1, er1; 1135 #ifdef WDCDEBUG 1136 u_int8_t sc0, sn0, cl0, ch0; 1137 u_int8_t sc1, sn1, cl1, ch1; 1138 #endif 1139 1140 if (poll) 1141 nloop = WDCNDELAY_RST; 1142 else 1143 nloop = WDC_RESET_WAIT * hz / 1000; 1144 /* wait for BSY to deassert */ 1145 for (timeout = 0; timeout < nloop; timeout++) { 1146 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1147 chp->wdc->select(chp,0); 1148 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1149 WDSD_IBM); /* master */ 1150 delay(10); 1151 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1152 er0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1153 #ifdef WDCDEBUG 1154 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1155 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1156 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1157 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1158 #endif 1159 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1160 chp->wdc->select(chp,1); 1161 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1162 WDSD_IBM | 0x10); /* slave */ 1163 delay(10); 1164 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1165 er1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1166 #ifdef WDCDEBUG 1167 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1168 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1169 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1170 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1171 #endif 1172 1173 if ((drv_mask & 0x01) == 0) { 1174 /* no master */ 1175 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1176 /* No master, slave is ready, it's done */ 1177 goto end; 1178 } 1179 } else if ((drv_mask & 0x02) == 0) { 1180 /* no slave */ 1181 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1182 /* No slave, master is ready, it's done */ 1183 goto end; 1184 } 1185 } else { 1186 /* Wait for both master and slave to be ready */ 1187 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1188 goto end; 1189 } 1190 } 1191 if (poll) 1192 delay(WDCDELAY); 1193 else 1194 tsleep(&nloop, PRIBIO, "atarst", 1); 1195 } 1196 /* Reset timed out. Maybe it's because drv_mask was not right */ 1197 if (st0 & WDCS_BSY) 1198 drv_mask &= ~0x01; 1199 if (st1 & WDCS_BSY) 1200 drv_mask &= ~0x02; 1201 end: 1202 if (er0 != 0x01 && er0 != 0x81) 1203 drv_mask &= ~0x01; 1204 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1205 "cl=0x%x ch=0x%x\n", 1206 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1207 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1208 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1209 "cl=0x%x ch=0x%x\n", 1210 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1211 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1212 1213 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, " 1214 "st0=0x%x er0=0x%x, st1=0x%x er1=0x%x\n", 1215 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1216 st0, er0, st1, er1), DEBUG_PROBE); 1217 1218 return drv_mask; 1219 } 1220 1221 /* 1222 * Wait for a drive to be !BSY, and have mask in its status register. 1223 * return -1 for a timeout after "timeout" ms. 1224 */ 1225 int 1226 __wdcwait(chp, mask, bits, timeout) 1227 struct channel_softc *chp; 1228 int mask, bits, timeout; 1229 { 1230 u_char status; 1231 int time = 0; 1232 1233 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1234 :"none", chp->channel), DEBUG_STATUS); 1235 chp->ch_error = 0; 1236 1237 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1238 1239 for (;;) { 1240 chp->ch_status = status = 1241 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1242 if ((status & (WDCS_BSY | mask)) == bits) 1243 break; 1244 if (++time > timeout) { 1245 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1246 "status %x error %x (mask 0x%x bits 0x%x)\n", 1247 time, status, 1248 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1249 wd_error), mask, bits), 1250 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1251 return(WDCWAIT_TOUT); 1252 } 1253 delay(WDCDELAY); 1254 } 1255 #ifdef WDCDEBUG 1256 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1257 printf("__wdcwait: did busy-wait, time=%d\n", time); 1258 #endif 1259 if (status & WDCS_ERR) 1260 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1261 wd_error); 1262 #ifdef WDCNDELAY_DEBUG 1263 /* After autoconfig, there should be no long delays. */ 1264 if (!cold && time > WDCNDELAY_DEBUG) { 1265 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1266 if (xfer == NULL) 1267 printf("%s channel %d: warning: busy-wait took %dus\n", 1268 chp->wdc->sc_dev.dv_xname, chp->channel, 1269 WDCDELAY * time); 1270 else 1271 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1272 chp->wdc->sc_dev.dv_xname, chp->channel, 1273 xfer->drive, 1274 WDCDELAY * time); 1275 } 1276 #endif 1277 return(WDCWAIT_OK); 1278 } 1279 1280 /* 1281 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1282 * thread if possible 1283 */ 1284 int 1285 wdcwait(chp, mask, bits, timeout, flags) 1286 struct channel_softc *chp; 1287 int mask, bits, timeout, flags; 1288 { 1289 int error, i, timeout_hz = mstohz(timeout); 1290 1291 if (timeout_hz == 0 || 1292 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1293 error = __wdcwait(chp, mask, bits, timeout); 1294 else { 1295 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1296 if (error != 0) { 1297 if (chp->ch_flags & WDCF_TH_RUN) { 1298 /* 1299 * we're running in the channel thread context 1300 */ 1301 for (i = 0; i < timeout_hz; i++) { 1302 if (__wdcwait(chp, mask, bits, 1303 WDCDELAY_POLL) == 0) { 1304 error = 0; 1305 break; 1306 } 1307 tsleep(&chp, PRIBIO, "atapoll", 1); 1308 } 1309 } else { 1310 /* 1311 * we're probably in interrupt context, 1312 * ask the thread to come back here 1313 */ 1314 chp->ch_queue->queue_freese++; 1315 wakeup(&chp->thread); 1316 return(WDCWAIT_THR); 1317 } 1318 } 1319 } 1320 return(error); 1321 } 1322 1323 1324 /* 1325 * Busy-wait for DMA to complete 1326 */ 1327 int 1328 wdc_dmawait(chp, xfer, timeout) 1329 struct channel_softc *chp; 1330 struct wdc_xfer *xfer; 1331 int timeout; 1332 { 1333 int time; 1334 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1335 chp->wdc->dma_status = 1336 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1337 chp->channel, xfer->drive, 0); 1338 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1339 return 0; 1340 delay(WDCDELAY); 1341 } 1342 /* timeout, force a DMA halt */ 1343 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1344 chp->channel, xfer->drive, 1); 1345 return 1; 1346 } 1347 1348 void 1349 wdctimeout(arg) 1350 void *arg; 1351 { 1352 struct channel_softc *chp = (struct channel_softc *)arg; 1353 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1354 int s; 1355 1356 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1357 1358 s = splbio(); 1359 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1360 __wdcerror(chp, "lost interrupt"); 1361 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1362 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1363 xfer->c_bcount, 1364 xfer->c_skip); 1365 if (chp->ch_flags & WDCF_DMA_WAIT) { 1366 chp->wdc->dma_status = 1367 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1368 chp->channel, xfer->drive, 1); 1369 chp->ch_flags &= ~WDCF_DMA_WAIT; 1370 } 1371 /* 1372 * Call the interrupt routine. If we just missed an interrupt, 1373 * it will do what's needed. Else, it will take the needed 1374 * action (reset the device). 1375 * Before that we need to reinstall the timeout callback, 1376 * in case it will miss another irq while in this transfer 1377 * We arbitray chose it to be 1s 1378 */ 1379 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1380 xfer->c_flags |= C_TIMEOU; 1381 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1382 xfer->c_intr(chp, xfer, 1); 1383 } else 1384 __wdcerror(chp, "missing untimeout"); 1385 splx(s); 1386 } 1387 1388 /* 1389 * Probe drive's capabilites, for use by the controller later 1390 * Assumes drvp points to an existing drive. 1391 * XXX this should be a controller-indep function 1392 */ 1393 void 1394 wdc_probe_caps(drvp) 1395 struct ata_drive_datas *drvp; 1396 { 1397 struct ataparams params, params2; 1398 struct channel_softc *chp = drvp->chnl_softc; 1399 struct device *drv_dev = drvp->drv_softc; 1400 struct wdc_softc *wdc = chp->wdc; 1401 int i, printed; 1402 char *sep = ""; 1403 int cf_flags; 1404 1405 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1406 /* IDENTIFY failed. Can't tell more about the device */ 1407 return; 1408 } 1409 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1410 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1411 /* 1412 * Controller claims 16 and 32 bit transfers. 1413 * Re-do an IDENTIFY with 32-bit transfers, 1414 * and compare results. 1415 */ 1416 drvp->drive_flags |= DRIVE_CAP32; 1417 ata_get_params(drvp, AT_WAIT, ¶ms2); 1418 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1419 /* Not good. fall back to 16bits */ 1420 drvp->drive_flags &= ~DRIVE_CAP32; 1421 } else { 1422 aprint_normal("%s: 32-bit data port\n", 1423 drv_dev->dv_xname); 1424 } 1425 } 1426 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1427 if (params.atap_ata_major > 0x01 && 1428 params.atap_ata_major != 0xffff) { 1429 for (i = 14; i > 0; i--) { 1430 if (params.atap_ata_major & (1 << i)) { 1431 aprint_normal("%s: ATA version %d\n", 1432 drv_dev->dv_xname, i); 1433 drvp->ata_vers = i; 1434 break; 1435 } 1436 } 1437 } 1438 #endif 1439 1440 /* An ATAPI device is at last PIO mode 3 */ 1441 if (drvp->drive_flags & DRIVE_ATAPI) 1442 drvp->PIO_mode = 3; 1443 1444 /* 1445 * It's not in the specs, but it seems that some drive 1446 * returns 0xffff in atap_extensions when this field is invalid 1447 */ 1448 if (params.atap_extensions != 0xffff && 1449 (params.atap_extensions & WDC_EXT_MODES)) { 1450 printed = 0; 1451 /* 1452 * XXX some drives report something wrong here (they claim to 1453 * support PIO mode 8 !). As mode is coded on 3 bits in 1454 * SET FEATURE, limit it to 7 (so limit i to 4). 1455 * If higher mode than 7 is found, abort. 1456 */ 1457 for (i = 7; i >= 0; i--) { 1458 if ((params.atap_piomode_supp & (1 << i)) == 0) 1459 continue; 1460 if (i > 4) 1461 return; 1462 /* 1463 * See if mode is accepted. 1464 * If the controller can't set its PIO mode, 1465 * assume the defaults are good, so don't try 1466 * to set it 1467 */ 1468 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1469 /* 1470 * It's OK to pool here, it's fast enouth 1471 * to not bother waiting for interrupt 1472 */ 1473 if (ata_set_mode(drvp, 0x08 | (i + 3), 1474 AT_WAIT) != CMD_OK) 1475 continue; 1476 if (!printed) { 1477 aprint_normal("%s: drive supports PIO mode %d", 1478 drv_dev->dv_xname, i + 3); 1479 sep = ","; 1480 printed = 1; 1481 } 1482 /* 1483 * If controller's driver can't set its PIO mode, 1484 * get the highter one for the drive. 1485 */ 1486 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1487 wdc->PIO_cap >= i + 3) { 1488 drvp->PIO_mode = i + 3; 1489 drvp->PIO_cap = i + 3; 1490 break; 1491 } 1492 } 1493 if (!printed) { 1494 /* 1495 * We didn't find a valid PIO mode. 1496 * Assume the values returned for DMA are buggy too 1497 */ 1498 return; 1499 } 1500 drvp->drive_flags |= DRIVE_MODE; 1501 printed = 0; 1502 for (i = 7; i >= 0; i--) { 1503 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1504 continue; 1505 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1506 (wdc->cap & WDC_CAPABILITY_MODE)) 1507 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1508 != CMD_OK) 1509 continue; 1510 if (!printed) { 1511 aprint_normal("%s DMA mode %d", sep, i); 1512 sep = ","; 1513 printed = 1; 1514 } 1515 if (wdc->cap & WDC_CAPABILITY_DMA) { 1516 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1517 wdc->DMA_cap < i) 1518 continue; 1519 drvp->DMA_mode = i; 1520 drvp->DMA_cap = i; 1521 drvp->drive_flags |= DRIVE_DMA; 1522 } 1523 break; 1524 } 1525 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1526 printed = 0; 1527 for (i = 7; i >= 0; i--) { 1528 if ((params.atap_udmamode_supp & (1 << i)) 1529 == 0) 1530 continue; 1531 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1532 (wdc->cap & WDC_CAPABILITY_UDMA)) 1533 if (ata_set_mode(drvp, 0x40 | i, 1534 AT_WAIT) != CMD_OK) 1535 continue; 1536 if (!printed) { 1537 aprint_normal("%s Ultra-DMA mode %d", 1538 sep, i); 1539 if (i == 2) 1540 aprint_normal(" (Ultra/33)"); 1541 else if (i == 4) 1542 aprint_normal(" (Ultra/66)"); 1543 else if (i == 5) 1544 aprint_normal(" (Ultra/100)"); 1545 else if (i == 6) 1546 aprint_normal(" (Ultra/133)"); 1547 sep = ","; 1548 printed = 1; 1549 } 1550 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1551 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1552 wdc->UDMA_cap < i) 1553 continue; 1554 drvp->UDMA_mode = i; 1555 drvp->UDMA_cap = i; 1556 drvp->drive_flags |= DRIVE_UDMA; 1557 } 1558 break; 1559 } 1560 } 1561 aprint_normal("\n"); 1562 } 1563 1564 /* Try to guess ATA version here, if it didn't get reported */ 1565 if (drvp->ata_vers == 0) { 1566 if (drvp->drive_flags & DRIVE_UDMA) 1567 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1568 else if (drvp->PIO_cap > 2) 1569 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1570 } 1571 cf_flags = drv_dev->dv_cfdata->cf_flags; 1572 if (cf_flags & ATA_CONFIG_PIO_SET) { 1573 drvp->PIO_mode = 1574 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1575 drvp->drive_flags |= DRIVE_MODE; 1576 } 1577 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1578 /* don't care about DMA modes */ 1579 return; 1580 } 1581 if (cf_flags & ATA_CONFIG_DMA_SET) { 1582 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1583 ATA_CONFIG_DMA_DISABLE) { 1584 drvp->drive_flags &= ~DRIVE_DMA; 1585 } else { 1586 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1587 ATA_CONFIG_DMA_OFF; 1588 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1589 } 1590 } 1591 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1592 /* don't care about UDMA modes */ 1593 return; 1594 } 1595 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1596 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1597 ATA_CONFIG_UDMA_DISABLE) { 1598 drvp->drive_flags &= ~DRIVE_UDMA; 1599 } else { 1600 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1601 ATA_CONFIG_UDMA_OFF; 1602 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1603 } 1604 } 1605 } 1606 1607 /* 1608 * downgrade the transfer mode of a drive after an error. return 1 if 1609 * downgrade was possible, 0 otherwise. 1610 */ 1611 int 1612 wdc_downgrade_mode(drvp, flags) 1613 struct ata_drive_datas *drvp; 1614 { 1615 struct channel_softc *chp = drvp->chnl_softc; 1616 struct device *drv_dev = drvp->drv_softc; 1617 struct wdc_softc *wdc = chp->wdc; 1618 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1619 1620 /* if drive or controller don't know its mode, we can't do much */ 1621 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1622 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1623 return 0; 1624 /* current drive mode was set by a config flag, let it this way */ 1625 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1626 (cf_flags & ATA_CONFIG_DMA_SET) || 1627 (cf_flags & ATA_CONFIG_UDMA_SET)) 1628 return 0; 1629 1630 /* 1631 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1632 * Maybe we didn't properly notice the cable type 1633 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1634 * It helps in some cases. 1635 */ 1636 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1637 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1638 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1639 drv_dev->dv_xname, drvp->UDMA_mode); 1640 } 1641 1642 /* 1643 * If we were using ultra-DMA, don't downgrade to multiword DMA 1644 * if we noticed a CRC error. It has been noticed that CRC errors 1645 * in ultra-DMA lead to silent data corruption in multiword DMA. 1646 * Data corruption is less likely to occur in PIO mode. 1647 */ 1648 else if ((drvp->drive_flags & DRIVE_UDMA) && 1649 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1650 drvp->drive_flags &= ~DRIVE_UDMA; 1651 drvp->drive_flags |= DRIVE_DMA; 1652 drvp->DMA_mode = drvp->DMA_cap; 1653 printf("%s: transfer error, downgrading to DMA mode %d\n", 1654 drv_dev->dv_xname, drvp->DMA_mode); 1655 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1656 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1657 drvp->PIO_mode = drvp->PIO_cap; 1658 printf("%s: transfer error, downgrading to PIO mode %d\n", 1659 drv_dev->dv_xname, drvp->PIO_mode); 1660 } else /* already using PIO, can't downgrade */ 1661 return 0; 1662 1663 wdc->set_modes(chp); 1664 wdc_print_modes(chp); 1665 /* reset the channel, which will shedule all drives for setup */ 1666 wdc_reset_channel(drvp, flags); 1667 return 1; 1668 } 1669 1670 int 1671 wdc_exec_command(drvp, wdc_c) 1672 struct ata_drive_datas *drvp; 1673 struct wdc_command *wdc_c; 1674 { 1675 struct channel_softc *chp = drvp->chnl_softc; 1676 struct wdc_xfer *xfer; 1677 int s, ret; 1678 1679 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1680 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1681 DEBUG_FUNCS); 1682 1683 /* set up an xfer and queue. Wait for completion */ 1684 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1685 WDC_NOSLEEP); 1686 if (xfer == NULL) { 1687 return WDC_TRY_AGAIN; 1688 } 1689 1690 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1691 wdc_c->flags |= AT_POLL; 1692 if (wdc_c->flags & AT_POLL) 1693 xfer->c_flags |= C_POLL; 1694 xfer->drive = drvp->drive; 1695 xfer->databuf = wdc_c->data; 1696 xfer->c_bcount = wdc_c->bcount; 1697 xfer->cmd = wdc_c; 1698 xfer->c_start = __wdccommand_start; 1699 xfer->c_intr = __wdccommand_intr; 1700 xfer->c_kill_xfer = __wdccommand_done; 1701 1702 s = splbio(); 1703 wdc_exec_xfer(chp, xfer); 1704 #ifdef DIAGNOSTIC 1705 if ((wdc_c->flags & AT_POLL) != 0 && 1706 (wdc_c->flags & AT_DONE) == 0) 1707 panic("wdc_exec_command: polled command not done"); 1708 #endif 1709 if (wdc_c->flags & AT_DONE) { 1710 ret = WDC_COMPLETE; 1711 } else { 1712 if (wdc_c->flags & AT_WAIT) { 1713 while ((wdc_c->flags & AT_DONE) == 0) { 1714 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1715 } 1716 ret = WDC_COMPLETE; 1717 } else { 1718 ret = WDC_QUEUED; 1719 } 1720 } 1721 splx(s); 1722 return ret; 1723 } 1724 1725 void 1726 __wdccommand_start(chp, xfer) 1727 struct channel_softc *chp; 1728 struct wdc_xfer *xfer; 1729 { 1730 int drive = xfer->drive; 1731 struct wdc_command *wdc_c = xfer->cmd; 1732 1733 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1734 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1735 DEBUG_FUNCS); 1736 1737 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1738 chp->wdc->select(chp,drive); 1739 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1740 WDSD_IBM | (drive << 4)); 1741 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1742 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1743 case WDCWAIT_OK: 1744 break; 1745 case WDCWAIT_TOUT: 1746 wdc_c->flags |= AT_TIMEOU; 1747 __wdccommand_done(chp, xfer); 1748 return; 1749 case WDCWAIT_THR: 1750 return; 1751 } 1752 if (wdc_c->flags & AT_POLL) { 1753 /* polled command, disable interrupts */ 1754 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1755 WDCTL_4BIT | WDCTL_IDS); 1756 } 1757 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1758 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1759 1760 if ((wdc_c->flags & AT_POLL) == 0) { 1761 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1762 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1763 wdctimeout, chp); 1764 return; 1765 } 1766 /* 1767 * Polled command. Wait for drive ready or drq. Done in intr(). 1768 * Wait for at last 400ns for status bit to be valid. 1769 */ 1770 delay(10); /* 400ns delay */ 1771 __wdccommand_intr(chp, xfer, 0); 1772 } 1773 1774 int 1775 __wdccommand_intr(chp, xfer, irq) 1776 struct channel_softc *chp; 1777 struct wdc_xfer *xfer; 1778 int irq; 1779 { 1780 struct wdc_command *wdc_c = xfer->cmd; 1781 int bcount = wdc_c->bcount; 1782 char *data = wdc_c->data; 1783 int wflags; 1784 1785 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1786 /* both wait and poll, we can tsleep here */ 1787 wflags = 0; 1788 } else { 1789 wflags = AT_POLL; 1790 } 1791 1792 again: 1793 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1794 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1795 /* 1796 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1797 * Reselect again, it doesn't hurt for others commands, and the time 1798 * penalty for the extra regiter write is acceptable, 1799 * wdc_exec_command() isn't called often (mosly for autoconfig) 1800 */ 1801 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1802 WDSD_IBM | (xfer->drive << 4)); 1803 if ((wdc_c->flags & AT_XFDONE) != 0) { 1804 /* 1805 * We have completed a data xfer. The drive should now be 1806 * in its initial state 1807 */ 1808 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1809 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1810 wflags) == WDCWAIT_TOUT) { 1811 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1812 return 0; /* IRQ was not for us */ 1813 wdc_c->flags |= AT_TIMEOU; 1814 } 1815 goto out; 1816 } 1817 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1818 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1819 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1820 return 0; /* IRQ was not for us */ 1821 wdc_c->flags |= AT_TIMEOU; 1822 goto out; 1823 } 1824 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1825 chp->wdc->irqack(chp); 1826 if (wdc_c->flags & AT_READ) { 1827 if ((chp->ch_status & WDCS_DRQ) == 0) { 1828 wdc_c->flags |= AT_TIMEOU; 1829 goto out; 1830 } 1831 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1832 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1833 0, (u_int32_t*)data, bcount >> 2); 1834 data += bcount & 0xfffffffc; 1835 bcount = bcount & 0x03; 1836 } 1837 if (bcount > 0) 1838 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1839 wd_data, (u_int16_t *)data, bcount >> 1); 1840 /* at this point the drive should be in its initial state */ 1841 wdc_c->flags |= AT_XFDONE; 1842 /* XXX should read status register here ? */ 1843 } else if (wdc_c->flags & AT_WRITE) { 1844 if ((chp->ch_status & WDCS_DRQ) == 0) { 1845 wdc_c->flags |= AT_TIMEOU; 1846 goto out; 1847 } 1848 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1849 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1850 0, (u_int32_t*)data, bcount >> 2); 1851 data += bcount & 0xfffffffc; 1852 bcount = bcount & 0x03; 1853 } 1854 if (bcount > 0) 1855 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1856 wd_data, (u_int16_t *)data, bcount >> 1); 1857 wdc_c->flags |= AT_XFDONE; 1858 if ((wdc_c->flags & AT_POLL) == 0) { 1859 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1860 callout_reset(&chp->ch_callout, 1861 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1862 return 1; 1863 } else { 1864 goto again; 1865 } 1866 } 1867 out: 1868 __wdccommand_done(chp, xfer); 1869 return 1; 1870 } 1871 1872 void 1873 __wdccommand_done(chp, xfer) 1874 struct channel_softc *chp; 1875 struct wdc_xfer *xfer; 1876 { 1877 struct wdc_command *wdc_c = xfer->cmd; 1878 1879 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1880 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1881 1882 callout_stop(&chp->ch_callout); 1883 1884 if (chp->ch_status & WDCS_DWF) 1885 wdc_c->flags |= AT_DF; 1886 if (chp->ch_status & WDCS_ERR) { 1887 wdc_c->flags |= AT_ERROR; 1888 wdc_c->r_error = chp->ch_error; 1889 } 1890 wdc_c->flags |= AT_DONE; 1891 if ((wdc_c->flags & AT_READREG) != 0 && 1892 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1893 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1894 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1895 wd_sdh); 1896 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1897 wd_cyl_hi) << 8; 1898 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1899 wd_cyl_lo); 1900 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1901 wd_sector); 1902 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1903 wd_seccnt); 1904 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1905 wd_error); 1906 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1907 wd_precomp); 1908 } 1909 1910 if (wdc_c->flags & AT_POLL) { 1911 /* enable interrupts */ 1912 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1913 WDCTL_4BIT); 1914 } 1915 wdc_free_xfer(chp, xfer); 1916 if (wdc_c->flags & AT_WAIT) 1917 wakeup(wdc_c); 1918 else if (wdc_c->callback) 1919 wdc_c->callback(wdc_c->callback_arg); 1920 wdcstart(chp); 1921 return; 1922 } 1923 1924 /* 1925 * Send a command. The drive should be ready. 1926 * Assumes interrupts are blocked. 1927 */ 1928 void 1929 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1930 struct channel_softc *chp; 1931 u_int8_t drive; 1932 u_int8_t command; 1933 u_int16_t cylin; 1934 u_int8_t head, sector, count, precomp; 1935 { 1936 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1937 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1938 chp->channel, drive, command, cylin, head, sector, count, precomp), 1939 DEBUG_FUNCS); 1940 1941 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1942 chp->wdc->select(chp,drive); 1943 1944 /* Select drive, head, and addressing mode. */ 1945 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1946 WDSD_IBM | (drive << 4) | head); 1947 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1948 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1949 precomp); 1950 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1951 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1952 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1953 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1954 1955 /* Send command. */ 1956 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1957 return; 1958 } 1959 1960 /* 1961 * Send a 48-bit addressing command. The drive should be ready. 1962 * Assumes interrupts are blocked. 1963 */ 1964 void 1965 wdccommandext(chp, drive, command, blkno, count) 1966 struct channel_softc *chp; 1967 u_int8_t drive; 1968 u_int8_t command; 1969 u_int64_t blkno; 1970 u_int16_t count; 1971 { 1972 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1973 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1974 chp->channel, drive, command, (u_int32_t) blkno, count), 1975 DEBUG_FUNCS); 1976 1977 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1978 chp->wdc->select(chp,drive); 1979 1980 /* Select drive, head, and addressing mode. */ 1981 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1982 (drive << 4) | WDSD_LBA); 1983 1984 /* previous */ 1985 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1986 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1987 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1988 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1989 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1990 1991 /* current */ 1992 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1993 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 1995 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 1996 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 1997 1998 /* Send command. */ 1999 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2000 return; 2001 } 2002 2003 /* 2004 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2005 * tested by the caller. 2006 */ 2007 void 2008 wdccommandshort(chp, drive, command) 2009 struct channel_softc *chp; 2010 int drive; 2011 int command; 2012 { 2013 2014 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2015 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2016 DEBUG_FUNCS); 2017 2018 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2019 chp->wdc->select(chp,drive); 2020 2021 /* Select drive. */ 2022 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2023 WDSD_IBM | (drive << 4)); 2024 2025 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2026 } 2027 2028 /* Add a command to the queue and start controller. Must be called at splbio */ 2029 2030 void 2031 wdc_exec_xfer(chp, xfer) 2032 struct channel_softc *chp; 2033 struct wdc_xfer *xfer; 2034 { 2035 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2036 chp->channel, xfer->drive), DEBUG_XFERS); 2037 2038 /* complete xfer setup */ 2039 xfer->chp = chp; 2040 2041 /* 2042 * If we are a polled command, and the list is not empty, 2043 * we are doing a dump. Drop the list to allow the polled command 2044 * to complete, we're going to reboot soon anyway. 2045 */ 2046 if ((xfer->c_flags & C_POLL) != 0 && 2047 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2048 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2049 } 2050 /* insert at the end of command list */ 2051 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2052 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2053 chp->ch_flags), DEBUG_XFERS); 2054 wdcstart(chp); 2055 } 2056 2057 struct wdc_xfer * 2058 wdc_get_xfer(flags) 2059 int flags; 2060 { 2061 struct wdc_xfer *xfer; 2062 int s; 2063 2064 s = splbio(); 2065 xfer = pool_get(&wdc_xfer_pool, 2066 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2067 splx(s); 2068 if (xfer != NULL) { 2069 memset(xfer, 0, sizeof(struct wdc_xfer)); 2070 } 2071 return xfer; 2072 } 2073 2074 void 2075 wdc_free_xfer(chp, xfer) 2076 struct channel_softc *chp; 2077 struct wdc_xfer *xfer; 2078 { 2079 struct wdc_softc *wdc = chp->wdc; 2080 int s; 2081 2082 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2083 (*wdc->free_hw)(chp); 2084 s = splbio(); 2085 chp->ch_flags &= ~WDCF_ACTIVE; 2086 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2087 pool_put(&wdc_xfer_pool, xfer); 2088 splx(s); 2089 } 2090 2091 /* 2092 * Kill off all pending xfers for a channel_softc. 2093 * 2094 * Must be called at splbio(). 2095 */ 2096 void 2097 wdc_kill_pending(chp) 2098 struct channel_softc *chp; 2099 { 2100 struct wdc_xfer *xfer; 2101 2102 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2103 chp = xfer->chp; 2104 (*xfer->c_kill_xfer)(chp, xfer); 2105 } 2106 } 2107 2108 static void 2109 __wdcerror(chp, msg) 2110 struct channel_softc *chp; 2111 char *msg; 2112 { 2113 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2114 2115 if (xfer == NULL) 2116 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2117 msg); 2118 else 2119 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2120 chp->channel, xfer->drive, msg); 2121 } 2122 2123 /* 2124 * the bit bucket 2125 */ 2126 void 2127 wdcbit_bucket(chp, size) 2128 struct channel_softc *chp; 2129 int size; 2130 { 2131 2132 for (; size >= 2; size -= 2) 2133 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2134 if (size) 2135 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2136 } 2137 2138 int 2139 wdc_addref(chp) 2140 struct channel_softc *chp; 2141 { 2142 struct wdc_softc *wdc = chp->wdc; 2143 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2144 int s, error = 0; 2145 2146 s = splbio(); 2147 if (adapt->adapt_refcnt++ == 0 && 2148 adapt->adapt_enable != NULL) { 2149 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2150 if (error) 2151 adapt->adapt_refcnt--; 2152 } 2153 splx(s); 2154 return (error); 2155 } 2156 2157 void 2158 wdc_delref(chp) 2159 struct channel_softc *chp; 2160 { 2161 struct wdc_softc *wdc = chp->wdc; 2162 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2163 int s; 2164 2165 s = splbio(); 2166 if (adapt->adapt_refcnt-- == 1 && 2167 adapt->adapt_enable != NULL) 2168 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2169 splx(s); 2170 } 2171 2172 void 2173 wdc_print_modes(struct channel_softc *chp) 2174 { 2175 int drive; 2176 struct ata_drive_datas *drvp; 2177 2178 for (drive = 0; drive < 2; drive++) { 2179 drvp = &chp->ch_drive[drive]; 2180 if ((drvp->drive_flags & DRIVE) == 0) 2181 continue; 2182 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2183 drvp->drv_softc->dv_xname, 2184 chp->wdc->sc_dev.dv_xname, 2185 chp->channel, drive, drvp->PIO_mode); 2186 if (drvp->drive_flags & DRIVE_DMA) 2187 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2188 if (drvp->drive_flags & DRIVE_UDMA) { 2189 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2190 if (drvp->UDMA_mode == 2) 2191 aprint_normal(" (Ultra/33)"); 2192 else if (drvp->UDMA_mode == 4) 2193 aprint_normal(" (Ultra/66)"); 2194 else if (drvp->UDMA_mode == 5) 2195 aprint_normal(" (Ultra/100)"); 2196 else if (drvp->UDMA_mode == 6) 2197 aprint_normal(" (Ultra/133)"); 2198 } 2199 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2200 aprint_normal(" (using DMA data transfers)"); 2201 aprint_normal("\n"); 2202 } 2203 } 2204
Indexes created Mon Sep 22 13:09:51 GMT 2025