wdc.c revision 1.149
1 /* $NetBSD: wdc.c,v 1.149 2003/10/29 22:09:41 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.149 2003/10/29 22:09:41 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 printf("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) { 272 s = splbio(); 273 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 274 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 275 chp->ch_queue->queue_freeze == 0)) { 276 chp->ch_flags &= ~WDCF_TH_RUN; 277 tsleep(&chp->thread, PRIBIO, "atath", 0); 278 chp->ch_flags |= WDCF_TH_RUN; 279 } 280 splx(s); 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 break; 283 s = splbio(); 284 if (chp->ch_flags & WDCF_TH_RESET) { 285 int drive; 286 (void) wdcreset(chp, RESET_SLEEP); 287 for (drive = 0; drive < 2; drive++) { 288 chp->ch_drive[drive].state = 0; 289 } 290 chp->ch_flags &= ~WDCF_TH_RESET; 291 chp->ch_queue->queue_freeze--; 292 wdcstart(chp); 293 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 294 chp->ch_queue->queue_freeze == 1) { 295 /* 296 * caller has bumped queue_freeze, decrease it 297 */ 298 chp->ch_queue->queue_freeze--; 299 xfer = chp->ch_queue->sc_xfer.tqh_first; 300 #ifdef DIAGNOSTIC 301 if (xfer == NULL) 302 panic("channel active with no xfer ?"); 303 #endif 304 xfer->c_start(chp, xfer); 305 } else if (chp->ch_queue->queue_freeze > 1) { 306 panic("queue_freeze"); 307 } 308 splx(s); 309 } 310 chp->thread = NULL; 311 wakeup(&chp->ch_flags); 312 kthread_exit(0); 313 } 314 315 void 316 atabusconfig(atabus_sc) 317 struct atabus_softc *atabus_sc; 318 { 319 struct channel_softc *chp = atabus_sc->sc_chan; 320 int ctrl_flags, i, error, need_delref = 0; 321 struct ataparams params; 322 struct atabus_initq *atabus_initq = NULL; 323 u_int8_t st0 = 0, st1 = 0; 324 325 if ((error = wdc_addref(chp)) != 0) { 326 aprint_error("%s: unable to enable controller\n", 327 chp->wdc->sc_dev.dv_xname); 328 goto out; 329 } 330 need_delref = 1; 331 332 if (__wdcprobe(chp, 0) == 0) 333 /* If no drives, abort attach here. */ 334 goto out; 335 336 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 337 for (i = 0; i < mstohz(3000); i++) { 338 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 339 chp->wdc->select(chp,0); 340 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 341 WDSD_IBM); 342 delay(10); /* 400ns delay */ 343 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 344 345 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 346 chp->wdc->select(chp,1); 347 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 348 WDSD_IBM | 0x10); 349 delay(10); /* 400ns delay */ 350 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 351 352 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 353 == 0 || 354 (st0 & WDCS_DRDY)) && 355 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 356 == 0 || 357 (st1 & WDCS_DRDY))) 358 break; 359 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 360 } 361 if ((st0 & WDCS_DRDY) == 0) 362 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 363 if ((st1 & WDCS_DRDY) == 0) 364 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 365 366 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 367 chp->wdc->sc_dev.dv_xname, 368 chp->channel, st0, st1), DEBUG_PROBE); 369 370 /* Wait a bit, some devices are weird just after a reset. */ 371 delay(5000); 372 373 for (i = 0; i < 2; i++) { 374 chp->ch_drive[i].chnl_softc = chp; 375 chp->ch_drive[i].drive = i; 376 /* 377 * Init error counter so that an error withing the first xfers 378 * will trigger a downgrade 379 */ 380 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 381 382 /* If controller can't do 16bit flag the drives as 32bit */ 383 if ((chp->wdc->cap & 384 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 385 WDC_CAPABILITY_DATA32) 386 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 387 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 388 continue; 389 390 /* Shortcut in case we've been shutdown */ 391 if (chp->ch_flags & WDCF_SHUTDOWN) 392 goto out; 393 394 /* issue an identify, to try to detect ghosts */ 395 error = ata_get_params(&chp->ch_drive[i], 396 AT_WAIT | AT_POLL, ¶ms); 397 if (error != CMD_OK) { 398 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 399 400 /* Shortcut in case we've been shutdown */ 401 if (chp->ch_flags & WDCF_SHUTDOWN) 402 goto out; 403 404 error = ata_get_params(&chp->ch_drive[i], 405 AT_WAIT | AT_POLL, ¶ms); 406 } 407 if (error == CMD_OK) { 408 /* If IDENTIFY succeded, this is not an OLD ctrl */ 409 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 410 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 411 } else { 412 chp->ch_drive[i].drive_flags &= 413 ~(DRIVE_ATA | DRIVE_ATAPI); 414 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 415 chp->wdc->sc_dev.dv_xname, 416 chp->channel, i, error), DEBUG_PROBE); 417 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 418 continue; 419 /* 420 * Pre-ATA drive ? 421 * Test registers writability (Error register not 422 * writable, but cyllo is), then try an ATA command. 423 */ 424 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 425 chp->wdc->select(chp,i); 426 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 427 WDSD_IBM | (i << 4)); 428 delay(10); /* 400ns delay */ 429 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 430 wd_error, 0x58); 431 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 432 wd_cyl_lo, 0xa5); 433 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 434 wd_error) == 0x58 || 435 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 436 wd_cyl_lo) != 0xa5) { 437 WDCDEBUG_PRINT(("%s:%d:%d: register " 438 "writability failed\n", 439 chp->wdc->sc_dev.dv_xname, 440 chp->channel, i), DEBUG_PROBE); 441 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 442 } 443 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 444 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 445 chp->wdc->sc_dev.dv_xname, 446 chp->channel, i), DEBUG_PROBE); 447 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 448 continue; 449 } 450 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 451 wd_command, WDCC_RECAL); 452 delay(10); /* 400ns delay */ 453 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 454 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 455 chp->wdc->sc_dev.dv_xname, 456 chp->channel, i), DEBUG_PROBE); 457 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 458 } 459 } 460 } 461 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 462 463 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 464 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 465 DEBUG_PROBE); 466 467 /* If no drives, abort here */ 468 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 469 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 470 goto out; 471 472 /* Make sure the devices probe in atabus order to avoid jitter. */ 473 simple_lock(&atabus_interlock); 474 while(1) { 475 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 476 if (atabus_initq->atabus_sc == atabus_sc) 477 break; 478 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 479 &atabus_interlock); 480 } 481 simple_unlock(&atabus_interlock); 482 483 /* 484 * Attach an ATAPI bus, if needed. 485 */ 486 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 487 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 488 #if NATAPIBUS > 0 489 wdc_atapibus_attach(atabus_sc); 490 #else 491 /* 492 * Fake the autoconfig "not configured" message 493 */ 494 aprint_normal("atapibus at %s not configured\n", 495 chp->wdc->sc_dev.dv_xname); 496 chp->atapibus = NULL; 497 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 498 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 499 #endif 500 } 501 502 for (i = 0; i < 2; i++) { 503 struct ata_device adev; 504 if ((chp->ch_drive[i].drive_flags & 505 (DRIVE_ATA | DRIVE_OLD)) == 0) { 506 continue; 507 } 508 memset(&adev, 0, sizeof(struct ata_device)); 509 adev.adev_bustype = &wdc_ata_bustype; 510 adev.adev_channel = chp->channel; 511 adev.adev_openings = 1; 512 adev.adev_drv_data = &chp->ch_drive[i]; 513 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 514 &adev, wdprint); 515 if (chp->ata_drives[i] != NULL) 516 wdc_probe_caps(&chp->ch_drive[i]); 517 else 518 chp->ch_drive[i].drive_flags &= 519 ~(DRIVE_ATA | DRIVE_OLD); 520 } 521 522 /* now that we know the drives, the controller can set its modes */ 523 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 524 chp->wdc->set_modes(chp); 525 wdc_print_modes(chp); 526 } 527 #if NATARAID > 0 528 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 529 for (i = 0; i < 2; i++) 530 if (chp->ata_drives[i] != NULL) 531 ata_raid_check_component(chp->ata_drives[i]); 532 #endif /* NATARAID > 0 */ 533 534 /* 535 * reset drive_flags for unnatached devices, reset state for attached 536 * ones 537 */ 538 for (i = 0; i < 2; i++) { 539 if (chp->ch_drive[i].drv_softc == NULL) 540 chp->ch_drive[i].drive_flags = 0; 541 else 542 chp->ch_drive[i].state = 0; 543 } 544 545 out: 546 if (atabus_initq == NULL) { 547 simple_lock(&atabus_interlock); 548 while(1) { 549 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 550 if (atabus_initq->atabus_sc == atabus_sc) 551 break; 552 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 553 &atabus_interlock); 554 } 555 simple_unlock(&atabus_interlock); 556 } 557 simple_lock(&atabus_interlock); 558 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 559 simple_unlock(&atabus_interlock); 560 561 free(atabus_initq, M_DEVBUF); 562 wakeup(&atabus_initq_head); 563 564 config_pending_decr(); 565 if (need_delref) 566 wdc_delref(chp); 567 } 568 569 570 int 571 wdprint(aux, pnp) 572 void *aux; 573 const char *pnp; 574 { 575 struct ata_device *adev = aux; 576 if (pnp) 577 aprint_normal("wd at %s", pnp); 578 aprint_normal(" drive %d", adev->adev_drv_data->drive); 579 return (UNCONF); 580 } 581 582 /* Test to see controller with at last one attached drive is there. 583 * Returns a bit for each possible drive found (0x01 for drive 0, 584 * 0x02 for drive 1). 585 * Logic: 586 * - If a status register is at 0xff, assume there is no drive here 587 * (ISA has pull-up resistors). Similarly if the status register has 588 * the value we last wrote to the bus (for IDE interfaces without pullups). 589 * If no drive at all -> return. 590 * - reset the controller, wait for it to complete (may take up to 31s !). 591 * If timeout -> return. 592 * - test ATA/ATAPI signatures. If at last one drive found -> return. 593 * - try an ATA command on the master. 594 */ 595 596 int 597 wdcprobe(chp) 598 struct channel_softc *chp; 599 { 600 return __wdcprobe(chp, 1); 601 } 602 603 int 604 __wdcprobe(chp, poll) 605 struct channel_softc *chp; 606 int poll; 607 { 608 u_int8_t st0, st1, sc, sn, cl, ch; 609 u_int8_t ret_value = 0x03; 610 u_int8_t drive; 611 612 /* 613 * Sanity check to see if the wdc channel responds at all. 614 */ 615 616 if (chp->wdc == NULL || 617 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 618 619 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 620 chp->wdc->select(chp,0); 621 622 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 623 WDSD_IBM); 624 delay(10); /* 400ns delay */ 625 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 626 627 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 628 chp->wdc->select(chp,1); 629 630 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 631 WDSD_IBM | 0x10); 632 delay(10); /* 400ns delay */ 633 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 634 635 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 636 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 637 chp->channel, st0, st1), DEBUG_PROBE); 638 639 if (st0 == 0xff || st0 == WDSD_IBM) 640 ret_value &= ~0x01; 641 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 642 ret_value &= ~0x02; 643 /* Register writability test, drive 0. */ 644 if (ret_value & 0x01) { 645 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 646 chp->wdc->select(chp,0); 647 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 648 WDSD_IBM); 649 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 650 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_cyl_lo) != 0x02) 652 ret_value &= ~0x01; 653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 654 0x01); 655 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 656 wd_cyl_lo) != 0x01) 657 ret_value &= ~0x01; 658 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 659 0x01); 660 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 661 wd_sector) != 0x01) 662 ret_value &= ~0x01; 663 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 664 0x02); 665 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 666 wd_sector) != 0x02) 667 ret_value &= ~0x01; 668 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 669 wd_cyl_lo) != 0x01) 670 ret_value &= ~0x01; 671 } 672 /* Register writability test, drive 1. */ 673 if (ret_value & 0x02) { 674 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 675 chp->wdc->select(chp,1); 676 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 677 WDSD_IBM | 0x10); 678 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 679 0x02); 680 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 681 wd_cyl_lo) != 0x02) 682 ret_value &= ~0x02; 683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 684 0x01); 685 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 686 wd_cyl_lo) != 0x01) 687 ret_value &= ~0x02; 688 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 689 0x01); 690 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 691 wd_sector) != 0x01) 692 ret_value &= ~0x02; 693 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 694 0x02); 695 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 696 wd_sector) != 0x02) 697 ret_value &= ~0x02; 698 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 699 wd_cyl_lo) != 0x01) 700 ret_value &= ~0x02; 701 } 702 703 if (ret_value == 0) 704 return 0; 705 } 706 707 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 708 chp->wdc->select(chp,0); 709 /* assert SRST, wait for reset to complete */ 710 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 711 WDSD_IBM); 712 delay(10); /* 400ns delay */ 713 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 714 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 715 DELAY(2000); 716 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 717 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 718 delay(10); /* 400ns delay */ 719 720 ret_value = __wdcwait_reset(chp, ret_value, poll); 721 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 722 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 723 ret_value), DEBUG_PROBE); 724 725 /* if reset failed, there's nothing here */ 726 if (ret_value == 0) 727 return 0; 728 729 /* 730 * Test presence of drives. First test register signatures looking for 731 * ATAPI devices. If it's not an ATAPI and reset said there may be 732 * something here assume it's ATA or OLD. Ghost will be killed later in 733 * attach routine. 734 */ 735 for (drive = 0; drive < 2; drive++) { 736 if ((ret_value & (0x01 << drive)) == 0) 737 continue; 738 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 739 chp->wdc->select(chp,drive); 740 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 741 WDSD_IBM | (drive << 4)); 742 delay(10); /* 400ns delay */ 743 /* Save registers contents */ 744 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 745 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 746 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 747 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 748 749 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 750 "cl=0x%x ch=0x%x\n", 751 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 752 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 753 /* 754 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 755 * we get wrong values here, so ignore it. 756 */ 757 if (cl == 0x14 && ch == 0xeb) { 758 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 759 } else { 760 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 761 if (chp->wdc == NULL || 762 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 763 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 764 } 765 } 766 return (ret_value); 767 } 768 769 void 770 wdcattach(chp) 771 struct channel_softc *chp; 772 { 773 static int inited = 0; 774 775 if (chp->ch_flags & WDCF_DISABLED) 776 return; 777 778 /* initialise global data */ 779 callout_init(&chp->ch_callout); 780 if (inited == 0) { 781 /* Initialize the wdc_xfer pool. */ 782 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 783 0, 0, "wdcspl", NULL); 784 inited++; 785 } 786 TAILQ_INIT(&chp->ch_queue->sc_xfer); 787 chp->ch_queue->queue_freeze = 0; 788 789 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 790 } 791 792 /* 793 * Call activate routine of underlying devices. 794 */ 795 int 796 atabusactivate(self, act) 797 struct device *self; 798 enum devact act; 799 { 800 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 801 struct channel_softc *chp = atabus_sc->sc_chan; 802 struct device *sc = 0; 803 int s, i, error = 0; 804 805 s = splbio(); 806 switch (act) { 807 case DVACT_ACTIVATE: 808 error = EOPNOTSUPP; 809 break; 810 811 case DVACT_DEACTIVATE: 812 /* 813 * We might call deactivate routine for 814 * the children of atapibus twice (once via 815 * atapibus, once directly), but since 816 * config_deactivate maintains DVF_ACTIVE flag, 817 * it's safe. 818 */ 819 sc = chp->atapibus; 820 if (sc != NULL) { 821 error = config_deactivate(sc); 822 if (error != 0) 823 goto out; 824 } 825 826 for (i = 0; i < 2; i++) { 827 sc = chp->ch_drive[i].drv_softc; 828 WDCDEBUG_PRINT(("atabusactivate: %s:" 829 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 830 sc == NULL ? "nodrv" : sc->dv_xname), 831 DEBUG_DETACH); 832 if (sc != NULL) { 833 error = config_deactivate(sc); 834 if (error != 0) 835 goto out; 836 } 837 } 838 break; 839 } 840 841 out: 842 splx(s); 843 844 #ifdef WDCDEBUG 845 if (sc && error != 0) 846 WDCDEBUG_PRINT(("atabusactivate: %s: " 847 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 848 error, sc->dv_xname), DEBUG_DETACH); 849 #endif 850 return (error); 851 } 852 853 int wdcactivate(self, act) 854 struct device *self; 855 enum devact act; 856 { 857 struct wdc_softc *wdc = (struct wdc_softc *)self; 858 int s, i, error = 0; 859 860 s = splbio(); 861 switch (act) { 862 case DVACT_ACTIVATE: 863 error = EOPNOTSUPP; 864 break; 865 866 case DVACT_DEACTIVATE: 867 for (i = 0; i < wdc->nchannels; i++) { 868 error = config_deactivate(wdc->channels[i]->atabus); 869 if (error) 870 break; 871 } 872 break; 873 } 874 splx(s); 875 return (error); 876 } 877 878 879 int 880 atabusdetach(self, flags) 881 struct device *self; 882 int flags; 883 { 884 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 885 struct channel_softc *chp = atabus_sc->sc_chan; 886 struct device *sc = 0; 887 int i, error = 0; 888 889 /* shutdown channel */ 890 chp->ch_flags |= WDCF_SHUTDOWN; 891 wakeup(&chp->thread); 892 while (chp->thread != NULL) 893 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 894 895 /* 896 * Detach atapibus and its children. 897 */ 898 sc = chp->atapibus; 899 if (sc != NULL) { 900 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 901 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 902 error = config_detach(sc, flags); 903 if (error != 0) 904 goto out; 905 } 906 907 /* 908 * Detach our other children. 909 */ 910 for (i = 0; i < 2; i++) { 911 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 912 continue; 913 sc = chp->ch_drive[i].drv_softc; 914 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 915 atabus_sc->sc_dev.dv_xname, 916 sc == NULL ? "nodrv" : sc->dv_xname), 917 DEBUG_DETACH); 918 if (sc != NULL) { 919 error = config_detach(sc, flags); 920 if (error != 0) 921 goto out; 922 } 923 } 924 925 wdc_kill_pending(chp); 926 927 out: 928 #ifdef WDCDEBUG 929 if (sc && error != 0) 930 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 931 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 932 DEBUG_DETACH); 933 #endif 934 return (error); 935 } 936 937 int 938 wdcdetach(self, flags) 939 struct device *self; 940 int flags; 941 { 942 struct wdc_softc *wdc = (struct wdc_softc *)self; 943 struct channel_softc *chp; 944 int i, error = 0; 945 946 for (i = 0; i < wdc->nchannels; i++) { 947 chp = wdc->channels[i]; 948 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 949 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 950 error = config_detach(chp->atabus, flags); 951 if (error) 952 break; 953 } 954 return (error); 955 } 956 957 /* 958 * Start I/O on a controller, for the given channel. 959 * The first xfer may be not for our channel if the channel queues 960 * are shared. 961 */ 962 void 963 wdcstart(chp) 964 struct channel_softc *chp; 965 { 966 struct wdc_xfer *xfer; 967 968 #ifdef WDC_DIAGNOSTIC 969 int spl1, spl2; 970 971 spl1 = splbio(); 972 spl2 = splbio(); 973 if (spl2 != spl1) { 974 printf("wdcstart: not at splbio()\n"); 975 panic("wdcstart"); 976 } 977 splx(spl2); 978 splx(spl1); 979 #endif /* WDC_DIAGNOSTIC */ 980 981 /* is there a xfer ? */ 982 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 983 return; 984 985 /* adjust chp, in case we have a shared queue */ 986 chp = xfer->chp; 987 988 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 989 return; /* channel aleady active */ 990 } 991 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 992 return; /* queue froozen */ 993 } 994 #ifdef DIAGNOSTIC 995 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 996 panic("wdcstart: channel waiting for irq"); 997 #endif 998 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 999 if (!(*chp->wdc->claim_hw)(chp, 0)) 1000 return; 1001 1002 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1003 chp->channel, xfer->drive), DEBUG_XFERS); 1004 chp->ch_flags |= WDCF_ACTIVE; 1005 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1006 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1007 chp->ch_drive[xfer->drive].state = 0; 1008 } 1009 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1010 KASSERT(xfer->c_flags & C_POLL); 1011 xfer->c_start(chp, xfer); 1012 } 1013 1014 /* restart an interrupted I/O */ 1015 void 1016 wdcrestart(v) 1017 void *v; 1018 { 1019 struct channel_softc *chp = v; 1020 int s; 1021 1022 s = splbio(); 1023 wdcstart(chp); 1024 splx(s); 1025 } 1026 1027 1028 /* 1029 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1030 * errors on the current operation, mark it done if necessary, and start the 1031 * next request. Also check for a partially done transfer, and continue with 1032 * the next chunk if so. 1033 */ 1034 int 1035 wdcintr(arg) 1036 void *arg; 1037 { 1038 struct channel_softc *chp = arg; 1039 struct wdc_xfer *xfer; 1040 int ret; 1041 1042 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1043 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1044 DEBUG_INTR); 1045 return (0); 1046 } 1047 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1048 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1049 /* try to clear the pending interrupt anyway */ 1050 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1051 return (0); 1052 } 1053 1054 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1055 xfer = chp->ch_queue->sc_xfer.tqh_first; 1056 if (chp->ch_flags & WDCF_DMA_WAIT) { 1057 chp->wdc->dma_status = 1058 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1059 xfer->drive, 0); 1060 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1061 /* IRQ not for us, not detected by DMA engine */ 1062 return 0; 1063 } 1064 chp->ch_flags &= ~WDCF_DMA_WAIT; 1065 } 1066 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1067 ret = xfer->c_intr(chp, xfer, 1); 1068 if (ret == 0) /* irq was not for us, still waiting for irq */ 1069 chp->ch_flags |= WDCF_IRQ_WAIT; 1070 return (ret); 1071 } 1072 1073 /* Put all disk in RESET state */ 1074 void 1075 wdc_reset_channel(drvp, flags) 1076 struct ata_drive_datas *drvp; 1077 int flags; 1078 { 1079 struct channel_softc *chp = drvp->chnl_softc; 1080 int drive; 1081 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1082 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1083 DEBUG_FUNCS); 1084 if ((flags & AT_POLL) == 0) { 1085 chp->ch_flags |= WDCF_TH_RESET; 1086 chp->ch_queue->queue_freeze++; 1087 wakeup(&chp->thread); 1088 return; 1089 } 1090 (void) wdcreset(chp, RESET_POLL); 1091 for (drive = 0; drive < 2; drive++) { 1092 chp->ch_drive[drive].state = 0; 1093 } 1094 } 1095 1096 int 1097 wdcreset(chp, poll) 1098 struct channel_softc *chp; 1099 int poll; 1100 { 1101 int drv_mask1, drv_mask2; 1102 1103 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1104 chp->wdc->select(chp,0); 1105 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1106 WDSD_IBM); /* master */ 1107 delay(10); /* 400ns delay */ 1108 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1109 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1110 delay(2000); 1111 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1112 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1113 WDCTL_4BIT | WDCTL_IDS); 1114 delay(10); /* 400ns delay */ 1115 1116 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1117 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1118 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1119 (poll == RESET_SLEEP) ? 0 : 1); 1120 if (drv_mask2 != drv_mask1) { 1121 printf("%s channel %d: reset failed for", 1122 chp->wdc->sc_dev.dv_xname, chp->channel); 1123 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1124 printf(" drive 0"); 1125 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1126 printf(" drive 1"); 1127 printf("\n"); 1128 } 1129 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1130 return (drv_mask1 != drv_mask2) ? 1 : 0; 1131 } 1132 1133 static int 1134 __wdcwait_reset(chp, drv_mask, poll) 1135 struct channel_softc *chp; 1136 int drv_mask; 1137 { 1138 int timeout, nloop; 1139 u_int8_t st0 = 0, st1 = 0; 1140 #ifdef WDCDEBUG 1141 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1142 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1143 #endif 1144 1145 if (poll) 1146 nloop = WDCNDELAY_RST; 1147 else 1148 nloop = WDC_RESET_WAIT * hz / 1000; 1149 /* wait for BSY to deassert */ 1150 for (timeout = 0; timeout < nloop; timeout++) { 1151 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1152 chp->wdc->select(chp,0); 1153 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1154 WDSD_IBM); /* master */ 1155 delay(10); 1156 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1157 #ifdef WDCDEBUG 1158 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1159 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1160 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1161 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1162 #endif 1163 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1164 chp->wdc->select(chp,1); 1165 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1166 WDSD_IBM | 0x10); /* slave */ 1167 delay(10); 1168 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1169 #ifdef WDCDEBUG 1170 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1171 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1172 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1173 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1174 #endif 1175 1176 if ((drv_mask & 0x01) == 0) { 1177 /* no master */ 1178 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1179 /* No master, slave is ready, it's done */ 1180 goto end; 1181 } 1182 } else if ((drv_mask & 0x02) == 0) { 1183 /* no slave */ 1184 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1185 /* No slave, master is ready, it's done */ 1186 goto end; 1187 } 1188 } else { 1189 /* Wait for both master and slave to be ready */ 1190 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1191 goto end; 1192 } 1193 } 1194 if (poll) 1195 delay(WDCDELAY); 1196 else 1197 tsleep(&nloop, PRIBIO, "atarst", 1); 1198 } 1199 /* Reset timed out. Maybe it's because drv_mask was not right */ 1200 if (st0 & WDCS_BSY) 1201 drv_mask &= ~0x01; 1202 if (st1 & WDCS_BSY) 1203 drv_mask &= ~0x02; 1204 end: 1205 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1206 "cl=0x%x ch=0x%x\n", 1207 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1208 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1209 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1210 "cl=0x%x ch=0x%x\n", 1211 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1212 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1213 1214 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1215 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1216 st0, st1), DEBUG_PROBE); 1217 1218 return drv_mask; 1219 } 1220 1221 /* 1222 * Wait for a drive to be !BSY, and have mask in its status register. 1223 * return -1 for a timeout after "timeout" ms. 1224 */ 1225 int 1226 __wdcwait(chp, mask, bits, timeout) 1227 struct channel_softc *chp; 1228 int mask, bits, timeout; 1229 { 1230 u_char status; 1231 int time = 0; 1232 1233 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1234 :"none", chp->channel), DEBUG_STATUS); 1235 chp->ch_error = 0; 1236 1237 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1238 1239 for (;;) { 1240 chp->ch_status = status = 1241 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1242 if ((status & (WDCS_BSY | mask)) == bits) 1243 break; 1244 if (++time > timeout) { 1245 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1246 "status %x error %x (mask 0x%x bits 0x%x)\n", 1247 time, status, 1248 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1249 wd_error), mask, bits), 1250 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1251 return(WDCWAIT_TOUT); 1252 } 1253 delay(WDCDELAY); 1254 } 1255 #ifdef WDCDEBUG 1256 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1257 printf("__wdcwait: did busy-wait, time=%d\n", time); 1258 #endif 1259 if (status & WDCS_ERR) 1260 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1261 wd_error); 1262 #ifdef WDCNDELAY_DEBUG 1263 /* After autoconfig, there should be no long delays. */ 1264 if (!cold && time > WDCNDELAY_DEBUG) { 1265 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1266 if (xfer == NULL) 1267 printf("%s channel %d: warning: busy-wait took %dus\n", 1268 chp->wdc->sc_dev.dv_xname, chp->channel, 1269 WDCDELAY * time); 1270 else 1271 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1272 chp->wdc->sc_dev.dv_xname, chp->channel, 1273 xfer->drive, 1274 WDCDELAY * time); 1275 } 1276 #endif 1277 return(WDCWAIT_OK); 1278 } 1279 1280 /* 1281 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1282 * thread if possible 1283 */ 1284 int 1285 wdcwait(chp, mask, bits, timeout, flags) 1286 struct channel_softc *chp; 1287 int mask, bits, timeout, flags; 1288 { 1289 int error, i, timeout_hz = mstohz(timeout); 1290 1291 if (timeout_hz == 0 || 1292 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1293 error = __wdcwait(chp, mask, bits, timeout); 1294 else { 1295 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1296 if (error != 0) { 1297 if ((chp->ch_flags & WDCF_TH_RUN) || 1298 (flags & AT_WAIT)) { 1299 /* 1300 * we're running in the channel thread 1301 * or some userland thread context 1302 */ 1303 for (i = 0; i < timeout_hz; i++) { 1304 if (__wdcwait(chp, mask, bits, 1305 WDCDELAY_POLL) == 0) { 1306 error = 0; 1307 break; 1308 } 1309 tsleep(&chp, PRIBIO, "atapoll", 1); 1310 } 1311 } else { 1312 /* 1313 * we're probably in interrupt context, 1314 * ask the thread to come back here 1315 */ 1316 #ifdef DIAGNOSTIC 1317 if (chp->ch_queue->queue_freeze > 0) 1318 panic("wdcwait: queue_freeze"); 1319 #endif 1320 chp->ch_queue->queue_freeze++; 1321 wakeup(&chp->thread); 1322 return(WDCWAIT_THR); 1323 } 1324 } 1325 } 1326 return(error); 1327 } 1328 1329 1330 /* 1331 * Busy-wait for DMA to complete 1332 */ 1333 int 1334 wdc_dmawait(chp, xfer, timeout) 1335 struct channel_softc *chp; 1336 struct wdc_xfer *xfer; 1337 int timeout; 1338 { 1339 int time; 1340 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1341 chp->wdc->dma_status = 1342 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1343 chp->channel, xfer->drive, 0); 1344 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1345 return 0; 1346 delay(WDCDELAY); 1347 } 1348 /* timeout, force a DMA halt */ 1349 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1350 chp->channel, xfer->drive, 1); 1351 return 1; 1352 } 1353 1354 void 1355 wdctimeout(arg) 1356 void *arg; 1357 { 1358 struct channel_softc *chp = (struct channel_softc *)arg; 1359 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1360 int s; 1361 1362 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1363 1364 s = splbio(); 1365 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1366 __wdcerror(chp, "lost interrupt"); 1367 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1368 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1369 xfer->c_bcount, 1370 xfer->c_skip); 1371 if (chp->ch_flags & WDCF_DMA_WAIT) { 1372 chp->wdc->dma_status = 1373 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1374 chp->channel, xfer->drive, 1); 1375 chp->ch_flags &= ~WDCF_DMA_WAIT; 1376 } 1377 /* 1378 * Call the interrupt routine. If we just missed an interrupt, 1379 * it will do what's needed. Else, it will take the needed 1380 * action (reset the device). 1381 * Before that we need to reinstall the timeout callback, 1382 * in case it will miss another irq while in this transfer 1383 * We arbitray chose it to be 1s 1384 */ 1385 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1386 xfer->c_flags |= C_TIMEOU; 1387 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1388 xfer->c_intr(chp, xfer, 1); 1389 } else 1390 __wdcerror(chp, "missing untimeout"); 1391 splx(s); 1392 } 1393 1394 /* 1395 * Probe drive's capabilites, for use by the controller later 1396 * Assumes drvp points to an existing drive. 1397 * XXX this should be a controller-indep function 1398 */ 1399 void 1400 wdc_probe_caps(drvp) 1401 struct ata_drive_datas *drvp; 1402 { 1403 struct ataparams params, params2; 1404 struct channel_softc *chp = drvp->chnl_softc; 1405 struct device *drv_dev = drvp->drv_softc; 1406 struct wdc_softc *wdc = chp->wdc; 1407 int i, printed; 1408 char *sep = ""; 1409 int cf_flags; 1410 1411 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1412 /* IDENTIFY failed. Can't tell more about the device */ 1413 return; 1414 } 1415 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1416 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1417 /* 1418 * Controller claims 16 and 32 bit transfers. 1419 * Re-do an IDENTIFY with 32-bit transfers, 1420 * and compare results. 1421 */ 1422 drvp->drive_flags |= DRIVE_CAP32; 1423 ata_get_params(drvp, AT_WAIT, ¶ms2); 1424 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1425 /* Not good. fall back to 16bits */ 1426 drvp->drive_flags &= ~DRIVE_CAP32; 1427 } else { 1428 aprint_normal("%s: 32-bit data port\n", 1429 drv_dev->dv_xname); 1430 } 1431 } 1432 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1433 if (params.atap_ata_major > 0x01 && 1434 params.atap_ata_major != 0xffff) { 1435 for (i = 14; i > 0; i--) { 1436 if (params.atap_ata_major & (1 << i)) { 1437 aprint_normal("%s: ATA version %d\n", 1438 drv_dev->dv_xname, i); 1439 drvp->ata_vers = i; 1440 break; 1441 } 1442 } 1443 } 1444 #endif 1445 1446 /* An ATAPI device is at last PIO mode 3 */ 1447 if (drvp->drive_flags & DRIVE_ATAPI) 1448 drvp->PIO_mode = 3; 1449 1450 /* 1451 * It's not in the specs, but it seems that some drive 1452 * returns 0xffff in atap_extensions when this field is invalid 1453 */ 1454 if (params.atap_extensions != 0xffff && 1455 (params.atap_extensions & WDC_EXT_MODES)) { 1456 printed = 0; 1457 /* 1458 * XXX some drives report something wrong here (they claim to 1459 * support PIO mode 8 !). As mode is coded on 3 bits in 1460 * SET FEATURE, limit it to 7 (so limit i to 4). 1461 * If higher mode than 7 is found, abort. 1462 */ 1463 for (i = 7; i >= 0; i--) { 1464 if ((params.atap_piomode_supp & (1 << i)) == 0) 1465 continue; 1466 if (i > 4) 1467 return; 1468 /* 1469 * See if mode is accepted. 1470 * If the controller can't set its PIO mode, 1471 * assume the defaults are good, so don't try 1472 * to set it 1473 */ 1474 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1475 /* 1476 * It's OK to pool here, it's fast enouth 1477 * to not bother waiting for interrupt 1478 */ 1479 if (ata_set_mode(drvp, 0x08 | (i + 3), 1480 AT_WAIT) != CMD_OK) 1481 continue; 1482 if (!printed) { 1483 aprint_normal("%s: drive supports PIO mode %d", 1484 drv_dev->dv_xname, i + 3); 1485 sep = ","; 1486 printed = 1; 1487 } 1488 /* 1489 * If controller's driver can't set its PIO mode, 1490 * get the highter one for the drive. 1491 */ 1492 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1493 wdc->PIO_cap >= i + 3) { 1494 drvp->PIO_mode = i + 3; 1495 drvp->PIO_cap = i + 3; 1496 break; 1497 } 1498 } 1499 if (!printed) { 1500 /* 1501 * We didn't find a valid PIO mode. 1502 * Assume the values returned for DMA are buggy too 1503 */ 1504 return; 1505 } 1506 drvp->drive_flags |= DRIVE_MODE; 1507 printed = 0; 1508 for (i = 7; i >= 0; i--) { 1509 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1510 continue; 1511 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1512 (wdc->cap & WDC_CAPABILITY_MODE)) 1513 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1514 != CMD_OK) 1515 continue; 1516 if (!printed) { 1517 aprint_normal("%s DMA mode %d", sep, i); 1518 sep = ","; 1519 printed = 1; 1520 } 1521 if (wdc->cap & WDC_CAPABILITY_DMA) { 1522 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1523 wdc->DMA_cap < i) 1524 continue; 1525 drvp->DMA_mode = i; 1526 drvp->DMA_cap = i; 1527 drvp->drive_flags |= DRIVE_DMA; 1528 } 1529 break; 1530 } 1531 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1532 printed = 0; 1533 for (i = 7; i >= 0; i--) { 1534 if ((params.atap_udmamode_supp & (1 << i)) 1535 == 0) 1536 continue; 1537 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1538 (wdc->cap & WDC_CAPABILITY_UDMA)) 1539 if (ata_set_mode(drvp, 0x40 | i, 1540 AT_WAIT) != CMD_OK) 1541 continue; 1542 if (!printed) { 1543 aprint_normal("%s Ultra-DMA mode %d", 1544 sep, i); 1545 if (i == 2) 1546 aprint_normal(" (Ultra/33)"); 1547 else if (i == 4) 1548 aprint_normal(" (Ultra/66)"); 1549 else if (i == 5) 1550 aprint_normal(" (Ultra/100)"); 1551 else if (i == 6) 1552 aprint_normal(" (Ultra/133)"); 1553 sep = ","; 1554 printed = 1; 1555 } 1556 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1557 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1558 wdc->UDMA_cap < i) 1559 continue; 1560 drvp->UDMA_mode = i; 1561 drvp->UDMA_cap = i; 1562 drvp->drive_flags |= DRIVE_UDMA; 1563 } 1564 break; 1565 } 1566 } 1567 aprint_normal("\n"); 1568 } 1569 1570 /* Try to guess ATA version here, if it didn't get reported */ 1571 if (drvp->ata_vers == 0) { 1572 if (drvp->drive_flags & DRIVE_UDMA) 1573 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1574 else if (drvp->PIO_cap > 2) 1575 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1576 } 1577 cf_flags = drv_dev->dv_cfdata->cf_flags; 1578 if (cf_flags & ATA_CONFIG_PIO_SET) { 1579 drvp->PIO_mode = 1580 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1581 drvp->drive_flags |= DRIVE_MODE; 1582 } 1583 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1584 /* don't care about DMA modes */ 1585 return; 1586 } 1587 if (cf_flags & ATA_CONFIG_DMA_SET) { 1588 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1589 ATA_CONFIG_DMA_DISABLE) { 1590 drvp->drive_flags &= ~DRIVE_DMA; 1591 } else { 1592 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1593 ATA_CONFIG_DMA_OFF; 1594 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1595 } 1596 } 1597 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1598 /* don't care about UDMA modes */ 1599 return; 1600 } 1601 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1602 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1603 ATA_CONFIG_UDMA_DISABLE) { 1604 drvp->drive_flags &= ~DRIVE_UDMA; 1605 } else { 1606 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1607 ATA_CONFIG_UDMA_OFF; 1608 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1609 } 1610 } 1611 } 1612 1613 /* 1614 * downgrade the transfer mode of a drive after an error. return 1 if 1615 * downgrade was possible, 0 otherwise. 1616 */ 1617 int 1618 wdc_downgrade_mode(drvp, flags) 1619 struct ata_drive_datas *drvp; 1620 { 1621 struct channel_softc *chp = drvp->chnl_softc; 1622 struct device *drv_dev = drvp->drv_softc; 1623 struct wdc_softc *wdc = chp->wdc; 1624 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1625 1626 /* if drive or controller don't know its mode, we can't do much */ 1627 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1628 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1629 return 0; 1630 /* current drive mode was set by a config flag, let it this way */ 1631 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1632 (cf_flags & ATA_CONFIG_DMA_SET) || 1633 (cf_flags & ATA_CONFIG_UDMA_SET)) 1634 return 0; 1635 1636 /* 1637 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1638 * Maybe we didn't properly notice the cable type 1639 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1640 * It helps in some cases. 1641 */ 1642 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1643 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1644 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1645 drv_dev->dv_xname, drvp->UDMA_mode); 1646 } 1647 1648 /* 1649 * If we were using ultra-DMA, don't downgrade to multiword DMA 1650 * if we noticed a CRC error. It has been noticed that CRC errors 1651 * in ultra-DMA lead to silent data corruption in multiword DMA. 1652 * Data corruption is less likely to occur in PIO mode. 1653 */ 1654 else if ((drvp->drive_flags & DRIVE_UDMA) && 1655 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1656 drvp->drive_flags &= ~DRIVE_UDMA; 1657 drvp->drive_flags |= DRIVE_DMA; 1658 drvp->DMA_mode = drvp->DMA_cap; 1659 printf("%s: transfer error, downgrading to DMA mode %d\n", 1660 drv_dev->dv_xname, drvp->DMA_mode); 1661 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1662 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1663 drvp->PIO_mode = drvp->PIO_cap; 1664 printf("%s: transfer error, downgrading to PIO mode %d\n", 1665 drv_dev->dv_xname, drvp->PIO_mode); 1666 } else /* already using PIO, can't downgrade */ 1667 return 0; 1668 1669 wdc->set_modes(chp); 1670 wdc_print_modes(chp); 1671 /* reset the channel, which will shedule all drives for setup */ 1672 wdc_reset_channel(drvp, flags); 1673 return 1; 1674 } 1675 1676 int 1677 wdc_exec_command(drvp, wdc_c) 1678 struct ata_drive_datas *drvp; 1679 struct wdc_command *wdc_c; 1680 { 1681 struct channel_softc *chp = drvp->chnl_softc; 1682 struct wdc_xfer *xfer; 1683 int s, ret; 1684 1685 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1686 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1687 DEBUG_FUNCS); 1688 1689 /* set up an xfer and queue. Wait for completion */ 1690 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1691 WDC_NOSLEEP); 1692 if (xfer == NULL) { 1693 return WDC_TRY_AGAIN; 1694 } 1695 1696 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1697 wdc_c->flags |= AT_POLL; 1698 if (wdc_c->flags & AT_POLL) 1699 xfer->c_flags |= C_POLL; 1700 xfer->drive = drvp->drive; 1701 xfer->databuf = wdc_c->data; 1702 xfer->c_bcount = wdc_c->bcount; 1703 xfer->cmd = wdc_c; 1704 xfer->c_start = __wdccommand_start; 1705 xfer->c_intr = __wdccommand_intr; 1706 xfer->c_kill_xfer = __wdccommand_done; 1707 1708 s = splbio(); 1709 wdc_exec_xfer(chp, xfer); 1710 #ifdef DIAGNOSTIC 1711 if ((wdc_c->flags & AT_POLL) != 0 && 1712 (wdc_c->flags & AT_DONE) == 0) 1713 panic("wdc_exec_command: polled command not done"); 1714 #endif 1715 if (wdc_c->flags & AT_DONE) { 1716 ret = WDC_COMPLETE; 1717 } else { 1718 if (wdc_c->flags & AT_WAIT) { 1719 while ((wdc_c->flags & AT_DONE) == 0) { 1720 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1721 } 1722 ret = WDC_COMPLETE; 1723 } else { 1724 ret = WDC_QUEUED; 1725 } 1726 } 1727 splx(s); 1728 return ret; 1729 } 1730 1731 void 1732 __wdccommand_start(chp, xfer) 1733 struct channel_softc *chp; 1734 struct wdc_xfer *xfer; 1735 { 1736 int drive = xfer->drive; 1737 struct wdc_command *wdc_c = xfer->cmd; 1738 1739 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1740 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1741 DEBUG_FUNCS); 1742 1743 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1744 chp->wdc->select(chp,drive); 1745 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1746 WDSD_IBM | (drive << 4)); 1747 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1748 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1749 case WDCWAIT_OK: 1750 break; 1751 case WDCWAIT_TOUT: 1752 wdc_c->flags |= AT_TIMEOU; 1753 __wdccommand_done(chp, xfer); 1754 return; 1755 case WDCWAIT_THR: 1756 return; 1757 } 1758 if (wdc_c->flags & AT_POLL) { 1759 /* polled command, disable interrupts */ 1760 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1761 WDCTL_4BIT | WDCTL_IDS); 1762 } 1763 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1764 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1765 1766 if ((wdc_c->flags & AT_POLL) == 0) { 1767 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1768 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1769 wdctimeout, chp); 1770 return; 1771 } 1772 /* 1773 * Polled command. Wait for drive ready or drq. Done in intr(). 1774 * Wait for at last 400ns for status bit to be valid. 1775 */ 1776 delay(10); /* 400ns delay */ 1777 __wdccommand_intr(chp, xfer, 0); 1778 } 1779 1780 int 1781 __wdccommand_intr(chp, xfer, irq) 1782 struct channel_softc *chp; 1783 struct wdc_xfer *xfer; 1784 int irq; 1785 { 1786 struct wdc_command *wdc_c = xfer->cmd; 1787 int bcount = wdc_c->bcount; 1788 char *data = wdc_c->data; 1789 int wflags; 1790 1791 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1792 /* both wait and poll, we can tsleep here */ 1793 wflags = AT_WAIT | AT_POLL; 1794 } else { 1795 wflags = AT_POLL; 1796 } 1797 1798 again: 1799 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1800 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1801 /* 1802 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1803 * Reselect again, it doesn't hurt for others commands, and the time 1804 * penalty for the extra regiter write is acceptable, 1805 * wdc_exec_command() isn't called often (mosly for autoconfig) 1806 */ 1807 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1808 WDSD_IBM | (xfer->drive << 4)); 1809 if ((wdc_c->flags & AT_XFDONE) != 0) { 1810 /* 1811 * We have completed a data xfer. The drive should now be 1812 * in its initial state 1813 */ 1814 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1815 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1816 wflags) == WDCWAIT_TOUT) { 1817 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1818 return 0; /* IRQ was not for us */ 1819 wdc_c->flags |= AT_TIMEOU; 1820 } 1821 goto out; 1822 } 1823 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1824 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1825 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1826 return 0; /* IRQ was not for us */ 1827 wdc_c->flags |= AT_TIMEOU; 1828 goto out; 1829 } 1830 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1831 chp->wdc->irqack(chp); 1832 if (wdc_c->flags & AT_READ) { 1833 if ((chp->ch_status & WDCS_DRQ) == 0) { 1834 wdc_c->flags |= AT_TIMEOU; 1835 goto out; 1836 } 1837 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1838 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1839 0, (u_int32_t*)data, bcount >> 2); 1840 data += bcount & 0xfffffffc; 1841 bcount = bcount & 0x03; 1842 } 1843 if (bcount > 0) 1844 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1845 wd_data, (u_int16_t *)data, bcount >> 1); 1846 /* at this point the drive should be in its initial state */ 1847 wdc_c->flags |= AT_XFDONE; 1848 /* XXX should read status register here ? */ 1849 } else if (wdc_c->flags & AT_WRITE) { 1850 if ((chp->ch_status & WDCS_DRQ) == 0) { 1851 wdc_c->flags |= AT_TIMEOU; 1852 goto out; 1853 } 1854 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1855 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1856 0, (u_int32_t*)data, bcount >> 2); 1857 data += bcount & 0xfffffffc; 1858 bcount = bcount & 0x03; 1859 } 1860 if (bcount > 0) 1861 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1862 wd_data, (u_int16_t *)data, bcount >> 1); 1863 wdc_c->flags |= AT_XFDONE; 1864 if ((wdc_c->flags & AT_POLL) == 0) { 1865 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1866 callout_reset(&chp->ch_callout, 1867 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1868 return 1; 1869 } else { 1870 goto again; 1871 } 1872 } 1873 out: 1874 __wdccommand_done(chp, xfer); 1875 return 1; 1876 } 1877 1878 void 1879 __wdccommand_done(chp, xfer) 1880 struct channel_softc *chp; 1881 struct wdc_xfer *xfer; 1882 { 1883 struct wdc_command *wdc_c = xfer->cmd; 1884 1885 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1886 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1887 1888 callout_stop(&chp->ch_callout); 1889 1890 if (chp->ch_status & WDCS_DWF) 1891 wdc_c->flags |= AT_DF; 1892 if (chp->ch_status & WDCS_ERR) { 1893 wdc_c->flags |= AT_ERROR; 1894 wdc_c->r_error = chp->ch_error; 1895 } 1896 wdc_c->flags |= AT_DONE; 1897 if ((wdc_c->flags & AT_READREG) != 0 && 1898 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1899 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1900 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1901 wd_sdh); 1902 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1903 wd_cyl_hi) << 8; 1904 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1905 wd_cyl_lo); 1906 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1907 wd_sector); 1908 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1909 wd_seccnt); 1910 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1911 wd_error); 1912 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1913 wd_precomp); 1914 } 1915 1916 if (wdc_c->flags & AT_POLL) { 1917 /* enable interrupts */ 1918 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1919 WDCTL_4BIT); 1920 } 1921 wdc_free_xfer(chp, xfer); 1922 if (wdc_c->flags & AT_WAIT) 1923 wakeup(wdc_c); 1924 else if (wdc_c->callback) 1925 wdc_c->callback(wdc_c->callback_arg); 1926 wdcstart(chp); 1927 return; 1928 } 1929 1930 /* 1931 * Send a command. The drive should be ready. 1932 * Assumes interrupts are blocked. 1933 */ 1934 void 1935 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1936 struct channel_softc *chp; 1937 u_int8_t drive; 1938 u_int8_t command; 1939 u_int16_t cylin; 1940 u_int8_t head, sector, count, precomp; 1941 { 1942 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1943 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1944 chp->channel, drive, command, cylin, head, sector, count, precomp), 1945 DEBUG_FUNCS); 1946 1947 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1948 chp->wdc->select(chp,drive); 1949 1950 /* Select drive, head, and addressing mode. */ 1951 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1952 WDSD_IBM | (drive << 4) | head); 1953 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1954 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1955 precomp); 1956 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1957 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1959 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1960 1961 /* Send command. */ 1962 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1963 return; 1964 } 1965 1966 /* 1967 * Send a 48-bit addressing command. The drive should be ready. 1968 * Assumes interrupts are blocked. 1969 */ 1970 void 1971 wdccommandext(chp, drive, command, blkno, count) 1972 struct channel_softc *chp; 1973 u_int8_t drive; 1974 u_int8_t command; 1975 u_int64_t blkno; 1976 u_int16_t count; 1977 { 1978 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1979 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1980 chp->channel, drive, command, (u_int32_t) blkno, count), 1981 DEBUG_FUNCS); 1982 1983 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1984 chp->wdc->select(chp,drive); 1985 1986 /* Select drive, head, and addressing mode. */ 1987 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1988 (drive << 4) | WDSD_LBA); 1989 1990 /* previous */ 1991 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1992 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1993 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1995 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1996 1997 /* current */ 1998 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1999 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 2000 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 2001 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 2003 2004 /* Send command. */ 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2006 return; 2007 } 2008 2009 /* 2010 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2011 * tested by the caller. 2012 */ 2013 void 2014 wdccommandshort(chp, drive, command) 2015 struct channel_softc *chp; 2016 int drive; 2017 int command; 2018 { 2019 2020 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2021 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2022 DEBUG_FUNCS); 2023 2024 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2025 chp->wdc->select(chp,drive); 2026 2027 /* Select drive. */ 2028 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2029 WDSD_IBM | (drive << 4)); 2030 2031 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2032 } 2033 2034 /* Add a command to the queue and start controller. Must be called at splbio */ 2035 2036 void 2037 wdc_exec_xfer(chp, xfer) 2038 struct channel_softc *chp; 2039 struct wdc_xfer *xfer; 2040 { 2041 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2042 chp->channel, xfer->drive), DEBUG_XFERS); 2043 2044 /* complete xfer setup */ 2045 xfer->chp = chp; 2046 2047 /* 2048 * If we are a polled command, and the list is not empty, 2049 * we are doing a dump. Drop the list to allow the polled command 2050 * to complete, we're going to reboot soon anyway. 2051 */ 2052 if ((xfer->c_flags & C_POLL) != 0 && 2053 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2054 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2055 } 2056 /* insert at the end of command list */ 2057 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2058 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2059 chp->ch_flags), DEBUG_XFERS); 2060 wdcstart(chp); 2061 } 2062 2063 struct wdc_xfer * 2064 wdc_get_xfer(flags) 2065 int flags; 2066 { 2067 struct wdc_xfer *xfer; 2068 int s; 2069 2070 s = splbio(); 2071 xfer = pool_get(&wdc_xfer_pool, 2072 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2073 splx(s); 2074 if (xfer != NULL) { 2075 memset(xfer, 0, sizeof(struct wdc_xfer)); 2076 } 2077 return xfer; 2078 } 2079 2080 void 2081 wdc_free_xfer(chp, xfer) 2082 struct channel_softc *chp; 2083 struct wdc_xfer *xfer; 2084 { 2085 struct wdc_softc *wdc = chp->wdc; 2086 int s; 2087 2088 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2089 (*wdc->free_hw)(chp); 2090 s = splbio(); 2091 chp->ch_flags &= ~WDCF_ACTIVE; 2092 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2093 pool_put(&wdc_xfer_pool, xfer); 2094 splx(s); 2095 } 2096 2097 /* 2098 * Kill off all pending xfers for a channel_softc. 2099 * 2100 * Must be called at splbio(). 2101 */ 2102 void 2103 wdc_kill_pending(chp) 2104 struct channel_softc *chp; 2105 { 2106 struct wdc_xfer *xfer; 2107 2108 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2109 chp = xfer->chp; 2110 (*xfer->c_kill_xfer)(chp, xfer); 2111 } 2112 } 2113 2114 static void 2115 __wdcerror(chp, msg) 2116 struct channel_softc *chp; 2117 char *msg; 2118 { 2119 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2120 2121 if (xfer == NULL) 2122 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2123 msg); 2124 else 2125 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2126 chp->channel, xfer->drive, msg); 2127 } 2128 2129 /* 2130 * the bit bucket 2131 */ 2132 void 2133 wdcbit_bucket(chp, size) 2134 struct channel_softc *chp; 2135 int size; 2136 { 2137 2138 for (; size >= 2; size -= 2) 2139 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2140 if (size) 2141 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2142 } 2143 2144 int 2145 wdc_addref(chp) 2146 struct channel_softc *chp; 2147 { 2148 struct wdc_softc *wdc = chp->wdc; 2149 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2150 int s, error = 0; 2151 2152 s = splbio(); 2153 if (adapt->adapt_refcnt++ == 0 && 2154 adapt->adapt_enable != NULL) { 2155 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2156 if (error) 2157 adapt->adapt_refcnt--; 2158 } 2159 splx(s); 2160 return (error); 2161 } 2162 2163 void 2164 wdc_delref(chp) 2165 struct channel_softc *chp; 2166 { 2167 struct wdc_softc *wdc = chp->wdc; 2168 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2169 int s; 2170 2171 s = splbio(); 2172 if (adapt->adapt_refcnt-- == 1 && 2173 adapt->adapt_enable != NULL) 2174 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2175 splx(s); 2176 } 2177 2178 void 2179 wdc_print_modes(struct channel_softc *chp) 2180 { 2181 int drive; 2182 struct ata_drive_datas *drvp; 2183 2184 for (drive = 0; drive < 2; drive++) { 2185 drvp = &chp->ch_drive[drive]; 2186 if ((drvp->drive_flags & DRIVE) == 0) 2187 continue; 2188 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2189 drvp->drv_softc->dv_xname, 2190 chp->wdc->sc_dev.dv_xname, 2191 chp->channel, drive, drvp->PIO_mode); 2192 if (drvp->drive_flags & DRIVE_DMA) 2193 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2194 if (drvp->drive_flags & DRIVE_UDMA) { 2195 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2196 if (drvp->UDMA_mode == 2) 2197 aprint_normal(" (Ultra/33)"); 2198 else if (drvp->UDMA_mode == 4) 2199 aprint_normal(" (Ultra/66)"); 2200 else if (drvp->UDMA_mode == 5) 2201 aprint_normal(" (Ultra/100)"); 2202 else if (drvp->UDMA_mode == 6) 2203 aprint_normal(" (Ultra/133)"); 2204 } 2205 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2206 aprint_normal(" (using DMA data transfers)"); 2207 aprint_normal("\n"); 2208 } 2209 } 2210
Indexes created Wed Sep 24 15:09:51 GMT 2025