wdc.c revision 1.150
1 /* $NetBSD: wdc.c,v 1.150 2003/10/30 01:58:17 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.150 2003/10/30 01:58:17 simonb Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 printf("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) { 272 s = splbio(); 273 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 274 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 275 chp->ch_queue->queue_freeze == 0)) { 276 chp->ch_flags &= ~WDCF_TH_RUN; 277 tsleep(&chp->thread, PRIBIO, "atath", 0); 278 chp->ch_flags |= WDCF_TH_RUN; 279 } 280 splx(s); 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 break; 283 s = splbio(); 284 if (chp->ch_flags & WDCF_TH_RESET) { 285 int drive; 286 (void) wdcreset(chp, RESET_SLEEP); 287 for (drive = 0; drive < 2; drive++) { 288 chp->ch_drive[drive].state = 0; 289 } 290 chp->ch_flags &= ~WDCF_TH_RESET; 291 chp->ch_queue->queue_freeze--; 292 wdcstart(chp); 293 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 294 chp->ch_queue->queue_freeze == 1) { 295 /* 296 * caller has bumped queue_freeze, decrease it 297 */ 298 chp->ch_queue->queue_freeze--; 299 xfer = chp->ch_queue->sc_xfer.tqh_first; 300 #ifdef DIAGNOSTIC 301 if (xfer == NULL) 302 panic("channel active with no xfer ?"); 303 #endif 304 xfer->c_start(chp, xfer); 305 } else if (chp->ch_queue->queue_freeze > 1) { 306 panic("queue_freeze"); 307 } 308 splx(s); 309 } 310 chp->thread = NULL; 311 wakeup(&chp->ch_flags); 312 kthread_exit(0); 313 } 314 315 void 316 atabusconfig(atabus_sc) 317 struct atabus_softc *atabus_sc; 318 { 319 struct channel_softc *chp = atabus_sc->sc_chan; 320 int i, error, need_delref = 0; 321 struct ataparams params; 322 struct atabus_initq *atabus_initq = NULL; 323 u_int8_t st0 = 0, st1 = 0; 324 325 if ((error = wdc_addref(chp)) != 0) { 326 aprint_error("%s: unable to enable controller\n", 327 chp->wdc->sc_dev.dv_xname); 328 goto out; 329 } 330 need_delref = 1; 331 332 if (__wdcprobe(chp, 0) == 0) 333 /* If no drives, abort attach here. */ 334 goto out; 335 336 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 337 for (i = 0; i < mstohz(3000); i++) { 338 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 339 chp->wdc->select(chp,0); 340 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 341 WDSD_IBM); 342 delay(10); /* 400ns delay */ 343 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 344 345 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 346 chp->wdc->select(chp,1); 347 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 348 WDSD_IBM | 0x10); 349 delay(10); /* 400ns delay */ 350 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 351 352 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 353 == 0 || 354 (st0 & WDCS_DRDY)) && 355 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 356 == 0 || 357 (st1 & WDCS_DRDY))) 358 break; 359 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 360 } 361 if ((st0 & WDCS_DRDY) == 0) 362 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 363 if ((st1 & WDCS_DRDY) == 0) 364 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 365 366 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 367 chp->wdc->sc_dev.dv_xname, 368 chp->channel, st0, st1), DEBUG_PROBE); 369 370 /* Wait a bit, some devices are weird just after a reset. */ 371 delay(5000); 372 373 for (i = 0; i < 2; i++) { 374 chp->ch_drive[i].chnl_softc = chp; 375 chp->ch_drive[i].drive = i; 376 /* 377 * Init error counter so that an error withing the first xfers 378 * will trigger a downgrade 379 */ 380 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 381 382 /* If controller can't do 16bit flag the drives as 32bit */ 383 if ((chp->wdc->cap & 384 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 385 WDC_CAPABILITY_DATA32) 386 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 387 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 388 continue; 389 390 /* Shortcut in case we've been shutdown */ 391 if (chp->ch_flags & WDCF_SHUTDOWN) 392 goto out; 393 394 /* issue an identify, to try to detect ghosts */ 395 error = ata_get_params(&chp->ch_drive[i], 396 AT_WAIT | AT_POLL, ¶ms); 397 if (error != CMD_OK) { 398 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 399 400 /* Shortcut in case we've been shutdown */ 401 if (chp->ch_flags & WDCF_SHUTDOWN) 402 goto out; 403 404 error = ata_get_params(&chp->ch_drive[i], 405 AT_WAIT | AT_POLL, ¶ms); 406 } 407 if (error == CMD_OK) { 408 /* If IDENTIFY succeded, this is not an OLD ctrl */ 409 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 410 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 411 } else { 412 chp->ch_drive[i].drive_flags &= 413 ~(DRIVE_ATA | DRIVE_ATAPI); 414 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 415 chp->wdc->sc_dev.dv_xname, 416 chp->channel, i, error), DEBUG_PROBE); 417 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 418 continue; 419 /* 420 * Pre-ATA drive ? 421 * Test registers writability (Error register not 422 * writable, but cyllo is), then try an ATA command. 423 */ 424 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 425 chp->wdc->select(chp,i); 426 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 427 WDSD_IBM | (i << 4)); 428 delay(10); /* 400ns delay */ 429 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 430 wd_error, 0x58); 431 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 432 wd_cyl_lo, 0xa5); 433 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 434 wd_error) == 0x58 || 435 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 436 wd_cyl_lo) != 0xa5) { 437 WDCDEBUG_PRINT(("%s:%d:%d: register " 438 "writability failed\n", 439 chp->wdc->sc_dev.dv_xname, 440 chp->channel, i), DEBUG_PROBE); 441 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 442 } 443 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 444 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 445 chp->wdc->sc_dev.dv_xname, 446 chp->channel, i), DEBUG_PROBE); 447 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 448 continue; 449 } 450 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 451 wd_command, WDCC_RECAL); 452 delay(10); /* 400ns delay */ 453 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 454 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 455 chp->wdc->sc_dev.dv_xname, 456 chp->channel, i), DEBUG_PROBE); 457 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 458 } 459 } 460 } 461 462 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 463 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 464 DEBUG_PROBE); 465 466 /* If no drives, abort here */ 467 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 468 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 469 goto out; 470 471 /* Make sure the devices probe in atabus order to avoid jitter. */ 472 simple_lock(&atabus_interlock); 473 while(1) { 474 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 475 if (atabus_initq->atabus_sc == atabus_sc) 476 break; 477 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 478 &atabus_interlock); 479 } 480 simple_unlock(&atabus_interlock); 481 482 /* 483 * Attach an ATAPI bus, if needed. 484 */ 485 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 486 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 487 #if NATAPIBUS > 0 488 wdc_atapibus_attach(atabus_sc); 489 #else 490 /* 491 * Fake the autoconfig "not configured" message 492 */ 493 aprint_normal("atapibus at %s not configured\n", 494 chp->wdc->sc_dev.dv_xname); 495 chp->atapibus = NULL; 496 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 497 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 498 #endif 499 } 500 501 for (i = 0; i < 2; i++) { 502 struct ata_device adev; 503 if ((chp->ch_drive[i].drive_flags & 504 (DRIVE_ATA | DRIVE_OLD)) == 0) { 505 continue; 506 } 507 memset(&adev, 0, sizeof(struct ata_device)); 508 adev.adev_bustype = &wdc_ata_bustype; 509 adev.adev_channel = chp->channel; 510 adev.adev_openings = 1; 511 adev.adev_drv_data = &chp->ch_drive[i]; 512 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 513 &adev, wdprint); 514 if (chp->ata_drives[i] != NULL) 515 wdc_probe_caps(&chp->ch_drive[i]); 516 else 517 chp->ch_drive[i].drive_flags &= 518 ~(DRIVE_ATA | DRIVE_OLD); 519 } 520 521 /* now that we know the drives, the controller can set its modes */ 522 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 523 chp->wdc->set_modes(chp); 524 wdc_print_modes(chp); 525 } 526 #if NATARAID > 0 527 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 528 for (i = 0; i < 2; i++) 529 if (chp->ata_drives[i] != NULL) 530 ata_raid_check_component(chp->ata_drives[i]); 531 #endif /* NATARAID > 0 */ 532 533 /* 534 * reset drive_flags for unnatached devices, reset state for attached 535 * ones 536 */ 537 for (i = 0; i < 2; i++) { 538 if (chp->ch_drive[i].drv_softc == NULL) 539 chp->ch_drive[i].drive_flags = 0; 540 else 541 chp->ch_drive[i].state = 0; 542 } 543 544 out: 545 if (atabus_initq == NULL) { 546 simple_lock(&atabus_interlock); 547 while(1) { 548 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 549 if (atabus_initq->atabus_sc == atabus_sc) 550 break; 551 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 552 &atabus_interlock); 553 } 554 simple_unlock(&atabus_interlock); 555 } 556 simple_lock(&atabus_interlock); 557 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 558 simple_unlock(&atabus_interlock); 559 560 free(atabus_initq, M_DEVBUF); 561 wakeup(&atabus_initq_head); 562 563 config_pending_decr(); 564 if (need_delref) 565 wdc_delref(chp); 566 } 567 568 569 int 570 wdprint(aux, pnp) 571 void *aux; 572 const char *pnp; 573 { 574 struct ata_device *adev = aux; 575 if (pnp) 576 aprint_normal("wd at %s", pnp); 577 aprint_normal(" drive %d", adev->adev_drv_data->drive); 578 return (UNCONF); 579 } 580 581 /* Test to see controller with at last one attached drive is there. 582 * Returns a bit for each possible drive found (0x01 for drive 0, 583 * 0x02 for drive 1). 584 * Logic: 585 * - If a status register is at 0xff, assume there is no drive here 586 * (ISA has pull-up resistors). Similarly if the status register has 587 * the value we last wrote to the bus (for IDE interfaces without pullups). 588 * If no drive at all -> return. 589 * - reset the controller, wait for it to complete (may take up to 31s !). 590 * If timeout -> return. 591 * - test ATA/ATAPI signatures. If at last one drive found -> return. 592 * - try an ATA command on the master. 593 */ 594 595 int 596 wdcprobe(chp) 597 struct channel_softc *chp; 598 { 599 return __wdcprobe(chp, 1); 600 } 601 602 int 603 __wdcprobe(chp, poll) 604 struct channel_softc *chp; 605 int poll; 606 { 607 u_int8_t st0, st1, sc, sn, cl, ch; 608 u_int8_t ret_value = 0x03; 609 u_int8_t drive; 610 611 /* 612 * Sanity check to see if the wdc channel responds at all. 613 */ 614 615 if (chp->wdc == NULL || 616 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 617 618 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 619 chp->wdc->select(chp,0); 620 621 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 622 WDSD_IBM); 623 delay(10); /* 400ns delay */ 624 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 625 626 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 627 chp->wdc->select(chp,1); 628 629 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 630 WDSD_IBM | 0x10); 631 delay(10); /* 400ns delay */ 632 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 633 634 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 635 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 636 chp->channel, st0, st1), DEBUG_PROBE); 637 638 if (st0 == 0xff || st0 == WDSD_IBM) 639 ret_value &= ~0x01; 640 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 641 ret_value &= ~0x02; 642 /* Register writability test, drive 0. */ 643 if (ret_value & 0x01) { 644 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 645 chp->wdc->select(chp,0); 646 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 647 WDSD_IBM); 648 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 649 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 650 wd_cyl_lo) != 0x02) 651 ret_value &= ~0x01; 652 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 653 0x01); 654 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 655 wd_cyl_lo) != 0x01) 656 ret_value &= ~0x01; 657 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 658 0x01); 659 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 660 wd_sector) != 0x01) 661 ret_value &= ~0x01; 662 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 663 0x02); 664 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 665 wd_sector) != 0x02) 666 ret_value &= ~0x01; 667 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 668 wd_cyl_lo) != 0x01) 669 ret_value &= ~0x01; 670 } 671 /* Register writability test, drive 1. */ 672 if (ret_value & 0x02) { 673 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 674 chp->wdc->select(chp,1); 675 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 676 WDSD_IBM | 0x10); 677 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 678 0x02); 679 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 680 wd_cyl_lo) != 0x02) 681 ret_value &= ~0x02; 682 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 683 0x01); 684 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 685 wd_cyl_lo) != 0x01) 686 ret_value &= ~0x02; 687 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 688 0x01); 689 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 690 wd_sector) != 0x01) 691 ret_value &= ~0x02; 692 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 693 0x02); 694 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 695 wd_sector) != 0x02) 696 ret_value &= ~0x02; 697 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 698 wd_cyl_lo) != 0x01) 699 ret_value &= ~0x02; 700 } 701 702 if (ret_value == 0) 703 return 0; 704 } 705 706 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 707 chp->wdc->select(chp,0); 708 /* assert SRST, wait for reset to complete */ 709 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 710 WDSD_IBM); 711 delay(10); /* 400ns delay */ 712 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 713 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 714 DELAY(2000); 715 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 716 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 717 delay(10); /* 400ns delay */ 718 719 ret_value = __wdcwait_reset(chp, ret_value, poll); 720 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 721 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 722 ret_value), DEBUG_PROBE); 723 724 /* if reset failed, there's nothing here */ 725 if (ret_value == 0) 726 return 0; 727 728 /* 729 * Test presence of drives. First test register signatures looking for 730 * ATAPI devices. If it's not an ATAPI and reset said there may be 731 * something here assume it's ATA or OLD. Ghost will be killed later in 732 * attach routine. 733 */ 734 for (drive = 0; drive < 2; drive++) { 735 if ((ret_value & (0x01 << drive)) == 0) 736 continue; 737 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 738 chp->wdc->select(chp,drive); 739 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 740 WDSD_IBM | (drive << 4)); 741 delay(10); /* 400ns delay */ 742 /* Save registers contents */ 743 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 744 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 745 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 746 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 747 748 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 749 "cl=0x%x ch=0x%x\n", 750 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 751 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 752 /* 753 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 754 * we get wrong values here, so ignore it. 755 */ 756 if (cl == 0x14 && ch == 0xeb) { 757 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 758 } else { 759 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 760 if (chp->wdc == NULL || 761 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 762 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 763 } 764 } 765 return (ret_value); 766 } 767 768 void 769 wdcattach(chp) 770 struct channel_softc *chp; 771 { 772 static int inited = 0; 773 774 if (chp->ch_flags & WDCF_DISABLED) 775 return; 776 777 /* initialise global data */ 778 callout_init(&chp->ch_callout); 779 if (inited == 0) { 780 /* Initialize the wdc_xfer pool. */ 781 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 782 0, 0, "wdcspl", NULL); 783 inited++; 784 } 785 TAILQ_INIT(&chp->ch_queue->sc_xfer); 786 chp->ch_queue->queue_freeze = 0; 787 788 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 789 } 790 791 /* 792 * Call activate routine of underlying devices. 793 */ 794 int 795 atabusactivate(self, act) 796 struct device *self; 797 enum devact act; 798 { 799 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 800 struct channel_softc *chp = atabus_sc->sc_chan; 801 struct device *sc = 0; 802 int s, i, error = 0; 803 804 s = splbio(); 805 switch (act) { 806 case DVACT_ACTIVATE: 807 error = EOPNOTSUPP; 808 break; 809 810 case DVACT_DEACTIVATE: 811 /* 812 * We might call deactivate routine for 813 * the children of atapibus twice (once via 814 * atapibus, once directly), but since 815 * config_deactivate maintains DVF_ACTIVE flag, 816 * it's safe. 817 */ 818 sc = chp->atapibus; 819 if (sc != NULL) { 820 error = config_deactivate(sc); 821 if (error != 0) 822 goto out; 823 } 824 825 for (i = 0; i < 2; i++) { 826 sc = chp->ch_drive[i].drv_softc; 827 WDCDEBUG_PRINT(("atabusactivate: %s:" 828 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 829 sc == NULL ? "nodrv" : sc->dv_xname), 830 DEBUG_DETACH); 831 if (sc != NULL) { 832 error = config_deactivate(sc); 833 if (error != 0) 834 goto out; 835 } 836 } 837 break; 838 } 839 840 out: 841 splx(s); 842 843 #ifdef WDCDEBUG 844 if (sc && error != 0) 845 WDCDEBUG_PRINT(("atabusactivate: %s: " 846 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 847 error, sc->dv_xname), DEBUG_DETACH); 848 #endif 849 return (error); 850 } 851 852 int wdcactivate(self, act) 853 struct device *self; 854 enum devact act; 855 { 856 struct wdc_softc *wdc = (struct wdc_softc *)self; 857 int s, i, error = 0; 858 859 s = splbio(); 860 switch (act) { 861 case DVACT_ACTIVATE: 862 error = EOPNOTSUPP; 863 break; 864 865 case DVACT_DEACTIVATE: 866 for (i = 0; i < wdc->nchannels; i++) { 867 error = config_deactivate(wdc->channels[i]->atabus); 868 if (error) 869 break; 870 } 871 break; 872 } 873 splx(s); 874 return (error); 875 } 876 877 878 int 879 atabusdetach(self, flags) 880 struct device *self; 881 int flags; 882 { 883 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 884 struct channel_softc *chp = atabus_sc->sc_chan; 885 struct device *sc = 0; 886 int i, error = 0; 887 888 /* shutdown channel */ 889 chp->ch_flags |= WDCF_SHUTDOWN; 890 wakeup(&chp->thread); 891 while (chp->thread != NULL) 892 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 893 894 /* 895 * Detach atapibus and its children. 896 */ 897 sc = chp->atapibus; 898 if (sc != NULL) { 899 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 900 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 901 error = config_detach(sc, flags); 902 if (error != 0) 903 goto out; 904 } 905 906 /* 907 * Detach our other children. 908 */ 909 for (i = 0; i < 2; i++) { 910 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 911 continue; 912 sc = chp->ch_drive[i].drv_softc; 913 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 914 atabus_sc->sc_dev.dv_xname, 915 sc == NULL ? "nodrv" : sc->dv_xname), 916 DEBUG_DETACH); 917 if (sc != NULL) { 918 error = config_detach(sc, flags); 919 if (error != 0) 920 goto out; 921 } 922 } 923 924 wdc_kill_pending(chp); 925 926 out: 927 #ifdef WDCDEBUG 928 if (sc && error != 0) 929 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 930 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 931 DEBUG_DETACH); 932 #endif 933 return (error); 934 } 935 936 int 937 wdcdetach(self, flags) 938 struct device *self; 939 int flags; 940 { 941 struct wdc_softc *wdc = (struct wdc_softc *)self; 942 struct channel_softc *chp; 943 int i, error = 0; 944 945 for (i = 0; i < wdc->nchannels; i++) { 946 chp = wdc->channels[i]; 947 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 948 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 949 error = config_detach(chp->atabus, flags); 950 if (error) 951 break; 952 } 953 return (error); 954 } 955 956 /* 957 * Start I/O on a controller, for the given channel. 958 * The first xfer may be not for our channel if the channel queues 959 * are shared. 960 */ 961 void 962 wdcstart(chp) 963 struct channel_softc *chp; 964 { 965 struct wdc_xfer *xfer; 966 967 #ifdef WDC_DIAGNOSTIC 968 int spl1, spl2; 969 970 spl1 = splbio(); 971 spl2 = splbio(); 972 if (spl2 != spl1) { 973 printf("wdcstart: not at splbio()\n"); 974 panic("wdcstart"); 975 } 976 splx(spl2); 977 splx(spl1); 978 #endif /* WDC_DIAGNOSTIC */ 979 980 /* is there a xfer ? */ 981 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 982 return; 983 984 /* adjust chp, in case we have a shared queue */ 985 chp = xfer->chp; 986 987 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 988 return; /* channel aleady active */ 989 } 990 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 991 return; /* queue froozen */ 992 } 993 #ifdef DIAGNOSTIC 994 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 995 panic("wdcstart: channel waiting for irq"); 996 #endif 997 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 998 if (!(*chp->wdc->claim_hw)(chp, 0)) 999 return; 1000 1001 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1002 chp->channel, xfer->drive), DEBUG_XFERS); 1003 chp->ch_flags |= WDCF_ACTIVE; 1004 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1005 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1006 chp->ch_drive[xfer->drive].state = 0; 1007 } 1008 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1009 KASSERT(xfer->c_flags & C_POLL); 1010 xfer->c_start(chp, xfer); 1011 } 1012 1013 /* restart an interrupted I/O */ 1014 void 1015 wdcrestart(v) 1016 void *v; 1017 { 1018 struct channel_softc *chp = v; 1019 int s; 1020 1021 s = splbio(); 1022 wdcstart(chp); 1023 splx(s); 1024 } 1025 1026 1027 /* 1028 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1029 * errors on the current operation, mark it done if necessary, and start the 1030 * next request. Also check for a partially done transfer, and continue with 1031 * the next chunk if so. 1032 */ 1033 int 1034 wdcintr(arg) 1035 void *arg; 1036 { 1037 struct channel_softc *chp = arg; 1038 struct wdc_xfer *xfer; 1039 int ret; 1040 1041 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1042 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1043 DEBUG_INTR); 1044 return (0); 1045 } 1046 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1047 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1048 /* try to clear the pending interrupt anyway */ 1049 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1050 return (0); 1051 } 1052 1053 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1054 xfer = chp->ch_queue->sc_xfer.tqh_first; 1055 if (chp->ch_flags & WDCF_DMA_WAIT) { 1056 chp->wdc->dma_status = 1057 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1058 xfer->drive, 0); 1059 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1060 /* IRQ not for us, not detected by DMA engine */ 1061 return 0; 1062 } 1063 chp->ch_flags &= ~WDCF_DMA_WAIT; 1064 } 1065 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1066 ret = xfer->c_intr(chp, xfer, 1); 1067 if (ret == 0) /* irq was not for us, still waiting for irq */ 1068 chp->ch_flags |= WDCF_IRQ_WAIT; 1069 return (ret); 1070 } 1071 1072 /* Put all disk in RESET state */ 1073 void 1074 wdc_reset_channel(drvp, flags) 1075 struct ata_drive_datas *drvp; 1076 int flags; 1077 { 1078 struct channel_softc *chp = drvp->chnl_softc; 1079 int drive; 1080 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1081 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1082 DEBUG_FUNCS); 1083 if ((flags & AT_POLL) == 0) { 1084 chp->ch_flags |= WDCF_TH_RESET; 1085 chp->ch_queue->queue_freeze++; 1086 wakeup(&chp->thread); 1087 return; 1088 } 1089 (void) wdcreset(chp, RESET_POLL); 1090 for (drive = 0; drive < 2; drive++) { 1091 chp->ch_drive[drive].state = 0; 1092 } 1093 } 1094 1095 int 1096 wdcreset(chp, poll) 1097 struct channel_softc *chp; 1098 int poll; 1099 { 1100 int drv_mask1, drv_mask2; 1101 1102 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1103 chp->wdc->select(chp,0); 1104 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1105 WDSD_IBM); /* master */ 1106 delay(10); /* 400ns delay */ 1107 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1108 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1109 delay(2000); 1110 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1111 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1112 WDCTL_4BIT | WDCTL_IDS); 1113 delay(10); /* 400ns delay */ 1114 1115 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1116 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1117 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1118 (poll == RESET_SLEEP) ? 0 : 1); 1119 if (drv_mask2 != drv_mask1) { 1120 printf("%s channel %d: reset failed for", 1121 chp->wdc->sc_dev.dv_xname, chp->channel); 1122 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1123 printf(" drive 0"); 1124 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1125 printf(" drive 1"); 1126 printf("\n"); 1127 } 1128 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1129 return (drv_mask1 != drv_mask2) ? 1 : 0; 1130 } 1131 1132 static int 1133 __wdcwait_reset(chp, drv_mask, poll) 1134 struct channel_softc *chp; 1135 int drv_mask; 1136 { 1137 int timeout, nloop; 1138 u_int8_t st0 = 0, st1 = 0; 1139 #ifdef WDCDEBUG 1140 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1141 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1142 #endif 1143 1144 if (poll) 1145 nloop = WDCNDELAY_RST; 1146 else 1147 nloop = WDC_RESET_WAIT * hz / 1000; 1148 /* wait for BSY to deassert */ 1149 for (timeout = 0; timeout < nloop; timeout++) { 1150 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1151 chp->wdc->select(chp,0); 1152 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1153 WDSD_IBM); /* master */ 1154 delay(10); 1155 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1156 #ifdef WDCDEBUG 1157 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1158 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1159 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1160 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1161 #endif 1162 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1163 chp->wdc->select(chp,1); 1164 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1165 WDSD_IBM | 0x10); /* slave */ 1166 delay(10); 1167 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1168 #ifdef WDCDEBUG 1169 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1170 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1171 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1172 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1173 #endif 1174 1175 if ((drv_mask & 0x01) == 0) { 1176 /* no master */ 1177 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1178 /* No master, slave is ready, it's done */ 1179 goto end; 1180 } 1181 } else if ((drv_mask & 0x02) == 0) { 1182 /* no slave */ 1183 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1184 /* No slave, master is ready, it's done */ 1185 goto end; 1186 } 1187 } else { 1188 /* Wait for both master and slave to be ready */ 1189 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1190 goto end; 1191 } 1192 } 1193 if (poll) 1194 delay(WDCDELAY); 1195 else 1196 tsleep(&nloop, PRIBIO, "atarst", 1); 1197 } 1198 /* Reset timed out. Maybe it's because drv_mask was not right */ 1199 if (st0 & WDCS_BSY) 1200 drv_mask &= ~0x01; 1201 if (st1 & WDCS_BSY) 1202 drv_mask &= ~0x02; 1203 end: 1204 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1205 "cl=0x%x ch=0x%x\n", 1206 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1207 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1208 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1209 "cl=0x%x ch=0x%x\n", 1210 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1211 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1212 1213 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1214 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1215 st0, st1), DEBUG_PROBE); 1216 1217 return drv_mask; 1218 } 1219 1220 /* 1221 * Wait for a drive to be !BSY, and have mask in its status register. 1222 * return -1 for a timeout after "timeout" ms. 1223 */ 1224 int 1225 __wdcwait(chp, mask, bits, timeout) 1226 struct channel_softc *chp; 1227 int mask, bits, timeout; 1228 { 1229 u_char status; 1230 int time = 0; 1231 1232 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1233 :"none", chp->channel), DEBUG_STATUS); 1234 chp->ch_error = 0; 1235 1236 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1237 1238 for (;;) { 1239 chp->ch_status = status = 1240 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1241 if ((status & (WDCS_BSY | mask)) == bits) 1242 break; 1243 if (++time > timeout) { 1244 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1245 "status %x error %x (mask 0x%x bits 0x%x)\n", 1246 time, status, 1247 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1248 wd_error), mask, bits), 1249 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1250 return(WDCWAIT_TOUT); 1251 } 1252 delay(WDCDELAY); 1253 } 1254 #ifdef WDCDEBUG 1255 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1256 printf("__wdcwait: did busy-wait, time=%d\n", time); 1257 #endif 1258 if (status & WDCS_ERR) 1259 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1260 wd_error); 1261 #ifdef WDCNDELAY_DEBUG 1262 /* After autoconfig, there should be no long delays. */ 1263 if (!cold && time > WDCNDELAY_DEBUG) { 1264 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1265 if (xfer == NULL) 1266 printf("%s channel %d: warning: busy-wait took %dus\n", 1267 chp->wdc->sc_dev.dv_xname, chp->channel, 1268 WDCDELAY * time); 1269 else 1270 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1271 chp->wdc->sc_dev.dv_xname, chp->channel, 1272 xfer->drive, 1273 WDCDELAY * time); 1274 } 1275 #endif 1276 return(WDCWAIT_OK); 1277 } 1278 1279 /* 1280 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1281 * thread if possible 1282 */ 1283 int 1284 wdcwait(chp, mask, bits, timeout, flags) 1285 struct channel_softc *chp; 1286 int mask, bits, timeout, flags; 1287 { 1288 int error, i, timeout_hz = mstohz(timeout); 1289 1290 if (timeout_hz == 0 || 1291 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1292 error = __wdcwait(chp, mask, bits, timeout); 1293 else { 1294 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1295 if (error != 0) { 1296 if ((chp->ch_flags & WDCF_TH_RUN) || 1297 (flags & AT_WAIT)) { 1298 /* 1299 * we're running in the channel thread 1300 * or some userland thread context 1301 */ 1302 for (i = 0; i < timeout_hz; i++) { 1303 if (__wdcwait(chp, mask, bits, 1304 WDCDELAY_POLL) == 0) { 1305 error = 0; 1306 break; 1307 } 1308 tsleep(&chp, PRIBIO, "atapoll", 1); 1309 } 1310 } else { 1311 /* 1312 * we're probably in interrupt context, 1313 * ask the thread to come back here 1314 */ 1315 #ifdef DIAGNOSTIC 1316 if (chp->ch_queue->queue_freeze > 0) 1317 panic("wdcwait: queue_freeze"); 1318 #endif 1319 chp->ch_queue->queue_freeze++; 1320 wakeup(&chp->thread); 1321 return(WDCWAIT_THR); 1322 } 1323 } 1324 } 1325 return(error); 1326 } 1327 1328 1329 /* 1330 * Busy-wait for DMA to complete 1331 */ 1332 int 1333 wdc_dmawait(chp, xfer, timeout) 1334 struct channel_softc *chp; 1335 struct wdc_xfer *xfer; 1336 int timeout; 1337 { 1338 int time; 1339 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1340 chp->wdc->dma_status = 1341 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1342 chp->channel, xfer->drive, 0); 1343 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1344 return 0; 1345 delay(WDCDELAY); 1346 } 1347 /* timeout, force a DMA halt */ 1348 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1349 chp->channel, xfer->drive, 1); 1350 return 1; 1351 } 1352 1353 void 1354 wdctimeout(arg) 1355 void *arg; 1356 { 1357 struct channel_softc *chp = (struct channel_softc *)arg; 1358 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1359 int s; 1360 1361 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1362 1363 s = splbio(); 1364 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1365 __wdcerror(chp, "lost interrupt"); 1366 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1367 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1368 xfer->c_bcount, 1369 xfer->c_skip); 1370 if (chp->ch_flags & WDCF_DMA_WAIT) { 1371 chp->wdc->dma_status = 1372 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1373 chp->channel, xfer->drive, 1); 1374 chp->ch_flags &= ~WDCF_DMA_WAIT; 1375 } 1376 /* 1377 * Call the interrupt routine. If we just missed an interrupt, 1378 * it will do what's needed. Else, it will take the needed 1379 * action (reset the device). 1380 * Before that we need to reinstall the timeout callback, 1381 * in case it will miss another irq while in this transfer 1382 * We arbitray chose it to be 1s 1383 */ 1384 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1385 xfer->c_flags |= C_TIMEOU; 1386 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1387 xfer->c_intr(chp, xfer, 1); 1388 } else 1389 __wdcerror(chp, "missing untimeout"); 1390 splx(s); 1391 } 1392 1393 /* 1394 * Probe drive's capabilites, for use by the controller later 1395 * Assumes drvp points to an existing drive. 1396 * XXX this should be a controller-indep function 1397 */ 1398 void 1399 wdc_probe_caps(drvp) 1400 struct ata_drive_datas *drvp; 1401 { 1402 struct ataparams params, params2; 1403 struct channel_softc *chp = drvp->chnl_softc; 1404 struct device *drv_dev = drvp->drv_softc; 1405 struct wdc_softc *wdc = chp->wdc; 1406 int i, printed; 1407 char *sep = ""; 1408 int cf_flags; 1409 1410 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1411 /* IDENTIFY failed. Can't tell more about the device */ 1412 return; 1413 } 1414 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1415 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1416 /* 1417 * Controller claims 16 and 32 bit transfers. 1418 * Re-do an IDENTIFY with 32-bit transfers, 1419 * and compare results. 1420 */ 1421 drvp->drive_flags |= DRIVE_CAP32; 1422 ata_get_params(drvp, AT_WAIT, ¶ms2); 1423 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1424 /* Not good. fall back to 16bits */ 1425 drvp->drive_flags &= ~DRIVE_CAP32; 1426 } else { 1427 aprint_normal("%s: 32-bit data port\n", 1428 drv_dev->dv_xname); 1429 } 1430 } 1431 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1432 if (params.atap_ata_major > 0x01 && 1433 params.atap_ata_major != 0xffff) { 1434 for (i = 14; i > 0; i--) { 1435 if (params.atap_ata_major & (1 << i)) { 1436 aprint_normal("%s: ATA version %d\n", 1437 drv_dev->dv_xname, i); 1438 drvp->ata_vers = i; 1439 break; 1440 } 1441 } 1442 } 1443 #endif 1444 1445 /* An ATAPI device is at last PIO mode 3 */ 1446 if (drvp->drive_flags & DRIVE_ATAPI) 1447 drvp->PIO_mode = 3; 1448 1449 /* 1450 * It's not in the specs, but it seems that some drive 1451 * returns 0xffff in atap_extensions when this field is invalid 1452 */ 1453 if (params.atap_extensions != 0xffff && 1454 (params.atap_extensions & WDC_EXT_MODES)) { 1455 printed = 0; 1456 /* 1457 * XXX some drives report something wrong here (they claim to 1458 * support PIO mode 8 !). As mode is coded on 3 bits in 1459 * SET FEATURE, limit it to 7 (so limit i to 4). 1460 * If higher mode than 7 is found, abort. 1461 */ 1462 for (i = 7; i >= 0; i--) { 1463 if ((params.atap_piomode_supp & (1 << i)) == 0) 1464 continue; 1465 if (i > 4) 1466 return; 1467 /* 1468 * See if mode is accepted. 1469 * If the controller can't set its PIO mode, 1470 * assume the defaults are good, so don't try 1471 * to set it 1472 */ 1473 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1474 /* 1475 * It's OK to pool here, it's fast enouth 1476 * to not bother waiting for interrupt 1477 */ 1478 if (ata_set_mode(drvp, 0x08 | (i + 3), 1479 AT_WAIT) != CMD_OK) 1480 continue; 1481 if (!printed) { 1482 aprint_normal("%s: drive supports PIO mode %d", 1483 drv_dev->dv_xname, i + 3); 1484 sep = ","; 1485 printed = 1; 1486 } 1487 /* 1488 * If controller's driver can't set its PIO mode, 1489 * get the highter one for the drive. 1490 */ 1491 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1492 wdc->PIO_cap >= i + 3) { 1493 drvp->PIO_mode = i + 3; 1494 drvp->PIO_cap = i + 3; 1495 break; 1496 } 1497 } 1498 if (!printed) { 1499 /* 1500 * We didn't find a valid PIO mode. 1501 * Assume the values returned for DMA are buggy too 1502 */ 1503 return; 1504 } 1505 drvp->drive_flags |= DRIVE_MODE; 1506 printed = 0; 1507 for (i = 7; i >= 0; i--) { 1508 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1509 continue; 1510 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1511 (wdc->cap & WDC_CAPABILITY_MODE)) 1512 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1513 != CMD_OK) 1514 continue; 1515 if (!printed) { 1516 aprint_normal("%s DMA mode %d", sep, i); 1517 sep = ","; 1518 printed = 1; 1519 } 1520 if (wdc->cap & WDC_CAPABILITY_DMA) { 1521 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1522 wdc->DMA_cap < i) 1523 continue; 1524 drvp->DMA_mode = i; 1525 drvp->DMA_cap = i; 1526 drvp->drive_flags |= DRIVE_DMA; 1527 } 1528 break; 1529 } 1530 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1531 printed = 0; 1532 for (i = 7; i >= 0; i--) { 1533 if ((params.atap_udmamode_supp & (1 << i)) 1534 == 0) 1535 continue; 1536 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1537 (wdc->cap & WDC_CAPABILITY_UDMA)) 1538 if (ata_set_mode(drvp, 0x40 | i, 1539 AT_WAIT) != CMD_OK) 1540 continue; 1541 if (!printed) { 1542 aprint_normal("%s Ultra-DMA mode %d", 1543 sep, i); 1544 if (i == 2) 1545 aprint_normal(" (Ultra/33)"); 1546 else if (i == 4) 1547 aprint_normal(" (Ultra/66)"); 1548 else if (i == 5) 1549 aprint_normal(" (Ultra/100)"); 1550 else if (i == 6) 1551 aprint_normal(" (Ultra/133)"); 1552 sep = ","; 1553 printed = 1; 1554 } 1555 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1556 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1557 wdc->UDMA_cap < i) 1558 continue; 1559 drvp->UDMA_mode = i; 1560 drvp->UDMA_cap = i; 1561 drvp->drive_flags |= DRIVE_UDMA; 1562 } 1563 break; 1564 } 1565 } 1566 aprint_normal("\n"); 1567 } 1568 1569 /* Try to guess ATA version here, if it didn't get reported */ 1570 if (drvp->ata_vers == 0) { 1571 if (drvp->drive_flags & DRIVE_UDMA) 1572 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1573 else if (drvp->PIO_cap > 2) 1574 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1575 } 1576 cf_flags = drv_dev->dv_cfdata->cf_flags; 1577 if (cf_flags & ATA_CONFIG_PIO_SET) { 1578 drvp->PIO_mode = 1579 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1580 drvp->drive_flags |= DRIVE_MODE; 1581 } 1582 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1583 /* don't care about DMA modes */ 1584 return; 1585 } 1586 if (cf_flags & ATA_CONFIG_DMA_SET) { 1587 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1588 ATA_CONFIG_DMA_DISABLE) { 1589 drvp->drive_flags &= ~DRIVE_DMA; 1590 } else { 1591 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1592 ATA_CONFIG_DMA_OFF; 1593 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1594 } 1595 } 1596 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1597 /* don't care about UDMA modes */ 1598 return; 1599 } 1600 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1601 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1602 ATA_CONFIG_UDMA_DISABLE) { 1603 drvp->drive_flags &= ~DRIVE_UDMA; 1604 } else { 1605 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1606 ATA_CONFIG_UDMA_OFF; 1607 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1608 } 1609 } 1610 } 1611 1612 /* 1613 * downgrade the transfer mode of a drive after an error. return 1 if 1614 * downgrade was possible, 0 otherwise. 1615 */ 1616 int 1617 wdc_downgrade_mode(drvp, flags) 1618 struct ata_drive_datas *drvp; 1619 { 1620 struct channel_softc *chp = drvp->chnl_softc; 1621 struct device *drv_dev = drvp->drv_softc; 1622 struct wdc_softc *wdc = chp->wdc; 1623 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1624 1625 /* if drive or controller don't know its mode, we can't do much */ 1626 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1627 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1628 return 0; 1629 /* current drive mode was set by a config flag, let it this way */ 1630 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1631 (cf_flags & ATA_CONFIG_DMA_SET) || 1632 (cf_flags & ATA_CONFIG_UDMA_SET)) 1633 return 0; 1634 1635 /* 1636 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1637 * Maybe we didn't properly notice the cable type 1638 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1639 * It helps in some cases. 1640 */ 1641 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1642 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1643 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1644 drv_dev->dv_xname, drvp->UDMA_mode); 1645 } 1646 1647 /* 1648 * If we were using ultra-DMA, don't downgrade to multiword DMA 1649 * if we noticed a CRC error. It has been noticed that CRC errors 1650 * in ultra-DMA lead to silent data corruption in multiword DMA. 1651 * Data corruption is less likely to occur in PIO mode. 1652 */ 1653 else if ((drvp->drive_flags & DRIVE_UDMA) && 1654 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1655 drvp->drive_flags &= ~DRIVE_UDMA; 1656 drvp->drive_flags |= DRIVE_DMA; 1657 drvp->DMA_mode = drvp->DMA_cap; 1658 printf("%s: transfer error, downgrading to DMA mode %d\n", 1659 drv_dev->dv_xname, drvp->DMA_mode); 1660 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1661 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1662 drvp->PIO_mode = drvp->PIO_cap; 1663 printf("%s: transfer error, downgrading to PIO mode %d\n", 1664 drv_dev->dv_xname, drvp->PIO_mode); 1665 } else /* already using PIO, can't downgrade */ 1666 return 0; 1667 1668 wdc->set_modes(chp); 1669 wdc_print_modes(chp); 1670 /* reset the channel, which will shedule all drives for setup */ 1671 wdc_reset_channel(drvp, flags); 1672 return 1; 1673 } 1674 1675 int 1676 wdc_exec_command(drvp, wdc_c) 1677 struct ata_drive_datas *drvp; 1678 struct wdc_command *wdc_c; 1679 { 1680 struct channel_softc *chp = drvp->chnl_softc; 1681 struct wdc_xfer *xfer; 1682 int s, ret; 1683 1684 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1685 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1686 DEBUG_FUNCS); 1687 1688 /* set up an xfer and queue. Wait for completion */ 1689 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1690 WDC_NOSLEEP); 1691 if (xfer == NULL) { 1692 return WDC_TRY_AGAIN; 1693 } 1694 1695 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1696 wdc_c->flags |= AT_POLL; 1697 if (wdc_c->flags & AT_POLL) 1698 xfer->c_flags |= C_POLL; 1699 xfer->drive = drvp->drive; 1700 xfer->databuf = wdc_c->data; 1701 xfer->c_bcount = wdc_c->bcount; 1702 xfer->cmd = wdc_c; 1703 xfer->c_start = __wdccommand_start; 1704 xfer->c_intr = __wdccommand_intr; 1705 xfer->c_kill_xfer = __wdccommand_done; 1706 1707 s = splbio(); 1708 wdc_exec_xfer(chp, xfer); 1709 #ifdef DIAGNOSTIC 1710 if ((wdc_c->flags & AT_POLL) != 0 && 1711 (wdc_c->flags & AT_DONE) == 0) 1712 panic("wdc_exec_command: polled command not done"); 1713 #endif 1714 if (wdc_c->flags & AT_DONE) { 1715 ret = WDC_COMPLETE; 1716 } else { 1717 if (wdc_c->flags & AT_WAIT) { 1718 while ((wdc_c->flags & AT_DONE) == 0) { 1719 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1720 } 1721 ret = WDC_COMPLETE; 1722 } else { 1723 ret = WDC_QUEUED; 1724 } 1725 } 1726 splx(s); 1727 return ret; 1728 } 1729 1730 void 1731 __wdccommand_start(chp, xfer) 1732 struct channel_softc *chp; 1733 struct wdc_xfer *xfer; 1734 { 1735 int drive = xfer->drive; 1736 struct wdc_command *wdc_c = xfer->cmd; 1737 1738 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1739 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1740 DEBUG_FUNCS); 1741 1742 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1743 chp->wdc->select(chp,drive); 1744 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1745 WDSD_IBM | (drive << 4)); 1746 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1747 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1748 case WDCWAIT_OK: 1749 break; 1750 case WDCWAIT_TOUT: 1751 wdc_c->flags |= AT_TIMEOU; 1752 __wdccommand_done(chp, xfer); 1753 return; 1754 case WDCWAIT_THR: 1755 return; 1756 } 1757 if (wdc_c->flags & AT_POLL) { 1758 /* polled command, disable interrupts */ 1759 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1760 WDCTL_4BIT | WDCTL_IDS); 1761 } 1762 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1763 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1764 1765 if ((wdc_c->flags & AT_POLL) == 0) { 1766 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1767 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1768 wdctimeout, chp); 1769 return; 1770 } 1771 /* 1772 * Polled command. Wait for drive ready or drq. Done in intr(). 1773 * Wait for at last 400ns for status bit to be valid. 1774 */ 1775 delay(10); /* 400ns delay */ 1776 __wdccommand_intr(chp, xfer, 0); 1777 } 1778 1779 int 1780 __wdccommand_intr(chp, xfer, irq) 1781 struct channel_softc *chp; 1782 struct wdc_xfer *xfer; 1783 int irq; 1784 { 1785 struct wdc_command *wdc_c = xfer->cmd; 1786 int bcount = wdc_c->bcount; 1787 char *data = wdc_c->data; 1788 int wflags; 1789 1790 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1791 /* both wait and poll, we can tsleep here */ 1792 wflags = AT_WAIT | AT_POLL; 1793 } else { 1794 wflags = AT_POLL; 1795 } 1796 1797 again: 1798 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1799 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1800 /* 1801 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1802 * Reselect again, it doesn't hurt for others commands, and the time 1803 * penalty for the extra regiter write is acceptable, 1804 * wdc_exec_command() isn't called often (mosly for autoconfig) 1805 */ 1806 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1807 WDSD_IBM | (xfer->drive << 4)); 1808 if ((wdc_c->flags & AT_XFDONE) != 0) { 1809 /* 1810 * We have completed a data xfer. The drive should now be 1811 * in its initial state 1812 */ 1813 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1814 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1815 wflags) == WDCWAIT_TOUT) { 1816 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1817 return 0; /* IRQ was not for us */ 1818 wdc_c->flags |= AT_TIMEOU; 1819 } 1820 goto out; 1821 } 1822 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1823 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1824 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1825 return 0; /* IRQ was not for us */ 1826 wdc_c->flags |= AT_TIMEOU; 1827 goto out; 1828 } 1829 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1830 chp->wdc->irqack(chp); 1831 if (wdc_c->flags & AT_READ) { 1832 if ((chp->ch_status & WDCS_DRQ) == 0) { 1833 wdc_c->flags |= AT_TIMEOU; 1834 goto out; 1835 } 1836 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1837 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1838 0, (u_int32_t*)data, bcount >> 2); 1839 data += bcount & 0xfffffffc; 1840 bcount = bcount & 0x03; 1841 } 1842 if (bcount > 0) 1843 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1844 wd_data, (u_int16_t *)data, bcount >> 1); 1845 /* at this point the drive should be in its initial state */ 1846 wdc_c->flags |= AT_XFDONE; 1847 /* XXX should read status register here ? */ 1848 } else if (wdc_c->flags & AT_WRITE) { 1849 if ((chp->ch_status & WDCS_DRQ) == 0) { 1850 wdc_c->flags |= AT_TIMEOU; 1851 goto out; 1852 } 1853 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1854 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1855 0, (u_int32_t*)data, bcount >> 2); 1856 data += bcount & 0xfffffffc; 1857 bcount = bcount & 0x03; 1858 } 1859 if (bcount > 0) 1860 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1861 wd_data, (u_int16_t *)data, bcount >> 1); 1862 wdc_c->flags |= AT_XFDONE; 1863 if ((wdc_c->flags & AT_POLL) == 0) { 1864 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1865 callout_reset(&chp->ch_callout, 1866 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1867 return 1; 1868 } else { 1869 goto again; 1870 } 1871 } 1872 out: 1873 __wdccommand_done(chp, xfer); 1874 return 1; 1875 } 1876 1877 void 1878 __wdccommand_done(chp, xfer) 1879 struct channel_softc *chp; 1880 struct wdc_xfer *xfer; 1881 { 1882 struct wdc_command *wdc_c = xfer->cmd; 1883 1884 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1885 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1886 1887 callout_stop(&chp->ch_callout); 1888 1889 if (chp->ch_status & WDCS_DWF) 1890 wdc_c->flags |= AT_DF; 1891 if (chp->ch_status & WDCS_ERR) { 1892 wdc_c->flags |= AT_ERROR; 1893 wdc_c->r_error = chp->ch_error; 1894 } 1895 wdc_c->flags |= AT_DONE; 1896 if ((wdc_c->flags & AT_READREG) != 0 && 1897 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1898 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1899 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1900 wd_sdh); 1901 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1902 wd_cyl_hi) << 8; 1903 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1904 wd_cyl_lo); 1905 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1906 wd_sector); 1907 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1908 wd_seccnt); 1909 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1910 wd_error); 1911 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1912 wd_precomp); 1913 } 1914 1915 if (wdc_c->flags & AT_POLL) { 1916 /* enable interrupts */ 1917 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1918 WDCTL_4BIT); 1919 } 1920 wdc_free_xfer(chp, xfer); 1921 if (wdc_c->flags & AT_WAIT) 1922 wakeup(wdc_c); 1923 else if (wdc_c->callback) 1924 wdc_c->callback(wdc_c->callback_arg); 1925 wdcstart(chp); 1926 return; 1927 } 1928 1929 /* 1930 * Send a command. The drive should be ready. 1931 * Assumes interrupts are blocked. 1932 */ 1933 void 1934 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1935 struct channel_softc *chp; 1936 u_int8_t drive; 1937 u_int8_t command; 1938 u_int16_t cylin; 1939 u_int8_t head, sector, count, precomp; 1940 { 1941 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1942 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1943 chp->channel, drive, command, cylin, head, sector, count, precomp), 1944 DEBUG_FUNCS); 1945 1946 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1947 chp->wdc->select(chp,drive); 1948 1949 /* Select drive, head, and addressing mode. */ 1950 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1951 WDSD_IBM | (drive << 4) | head); 1952 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1953 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1954 precomp); 1955 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1956 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1957 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1959 1960 /* Send command. */ 1961 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1962 return; 1963 } 1964 1965 /* 1966 * Send a 48-bit addressing command. The drive should be ready. 1967 * Assumes interrupts are blocked. 1968 */ 1969 void 1970 wdccommandext(chp, drive, command, blkno, count) 1971 struct channel_softc *chp; 1972 u_int8_t drive; 1973 u_int8_t command; 1974 u_int64_t blkno; 1975 u_int16_t count; 1976 { 1977 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1978 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1979 chp->channel, drive, command, (u_int32_t) blkno, count), 1980 DEBUG_FUNCS); 1981 1982 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1983 chp->wdc->select(chp,drive); 1984 1985 /* Select drive, head, and addressing mode. */ 1986 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1987 (drive << 4) | WDSD_LBA); 1988 1989 /* previous */ 1990 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1991 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1992 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1993 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 1995 1996 /* current */ 1997 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1998 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1999 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 2000 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 2001 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 2002 2003 /* Send command. */ 2004 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2005 return; 2006 } 2007 2008 /* 2009 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2010 * tested by the caller. 2011 */ 2012 void 2013 wdccommandshort(chp, drive, command) 2014 struct channel_softc *chp; 2015 int drive; 2016 int command; 2017 { 2018 2019 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2020 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2021 DEBUG_FUNCS); 2022 2023 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2024 chp->wdc->select(chp,drive); 2025 2026 /* Select drive. */ 2027 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2028 WDSD_IBM | (drive << 4)); 2029 2030 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2031 } 2032 2033 /* Add a command to the queue and start controller. Must be called at splbio */ 2034 2035 void 2036 wdc_exec_xfer(chp, xfer) 2037 struct channel_softc *chp; 2038 struct wdc_xfer *xfer; 2039 { 2040 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2041 chp->channel, xfer->drive), DEBUG_XFERS); 2042 2043 /* complete xfer setup */ 2044 xfer->chp = chp; 2045 2046 /* 2047 * If we are a polled command, and the list is not empty, 2048 * we are doing a dump. Drop the list to allow the polled command 2049 * to complete, we're going to reboot soon anyway. 2050 */ 2051 if ((xfer->c_flags & C_POLL) != 0 && 2052 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2053 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2054 } 2055 /* insert at the end of command list */ 2056 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2057 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2058 chp->ch_flags), DEBUG_XFERS); 2059 wdcstart(chp); 2060 } 2061 2062 struct wdc_xfer * 2063 wdc_get_xfer(flags) 2064 int flags; 2065 { 2066 struct wdc_xfer *xfer; 2067 int s; 2068 2069 s = splbio(); 2070 xfer = pool_get(&wdc_xfer_pool, 2071 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2072 splx(s); 2073 if (xfer != NULL) { 2074 memset(xfer, 0, sizeof(struct wdc_xfer)); 2075 } 2076 return xfer; 2077 } 2078 2079 void 2080 wdc_free_xfer(chp, xfer) 2081 struct channel_softc *chp; 2082 struct wdc_xfer *xfer; 2083 { 2084 struct wdc_softc *wdc = chp->wdc; 2085 int s; 2086 2087 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2088 (*wdc->free_hw)(chp); 2089 s = splbio(); 2090 chp->ch_flags &= ~WDCF_ACTIVE; 2091 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2092 pool_put(&wdc_xfer_pool, xfer); 2093 splx(s); 2094 } 2095 2096 /* 2097 * Kill off all pending xfers for a channel_softc. 2098 * 2099 * Must be called at splbio(). 2100 */ 2101 void 2102 wdc_kill_pending(chp) 2103 struct channel_softc *chp; 2104 { 2105 struct wdc_xfer *xfer; 2106 2107 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2108 chp = xfer->chp; 2109 (*xfer->c_kill_xfer)(chp, xfer); 2110 } 2111 } 2112 2113 static void 2114 __wdcerror(chp, msg) 2115 struct channel_softc *chp; 2116 char *msg; 2117 { 2118 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2119 2120 if (xfer == NULL) 2121 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2122 msg); 2123 else 2124 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2125 chp->channel, xfer->drive, msg); 2126 } 2127 2128 /* 2129 * the bit bucket 2130 */ 2131 void 2132 wdcbit_bucket(chp, size) 2133 struct channel_softc *chp; 2134 int size; 2135 { 2136 2137 for (; size >= 2; size -= 2) 2138 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2139 if (size) 2140 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2141 } 2142 2143 int 2144 wdc_addref(chp) 2145 struct channel_softc *chp; 2146 { 2147 struct wdc_softc *wdc = chp->wdc; 2148 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2149 int s, error = 0; 2150 2151 s = splbio(); 2152 if (adapt->adapt_refcnt++ == 0 && 2153 adapt->adapt_enable != NULL) { 2154 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2155 if (error) 2156 adapt->adapt_refcnt--; 2157 } 2158 splx(s); 2159 return (error); 2160 } 2161 2162 void 2163 wdc_delref(chp) 2164 struct channel_softc *chp; 2165 { 2166 struct wdc_softc *wdc = chp->wdc; 2167 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2168 int s; 2169 2170 s = splbio(); 2171 if (adapt->adapt_refcnt-- == 1 && 2172 adapt->adapt_enable != NULL) 2173 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2174 splx(s); 2175 } 2176 2177 void 2178 wdc_print_modes(struct channel_softc *chp) 2179 { 2180 int drive; 2181 struct ata_drive_datas *drvp; 2182 2183 for (drive = 0; drive < 2; drive++) { 2184 drvp = &chp->ch_drive[drive]; 2185 if ((drvp->drive_flags & DRIVE) == 0) 2186 continue; 2187 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2188 drvp->drv_softc->dv_xname, 2189 chp->wdc->sc_dev.dv_xname, 2190 chp->channel, drive, drvp->PIO_mode); 2191 if (drvp->drive_flags & DRIVE_DMA) 2192 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2193 if (drvp->drive_flags & DRIVE_UDMA) { 2194 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2195 if (drvp->UDMA_mode == 2) 2196 aprint_normal(" (Ultra/33)"); 2197 else if (drvp->UDMA_mode == 4) 2198 aprint_normal(" (Ultra/66)"); 2199 else if (drvp->UDMA_mode == 5) 2200 aprint_normal(" (Ultra/100)"); 2201 else if (drvp->UDMA_mode == 6) 2202 aprint_normal(" (Ultra/133)"); 2203 } 2204 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2205 aprint_normal(" (using DMA data transfers)"); 2206 aprint_normal("\n"); 2207 } 2208 } 2209
Indexes created Wed Sep 24 22:09:59 GMT 2025