wdc.c revision 1.153
1 /* $NetBSD: wdc.c,v 1.153 2003/11/07 08:58:33 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.153 2003/11/07 08:58:33 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 aprint_normal("\n"); 236 aprint_naive("\n"); 237 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 238 atabus_initq->atabus_sc = atabus_sc; 239 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 240 config_pending_incr(); 241 kthread_create(atabus_create_thread, atabus_sc); 242 243 } 244 245 void 246 atabus_create_thread(arg) 247 void *arg; 248 { 249 struct atabus_softc *atabus_sc = arg; 250 struct channel_softc *chp = atabus_sc->sc_chan; 251 int error; 252 253 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 254 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 255 printf("unable to create kernel thread for %s: error %d\n", 256 atabus_sc->sc_dev.dv_xname, error); 257 } 258 259 void 260 atabus_thread(arg) 261 void *arg; 262 { 263 struct atabus_softc *atabus_sc = arg; 264 struct channel_softc *chp = atabus_sc->sc_chan; 265 struct wdc_xfer *xfer; 266 int s; 267 268 s = splbio(); 269 chp->ch_flags |= WDCF_TH_RUN; 270 splx(s); 271 atabusconfig(atabus_sc); 272 for(;;) { 273 s = splbio(); 274 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 275 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 276 chp->ch_queue->queue_freeze == 0)) { 277 chp->ch_flags &= ~WDCF_TH_RUN; 278 tsleep(&chp->thread, PRIBIO, "atath", 0); 279 chp->ch_flags |= WDCF_TH_RUN; 280 } 281 splx(s); 282 if (chp->ch_flags & WDCF_SHUTDOWN) 283 break; 284 s = splbio(); 285 if (chp->ch_flags & WDCF_TH_RESET) { 286 int drive; 287 (void) wdcreset(chp, RESET_SLEEP); 288 for (drive = 0; drive < 2; drive++) { 289 chp->ch_drive[drive].state = 0; 290 } 291 chp->ch_flags &= ~WDCF_TH_RESET; 292 chp->ch_queue->queue_freeze--; 293 wdcstart(chp); 294 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 295 chp->ch_queue->queue_freeze == 1) { 296 /* 297 * caller has bumped queue_freeze, decrease it 298 */ 299 chp->ch_queue->queue_freeze--; 300 xfer = chp->ch_queue->sc_xfer.tqh_first; 301 #ifdef DIAGNOSTIC 302 if (xfer == NULL) 303 panic("channel active with no xfer ?"); 304 #endif 305 xfer->c_start(chp, xfer); 306 } else if (chp->ch_queue->queue_freeze > 1) { 307 panic("queue_freeze"); 308 } 309 splx(s); 310 } 311 chp->thread = NULL; 312 wakeup(&chp->ch_flags); 313 kthread_exit(0); 314 } 315 316 void 317 atabusconfig(atabus_sc) 318 struct atabus_softc *atabus_sc; 319 { 320 struct channel_softc *chp = atabus_sc->sc_chan; 321 int i, error, need_delref = 0; 322 struct ataparams params; 323 struct atabus_initq *atabus_initq = NULL; 324 u_int8_t st0 = 0, st1 = 0; 325 326 if ((error = wdc_addref(chp)) != 0) { 327 aprint_error("%s: unable to enable controller\n", 328 chp->wdc->sc_dev.dv_xname); 329 goto out; 330 } 331 need_delref = 1; 332 333 if (__wdcprobe(chp, 0) == 0) 334 /* If no drives, abort attach here. */ 335 goto out; 336 337 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 338 for (i = 0; i < mstohz(3000); i++) { 339 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 340 chp->wdc->select(chp,0); 341 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 342 WDSD_IBM); 343 delay(10); /* 400ns delay */ 344 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 345 346 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 347 chp->wdc->select(chp,1); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 349 WDSD_IBM | 0x10); 350 delay(10); /* 400ns delay */ 351 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 352 353 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 354 == 0 || 355 (st0 & WDCS_DRDY)) && 356 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 357 == 0 || 358 (st1 & WDCS_DRDY))) 359 break; 360 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 361 } 362 if ((st0 & WDCS_DRDY) == 0) 363 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 364 if ((st1 & WDCS_DRDY) == 0) 365 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 366 367 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 368 chp->wdc->sc_dev.dv_xname, 369 chp->channel, st0, st1), DEBUG_PROBE); 370 371 /* Wait a bit, some devices are weird just after a reset. */ 372 delay(5000); 373 374 for (i = 0; i < 2; i++) { 375 chp->ch_drive[i].chnl_softc = chp; 376 chp->ch_drive[i].drive = i; 377 /* 378 * Init error counter so that an error withing the first xfers 379 * will trigger a downgrade 380 */ 381 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 382 383 /* If controller can't do 16bit flag the drives as 32bit */ 384 if ((chp->wdc->cap & 385 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 386 WDC_CAPABILITY_DATA32) 387 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 388 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 389 continue; 390 391 /* Shortcut in case we've been shutdown */ 392 if (chp->ch_flags & WDCF_SHUTDOWN) 393 goto out; 394 395 /* issue an identify, to try to detect ghosts */ 396 error = ata_get_params(&chp->ch_drive[i], 397 AT_WAIT | AT_POLL, ¶ms); 398 if (error != CMD_OK) { 399 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 400 401 /* Shortcut in case we've been shutdown */ 402 if (chp->ch_flags & WDCF_SHUTDOWN) 403 goto out; 404 405 error = ata_get_params(&chp->ch_drive[i], 406 AT_WAIT | AT_POLL, ¶ms); 407 } 408 if (error == CMD_OK) { 409 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 410 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 411 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 412 } else { 413 chp->ch_drive[i].drive_flags &= 414 ~(DRIVE_ATA | DRIVE_ATAPI); 415 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 416 chp->wdc->sc_dev.dv_xname, 417 chp->channel, i, error), DEBUG_PROBE); 418 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 419 continue; 420 /* 421 * Pre-ATA drive ? 422 * Test registers writability (Error register not 423 * writable, but cyllo is), then try an ATA command. 424 */ 425 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 426 chp->wdc->select(chp,i); 427 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 428 WDSD_IBM | (i << 4)); 429 delay(10); /* 400ns delay */ 430 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 431 wd_error, 0x58); 432 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 433 wd_cyl_lo, 0xa5); 434 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 435 wd_error) == 0x58 || 436 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 437 wd_cyl_lo) != 0xa5) { 438 WDCDEBUG_PRINT(("%s:%d:%d: register " 439 "writability failed\n", 440 chp->wdc->sc_dev.dv_xname, 441 chp->channel, i), DEBUG_PROBE); 442 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 443 } 444 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 445 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 446 chp->wdc->sc_dev.dv_xname, 447 chp->channel, i), DEBUG_PROBE); 448 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 449 continue; 450 } 451 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 452 wd_command, WDCC_RECAL); 453 delay(10); /* 400ns delay */ 454 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 455 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 456 chp->wdc->sc_dev.dv_xname, 457 chp->channel, i), DEBUG_PROBE); 458 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 459 } 460 } 461 } 462 463 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 464 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 465 DEBUG_PROBE); 466 467 /* If no drives, abort here */ 468 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 469 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 470 goto out; 471 472 /* Make sure the devices probe in atabus order to avoid jitter. */ 473 simple_lock(&atabus_interlock); 474 while(1) { 475 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 476 if (atabus_initq->atabus_sc == atabus_sc) 477 break; 478 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 479 &atabus_interlock); 480 } 481 simple_unlock(&atabus_interlock); 482 483 /* 484 * Attach an ATAPI bus, if needed. 485 */ 486 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 487 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 488 #if NATAPIBUS > 0 489 wdc_atapibus_attach(atabus_sc); 490 #else 491 /* 492 * Fake the autoconfig "not configured" message 493 */ 494 aprint_normal("atapibus at %s not configured\n", 495 chp->wdc->sc_dev.dv_xname); 496 chp->atapibus = NULL; 497 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 498 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 499 #endif 500 } 501 502 for (i = 0; i < 2; i++) { 503 struct ata_device adev; 504 if ((chp->ch_drive[i].drive_flags & 505 (DRIVE_ATA | DRIVE_OLD)) == 0) { 506 continue; 507 } 508 memset(&adev, 0, sizeof(struct ata_device)); 509 adev.adev_bustype = &wdc_ata_bustype; 510 adev.adev_channel = chp->channel; 511 adev.adev_openings = 1; 512 adev.adev_drv_data = &chp->ch_drive[i]; 513 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 514 &adev, wdprint); 515 if (chp->ata_drives[i] != NULL) 516 wdc_probe_caps(&chp->ch_drive[i]); 517 else 518 chp->ch_drive[i].drive_flags &= 519 ~(DRIVE_ATA | DRIVE_OLD); 520 } 521 522 /* now that we know the drives, the controller can set its modes */ 523 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 524 chp->wdc->set_modes(chp); 525 wdc_print_modes(chp); 526 } 527 #if NATARAID > 0 528 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 529 for (i = 0; i < 2; i++) 530 if (chp->ata_drives[i] != NULL) 531 ata_raid_check_component(chp->ata_drives[i]); 532 #endif /* NATARAID > 0 */ 533 534 /* 535 * reset drive_flags for unattached devices, reset state for attached 536 * ones 537 */ 538 for (i = 0; i < 2; i++) { 539 if (chp->ch_drive[i].drv_softc == NULL) 540 chp->ch_drive[i].drive_flags = 0; 541 else 542 chp->ch_drive[i].state = 0; 543 } 544 545 out: 546 if (atabus_initq == NULL) { 547 simple_lock(&atabus_interlock); 548 while(1) { 549 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 550 if (atabus_initq->atabus_sc == atabus_sc) 551 break; 552 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 553 &atabus_interlock); 554 } 555 simple_unlock(&atabus_interlock); 556 } 557 simple_lock(&atabus_interlock); 558 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 559 simple_unlock(&atabus_interlock); 560 561 free(atabus_initq, M_DEVBUF); 562 wakeup(&atabus_initq_head); 563 564 config_pending_decr(); 565 if (need_delref) 566 wdc_delref(chp); 567 } 568 569 570 int 571 wdprint(aux, pnp) 572 void *aux; 573 const char *pnp; 574 { 575 struct ata_device *adev = aux; 576 if (pnp) 577 aprint_normal("wd at %s", pnp); 578 aprint_normal(" drive %d", adev->adev_drv_data->drive); 579 return (UNCONF); 580 } 581 582 /* Test to see controller with at last one attached drive is there. 583 * Returns a bit for each possible drive found (0x01 for drive 0, 584 * 0x02 for drive 1). 585 * Logic: 586 * - If a status register is at 0xff, assume there is no drive here 587 * (ISA has pull-up resistors). Similarly if the status register has 588 * the value we last wrote to the bus (for IDE interfaces without pullups). 589 * If no drive at all -> return. 590 * - reset the controller, wait for it to complete (may take up to 31s !). 591 * If timeout -> return. 592 * - test ATA/ATAPI signatures. If at last one drive found -> return. 593 * - try an ATA command on the master. 594 */ 595 596 int 597 wdcprobe(chp) 598 struct channel_softc *chp; 599 { 600 return __wdcprobe(chp, 1); 601 } 602 603 int 604 __wdcprobe(chp, poll) 605 struct channel_softc *chp; 606 int poll; 607 { 608 u_int8_t st0, st1, sc, sn, cl, ch; 609 u_int8_t ret_value = 0x03; 610 u_int8_t drive; 611 612 /* 613 * Sanity check to see if the wdc channel responds at all. 614 */ 615 616 if (chp->wdc == NULL || 617 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 618 619 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 620 chp->wdc->select(chp,0); 621 622 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 623 WDSD_IBM); 624 delay(10); /* 400ns delay */ 625 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 626 627 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 628 chp->wdc->select(chp,1); 629 630 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 631 WDSD_IBM | 0x10); 632 delay(10); /* 400ns delay */ 633 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 634 635 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 636 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 637 chp->channel, st0, st1), DEBUG_PROBE); 638 639 if (st0 == 0xff || st0 == WDSD_IBM) 640 ret_value &= ~0x01; 641 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 642 ret_value &= ~0x02; 643 /* Register writability test, drive 0. */ 644 if (ret_value & 0x01) { 645 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 646 chp->wdc->select(chp,0); 647 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 648 WDSD_IBM); 649 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 650 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_cyl_lo) != 0x02) 652 ret_value &= ~0x01; 653 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 654 0x01); 655 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 656 wd_cyl_lo) != 0x01) 657 ret_value &= ~0x01; 658 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 659 0x01); 660 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 661 wd_sector) != 0x01) 662 ret_value &= ~0x01; 663 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 664 0x02); 665 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 666 wd_sector) != 0x02) 667 ret_value &= ~0x01; 668 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 669 wd_cyl_lo) != 0x01) 670 ret_value &= ~0x01; 671 } 672 /* Register writability test, drive 1. */ 673 if (ret_value & 0x02) { 674 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 675 chp->wdc->select(chp,1); 676 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 677 WDSD_IBM | 0x10); 678 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 679 0x02); 680 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 681 wd_cyl_lo) != 0x02) 682 ret_value &= ~0x02; 683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 684 0x01); 685 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 686 wd_cyl_lo) != 0x01) 687 ret_value &= ~0x02; 688 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 689 0x01); 690 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 691 wd_sector) != 0x01) 692 ret_value &= ~0x02; 693 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 694 0x02); 695 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 696 wd_sector) != 0x02) 697 ret_value &= ~0x02; 698 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 699 wd_cyl_lo) != 0x01) 700 ret_value &= ~0x02; 701 } 702 703 if (ret_value == 0) 704 return 0; 705 } 706 707 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 708 chp->wdc->select(chp,0); 709 /* assert SRST, wait for reset to complete */ 710 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 711 WDSD_IBM); 712 delay(10); /* 400ns delay */ 713 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 714 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 715 DELAY(2000); 716 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 717 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 718 delay(10); /* 400ns delay */ 719 720 ret_value = __wdcwait_reset(chp, ret_value, poll); 721 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 722 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 723 ret_value), DEBUG_PROBE); 724 725 /* if reset failed, there's nothing here */ 726 if (ret_value == 0) 727 return 0; 728 729 /* 730 * Test presence of drives. First test register signatures looking for 731 * ATAPI devices. If it's not an ATAPI and reset said there may be 732 * something here assume it's ATA or OLD. Ghost will be killed later in 733 * attach routine. 734 */ 735 for (drive = 0; drive < 2; drive++) { 736 if ((ret_value & (0x01 << drive)) == 0) 737 continue; 738 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 739 chp->wdc->select(chp,drive); 740 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 741 WDSD_IBM | (drive << 4)); 742 delay(10); /* 400ns delay */ 743 /* Save registers contents */ 744 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 745 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 746 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 747 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 748 749 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 750 "cl=0x%x ch=0x%x\n", 751 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 752 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 753 /* 754 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 755 * we get wrong values here, so ignore it. 756 */ 757 if (cl == 0x14 && ch == 0xeb) { 758 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 759 } else { 760 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 761 if (chp->wdc == NULL || 762 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 763 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 764 } 765 } 766 return (ret_value); 767 } 768 769 void 770 wdcattach(chp) 771 struct channel_softc *chp; 772 { 773 static int inited = 0; 774 775 if (chp->ch_flags & WDCF_DISABLED) 776 return; 777 778 /* initialise global data */ 779 callout_init(&chp->ch_callout); 780 if (inited == 0) { 781 /* Initialize the wdc_xfer pool. */ 782 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 783 0, 0, "wdcspl", NULL); 784 inited++; 785 } 786 TAILQ_INIT(&chp->ch_queue->sc_xfer); 787 chp->ch_queue->queue_freeze = 0; 788 789 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 790 } 791 792 /* 793 * Call activate routine of underlying devices. 794 */ 795 int 796 atabusactivate(self, act) 797 struct device *self; 798 enum devact act; 799 { 800 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 801 struct channel_softc *chp = atabus_sc->sc_chan; 802 struct device *sc = 0; 803 int s, i, error = 0; 804 805 s = splbio(); 806 switch (act) { 807 case DVACT_ACTIVATE: 808 error = EOPNOTSUPP; 809 break; 810 811 case DVACT_DEACTIVATE: 812 /* 813 * We might call deactivate routine for 814 * the children of atapibus twice (once via 815 * atapibus, once directly), but since 816 * config_deactivate maintains DVF_ACTIVE flag, 817 * it's safe. 818 */ 819 sc = chp->atapibus; 820 if (sc != NULL) { 821 error = config_deactivate(sc); 822 if (error != 0) 823 goto out; 824 } 825 826 for (i = 0; i < 2; i++) { 827 sc = chp->ch_drive[i].drv_softc; 828 WDCDEBUG_PRINT(("atabusactivate: %s:" 829 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 830 sc == NULL ? "nodrv" : sc->dv_xname), 831 DEBUG_DETACH); 832 if (sc != NULL) { 833 error = config_deactivate(sc); 834 if (error != 0) 835 goto out; 836 } 837 } 838 break; 839 } 840 841 out: 842 splx(s); 843 844 #ifdef WDCDEBUG 845 if (sc && error != 0) 846 WDCDEBUG_PRINT(("atabusactivate: %s: " 847 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 848 error, sc->dv_xname), DEBUG_DETACH); 849 #endif 850 return (error); 851 } 852 853 int wdcactivate(self, act) 854 struct device *self; 855 enum devact act; 856 { 857 struct wdc_softc *wdc = (struct wdc_softc *)self; 858 int s, i, error = 0; 859 860 s = splbio(); 861 switch (act) { 862 case DVACT_ACTIVATE: 863 error = EOPNOTSUPP; 864 break; 865 866 case DVACT_DEACTIVATE: 867 for (i = 0; i < wdc->nchannels; i++) { 868 error = config_deactivate(wdc->channels[i]->atabus); 869 if (error) 870 break; 871 } 872 break; 873 } 874 splx(s); 875 return (error); 876 } 877 878 879 int 880 atabusdetach(self, flags) 881 struct device *self; 882 int flags; 883 { 884 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 885 struct channel_softc *chp = atabus_sc->sc_chan; 886 struct device *sc = 0; 887 int i, error = 0; 888 889 /* shutdown channel */ 890 chp->ch_flags |= WDCF_SHUTDOWN; 891 wakeup(&chp->thread); 892 while (chp->thread != NULL) 893 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 894 895 /* 896 * Detach atapibus and its children. 897 */ 898 sc = chp->atapibus; 899 if (sc != NULL) { 900 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 901 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 902 error = config_detach(sc, flags); 903 if (error != 0) 904 goto out; 905 } 906 907 /* 908 * Detach our other children. 909 */ 910 for (i = 0; i < 2; i++) { 911 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 912 continue; 913 sc = chp->ch_drive[i].drv_softc; 914 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 915 atabus_sc->sc_dev.dv_xname, 916 sc == NULL ? "nodrv" : sc->dv_xname), 917 DEBUG_DETACH); 918 if (sc != NULL) { 919 error = config_detach(sc, flags); 920 if (error != 0) 921 goto out; 922 } 923 } 924 925 wdc_kill_pending(chp); 926 927 out: 928 #ifdef WDCDEBUG 929 if (sc && error != 0) 930 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 931 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 932 DEBUG_DETACH); 933 #endif 934 return (error); 935 } 936 937 int 938 wdcdetach(self, flags) 939 struct device *self; 940 int flags; 941 { 942 struct wdc_softc *wdc = (struct wdc_softc *)self; 943 struct channel_softc *chp; 944 int i, error = 0; 945 946 for (i = 0; i < wdc->nchannels; i++) { 947 chp = wdc->channels[i]; 948 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 949 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 950 error = config_detach(chp->atabus, flags); 951 if (error) 952 break; 953 } 954 return (error); 955 } 956 957 /* 958 * Start I/O on a controller, for the given channel. 959 * The first xfer may be not for our channel if the channel queues 960 * are shared. 961 */ 962 void 963 wdcstart(chp) 964 struct channel_softc *chp; 965 { 966 struct wdc_xfer *xfer; 967 968 #ifdef WDC_DIAGNOSTIC 969 int spl1, spl2; 970 971 spl1 = splbio(); 972 spl2 = splbio(); 973 if (spl2 != spl1) { 974 printf("wdcstart: not at splbio()\n"); 975 panic("wdcstart"); 976 } 977 splx(spl2); 978 splx(spl1); 979 #endif /* WDC_DIAGNOSTIC */ 980 981 /* is there a xfer ? */ 982 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 983 return; 984 985 /* adjust chp, in case we have a shared queue */ 986 chp = xfer->chp; 987 988 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 989 return; /* channel aleady active */ 990 } 991 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 992 return; /* queue froozen */ 993 } 994 #ifdef DIAGNOSTIC 995 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 996 panic("wdcstart: channel waiting for irq"); 997 #endif 998 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 999 if (!(*chp->wdc->claim_hw)(chp, 0)) 1000 return; 1001 1002 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1003 chp->channel, xfer->drive), DEBUG_XFERS); 1004 chp->ch_flags |= WDCF_ACTIVE; 1005 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1006 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1007 chp->ch_drive[xfer->drive].state = 0; 1008 } 1009 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1010 KASSERT(xfer->c_flags & C_POLL); 1011 xfer->c_start(chp, xfer); 1012 } 1013 1014 /* restart an interrupted I/O */ 1015 void 1016 wdcrestart(v) 1017 void *v; 1018 { 1019 struct channel_softc *chp = v; 1020 int s; 1021 1022 s = splbio(); 1023 wdcstart(chp); 1024 splx(s); 1025 } 1026 1027 1028 /* 1029 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1030 * errors on the current operation, mark it done if necessary, and start the 1031 * next request. Also check for a partially done transfer, and continue with 1032 * the next chunk if so. 1033 */ 1034 int 1035 wdcintr(arg) 1036 void *arg; 1037 { 1038 struct channel_softc *chp = arg; 1039 struct wdc_xfer *xfer; 1040 int ret; 1041 1042 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1043 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1044 DEBUG_INTR); 1045 return (0); 1046 } 1047 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1048 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1049 /* try to clear the pending interrupt anyway */ 1050 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1051 return (0); 1052 } 1053 1054 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1055 xfer = chp->ch_queue->sc_xfer.tqh_first; 1056 if (chp->ch_flags & WDCF_DMA_WAIT) { 1057 chp->wdc->dma_status = 1058 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1059 xfer->drive, 0); 1060 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1061 /* IRQ not for us, not detected by DMA engine */ 1062 return 0; 1063 } 1064 chp->ch_flags &= ~WDCF_DMA_WAIT; 1065 } 1066 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1067 ret = xfer->c_intr(chp, xfer, 1); 1068 if (ret == 0) /* irq was not for us, still waiting for irq */ 1069 chp->ch_flags |= WDCF_IRQ_WAIT; 1070 return (ret); 1071 } 1072 1073 /* Put all disk in RESET state */ 1074 void 1075 wdc_reset_channel(drvp, flags) 1076 struct ata_drive_datas *drvp; 1077 int flags; 1078 { 1079 struct channel_softc *chp = drvp->chnl_softc; 1080 int drive; 1081 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1082 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1083 DEBUG_FUNCS); 1084 if ((flags & AT_POLL) == 0) { 1085 if (chp->ch_flags & WDCF_TH_RESET) { 1086 /* no need to schedule a reset more than one time */ 1087 return; 1088 } 1089 chp->ch_flags |= WDCF_TH_RESET; 1090 chp->ch_queue->queue_freeze++; 1091 wakeup(&chp->thread); 1092 return; 1093 } 1094 (void) wdcreset(chp, RESET_POLL); 1095 for (drive = 0; drive < 2; drive++) { 1096 chp->ch_drive[drive].state = 0; 1097 } 1098 } 1099 1100 int 1101 wdcreset(chp, poll) 1102 struct channel_softc *chp; 1103 int poll; 1104 { 1105 int drv_mask1, drv_mask2; 1106 1107 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1108 chp->wdc->select(chp,0); 1109 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1110 WDSD_IBM); /* master */ 1111 delay(10); /* 400ns delay */ 1112 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1113 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1114 delay(2000); 1115 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1116 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1117 WDCTL_4BIT | WDCTL_IDS); 1118 delay(10); /* 400ns delay */ 1119 1120 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1121 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1122 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1123 (poll == RESET_SLEEP) ? 0 : 1); 1124 if (drv_mask2 != drv_mask1) { 1125 printf("%s channel %d: reset failed for", 1126 chp->wdc->sc_dev.dv_xname, chp->channel); 1127 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1128 printf(" drive 0"); 1129 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1130 printf(" drive 1"); 1131 printf("\n"); 1132 } 1133 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1134 return (drv_mask1 != drv_mask2) ? 1 : 0; 1135 } 1136 1137 static int 1138 __wdcwait_reset(chp, drv_mask, poll) 1139 struct channel_softc *chp; 1140 int drv_mask; 1141 { 1142 int timeout, nloop; 1143 u_int8_t st0 = 0, st1 = 0; 1144 #ifdef WDCDEBUG 1145 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1146 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1147 #endif 1148 1149 if (poll) 1150 nloop = WDCNDELAY_RST; 1151 else 1152 nloop = WDC_RESET_WAIT * hz / 1000; 1153 /* wait for BSY to deassert */ 1154 for (timeout = 0; timeout < nloop; timeout++) { 1155 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1156 chp->wdc->select(chp,0); 1157 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1158 WDSD_IBM); /* master */ 1159 delay(10); 1160 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1161 #ifdef WDCDEBUG 1162 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1163 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1164 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1165 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1166 #endif 1167 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1168 chp->wdc->select(chp,1); 1169 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1170 WDSD_IBM | 0x10); /* slave */ 1171 delay(10); 1172 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1173 #ifdef WDCDEBUG 1174 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1175 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1176 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1177 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1178 #endif 1179 1180 if ((drv_mask & 0x01) == 0) { 1181 /* no master */ 1182 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1183 /* No master, slave is ready, it's done */ 1184 goto end; 1185 } 1186 } else if ((drv_mask & 0x02) == 0) { 1187 /* no slave */ 1188 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1189 /* No slave, master is ready, it's done */ 1190 goto end; 1191 } 1192 } else { 1193 /* Wait for both master and slave to be ready */ 1194 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1195 goto end; 1196 } 1197 } 1198 if (poll) 1199 delay(WDCDELAY); 1200 else 1201 tsleep(&nloop, PRIBIO, "atarst", 1); 1202 } 1203 /* Reset timed out. Maybe it's because drv_mask was not right */ 1204 if (st0 & WDCS_BSY) 1205 drv_mask &= ~0x01; 1206 if (st1 & WDCS_BSY) 1207 drv_mask &= ~0x02; 1208 end: 1209 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1210 "cl=0x%x ch=0x%x\n", 1211 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1212 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1213 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1214 "cl=0x%x ch=0x%x\n", 1215 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1216 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1217 1218 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1219 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1220 st0, st1), DEBUG_PROBE); 1221 1222 return drv_mask; 1223 } 1224 1225 /* 1226 * Wait for a drive to be !BSY, and have mask in its status register. 1227 * return -1 for a timeout after "timeout" ms. 1228 */ 1229 int 1230 __wdcwait(chp, mask, bits, timeout) 1231 struct channel_softc *chp; 1232 int mask, bits, timeout; 1233 { 1234 u_char status; 1235 int time = 0; 1236 1237 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1238 :"none", chp->channel), DEBUG_STATUS); 1239 chp->ch_error = 0; 1240 1241 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1242 1243 for (;;) { 1244 chp->ch_status = status = 1245 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1246 if ((status & (WDCS_BSY | mask)) == bits) 1247 break; 1248 if (++time > timeout) { 1249 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1250 "status %x error %x (mask 0x%x bits 0x%x)\n", 1251 time, status, 1252 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1253 wd_error), mask, bits), 1254 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1255 return(WDCWAIT_TOUT); 1256 } 1257 delay(WDCDELAY); 1258 } 1259 #ifdef WDCDEBUG 1260 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1261 printf("__wdcwait: did busy-wait, time=%d\n", time); 1262 #endif 1263 if (status & WDCS_ERR) 1264 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1265 wd_error); 1266 #ifdef WDCNDELAY_DEBUG 1267 /* After autoconfig, there should be no long delays. */ 1268 if (!cold && time > WDCNDELAY_DEBUG) { 1269 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1270 if (xfer == NULL) 1271 printf("%s channel %d: warning: busy-wait took %dus\n", 1272 chp->wdc->sc_dev.dv_xname, chp->channel, 1273 WDCDELAY * time); 1274 else 1275 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1276 chp->wdc->sc_dev.dv_xname, chp->channel, 1277 xfer->drive, 1278 WDCDELAY * time); 1279 } 1280 #endif 1281 return(WDCWAIT_OK); 1282 } 1283 1284 /* 1285 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1286 * thread if possible 1287 */ 1288 int 1289 wdcwait(chp, mask, bits, timeout, flags) 1290 struct channel_softc *chp; 1291 int mask, bits, timeout, flags; 1292 { 1293 int error, i, timeout_hz = mstohz(timeout); 1294 1295 if (timeout_hz == 0 || 1296 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1297 error = __wdcwait(chp, mask, bits, timeout); 1298 else { 1299 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1300 if (error != 0) { 1301 if ((chp->ch_flags & WDCF_TH_RUN) || 1302 (flags & AT_WAIT)) { 1303 /* 1304 * we're running in the channel thread 1305 * or some userland thread context 1306 */ 1307 for (i = 0; i < timeout_hz; i++) { 1308 if (__wdcwait(chp, mask, bits, 1309 WDCDELAY_POLL) == 0) { 1310 error = 0; 1311 break; 1312 } 1313 tsleep(&chp, PRIBIO, "atapoll", 1); 1314 } 1315 } else { 1316 /* 1317 * we're probably in interrupt context, 1318 * ask the thread to come back here 1319 */ 1320 #ifdef DIAGNOSTIC 1321 if (chp->ch_queue->queue_freeze > 0) 1322 panic("wdcwait: queue_freeze"); 1323 #endif 1324 chp->ch_queue->queue_freeze++; 1325 wakeup(&chp->thread); 1326 return(WDCWAIT_THR); 1327 } 1328 } 1329 } 1330 return(error); 1331 } 1332 1333 1334 /* 1335 * Busy-wait for DMA to complete 1336 */ 1337 int 1338 wdc_dmawait(chp, xfer, timeout) 1339 struct channel_softc *chp; 1340 struct wdc_xfer *xfer; 1341 int timeout; 1342 { 1343 int time; 1344 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1345 chp->wdc->dma_status = 1346 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1347 chp->channel, xfer->drive, 0); 1348 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1349 return 0; 1350 delay(WDCDELAY); 1351 } 1352 /* timeout, force a DMA halt */ 1353 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1354 chp->channel, xfer->drive, 1); 1355 return 1; 1356 } 1357 1358 void 1359 wdctimeout(arg) 1360 void *arg; 1361 { 1362 struct channel_softc *chp = (struct channel_softc *)arg; 1363 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1364 int s; 1365 1366 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1367 1368 s = splbio(); 1369 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1370 __wdcerror(chp, "lost interrupt"); 1371 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1372 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1373 xfer->c_bcount, 1374 xfer->c_skip); 1375 if (chp->ch_flags & WDCF_DMA_WAIT) { 1376 chp->wdc->dma_status = 1377 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1378 chp->channel, xfer->drive, 1); 1379 chp->ch_flags &= ~WDCF_DMA_WAIT; 1380 } 1381 /* 1382 * Call the interrupt routine. If we just missed an interrupt, 1383 * it will do what's needed. Else, it will take the needed 1384 * action (reset the device). 1385 * Before that we need to reinstall the timeout callback, 1386 * in case it will miss another irq while in this transfer 1387 * We arbitray chose it to be 1s 1388 */ 1389 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1390 xfer->c_flags |= C_TIMEOU; 1391 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1392 xfer->c_intr(chp, xfer, 1); 1393 } else 1394 __wdcerror(chp, "missing untimeout"); 1395 splx(s); 1396 } 1397 1398 /* 1399 * Probe drive's capabilities, for use by the controller later 1400 * Assumes drvp points to an existing drive. 1401 * XXX this should be a controller-indep function 1402 */ 1403 void 1404 wdc_probe_caps(drvp) 1405 struct ata_drive_datas *drvp; 1406 { 1407 struct ataparams params, params2; 1408 struct channel_softc *chp = drvp->chnl_softc; 1409 struct device *drv_dev = drvp->drv_softc; 1410 struct wdc_softc *wdc = chp->wdc; 1411 int i, printed; 1412 char *sep = ""; 1413 int cf_flags; 1414 1415 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1416 /* IDENTIFY failed. Can't tell more about the device */ 1417 return; 1418 } 1419 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1420 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1421 /* 1422 * Controller claims 16 and 32 bit transfers. 1423 * Re-do an IDENTIFY with 32-bit transfers, 1424 * and compare results. 1425 */ 1426 drvp->drive_flags |= DRIVE_CAP32; 1427 ata_get_params(drvp, AT_WAIT, ¶ms2); 1428 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1429 /* Not good. fall back to 16bits */ 1430 drvp->drive_flags &= ~DRIVE_CAP32; 1431 } else { 1432 aprint_normal("%s: 32-bit data port\n", 1433 drv_dev->dv_xname); 1434 } 1435 } 1436 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1437 if (params.atap_ata_major > 0x01 && 1438 params.atap_ata_major != 0xffff) { 1439 for (i = 14; i > 0; i--) { 1440 if (params.atap_ata_major & (1 << i)) { 1441 aprint_normal("%s: ATA version %d\n", 1442 drv_dev->dv_xname, i); 1443 drvp->ata_vers = i; 1444 break; 1445 } 1446 } 1447 } 1448 #endif 1449 1450 /* An ATAPI device is at last PIO mode 3 */ 1451 if (drvp->drive_flags & DRIVE_ATAPI) 1452 drvp->PIO_mode = 3; 1453 1454 /* 1455 * It's not in the specs, but it seems that some drive 1456 * returns 0xffff in atap_extensions when this field is invalid 1457 */ 1458 if (params.atap_extensions != 0xffff && 1459 (params.atap_extensions & WDC_EXT_MODES)) { 1460 printed = 0; 1461 /* 1462 * XXX some drives report something wrong here (they claim to 1463 * support PIO mode 8 !). As mode is coded on 3 bits in 1464 * SET FEATURE, limit it to 7 (so limit i to 4). 1465 * If higher mode than 7 is found, abort. 1466 */ 1467 for (i = 7; i >= 0; i--) { 1468 if ((params.atap_piomode_supp & (1 << i)) == 0) 1469 continue; 1470 if (i > 4) 1471 return; 1472 /* 1473 * See if mode is accepted. 1474 * If the controller can't set its PIO mode, 1475 * assume the defaults are good, so don't try 1476 * to set it 1477 */ 1478 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1479 /* 1480 * It's OK to pool here, it's fast enouth 1481 * to not bother waiting for interrupt 1482 */ 1483 if (ata_set_mode(drvp, 0x08 | (i + 3), 1484 AT_WAIT) != CMD_OK) 1485 continue; 1486 if (!printed) { 1487 aprint_normal("%s: drive supports PIO mode %d", 1488 drv_dev->dv_xname, i + 3); 1489 sep = ","; 1490 printed = 1; 1491 } 1492 /* 1493 * If controller's driver can't set its PIO mode, 1494 * get the highter one for the drive. 1495 */ 1496 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1497 wdc->PIO_cap >= i + 3) { 1498 drvp->PIO_mode = i + 3; 1499 drvp->PIO_cap = i + 3; 1500 break; 1501 } 1502 } 1503 if (!printed) { 1504 /* 1505 * We didn't find a valid PIO mode. 1506 * Assume the values returned for DMA are buggy too 1507 */ 1508 return; 1509 } 1510 drvp->drive_flags |= DRIVE_MODE; 1511 printed = 0; 1512 for (i = 7; i >= 0; i--) { 1513 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1514 continue; 1515 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1516 (wdc->cap & WDC_CAPABILITY_MODE)) 1517 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1518 != CMD_OK) 1519 continue; 1520 if (!printed) { 1521 aprint_normal("%s DMA mode %d", sep, i); 1522 sep = ","; 1523 printed = 1; 1524 } 1525 if (wdc->cap & WDC_CAPABILITY_DMA) { 1526 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1527 wdc->DMA_cap < i) 1528 continue; 1529 drvp->DMA_mode = i; 1530 drvp->DMA_cap = i; 1531 drvp->drive_flags |= DRIVE_DMA; 1532 } 1533 break; 1534 } 1535 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1536 printed = 0; 1537 for (i = 7; i >= 0; i--) { 1538 if ((params.atap_udmamode_supp & (1 << i)) 1539 == 0) 1540 continue; 1541 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1542 (wdc->cap & WDC_CAPABILITY_UDMA)) 1543 if (ata_set_mode(drvp, 0x40 | i, 1544 AT_WAIT) != CMD_OK) 1545 continue; 1546 if (!printed) { 1547 aprint_normal("%s Ultra-DMA mode %d", 1548 sep, i); 1549 if (i == 2) 1550 aprint_normal(" (Ultra/33)"); 1551 else if (i == 4) 1552 aprint_normal(" (Ultra/66)"); 1553 else if (i == 5) 1554 aprint_normal(" (Ultra/100)"); 1555 else if (i == 6) 1556 aprint_normal(" (Ultra/133)"); 1557 sep = ","; 1558 printed = 1; 1559 } 1560 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1561 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1562 wdc->UDMA_cap < i) 1563 continue; 1564 drvp->UDMA_mode = i; 1565 drvp->UDMA_cap = i; 1566 drvp->drive_flags |= DRIVE_UDMA; 1567 } 1568 break; 1569 } 1570 } 1571 aprint_normal("\n"); 1572 } 1573 1574 /* Try to guess ATA version here, if it didn't get reported */ 1575 if (drvp->ata_vers == 0) { 1576 if (drvp->drive_flags & DRIVE_UDMA) 1577 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1578 else if (drvp->PIO_cap > 2) 1579 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1580 } 1581 cf_flags = drv_dev->dv_cfdata->cf_flags; 1582 if (cf_flags & ATA_CONFIG_PIO_SET) { 1583 drvp->PIO_mode = 1584 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1585 drvp->drive_flags |= DRIVE_MODE; 1586 } 1587 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1588 /* don't care about DMA modes */ 1589 return; 1590 } 1591 if (cf_flags & ATA_CONFIG_DMA_SET) { 1592 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1593 ATA_CONFIG_DMA_DISABLE) { 1594 drvp->drive_flags &= ~DRIVE_DMA; 1595 } else { 1596 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1597 ATA_CONFIG_DMA_OFF; 1598 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1599 } 1600 } 1601 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1602 /* don't care about UDMA modes */ 1603 return; 1604 } 1605 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1606 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1607 ATA_CONFIG_UDMA_DISABLE) { 1608 drvp->drive_flags &= ~DRIVE_UDMA; 1609 } else { 1610 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1611 ATA_CONFIG_UDMA_OFF; 1612 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1613 } 1614 } 1615 } 1616 1617 /* 1618 * downgrade the transfer mode of a drive after an error. return 1 if 1619 * downgrade was possible, 0 otherwise. 1620 */ 1621 int 1622 wdc_downgrade_mode(drvp, flags) 1623 struct ata_drive_datas *drvp; 1624 { 1625 struct channel_softc *chp = drvp->chnl_softc; 1626 struct device *drv_dev = drvp->drv_softc; 1627 struct wdc_softc *wdc = chp->wdc; 1628 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1629 1630 /* if drive or controller don't know its mode, we can't do much */ 1631 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1632 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1633 return 0; 1634 /* current drive mode was set by a config flag, let it this way */ 1635 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1636 (cf_flags & ATA_CONFIG_DMA_SET) || 1637 (cf_flags & ATA_CONFIG_UDMA_SET)) 1638 return 0; 1639 1640 /* 1641 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1642 * Maybe we didn't properly notice the cable type 1643 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1644 * It helps in some cases. 1645 */ 1646 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1647 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1648 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1649 drv_dev->dv_xname, drvp->UDMA_mode); 1650 } 1651 1652 /* 1653 * If we were using ultra-DMA, don't downgrade to multiword DMA 1654 * if we noticed a CRC error. It has been noticed that CRC errors 1655 * in ultra-DMA lead to silent data corruption in multiword DMA. 1656 * Data corruption is less likely to occur in PIO mode. 1657 */ 1658 else if ((drvp->drive_flags & DRIVE_UDMA) && 1659 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1660 drvp->drive_flags &= ~DRIVE_UDMA; 1661 drvp->drive_flags |= DRIVE_DMA; 1662 drvp->DMA_mode = drvp->DMA_cap; 1663 printf("%s: transfer error, downgrading to DMA mode %d\n", 1664 drv_dev->dv_xname, drvp->DMA_mode); 1665 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1666 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1667 drvp->PIO_mode = drvp->PIO_cap; 1668 printf("%s: transfer error, downgrading to PIO mode %d\n", 1669 drv_dev->dv_xname, drvp->PIO_mode); 1670 } else /* already using PIO, can't downgrade */ 1671 return 0; 1672 1673 wdc->set_modes(chp); 1674 wdc_print_modes(chp); 1675 /* reset the channel, which will shedule all drives for setup */ 1676 wdc_reset_channel(drvp, flags); 1677 return 1; 1678 } 1679 1680 int 1681 wdc_exec_command(drvp, wdc_c) 1682 struct ata_drive_datas *drvp; 1683 struct wdc_command *wdc_c; 1684 { 1685 struct channel_softc *chp = drvp->chnl_softc; 1686 struct wdc_xfer *xfer; 1687 int s, ret; 1688 1689 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1690 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1691 DEBUG_FUNCS); 1692 1693 /* set up an xfer and queue. Wait for completion */ 1694 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1695 WDC_NOSLEEP); 1696 if (xfer == NULL) { 1697 return WDC_TRY_AGAIN; 1698 } 1699 1700 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1701 wdc_c->flags |= AT_POLL; 1702 if (wdc_c->flags & AT_POLL) 1703 xfer->c_flags |= C_POLL; 1704 xfer->drive = drvp->drive; 1705 xfer->databuf = wdc_c->data; 1706 xfer->c_bcount = wdc_c->bcount; 1707 xfer->cmd = wdc_c; 1708 xfer->c_start = __wdccommand_start; 1709 xfer->c_intr = __wdccommand_intr; 1710 xfer->c_kill_xfer = __wdccommand_done; 1711 1712 s = splbio(); 1713 wdc_exec_xfer(chp, xfer); 1714 #ifdef DIAGNOSTIC 1715 if ((wdc_c->flags & AT_POLL) != 0 && 1716 (wdc_c->flags & AT_DONE) == 0) 1717 panic("wdc_exec_command: polled command not done"); 1718 #endif 1719 if (wdc_c->flags & AT_DONE) { 1720 ret = WDC_COMPLETE; 1721 } else { 1722 if (wdc_c->flags & AT_WAIT) { 1723 while ((wdc_c->flags & AT_DONE) == 0) { 1724 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1725 } 1726 ret = WDC_COMPLETE; 1727 } else { 1728 ret = WDC_QUEUED; 1729 } 1730 } 1731 splx(s); 1732 return ret; 1733 } 1734 1735 void 1736 __wdccommand_start(chp, xfer) 1737 struct channel_softc *chp; 1738 struct wdc_xfer *xfer; 1739 { 1740 int drive = xfer->drive; 1741 struct wdc_command *wdc_c = xfer->cmd; 1742 1743 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1744 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1745 DEBUG_FUNCS); 1746 1747 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1748 chp->wdc->select(chp,drive); 1749 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1750 WDSD_IBM | (drive << 4)); 1751 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1752 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1753 case WDCWAIT_OK: 1754 break; 1755 case WDCWAIT_TOUT: 1756 wdc_c->flags |= AT_TIMEOU; 1757 __wdccommand_done(chp, xfer); 1758 return; 1759 case WDCWAIT_THR: 1760 return; 1761 } 1762 if (wdc_c->flags & AT_POLL) { 1763 /* polled command, disable interrupts */ 1764 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1765 WDCTL_4BIT | WDCTL_IDS); 1766 } 1767 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1768 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1769 1770 if ((wdc_c->flags & AT_POLL) == 0) { 1771 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1772 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1773 wdctimeout, chp); 1774 return; 1775 } 1776 /* 1777 * Polled command. Wait for drive ready or drq. Done in intr(). 1778 * Wait for at last 400ns for status bit to be valid. 1779 */ 1780 delay(10); /* 400ns delay */ 1781 __wdccommand_intr(chp, xfer, 0); 1782 } 1783 1784 int 1785 __wdccommand_intr(chp, xfer, irq) 1786 struct channel_softc *chp; 1787 struct wdc_xfer *xfer; 1788 int irq; 1789 { 1790 struct wdc_command *wdc_c = xfer->cmd; 1791 int bcount = wdc_c->bcount; 1792 char *data = wdc_c->data; 1793 int wflags; 1794 1795 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1796 /* both wait and poll, we can tsleep here */ 1797 wflags = AT_WAIT | AT_POLL; 1798 } else { 1799 wflags = AT_POLL; 1800 } 1801 1802 again: 1803 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1804 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1805 /* 1806 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1807 * Reselect again, it doesn't hurt for others commands, and the time 1808 * penalty for the extra regiter write is acceptable, 1809 * wdc_exec_command() isn't called often (mosly for autoconfig) 1810 */ 1811 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1812 WDSD_IBM | (xfer->drive << 4)); 1813 if ((wdc_c->flags & AT_XFDONE) != 0) { 1814 /* 1815 * We have completed a data xfer. The drive should now be 1816 * in its initial state 1817 */ 1818 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1819 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1820 wflags) == WDCWAIT_TOUT) { 1821 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1822 return 0; /* IRQ was not for us */ 1823 wdc_c->flags |= AT_TIMEOU; 1824 } 1825 goto out; 1826 } 1827 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1828 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1829 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1830 return 0; /* IRQ was not for us */ 1831 wdc_c->flags |= AT_TIMEOU; 1832 goto out; 1833 } 1834 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1835 chp->wdc->irqack(chp); 1836 if (wdc_c->flags & AT_READ) { 1837 if ((chp->ch_status & WDCS_DRQ) == 0) { 1838 wdc_c->flags |= AT_TIMEOU; 1839 goto out; 1840 } 1841 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1842 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1843 0, (u_int32_t*)data, bcount >> 2); 1844 data += bcount & 0xfffffffc; 1845 bcount = bcount & 0x03; 1846 } 1847 if (bcount > 0) 1848 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1849 wd_data, (u_int16_t *)data, bcount >> 1); 1850 /* at this point the drive should be in its initial state */ 1851 wdc_c->flags |= AT_XFDONE; 1852 /* XXX should read status register here ? */ 1853 } else if (wdc_c->flags & AT_WRITE) { 1854 if ((chp->ch_status & WDCS_DRQ) == 0) { 1855 wdc_c->flags |= AT_TIMEOU; 1856 goto out; 1857 } 1858 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1859 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1860 0, (u_int32_t*)data, bcount >> 2); 1861 data += bcount & 0xfffffffc; 1862 bcount = bcount & 0x03; 1863 } 1864 if (bcount > 0) 1865 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1866 wd_data, (u_int16_t *)data, bcount >> 1); 1867 wdc_c->flags |= AT_XFDONE; 1868 if ((wdc_c->flags & AT_POLL) == 0) { 1869 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1870 callout_reset(&chp->ch_callout, 1871 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1872 return 1; 1873 } else { 1874 goto again; 1875 } 1876 } 1877 out: 1878 __wdccommand_done(chp, xfer); 1879 return 1; 1880 } 1881 1882 void 1883 __wdccommand_done(chp, xfer) 1884 struct channel_softc *chp; 1885 struct wdc_xfer *xfer; 1886 { 1887 struct wdc_command *wdc_c = xfer->cmd; 1888 1889 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1890 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1891 1892 callout_stop(&chp->ch_callout); 1893 1894 if (chp->ch_status & WDCS_DWF) 1895 wdc_c->flags |= AT_DF; 1896 if (chp->ch_status & WDCS_ERR) { 1897 wdc_c->flags |= AT_ERROR; 1898 wdc_c->r_error = chp->ch_error; 1899 } 1900 wdc_c->flags |= AT_DONE; 1901 if ((wdc_c->flags & AT_READREG) != 0 && 1902 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1903 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1904 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1905 wd_sdh); 1906 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1907 wd_cyl_hi) << 8; 1908 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1909 wd_cyl_lo); 1910 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1911 wd_sector); 1912 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1913 wd_seccnt); 1914 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1915 wd_error); 1916 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1917 wd_precomp); 1918 } 1919 1920 if (wdc_c->flags & AT_POLL) { 1921 /* enable interrupts */ 1922 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1923 WDCTL_4BIT); 1924 } 1925 wdc_free_xfer(chp, xfer); 1926 if (wdc_c->flags & AT_WAIT) 1927 wakeup(wdc_c); 1928 else if (wdc_c->callback) 1929 wdc_c->callback(wdc_c->callback_arg); 1930 wdcstart(chp); 1931 return; 1932 } 1933 1934 /* 1935 * Send a command. The drive should be ready. 1936 * Assumes interrupts are blocked. 1937 */ 1938 void 1939 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1940 struct channel_softc *chp; 1941 u_int8_t drive; 1942 u_int8_t command; 1943 u_int16_t cylin; 1944 u_int8_t head, sector, count, precomp; 1945 { 1946 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1947 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1948 chp->channel, drive, command, cylin, head, sector, count, precomp), 1949 DEBUG_FUNCS); 1950 1951 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1952 chp->wdc->select(chp,drive); 1953 1954 /* Select drive, head, and addressing mode. */ 1955 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1956 WDSD_IBM | (drive << 4) | head); 1957 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1959 precomp); 1960 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1961 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1962 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1963 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1964 1965 /* Send command. */ 1966 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1967 return; 1968 } 1969 1970 /* 1971 * Send a 48-bit addressing command. The drive should be ready. 1972 * Assumes interrupts are blocked. 1973 */ 1974 void 1975 wdccommandext(chp, drive, command, blkno, count) 1976 struct channel_softc *chp; 1977 u_int8_t drive; 1978 u_int8_t command; 1979 u_int64_t blkno; 1980 u_int16_t count; 1981 { 1982 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1983 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1984 chp->channel, drive, command, (u_int32_t) blkno, count), 1985 DEBUG_FUNCS); 1986 1987 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1988 chp->wdc->select(chp,drive); 1989 1990 /* Select drive, head, and addressing mode. */ 1991 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1992 (drive << 4) | WDSD_LBA); 1993 1994 /* previous */ 1995 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 1996 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 1997 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 1998 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 1999 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 2000 2001 /* current */ 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 2003 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 2004 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 2006 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 2007 2008 /* Send command. */ 2009 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2010 return; 2011 } 2012 2013 /* 2014 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2015 * tested by the caller. 2016 */ 2017 void 2018 wdccommandshort(chp, drive, command) 2019 struct channel_softc *chp; 2020 int drive; 2021 int command; 2022 { 2023 2024 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2025 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2026 DEBUG_FUNCS); 2027 2028 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2029 chp->wdc->select(chp,drive); 2030 2031 /* Select drive. */ 2032 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2033 WDSD_IBM | (drive << 4)); 2034 2035 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2036 } 2037 2038 /* Add a command to the queue and start controller. Must be called at splbio */ 2039 2040 void 2041 wdc_exec_xfer(chp, xfer) 2042 struct channel_softc *chp; 2043 struct wdc_xfer *xfer; 2044 { 2045 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2046 chp->channel, xfer->drive), DEBUG_XFERS); 2047 2048 /* complete xfer setup */ 2049 xfer->chp = chp; 2050 2051 /* 2052 * If we are a polled command, and the list is not empty, 2053 * we are doing a dump. Drop the list to allow the polled command 2054 * to complete, we're going to reboot soon anyway. 2055 */ 2056 if ((xfer->c_flags & C_POLL) != 0 && 2057 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2058 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2059 } 2060 /* insert at the end of command list */ 2061 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2062 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2063 chp->ch_flags), DEBUG_XFERS); 2064 wdcstart(chp); 2065 } 2066 2067 struct wdc_xfer * 2068 wdc_get_xfer(flags) 2069 int flags; 2070 { 2071 struct wdc_xfer *xfer; 2072 int s; 2073 2074 s = splbio(); 2075 xfer = pool_get(&wdc_xfer_pool, 2076 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2077 splx(s); 2078 if (xfer != NULL) { 2079 memset(xfer, 0, sizeof(struct wdc_xfer)); 2080 } 2081 return xfer; 2082 } 2083 2084 void 2085 wdc_free_xfer(chp, xfer) 2086 struct channel_softc *chp; 2087 struct wdc_xfer *xfer; 2088 { 2089 struct wdc_softc *wdc = chp->wdc; 2090 int s; 2091 2092 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2093 (*wdc->free_hw)(chp); 2094 s = splbio(); 2095 chp->ch_flags &= ~WDCF_ACTIVE; 2096 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2097 pool_put(&wdc_xfer_pool, xfer); 2098 splx(s); 2099 } 2100 2101 /* 2102 * Kill off all pending xfers for a channel_softc. 2103 * 2104 * Must be called at splbio(). 2105 */ 2106 void 2107 wdc_kill_pending(chp) 2108 struct channel_softc *chp; 2109 { 2110 struct wdc_xfer *xfer; 2111 2112 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2113 chp = xfer->chp; 2114 (*xfer->c_kill_xfer)(chp, xfer); 2115 } 2116 } 2117 2118 static void 2119 __wdcerror(chp, msg) 2120 struct channel_softc *chp; 2121 char *msg; 2122 { 2123 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2124 2125 if (xfer == NULL) 2126 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2127 msg); 2128 else 2129 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2130 chp->channel, xfer->drive, msg); 2131 } 2132 2133 /* 2134 * the bit bucket 2135 */ 2136 void 2137 wdcbit_bucket(chp, size) 2138 struct channel_softc *chp; 2139 int size; 2140 { 2141 2142 for (; size >= 2; size -= 2) 2143 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2144 if (size) 2145 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2146 } 2147 2148 int 2149 wdc_addref(chp) 2150 struct channel_softc *chp; 2151 { 2152 struct wdc_softc *wdc = chp->wdc; 2153 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2154 int s, error = 0; 2155 2156 s = splbio(); 2157 if (adapt->adapt_refcnt++ == 0 && 2158 adapt->adapt_enable != NULL) { 2159 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2160 if (error) 2161 adapt->adapt_refcnt--; 2162 } 2163 splx(s); 2164 return (error); 2165 } 2166 2167 void 2168 wdc_delref(chp) 2169 struct channel_softc *chp; 2170 { 2171 struct wdc_softc *wdc = chp->wdc; 2172 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2173 int s; 2174 2175 s = splbio(); 2176 if (adapt->adapt_refcnt-- == 1 && 2177 adapt->adapt_enable != NULL) 2178 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2179 splx(s); 2180 } 2181 2182 void 2183 wdc_print_modes(struct channel_softc *chp) 2184 { 2185 int drive; 2186 struct ata_drive_datas *drvp; 2187 2188 for (drive = 0; drive < 2; drive++) { 2189 drvp = &chp->ch_drive[drive]; 2190 if ((drvp->drive_flags & DRIVE) == 0) 2191 continue; 2192 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2193 drvp->drv_softc->dv_xname, 2194 chp->wdc->sc_dev.dv_xname, 2195 chp->channel, drive, drvp->PIO_mode); 2196 if (drvp->drive_flags & DRIVE_DMA) 2197 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2198 if (drvp->drive_flags & DRIVE_UDMA) { 2199 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2200 if (drvp->UDMA_mode == 2) 2201 aprint_normal(" (Ultra/33)"); 2202 else if (drvp->UDMA_mode == 4) 2203 aprint_normal(" (Ultra/66)"); 2204 else if (drvp->UDMA_mode == 5) 2205 aprint_normal(" (Ultra/100)"); 2206 else if (drvp->UDMA_mode == 6) 2207 aprint_normal(" (Ultra/133)"); 2208 } 2209 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2210 aprint_normal(" (using DMA data transfers)"); 2211 aprint_normal("\n"); 2212 } 2213 } 2214
Indexes created Tue Sep 23 07:09:52 GMT 2025