wdc.c revision 1.156
1 /* $NetBSD: wdc.c,v 1.156 2003/11/25 21:03:15 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.156 2003/11/25 21:03:15 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 aprint_normal("\n"); 236 aprint_naive("\n"); 237 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 238 atabus_initq->atabus_sc = atabus_sc; 239 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 240 config_pending_incr(); 241 kthread_create(atabus_create_thread, atabus_sc); 242 243 } 244 245 void 246 atabus_create_thread(arg) 247 void *arg; 248 { 249 struct atabus_softc *atabus_sc = arg; 250 struct channel_softc *chp = atabus_sc->sc_chan; 251 int error; 252 253 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 254 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 255 printf("unable to create kernel thread for %s: error %d\n", 256 atabus_sc->sc_dev.dv_xname, error); 257 } 258 259 void 260 atabus_thread(arg) 261 void *arg; 262 { 263 struct atabus_softc *atabus_sc = arg; 264 struct channel_softc *chp = atabus_sc->sc_chan; 265 struct wdc_xfer *xfer; 266 int s; 267 268 s = splbio(); 269 chp->ch_flags |= WDCF_TH_RUN; 270 splx(s); 271 atabusconfig(atabus_sc); 272 for(;;) { 273 s = splbio(); 274 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 275 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 276 chp->ch_queue->queue_freeze == 0)) { 277 chp->ch_flags &= ~WDCF_TH_RUN; 278 tsleep(&chp->thread, PRIBIO, "atath", 0); 279 chp->ch_flags |= WDCF_TH_RUN; 280 } 281 splx(s); 282 if (chp->ch_flags & WDCF_SHUTDOWN) 283 break; 284 s = splbio(); 285 if (chp->ch_flags & WDCF_TH_RESET) { 286 int drive; 287 (void) wdcreset(chp, RESET_SLEEP); 288 for (drive = 0; drive < 2; drive++) { 289 chp->ch_drive[drive].state = 0; 290 } 291 chp->ch_flags &= ~WDCF_TH_RESET; 292 chp->ch_queue->queue_freeze--; 293 wdcstart(chp); 294 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 295 chp->ch_queue->queue_freeze == 1) { 296 /* 297 * caller has bumped queue_freeze, decrease it 298 */ 299 chp->ch_queue->queue_freeze--; 300 xfer = chp->ch_queue->sc_xfer.tqh_first; 301 #ifdef DIAGNOSTIC 302 if (xfer == NULL) 303 panic("channel active with no xfer ?"); 304 #endif 305 xfer->c_start(chp, xfer); 306 } else if (chp->ch_queue->queue_freeze > 1) { 307 panic("queue_freeze"); 308 } 309 splx(s); 310 } 311 chp->thread = NULL; 312 wakeup(&chp->ch_flags); 313 kthread_exit(0); 314 } 315 316 void 317 atabusconfig(atabus_sc) 318 struct atabus_softc *atabus_sc; 319 { 320 struct channel_softc *chp = atabus_sc->sc_chan; 321 int i, error, need_delref = 0; 322 struct ataparams params; 323 struct atabus_initq *atabus_initq = NULL; 324 u_int8_t st0 = 0, st1 = 0; 325 326 if ((error = wdc_addref(chp)) != 0) { 327 aprint_error("%s: unable to enable controller\n", 328 chp->wdc->sc_dev.dv_xname); 329 goto out; 330 } 331 need_delref = 1; 332 333 if (__wdcprobe(chp, 0) == 0) 334 /* If no drives, abort attach here. */ 335 goto out; 336 337 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 338 for (i = 0; i < mstohz(3000); i++) { 339 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 340 chp->wdc->select(chp,0); 341 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 342 WDSD_IBM); 343 delay(10); /* 400ns delay */ 344 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 345 346 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 347 chp->wdc->select(chp,1); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 349 WDSD_IBM | 0x10); 350 delay(10); /* 400ns delay */ 351 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 352 353 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 354 == 0 || 355 (st0 & WDCS_DRDY)) && 356 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 357 == 0 || 358 (st1 & WDCS_DRDY))) 359 break; 360 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 361 } 362 if ((st0 & WDCS_DRDY) == 0) 363 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 364 if ((st1 & WDCS_DRDY) == 0) 365 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 366 367 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 368 chp->wdc->sc_dev.dv_xname, 369 chp->channel, st0, st1), DEBUG_PROBE); 370 371 /* Wait a bit, some devices are weird just after a reset. */ 372 delay(5000); 373 374 for (i = 0; i < 2; i++) { 375 chp->ch_drive[i].chnl_softc = chp; 376 chp->ch_drive[i].drive = i; 377 /* 378 * Init error counter so that an error withing the first xfers 379 * will trigger a downgrade 380 */ 381 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 382 383 /* If controller can't do 16bit flag the drives as 32bit */ 384 if ((chp->wdc->cap & 385 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 386 WDC_CAPABILITY_DATA32) 387 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 388 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 389 continue; 390 391 /* Shortcut in case we've been shutdown */ 392 if (chp->ch_flags & WDCF_SHUTDOWN) 393 goto out; 394 395 /* issue an identify, to try to detect ghosts */ 396 error = ata_get_params(&chp->ch_drive[i], 397 AT_WAIT | AT_POLL, ¶ms); 398 if (error != CMD_OK) { 399 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 400 401 /* Shortcut in case we've been shutdown */ 402 if (chp->ch_flags & WDCF_SHUTDOWN) 403 goto out; 404 405 error = ata_get_params(&chp->ch_drive[i], 406 AT_WAIT | AT_POLL, ¶ms); 407 } 408 if (error == CMD_OK) { 409 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 410 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 411 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 412 } else { 413 chp->ch_drive[i].drive_flags &= 414 ~(DRIVE_ATA | DRIVE_ATAPI); 415 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 416 chp->wdc->sc_dev.dv_xname, 417 chp->channel, i, error), DEBUG_PROBE); 418 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 419 continue; 420 /* 421 * Pre-ATA drive ? 422 * Test registers writability (Error register not 423 * writable, but cyllo is), then try an ATA command. 424 */ 425 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 426 chp->wdc->select(chp,i); 427 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 428 WDSD_IBM | (i << 4)); 429 delay(10); /* 400ns delay */ 430 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 431 wd_error, 0x58); 432 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 433 wd_cyl_lo, 0xa5); 434 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 435 wd_error) == 0x58 || 436 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 437 wd_cyl_lo) != 0xa5) { 438 WDCDEBUG_PRINT(("%s:%d:%d: register " 439 "writability failed\n", 440 chp->wdc->sc_dev.dv_xname, 441 chp->channel, i), DEBUG_PROBE); 442 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 443 continue; 444 } 445 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 446 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 447 chp->wdc->sc_dev.dv_xname, 448 chp->channel, i), DEBUG_PROBE); 449 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 450 continue; 451 } 452 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 453 wd_command, WDCC_RECAL); 454 delay(10); /* 400ns delay */ 455 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 456 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 457 chp->wdc->sc_dev.dv_xname, 458 chp->channel, i), DEBUG_PROBE); 459 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 460 } else { 461 chp->ch_drive[0].drive_flags &= 462 ~(DRIVE_ATA | DRIVE_ATAPI); 463 chp->ch_drive[1].drive_flags &= 464 ~(DRIVE_ATA | DRIVE_ATAPI); 465 } 466 } 467 } 468 469 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 470 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 471 DEBUG_PROBE); 472 473 /* If no drives, abort here */ 474 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 475 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 476 goto out; 477 478 /* Make sure the devices probe in atabus order to avoid jitter. */ 479 simple_lock(&atabus_interlock); 480 while(1) { 481 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 482 if (atabus_initq->atabus_sc == atabus_sc) 483 break; 484 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 485 &atabus_interlock); 486 } 487 simple_unlock(&atabus_interlock); 488 489 /* 490 * Attach an ATAPI bus, if needed. 491 */ 492 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 493 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 494 #if NATAPIBUS > 0 495 wdc_atapibus_attach(atabus_sc); 496 #else 497 /* 498 * Fake the autoconfig "not configured" message 499 */ 500 aprint_normal("atapibus at %s not configured\n", 501 chp->wdc->sc_dev.dv_xname); 502 chp->atapibus = NULL; 503 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 504 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 505 #endif 506 } 507 508 for (i = 0; i < 2; i++) { 509 struct ata_device adev; 510 if ((chp->ch_drive[i].drive_flags & 511 (DRIVE_ATA | DRIVE_OLD)) == 0) { 512 continue; 513 } 514 memset(&adev, 0, sizeof(struct ata_device)); 515 adev.adev_bustype = &wdc_ata_bustype; 516 adev.adev_channel = chp->channel; 517 adev.adev_openings = 1; 518 adev.adev_drv_data = &chp->ch_drive[i]; 519 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 520 &adev, wdprint); 521 if (chp->ata_drives[i] != NULL) 522 wdc_probe_caps(&chp->ch_drive[i]); 523 else 524 chp->ch_drive[i].drive_flags &= 525 ~(DRIVE_ATA | DRIVE_OLD); 526 } 527 528 /* now that we know the drives, the controller can set its modes */ 529 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 530 chp->wdc->set_modes(chp); 531 wdc_print_modes(chp); 532 } 533 #if NATARAID > 0 534 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 535 for (i = 0; i < 2; i++) 536 if (chp->ata_drives[i] != NULL) 537 ata_raid_check_component(chp->ata_drives[i]); 538 #endif /* NATARAID > 0 */ 539 540 /* 541 * reset drive_flags for unattached devices, reset state for attached 542 * ones 543 */ 544 for (i = 0; i < 2; i++) { 545 if (chp->ch_drive[i].drv_softc == NULL) 546 chp->ch_drive[i].drive_flags = 0; 547 else 548 chp->ch_drive[i].state = 0; 549 } 550 551 out: 552 if (atabus_initq == NULL) { 553 simple_lock(&atabus_interlock); 554 while(1) { 555 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 556 if (atabus_initq->atabus_sc == atabus_sc) 557 break; 558 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 559 &atabus_interlock); 560 } 561 simple_unlock(&atabus_interlock); 562 } 563 simple_lock(&atabus_interlock); 564 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 565 simple_unlock(&atabus_interlock); 566 567 free(atabus_initq, M_DEVBUF); 568 wakeup(&atabus_initq_head); 569 570 config_pending_decr(); 571 if (need_delref) 572 wdc_delref(chp); 573 } 574 575 576 int 577 wdprint(aux, pnp) 578 void *aux; 579 const char *pnp; 580 { 581 struct ata_device *adev = aux; 582 if (pnp) 583 aprint_normal("wd at %s", pnp); 584 aprint_normal(" drive %d", adev->adev_drv_data->drive); 585 return (UNCONF); 586 } 587 588 /* Test to see controller with at last one attached drive is there. 589 * Returns a bit for each possible drive found (0x01 for drive 0, 590 * 0x02 for drive 1). 591 * Logic: 592 * - If a status register is at 0xff, assume there is no drive here 593 * (ISA has pull-up resistors). Similarly if the status register has 594 * the value we last wrote to the bus (for IDE interfaces without pullups). 595 * If no drive at all -> return. 596 * - reset the controller, wait for it to complete (may take up to 31s !). 597 * If timeout -> return. 598 * - test ATA/ATAPI signatures. If at last one drive found -> return. 599 * - try an ATA command on the master. 600 */ 601 602 int 603 wdcprobe(chp) 604 struct channel_softc *chp; 605 { 606 return __wdcprobe(chp, 1); 607 } 608 609 int 610 __wdcprobe(chp, poll) 611 struct channel_softc *chp; 612 int poll; 613 { 614 u_int8_t st0, st1, sc, sn, cl, ch; 615 u_int8_t ret_value = 0x03; 616 u_int8_t drive; 617 int s; 618 619 /* 620 * Sanity check to see if the wdc channel responds at all. 621 */ 622 623 if (chp->wdc == NULL || 624 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 625 626 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 627 chp->wdc->select(chp,0); 628 629 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 630 WDSD_IBM); 631 delay(10); /* 400ns delay */ 632 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 633 634 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 635 chp->wdc->select(chp,1); 636 637 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 638 WDSD_IBM | 0x10); 639 delay(10); /* 400ns delay */ 640 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 641 642 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 643 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 644 chp->channel, st0, st1), DEBUG_PROBE); 645 646 if (st0 == 0xff || st0 == WDSD_IBM) 647 ret_value &= ~0x01; 648 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 649 ret_value &= ~0x02; 650 /* Register writability test, drive 0. */ 651 if (ret_value & 0x01) { 652 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 653 chp->wdc->select(chp,0); 654 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 655 WDSD_IBM); 656 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0x02); 657 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 658 wd_cyl_lo) != 0x02) 659 ret_value &= ~0x01; 660 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 661 0x01); 662 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 663 wd_cyl_lo) != 0x01) 664 ret_value &= ~0x01; 665 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 666 0x01); 667 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 668 wd_sector) != 0x01) 669 ret_value &= ~0x01; 670 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 671 0x02); 672 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 673 wd_sector) != 0x02) 674 ret_value &= ~0x01; 675 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 676 wd_cyl_lo) != 0x01) 677 ret_value &= ~0x01; 678 } 679 /* Register writability test, drive 1. */ 680 if (ret_value & 0x02) { 681 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 682 chp->wdc->select(chp,1); 683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 684 WDSD_IBM | 0x10); 685 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 686 0x02); 687 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 688 wd_cyl_lo) != 0x02) 689 ret_value &= ~0x02; 690 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 691 0x01); 692 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 693 wd_cyl_lo) != 0x01) 694 ret_value &= ~0x02; 695 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 696 0x01); 697 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 698 wd_sector) != 0x01) 699 ret_value &= ~0x02; 700 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, 701 0x02); 702 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 703 wd_sector) != 0x02) 704 ret_value &= ~0x02; 705 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 706 wd_cyl_lo) != 0x01) 707 ret_value &= ~0x02; 708 } 709 710 if (ret_value == 0) 711 return 0; 712 } 713 714 s = splbio(); 715 716 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 717 chp->wdc->select(chp,0); 718 /* assert SRST, wait for reset to complete */ 719 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 720 WDSD_IBM); 721 delay(10); /* 400ns delay */ 722 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 723 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 724 DELAY(2000); 725 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 726 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 727 delay(10); /* 400ns delay */ 728 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 729 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 730 chp->wdc->irqack(chp); 731 splx(s); 732 733 ret_value = __wdcwait_reset(chp, ret_value, poll); 734 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 735 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 736 ret_value), DEBUG_PROBE); 737 738 /* if reset failed, there's nothing here */ 739 if (ret_value == 0) 740 return 0; 741 742 /* 743 * Test presence of drives. First test register signatures looking for 744 * ATAPI devices. If it's not an ATAPI and reset said there may be 745 * something here assume it's ATA or OLD. Ghost will be killed later in 746 * attach routine. 747 */ 748 for (drive = 0; drive < 2; drive++) { 749 if ((ret_value & (0x01 << drive)) == 0) 750 continue; 751 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 752 chp->wdc->select(chp,drive); 753 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 754 WDSD_IBM | (drive << 4)); 755 delay(10); /* 400ns delay */ 756 /* Save registers contents */ 757 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 758 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 759 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 760 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 761 762 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 763 "cl=0x%x ch=0x%x\n", 764 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 765 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 766 /* 767 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 768 * we get wrong values here, so ignore it. 769 */ 770 if (cl == 0x14 && ch == 0xeb) { 771 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 772 } else { 773 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 774 if (chp->wdc == NULL || 775 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 776 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 777 } 778 } 779 return (ret_value); 780 } 781 782 void 783 wdcattach(chp) 784 struct channel_softc *chp; 785 { 786 static int inited = 0; 787 788 if (chp->ch_flags & WDCF_DISABLED) 789 return; 790 791 /* initialise global data */ 792 callout_init(&chp->ch_callout); 793 if (inited == 0) { 794 /* Initialize the wdc_xfer pool. */ 795 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 796 0, 0, "wdcspl", NULL); 797 inited++; 798 } 799 TAILQ_INIT(&chp->ch_queue->sc_xfer); 800 chp->ch_queue->queue_freeze = 0; 801 802 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 803 } 804 805 /* 806 * Call activate routine of underlying devices. 807 */ 808 int 809 atabusactivate(self, act) 810 struct device *self; 811 enum devact act; 812 { 813 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 814 struct channel_softc *chp = atabus_sc->sc_chan; 815 struct device *sc = 0; 816 int s, i, error = 0; 817 818 s = splbio(); 819 switch (act) { 820 case DVACT_ACTIVATE: 821 error = EOPNOTSUPP; 822 break; 823 824 case DVACT_DEACTIVATE: 825 /* 826 * We might call deactivate routine for 827 * the children of atapibus twice (once via 828 * atapibus, once directly), but since 829 * config_deactivate maintains DVF_ACTIVE flag, 830 * it's safe. 831 */ 832 sc = chp->atapibus; 833 if (sc != NULL) { 834 error = config_deactivate(sc); 835 if (error != 0) 836 goto out; 837 } 838 839 for (i = 0; i < 2; i++) { 840 sc = chp->ch_drive[i].drv_softc; 841 WDCDEBUG_PRINT(("atabusactivate: %s:" 842 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 843 sc == NULL ? "nodrv" : sc->dv_xname), 844 DEBUG_DETACH); 845 if (sc != NULL) { 846 error = config_deactivate(sc); 847 if (error != 0) 848 goto out; 849 } 850 } 851 break; 852 } 853 854 out: 855 splx(s); 856 857 #ifdef WDCDEBUG 858 if (sc && error != 0) 859 WDCDEBUG_PRINT(("atabusactivate: %s: " 860 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 861 error, sc->dv_xname), DEBUG_DETACH); 862 #endif 863 return (error); 864 } 865 866 int wdcactivate(self, act) 867 struct device *self; 868 enum devact act; 869 { 870 struct wdc_softc *wdc = (struct wdc_softc *)self; 871 int s, i, error = 0; 872 873 s = splbio(); 874 switch (act) { 875 case DVACT_ACTIVATE: 876 error = EOPNOTSUPP; 877 break; 878 879 case DVACT_DEACTIVATE: 880 for (i = 0; i < wdc->nchannels; i++) { 881 error = config_deactivate(wdc->channels[i]->atabus); 882 if (error) 883 break; 884 } 885 break; 886 } 887 splx(s); 888 return (error); 889 } 890 891 892 int 893 atabusdetach(self, flags) 894 struct device *self; 895 int flags; 896 { 897 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 898 struct channel_softc *chp = atabus_sc->sc_chan; 899 struct device *sc = 0; 900 int i, error = 0; 901 902 /* shutdown channel */ 903 chp->ch_flags |= WDCF_SHUTDOWN; 904 wakeup(&chp->thread); 905 while (chp->thread != NULL) 906 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 907 908 /* 909 * Detach atapibus and its children. 910 */ 911 sc = chp->atapibus; 912 if (sc != NULL) { 913 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 914 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 915 error = config_detach(sc, flags); 916 if (error != 0) 917 goto out; 918 } 919 920 /* 921 * Detach our other children. 922 */ 923 for (i = 0; i < 2; i++) { 924 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 925 continue; 926 sc = chp->ch_drive[i].drv_softc; 927 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 928 atabus_sc->sc_dev.dv_xname, 929 sc == NULL ? "nodrv" : sc->dv_xname), 930 DEBUG_DETACH); 931 if (sc != NULL) { 932 error = config_detach(sc, flags); 933 if (error != 0) 934 goto out; 935 } 936 } 937 938 wdc_kill_pending(chp); 939 940 out: 941 #ifdef WDCDEBUG 942 if (sc && error != 0) 943 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 944 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 945 DEBUG_DETACH); 946 #endif 947 return (error); 948 } 949 950 int 951 wdcdetach(self, flags) 952 struct device *self; 953 int flags; 954 { 955 struct wdc_softc *wdc = (struct wdc_softc *)self; 956 struct channel_softc *chp; 957 int i, error = 0; 958 959 for (i = 0; i < wdc->nchannels; i++) { 960 chp = wdc->channels[i]; 961 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 962 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 963 error = config_detach(chp->atabus, flags); 964 if (error) 965 break; 966 } 967 return (error); 968 } 969 970 /* 971 * Start I/O on a controller, for the given channel. 972 * The first xfer may be not for our channel if the channel queues 973 * are shared. 974 */ 975 void 976 wdcstart(chp) 977 struct channel_softc *chp; 978 { 979 struct wdc_xfer *xfer; 980 981 #ifdef WDC_DIAGNOSTIC 982 int spl1, spl2; 983 984 spl1 = splbio(); 985 spl2 = splbio(); 986 if (spl2 != spl1) { 987 printf("wdcstart: not at splbio()\n"); 988 panic("wdcstart"); 989 } 990 splx(spl2); 991 splx(spl1); 992 #endif /* WDC_DIAGNOSTIC */ 993 994 /* is there a xfer ? */ 995 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 996 return; 997 998 /* adjust chp, in case we have a shared queue */ 999 chp = xfer->chp; 1000 1001 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 1002 return; /* channel aleady active */ 1003 } 1004 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 1005 return; /* queue froozen */ 1006 } 1007 #ifdef DIAGNOSTIC 1008 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 1009 panic("wdcstart: channel waiting for irq"); 1010 #endif 1011 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 1012 if (!(*chp->wdc->claim_hw)(chp, 0)) 1013 return; 1014 1015 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1016 chp->channel, xfer->drive), DEBUG_XFERS); 1017 chp->ch_flags |= WDCF_ACTIVE; 1018 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1019 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1020 chp->ch_drive[xfer->drive].state = 0; 1021 } 1022 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1023 KASSERT(xfer->c_flags & C_POLL); 1024 xfer->c_start(chp, xfer); 1025 } 1026 1027 /* restart an interrupted I/O */ 1028 void 1029 wdcrestart(v) 1030 void *v; 1031 { 1032 struct channel_softc *chp = v; 1033 int s; 1034 1035 s = splbio(); 1036 wdcstart(chp); 1037 splx(s); 1038 } 1039 1040 1041 /* 1042 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1043 * errors on the current operation, mark it done if necessary, and start the 1044 * next request. Also check for a partially done transfer, and continue with 1045 * the next chunk if so. 1046 */ 1047 int 1048 wdcintr(arg) 1049 void *arg; 1050 { 1051 struct channel_softc *chp = arg; 1052 struct wdc_xfer *xfer; 1053 int ret; 1054 1055 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1056 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1057 DEBUG_INTR); 1058 return (0); 1059 } 1060 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1061 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1062 /* try to clear the pending interrupt anyway */ 1063 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1064 return (0); 1065 } 1066 1067 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1068 xfer = chp->ch_queue->sc_xfer.tqh_first; 1069 if (chp->ch_flags & WDCF_DMA_WAIT) { 1070 chp->wdc->dma_status = 1071 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1072 xfer->drive, 0); 1073 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1074 /* IRQ not for us, not detected by DMA engine */ 1075 return 0; 1076 } 1077 chp->ch_flags &= ~WDCF_DMA_WAIT; 1078 } 1079 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1080 ret = xfer->c_intr(chp, xfer, 1); 1081 if (ret == 0) /* irq was not for us, still waiting for irq */ 1082 chp->ch_flags |= WDCF_IRQ_WAIT; 1083 return (ret); 1084 } 1085 1086 /* Put all disk in RESET state */ 1087 void 1088 wdc_reset_channel(drvp, flags) 1089 struct ata_drive_datas *drvp; 1090 int flags; 1091 { 1092 struct channel_softc *chp = drvp->chnl_softc; 1093 int drive; 1094 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1095 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1096 DEBUG_FUNCS); 1097 if ((flags & AT_POLL) == 0) { 1098 if (chp->ch_flags & WDCF_TH_RESET) { 1099 /* no need to schedule a reset more than one time */ 1100 return; 1101 } 1102 chp->ch_flags |= WDCF_TH_RESET; 1103 chp->ch_queue->queue_freeze++; 1104 wakeup(&chp->thread); 1105 return; 1106 } 1107 (void) wdcreset(chp, RESET_POLL); 1108 for (drive = 0; drive < 2; drive++) { 1109 chp->ch_drive[drive].state = 0; 1110 } 1111 } 1112 1113 int 1114 wdcreset(chp, poll) 1115 struct channel_softc *chp; 1116 int poll; 1117 { 1118 int drv_mask1, drv_mask2; 1119 int s = 0; 1120 1121 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1122 chp->wdc->select(chp,0); 1123 if (poll != RESET_SLEEP) 1124 s = splbio(); 1125 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1126 WDSD_IBM); /* master */ 1127 delay(10); /* 400ns delay */ 1128 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1129 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1130 delay(2000); 1131 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 1132 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1133 WDCTL_4BIT | WDCTL_IDS); 1134 delay(10); /* 400ns delay */ 1135 if (poll != RESET_SLEEP) { 1136 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1137 chp->wdc->irqack(chp); 1138 splx(s); 1139 } 1140 1141 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1142 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1143 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1144 (poll == RESET_SLEEP) ? 0 : 1); 1145 if (drv_mask2 != drv_mask1) { 1146 printf("%s channel %d: reset failed for", 1147 chp->wdc->sc_dev.dv_xname, chp->channel); 1148 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1149 printf(" drive 0"); 1150 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1151 printf(" drive 1"); 1152 printf("\n"); 1153 } 1154 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1155 return (drv_mask1 != drv_mask2) ? 1 : 0; 1156 } 1157 1158 static int 1159 __wdcwait_reset(chp, drv_mask, poll) 1160 struct channel_softc *chp; 1161 int drv_mask; 1162 { 1163 int timeout, nloop; 1164 u_int8_t st0 = 0, st1 = 0; 1165 #ifdef WDCDEBUG 1166 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1167 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1168 #endif 1169 1170 if (poll) 1171 nloop = WDCNDELAY_RST; 1172 else 1173 nloop = WDC_RESET_WAIT * hz / 1000; 1174 /* wait for BSY to deassert */ 1175 for (timeout = 0; timeout < nloop; timeout++) { 1176 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1177 chp->wdc->select(chp,0); 1178 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1179 WDSD_IBM); /* master */ 1180 delay(10); 1181 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1182 #ifdef WDCDEBUG 1183 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1184 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1185 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1186 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1187 #endif 1188 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1189 chp->wdc->select(chp,1); 1190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1191 WDSD_IBM | 0x10); /* slave */ 1192 delay(10); 1193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1194 #ifdef WDCDEBUG 1195 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 1196 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 1197 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 1198 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 1199 #endif 1200 1201 if ((drv_mask & 0x01) == 0) { 1202 /* no master */ 1203 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1204 /* No master, slave is ready, it's done */ 1205 goto end; 1206 } 1207 } else if ((drv_mask & 0x02) == 0) { 1208 /* no slave */ 1209 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1210 /* No slave, master is ready, it's done */ 1211 goto end; 1212 } 1213 } else { 1214 /* Wait for both master and slave to be ready */ 1215 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1216 goto end; 1217 } 1218 } 1219 if (poll) 1220 delay(WDCDELAY); 1221 else 1222 tsleep(&nloop, PRIBIO, "atarst", 1); 1223 } 1224 /* Reset timed out. Maybe it's because drv_mask was not right */ 1225 if (st0 & WDCS_BSY) 1226 drv_mask &= ~0x01; 1227 if (st1 & WDCS_BSY) 1228 drv_mask &= ~0x02; 1229 end: 1230 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1231 "cl=0x%x ch=0x%x\n", 1232 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1233 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1234 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1235 "cl=0x%x ch=0x%x\n", 1236 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1237 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1238 1239 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1240 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1241 st0, st1), DEBUG_PROBE); 1242 1243 return drv_mask; 1244 } 1245 1246 /* 1247 * Wait for a drive to be !BSY, and have mask in its status register. 1248 * return -1 for a timeout after "timeout" ms. 1249 */ 1250 int 1251 __wdcwait(chp, mask, bits, timeout) 1252 struct channel_softc *chp; 1253 int mask, bits, timeout; 1254 { 1255 u_char status; 1256 int time = 0; 1257 1258 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1259 :"none", chp->channel), DEBUG_STATUS); 1260 chp->ch_error = 0; 1261 1262 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1263 1264 for (;;) { 1265 chp->ch_status = status = 1266 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 1267 if ((status & (WDCS_BSY | mask)) == bits) 1268 break; 1269 if (++time > timeout) { 1270 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1271 "status %x error %x (mask 0x%x bits 0x%x)\n", 1272 time, status, 1273 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1274 wd_error), mask, bits), 1275 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1276 return(WDCWAIT_TOUT); 1277 } 1278 delay(WDCDELAY); 1279 } 1280 #ifdef WDCDEBUG 1281 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1282 printf("__wdcwait: did busy-wait, time=%d\n", time); 1283 #endif 1284 if (status & WDCS_ERR) 1285 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1286 wd_error); 1287 #ifdef WDCNDELAY_DEBUG 1288 /* After autoconfig, there should be no long delays. */ 1289 if (!cold && time > WDCNDELAY_DEBUG) { 1290 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1291 if (xfer == NULL) 1292 printf("%s channel %d: warning: busy-wait took %dus\n", 1293 chp->wdc->sc_dev.dv_xname, chp->channel, 1294 WDCDELAY * time); 1295 else 1296 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1297 chp->wdc->sc_dev.dv_xname, chp->channel, 1298 xfer->drive, 1299 WDCDELAY * time); 1300 } 1301 #endif 1302 return(WDCWAIT_OK); 1303 } 1304 1305 /* 1306 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1307 * thread if possible 1308 */ 1309 int 1310 wdcwait(chp, mask, bits, timeout, flags) 1311 struct channel_softc *chp; 1312 int mask, bits, timeout, flags; 1313 { 1314 int error, i, timeout_hz = mstohz(timeout); 1315 1316 if (timeout_hz == 0 || 1317 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1318 error = __wdcwait(chp, mask, bits, timeout); 1319 else { 1320 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1321 if (error != 0) { 1322 if ((chp->ch_flags & WDCF_TH_RUN) || 1323 (flags & AT_WAIT)) { 1324 /* 1325 * we're running in the channel thread 1326 * or some userland thread context 1327 */ 1328 for (i = 0; i < timeout_hz; i++) { 1329 if (__wdcwait(chp, mask, bits, 1330 WDCDELAY_POLL) == 0) { 1331 error = 0; 1332 break; 1333 } 1334 tsleep(&chp, PRIBIO, "atapoll", 1); 1335 } 1336 } else { 1337 /* 1338 * we're probably in interrupt context, 1339 * ask the thread to come back here 1340 */ 1341 #ifdef DIAGNOSTIC 1342 if (chp->ch_queue->queue_freeze > 0) 1343 panic("wdcwait: queue_freeze"); 1344 #endif 1345 chp->ch_queue->queue_freeze++; 1346 wakeup(&chp->thread); 1347 return(WDCWAIT_THR); 1348 } 1349 } 1350 } 1351 return(error); 1352 } 1353 1354 1355 /* 1356 * Busy-wait for DMA to complete 1357 */ 1358 int 1359 wdc_dmawait(chp, xfer, timeout) 1360 struct channel_softc *chp; 1361 struct wdc_xfer *xfer; 1362 int timeout; 1363 { 1364 int time; 1365 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1366 chp->wdc->dma_status = 1367 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1368 chp->channel, xfer->drive, 0); 1369 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1370 return 0; 1371 delay(WDCDELAY); 1372 } 1373 /* timeout, force a DMA halt */ 1374 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1375 chp->channel, xfer->drive, 1); 1376 return 1; 1377 } 1378 1379 void 1380 wdctimeout(arg) 1381 void *arg; 1382 { 1383 struct channel_softc *chp = (struct channel_softc *)arg; 1384 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1385 int s; 1386 1387 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1388 1389 s = splbio(); 1390 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1391 __wdcerror(chp, "lost interrupt"); 1392 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1393 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1394 xfer->c_bcount, 1395 xfer->c_skip); 1396 if (chp->ch_flags & WDCF_DMA_WAIT) { 1397 chp->wdc->dma_status = 1398 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1399 chp->channel, xfer->drive, 1); 1400 chp->ch_flags &= ~WDCF_DMA_WAIT; 1401 } 1402 /* 1403 * Call the interrupt routine. If we just missed an interrupt, 1404 * it will do what's needed. Else, it will take the needed 1405 * action (reset the device). 1406 * Before that we need to reinstall the timeout callback, 1407 * in case it will miss another irq while in this transfer 1408 * We arbitray chose it to be 1s 1409 */ 1410 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1411 xfer->c_flags |= C_TIMEOU; 1412 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1413 xfer->c_intr(chp, xfer, 1); 1414 } else 1415 __wdcerror(chp, "missing untimeout"); 1416 splx(s); 1417 } 1418 1419 /* 1420 * Probe drive's capabilities, for use by the controller later 1421 * Assumes drvp points to an existing drive. 1422 * XXX this should be a controller-indep function 1423 */ 1424 void 1425 wdc_probe_caps(drvp) 1426 struct ata_drive_datas *drvp; 1427 { 1428 struct ataparams params, params2; 1429 struct channel_softc *chp = drvp->chnl_softc; 1430 struct device *drv_dev = drvp->drv_softc; 1431 struct wdc_softc *wdc = chp->wdc; 1432 int i, printed; 1433 char *sep = ""; 1434 int cf_flags; 1435 1436 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1437 /* IDENTIFY failed. Can't tell more about the device */ 1438 return; 1439 } 1440 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1441 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1442 /* 1443 * Controller claims 16 and 32 bit transfers. 1444 * Re-do an IDENTIFY with 32-bit transfers, 1445 * and compare results. 1446 */ 1447 drvp->drive_flags |= DRIVE_CAP32; 1448 ata_get_params(drvp, AT_WAIT, ¶ms2); 1449 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1450 /* Not good. fall back to 16bits */ 1451 drvp->drive_flags &= ~DRIVE_CAP32; 1452 } else { 1453 aprint_normal("%s: 32-bit data port\n", 1454 drv_dev->dv_xname); 1455 } 1456 } 1457 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1458 if (params.atap_ata_major > 0x01 && 1459 params.atap_ata_major != 0xffff) { 1460 for (i = 14; i > 0; i--) { 1461 if (params.atap_ata_major & (1 << i)) { 1462 aprint_normal("%s: ATA version %d\n", 1463 drv_dev->dv_xname, i); 1464 drvp->ata_vers = i; 1465 break; 1466 } 1467 } 1468 } 1469 #endif 1470 1471 /* An ATAPI device is at last PIO mode 3 */ 1472 if (drvp->drive_flags & DRIVE_ATAPI) 1473 drvp->PIO_mode = 3; 1474 1475 /* 1476 * It's not in the specs, but it seems that some drive 1477 * returns 0xffff in atap_extensions when this field is invalid 1478 */ 1479 if (params.atap_extensions != 0xffff && 1480 (params.atap_extensions & WDC_EXT_MODES)) { 1481 printed = 0; 1482 /* 1483 * XXX some drives report something wrong here (they claim to 1484 * support PIO mode 8 !). As mode is coded on 3 bits in 1485 * SET FEATURE, limit it to 7 (so limit i to 4). 1486 * If higher mode than 7 is found, abort. 1487 */ 1488 for (i = 7; i >= 0; i--) { 1489 if ((params.atap_piomode_supp & (1 << i)) == 0) 1490 continue; 1491 if (i > 4) 1492 return; 1493 /* 1494 * See if mode is accepted. 1495 * If the controller can't set its PIO mode, 1496 * assume the defaults are good, so don't try 1497 * to set it 1498 */ 1499 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1500 /* 1501 * It's OK to pool here, it's fast enouth 1502 * to not bother waiting for interrupt 1503 */ 1504 if (ata_set_mode(drvp, 0x08 | (i + 3), 1505 AT_WAIT) != CMD_OK) 1506 continue; 1507 if (!printed) { 1508 aprint_normal("%s: drive supports PIO mode %d", 1509 drv_dev->dv_xname, i + 3); 1510 sep = ","; 1511 printed = 1; 1512 } 1513 /* 1514 * If controller's driver can't set its PIO mode, 1515 * get the highter one for the drive. 1516 */ 1517 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1518 wdc->PIO_cap >= i + 3) { 1519 drvp->PIO_mode = i + 3; 1520 drvp->PIO_cap = i + 3; 1521 break; 1522 } 1523 } 1524 if (!printed) { 1525 /* 1526 * We didn't find a valid PIO mode. 1527 * Assume the values returned for DMA are buggy too 1528 */ 1529 return; 1530 } 1531 drvp->drive_flags |= DRIVE_MODE; 1532 printed = 0; 1533 for (i = 7; i >= 0; i--) { 1534 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1535 continue; 1536 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1537 (wdc->cap & WDC_CAPABILITY_MODE)) 1538 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1539 != CMD_OK) 1540 continue; 1541 if (!printed) { 1542 aprint_normal("%s DMA mode %d", sep, i); 1543 sep = ","; 1544 printed = 1; 1545 } 1546 if (wdc->cap & WDC_CAPABILITY_DMA) { 1547 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1548 wdc->DMA_cap < i) 1549 continue; 1550 drvp->DMA_mode = i; 1551 drvp->DMA_cap = i; 1552 drvp->drive_flags |= DRIVE_DMA; 1553 } 1554 break; 1555 } 1556 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1557 printed = 0; 1558 for (i = 7; i >= 0; i--) { 1559 if ((params.atap_udmamode_supp & (1 << i)) 1560 == 0) 1561 continue; 1562 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1563 (wdc->cap & WDC_CAPABILITY_UDMA)) 1564 if (ata_set_mode(drvp, 0x40 | i, 1565 AT_WAIT) != CMD_OK) 1566 continue; 1567 if (!printed) { 1568 aprint_normal("%s Ultra-DMA mode %d", 1569 sep, i); 1570 if (i == 2) 1571 aprint_normal(" (Ultra/33)"); 1572 else if (i == 4) 1573 aprint_normal(" (Ultra/66)"); 1574 else if (i == 5) 1575 aprint_normal(" (Ultra/100)"); 1576 else if (i == 6) 1577 aprint_normal(" (Ultra/133)"); 1578 sep = ","; 1579 printed = 1; 1580 } 1581 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1582 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1583 wdc->UDMA_cap < i) 1584 continue; 1585 drvp->UDMA_mode = i; 1586 drvp->UDMA_cap = i; 1587 drvp->drive_flags |= DRIVE_UDMA; 1588 } 1589 break; 1590 } 1591 } 1592 aprint_normal("\n"); 1593 } 1594 1595 /* Try to guess ATA version here, if it didn't get reported */ 1596 if (drvp->ata_vers == 0) { 1597 if (drvp->drive_flags & DRIVE_UDMA) 1598 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1599 else if (drvp->PIO_cap > 2) 1600 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1601 } 1602 cf_flags = drv_dev->dv_cfdata->cf_flags; 1603 if (cf_flags & ATA_CONFIG_PIO_SET) { 1604 drvp->PIO_mode = 1605 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1606 drvp->drive_flags |= DRIVE_MODE; 1607 } 1608 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1609 /* don't care about DMA modes */ 1610 return; 1611 } 1612 if (cf_flags & ATA_CONFIG_DMA_SET) { 1613 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1614 ATA_CONFIG_DMA_DISABLE) { 1615 drvp->drive_flags &= ~DRIVE_DMA; 1616 } else { 1617 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1618 ATA_CONFIG_DMA_OFF; 1619 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1620 } 1621 } 1622 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1623 /* don't care about UDMA modes */ 1624 return; 1625 } 1626 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1627 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1628 ATA_CONFIG_UDMA_DISABLE) { 1629 drvp->drive_flags &= ~DRIVE_UDMA; 1630 } else { 1631 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1632 ATA_CONFIG_UDMA_OFF; 1633 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1634 } 1635 } 1636 } 1637 1638 /* 1639 * downgrade the transfer mode of a drive after an error. return 1 if 1640 * downgrade was possible, 0 otherwise. 1641 */ 1642 int 1643 wdc_downgrade_mode(drvp, flags) 1644 struct ata_drive_datas *drvp; 1645 { 1646 struct channel_softc *chp = drvp->chnl_softc; 1647 struct device *drv_dev = drvp->drv_softc; 1648 struct wdc_softc *wdc = chp->wdc; 1649 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1650 1651 /* if drive or controller don't know its mode, we can't do much */ 1652 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1653 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1654 return 0; 1655 /* current drive mode was set by a config flag, let it this way */ 1656 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1657 (cf_flags & ATA_CONFIG_DMA_SET) || 1658 (cf_flags & ATA_CONFIG_UDMA_SET)) 1659 return 0; 1660 1661 /* 1662 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1663 * Maybe we didn't properly notice the cable type 1664 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1665 * It helps in some cases. 1666 */ 1667 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1668 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1669 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1670 drv_dev->dv_xname, drvp->UDMA_mode); 1671 } 1672 1673 /* 1674 * If we were using ultra-DMA, don't downgrade to multiword DMA 1675 * if we noticed a CRC error. It has been noticed that CRC errors 1676 * in ultra-DMA lead to silent data corruption in multiword DMA. 1677 * Data corruption is less likely to occur in PIO mode. 1678 */ 1679 else if ((drvp->drive_flags & DRIVE_UDMA) && 1680 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1681 drvp->drive_flags &= ~DRIVE_UDMA; 1682 drvp->drive_flags |= DRIVE_DMA; 1683 drvp->DMA_mode = drvp->DMA_cap; 1684 printf("%s: transfer error, downgrading to DMA mode %d\n", 1685 drv_dev->dv_xname, drvp->DMA_mode); 1686 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1687 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1688 drvp->PIO_mode = drvp->PIO_cap; 1689 printf("%s: transfer error, downgrading to PIO mode %d\n", 1690 drv_dev->dv_xname, drvp->PIO_mode); 1691 } else /* already using PIO, can't downgrade */ 1692 return 0; 1693 1694 wdc->set_modes(chp); 1695 wdc_print_modes(chp); 1696 /* reset the channel, which will shedule all drives for setup */ 1697 wdc_reset_channel(drvp, flags); 1698 return 1; 1699 } 1700 1701 int 1702 wdc_exec_command(drvp, wdc_c) 1703 struct ata_drive_datas *drvp; 1704 struct wdc_command *wdc_c; 1705 { 1706 struct channel_softc *chp = drvp->chnl_softc; 1707 struct wdc_xfer *xfer; 1708 int s, ret; 1709 1710 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1711 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1712 DEBUG_FUNCS); 1713 1714 /* set up an xfer and queue. Wait for completion */ 1715 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1716 WDC_NOSLEEP); 1717 if (xfer == NULL) { 1718 return WDC_TRY_AGAIN; 1719 } 1720 1721 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1722 wdc_c->flags |= AT_POLL; 1723 if (wdc_c->flags & AT_POLL) 1724 xfer->c_flags |= C_POLL; 1725 xfer->drive = drvp->drive; 1726 xfer->databuf = wdc_c->data; 1727 xfer->c_bcount = wdc_c->bcount; 1728 xfer->cmd = wdc_c; 1729 xfer->c_start = __wdccommand_start; 1730 xfer->c_intr = __wdccommand_intr; 1731 xfer->c_kill_xfer = __wdccommand_done; 1732 1733 s = splbio(); 1734 wdc_exec_xfer(chp, xfer); 1735 #ifdef DIAGNOSTIC 1736 if ((wdc_c->flags & AT_POLL) != 0 && 1737 (wdc_c->flags & AT_DONE) == 0) 1738 panic("wdc_exec_command: polled command not done"); 1739 #endif 1740 if (wdc_c->flags & AT_DONE) { 1741 ret = WDC_COMPLETE; 1742 } else { 1743 if (wdc_c->flags & AT_WAIT) { 1744 while ((wdc_c->flags & AT_DONE) == 0) { 1745 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1746 } 1747 ret = WDC_COMPLETE; 1748 } else { 1749 ret = WDC_QUEUED; 1750 } 1751 } 1752 splx(s); 1753 return ret; 1754 } 1755 1756 void 1757 __wdccommand_start(chp, xfer) 1758 struct channel_softc *chp; 1759 struct wdc_xfer *xfer; 1760 { 1761 int drive = xfer->drive; 1762 struct wdc_command *wdc_c = xfer->cmd; 1763 1764 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1765 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1766 DEBUG_FUNCS); 1767 1768 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1769 chp->wdc->select(chp,drive); 1770 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1771 WDSD_IBM | (drive << 4)); 1772 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1773 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1774 case WDCWAIT_OK: 1775 break; 1776 case WDCWAIT_TOUT: 1777 wdc_c->flags |= AT_TIMEOU; 1778 __wdccommand_done(chp, xfer); 1779 return; 1780 case WDCWAIT_THR: 1781 return; 1782 } 1783 if (wdc_c->flags & AT_POLL) { 1784 /* polled command, disable interrupts */ 1785 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1786 WDCTL_4BIT | WDCTL_IDS); 1787 } 1788 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1789 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1790 1791 if ((wdc_c->flags & AT_POLL) == 0) { 1792 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1793 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1794 wdctimeout, chp); 1795 return; 1796 } 1797 /* 1798 * Polled command. Wait for drive ready or drq. Done in intr(). 1799 * Wait for at last 400ns for status bit to be valid. 1800 */ 1801 delay(10); /* 400ns delay */ 1802 __wdccommand_intr(chp, xfer, 0); 1803 } 1804 1805 int 1806 __wdccommand_intr(chp, xfer, irq) 1807 struct channel_softc *chp; 1808 struct wdc_xfer *xfer; 1809 int irq; 1810 { 1811 struct wdc_command *wdc_c = xfer->cmd; 1812 int bcount = wdc_c->bcount; 1813 char *data = wdc_c->data; 1814 int wflags; 1815 1816 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1817 /* both wait and poll, we can tsleep here */ 1818 wflags = AT_WAIT | AT_POLL; 1819 } else { 1820 wflags = AT_POLL; 1821 } 1822 1823 again: 1824 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1825 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1826 /* 1827 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1828 * Reselect again, it doesn't hurt for others commands, and the time 1829 * penalty for the extra regiter write is acceptable, 1830 * wdc_exec_command() isn't called often (mosly for autoconfig) 1831 */ 1832 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1833 WDSD_IBM | (xfer->drive << 4)); 1834 if ((wdc_c->flags & AT_XFDONE) != 0) { 1835 /* 1836 * We have completed a data xfer. The drive should now be 1837 * in its initial state 1838 */ 1839 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1840 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1841 wflags) == WDCWAIT_TOUT) { 1842 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1843 return 0; /* IRQ was not for us */ 1844 wdc_c->flags |= AT_TIMEOU; 1845 } 1846 goto out; 1847 } 1848 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1849 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1850 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1851 return 0; /* IRQ was not for us */ 1852 wdc_c->flags |= AT_TIMEOU; 1853 goto out; 1854 } 1855 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1856 chp->wdc->irqack(chp); 1857 if (wdc_c->flags & AT_READ) { 1858 if ((chp->ch_status & WDCS_DRQ) == 0) { 1859 wdc_c->flags |= AT_TIMEOU; 1860 goto out; 1861 } 1862 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1863 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1864 0, (u_int32_t*)data, bcount >> 2); 1865 data += bcount & 0xfffffffc; 1866 bcount = bcount & 0x03; 1867 } 1868 if (bcount > 0) 1869 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1870 wd_data, (u_int16_t *)data, bcount >> 1); 1871 /* at this point the drive should be in its initial state */ 1872 wdc_c->flags |= AT_XFDONE; 1873 /* XXX should read status register here ? */ 1874 } else if (wdc_c->flags & AT_WRITE) { 1875 if ((chp->ch_status & WDCS_DRQ) == 0) { 1876 wdc_c->flags |= AT_TIMEOU; 1877 goto out; 1878 } 1879 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1880 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1881 0, (u_int32_t*)data, bcount >> 2); 1882 data += bcount & 0xfffffffc; 1883 bcount = bcount & 0x03; 1884 } 1885 if (bcount > 0) 1886 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1887 wd_data, (u_int16_t *)data, bcount >> 1); 1888 wdc_c->flags |= AT_XFDONE; 1889 if ((wdc_c->flags & AT_POLL) == 0) { 1890 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1891 callout_reset(&chp->ch_callout, 1892 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1893 return 1; 1894 } else { 1895 goto again; 1896 } 1897 } 1898 out: 1899 __wdccommand_done(chp, xfer); 1900 return 1; 1901 } 1902 1903 void 1904 __wdccommand_done(chp, xfer) 1905 struct channel_softc *chp; 1906 struct wdc_xfer *xfer; 1907 { 1908 struct wdc_command *wdc_c = xfer->cmd; 1909 1910 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1911 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1912 1913 callout_stop(&chp->ch_callout); 1914 1915 if (chp->ch_status & WDCS_DWF) 1916 wdc_c->flags |= AT_DF; 1917 if (chp->ch_status & WDCS_ERR) { 1918 wdc_c->flags |= AT_ERROR; 1919 wdc_c->r_error = chp->ch_error; 1920 } 1921 wdc_c->flags |= AT_DONE; 1922 if ((wdc_c->flags & AT_READREG) != 0 && 1923 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1924 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1925 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1926 wd_sdh); 1927 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1928 wd_cyl_hi) << 8; 1929 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1930 wd_cyl_lo); 1931 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1932 wd_sector); 1933 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1934 wd_seccnt); 1935 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1936 wd_error); 1937 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1938 wd_precomp); 1939 } 1940 1941 if (wdc_c->flags & AT_POLL) { 1942 /* enable interrupts */ 1943 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1944 WDCTL_4BIT); 1945 } 1946 wdc_free_xfer(chp, xfer); 1947 if (wdc_c->flags & AT_WAIT) 1948 wakeup(wdc_c); 1949 else if (wdc_c->callback) 1950 wdc_c->callback(wdc_c->callback_arg); 1951 wdcstart(chp); 1952 return; 1953 } 1954 1955 /* 1956 * Send a command. The drive should be ready. 1957 * Assumes interrupts are blocked. 1958 */ 1959 void 1960 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1961 struct channel_softc *chp; 1962 u_int8_t drive; 1963 u_int8_t command; 1964 u_int16_t cylin; 1965 u_int8_t head, sector, count, precomp; 1966 { 1967 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1968 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1969 chp->channel, drive, command, cylin, head, sector, count, precomp), 1970 DEBUG_FUNCS); 1971 1972 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1973 chp->wdc->select(chp,drive); 1974 1975 /* Select drive, head, and addressing mode. */ 1976 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1977 WDSD_IBM | (drive << 4) | head); 1978 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1979 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1980 precomp); 1981 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1982 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1983 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1984 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1985 1986 /* Send command. */ 1987 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1988 return; 1989 } 1990 1991 /* 1992 * Send a 48-bit addressing command. The drive should be ready. 1993 * Assumes interrupts are blocked. 1994 */ 1995 void 1996 wdccommandext(chp, drive, command, blkno, count) 1997 struct channel_softc *chp; 1998 u_int8_t drive; 1999 u_int8_t command; 2000 u_int64_t blkno; 2001 u_int16_t count; 2002 { 2003 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2004 "count=%d\n", chp->wdc->sc_dev.dv_xname, 2005 chp->channel, drive, command, (u_int32_t) blkno, count), 2006 DEBUG_FUNCS); 2007 2008 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2009 chp->wdc->select(chp,drive); 2010 2011 /* Select drive, head, and addressing mode. */ 2012 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2013 (drive << 4) | WDSD_LBA); 2014 2015 /* previous */ 2016 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 2017 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count >> 8); 2018 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 40); 2019 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 32); 2020 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno >> 24); 2021 2022 /* current */ 2023 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_features, 0); 2024 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 2025 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_hi, blkno >> 16); 2026 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_mi, blkno >> 8); 2027 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_lba_lo, blkno); 2028 2029 /* Send command. */ 2030 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2031 return; 2032 } 2033 2034 /* 2035 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2036 * tested by the caller. 2037 */ 2038 void 2039 wdccommandshort(chp, drive, command) 2040 struct channel_softc *chp; 2041 int drive; 2042 int command; 2043 { 2044 2045 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2046 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2047 DEBUG_FUNCS); 2048 2049 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2050 chp->wdc->select(chp,drive); 2051 2052 /* Select drive. */ 2053 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 2054 WDSD_IBM | (drive << 4)); 2055 2056 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 2057 } 2058 2059 /* Add a command to the queue and start controller. Must be called at splbio */ 2060 2061 void 2062 wdc_exec_xfer(chp, xfer) 2063 struct channel_softc *chp; 2064 struct wdc_xfer *xfer; 2065 { 2066 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2067 chp->channel, xfer->drive), DEBUG_XFERS); 2068 2069 /* complete xfer setup */ 2070 xfer->chp = chp; 2071 2072 /* 2073 * If we are a polled command, and the list is not empty, 2074 * we are doing a dump. Drop the list to allow the polled command 2075 * to complete, we're going to reboot soon anyway. 2076 */ 2077 if ((xfer->c_flags & C_POLL) != 0 && 2078 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2079 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2080 } 2081 /* insert at the end of command list */ 2082 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2083 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2084 chp->ch_flags), DEBUG_XFERS); 2085 wdcstart(chp); 2086 } 2087 2088 struct wdc_xfer * 2089 wdc_get_xfer(flags) 2090 int flags; 2091 { 2092 struct wdc_xfer *xfer; 2093 int s; 2094 2095 s = splbio(); 2096 xfer = pool_get(&wdc_xfer_pool, 2097 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2098 splx(s); 2099 if (xfer != NULL) { 2100 memset(xfer, 0, sizeof(struct wdc_xfer)); 2101 } 2102 return xfer; 2103 } 2104 2105 void 2106 wdc_free_xfer(chp, xfer) 2107 struct channel_softc *chp; 2108 struct wdc_xfer *xfer; 2109 { 2110 struct wdc_softc *wdc = chp->wdc; 2111 int s; 2112 2113 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2114 (*wdc->free_hw)(chp); 2115 s = splbio(); 2116 chp->ch_flags &= ~WDCF_ACTIVE; 2117 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2118 pool_put(&wdc_xfer_pool, xfer); 2119 splx(s); 2120 } 2121 2122 /* 2123 * Kill off all pending xfers for a channel_softc. 2124 * 2125 * Must be called at splbio(). 2126 */ 2127 void 2128 wdc_kill_pending(chp) 2129 struct channel_softc *chp; 2130 { 2131 struct wdc_xfer *xfer; 2132 2133 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2134 chp = xfer->chp; 2135 (*xfer->c_kill_xfer)(chp, xfer); 2136 } 2137 } 2138 2139 static void 2140 __wdcerror(chp, msg) 2141 struct channel_softc *chp; 2142 char *msg; 2143 { 2144 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2145 2146 if (xfer == NULL) 2147 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2148 msg); 2149 else 2150 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2151 chp->channel, xfer->drive, msg); 2152 } 2153 2154 /* 2155 * the bit bucket 2156 */ 2157 void 2158 wdcbit_bucket(chp, size) 2159 struct channel_softc *chp; 2160 int size; 2161 { 2162 2163 for (; size >= 2; size -= 2) 2164 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 2165 if (size) 2166 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 2167 } 2168 2169 int 2170 wdc_addref(chp) 2171 struct channel_softc *chp; 2172 { 2173 struct wdc_softc *wdc = chp->wdc; 2174 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2175 int s, error = 0; 2176 2177 s = splbio(); 2178 if (adapt->adapt_refcnt++ == 0 && 2179 adapt->adapt_enable != NULL) { 2180 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2181 if (error) 2182 adapt->adapt_refcnt--; 2183 } 2184 splx(s); 2185 return (error); 2186 } 2187 2188 void 2189 wdc_delref(chp) 2190 struct channel_softc *chp; 2191 { 2192 struct wdc_softc *wdc = chp->wdc; 2193 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2194 int s; 2195 2196 s = splbio(); 2197 if (adapt->adapt_refcnt-- == 1 && 2198 adapt->adapt_enable != NULL) 2199 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2200 splx(s); 2201 } 2202 2203 void 2204 wdc_print_modes(struct channel_softc *chp) 2205 { 2206 int drive; 2207 struct ata_drive_datas *drvp; 2208 2209 for (drive = 0; drive < 2; drive++) { 2210 drvp = &chp->ch_drive[drive]; 2211 if ((drvp->drive_flags & DRIVE) == 0) 2212 continue; 2213 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2214 drvp->drv_softc->dv_xname, 2215 chp->wdc->sc_dev.dv_xname, 2216 chp->channel, drive, drvp->PIO_mode); 2217 if (drvp->drive_flags & DRIVE_DMA) 2218 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2219 if (drvp->drive_flags & DRIVE_UDMA) { 2220 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2221 if (drvp->UDMA_mode == 2) 2222 aprint_normal(" (Ultra/33)"); 2223 else if (drvp->UDMA_mode == 4) 2224 aprint_normal(" (Ultra/66)"); 2225 else if (drvp->UDMA_mode == 5) 2226 aprint_normal(" (Ultra/100)"); 2227 else if (drvp->UDMA_mode == 6) 2228 aprint_normal(" (Ultra/133)"); 2229 } 2230 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2231 aprint_normal(" (using DMA data transfers)"); 2232 aprint_normal("\n"); 2233 } 2234 } 2235
Indexes created Fri Sep 26 08:10:20 GMT 2025