wdc.c revision 1.157
1 /* $NetBSD: wdc.c,v 1.157 2003/11/27 23:02:40 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.157 2003/11/27 23:02:40 fvdl Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/wdvar.h> 103 #include <dev/ata/atareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include "locators.h" 108 109 #include "ataraid.h" 110 #include "atapibus.h" 111 #include "wd.h" 112 113 #if NATARAID > 0 114 #include <dev/ata/ata_raidvar.h> 115 #endif 116 117 #define WDCDELAY 100 /* 100 microseconds */ 118 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 119 #if 0 120 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 121 #define WDCNDELAY_DEBUG 50 122 #endif 123 124 /* When polling wait that much and then tsleep for 1/hz seconds */ 125 #define WDCDELAY_POLL 1 /* ms */ 126 127 /* timeout for the control commands */ 128 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 129 130 struct pool wdc_xfer_pool; 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL, 144 NULL 145 }; 146 #endif 147 148 int atabusmatch __P((struct device *, struct cfdata *, void *)); 149 void atabusattach __P((struct device *, struct device *, void *)); 150 void atabus_create_thread __P((void *)); 151 void atabus_thread __P((void *)); 152 void atabusconfig __P((struct atabus_softc *)); 153 int atabusactivate __P((struct device *, enum devact)); 154 int atabusdetach __P((struct device *, int flags)); 155 int atabusprint __P((void *, const char *)); 156 157 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 158 atabusmatch, atabusattach, atabusdetach, atabusactivate); 159 160 struct atabus_initq { 161 struct atabus_softc *atabus_sc; 162 TAILQ_ENTRY(atabus_initq) atabus_initq; 163 }; 164 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 165 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 166 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 167 168 int __wdcprobe __P((struct channel_softc*, int)); 169 static void __wdcerror __P((struct channel_softc*, char *)); 170 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 171 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 172 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 173 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 174 int __wdcwait __P((struct channel_softc *, int, int, int)); 175 int wdprint __P((void *, const char *)); 176 void wdc_finish_attach __P((struct device *)); 177 void wdc_channel_attach __P((struct channel_softc *)); 178 179 #define DEBUG_INTR 0x01 180 #define DEBUG_XFERS 0x02 181 #define DEBUG_STATUS 0x04 182 #define DEBUG_FUNCS 0x08 183 #define DEBUG_PROBE 0x10 184 #define DEBUG_DETACH 0x20 185 #define DEBUG_DELAY 0x40 186 #ifdef WDCDEBUG 187 int wdcdebug_mask = 0; 188 int wdc_nxfer = 0; 189 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 190 #else 191 #define WDCDEBUG_PRINT(args, level) 192 #endif 193 194 int 195 atabusprint(aux, pnp) 196 void *aux; 197 const char *pnp; 198 { 199 struct channel_softc *chan = aux; 200 if (pnp) 201 aprint_normal("atabus at %s", pnp); 202 aprint_normal(" channel %d", chan->channel); 203 return (UNCONF); 204 } 205 206 int 207 atabusmatch(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct channel_softc *chp = aux; 213 214 if (chp == NULL) 215 return (0); 216 217 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 218 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 219 return (0); 220 221 return (1); 222 } 223 224 void 225 atabusattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 230 struct channel_softc *chp = aux; 231 struct atabus_initq *atabus_initq; 232 233 atabus_sc->sc_chan = chp; 234 235 aprint_normal("\n"); 236 aprint_naive("\n"); 237 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 238 atabus_initq->atabus_sc = atabus_sc; 239 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 240 config_pending_incr(); 241 kthread_create(atabus_create_thread, atabus_sc); 242 243 } 244 245 void 246 atabus_create_thread(arg) 247 void *arg; 248 { 249 struct atabus_softc *atabus_sc = arg; 250 struct channel_softc *chp = atabus_sc->sc_chan; 251 int error; 252 253 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 254 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 255 printf("unable to create kernel thread for %s: error %d\n", 256 atabus_sc->sc_dev.dv_xname, error); 257 } 258 259 void 260 atabus_thread(arg) 261 void *arg; 262 { 263 struct atabus_softc *atabus_sc = arg; 264 struct channel_softc *chp = atabus_sc->sc_chan; 265 struct wdc_xfer *xfer; 266 int s; 267 268 s = splbio(); 269 chp->ch_flags |= WDCF_TH_RUN; 270 splx(s); 271 atabusconfig(atabus_sc); 272 for(;;) { 273 s = splbio(); 274 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 275 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 276 chp->ch_queue->queue_freeze == 0)) { 277 chp->ch_flags &= ~WDCF_TH_RUN; 278 tsleep(&chp->thread, PRIBIO, "atath", 0); 279 chp->ch_flags |= WDCF_TH_RUN; 280 } 281 splx(s); 282 if (chp->ch_flags & WDCF_SHUTDOWN) 283 break; 284 s = splbio(); 285 if (chp->ch_flags & WDCF_TH_RESET) { 286 int drive; 287 (void) wdcreset(chp, RESET_SLEEP); 288 for (drive = 0; drive < 2; drive++) { 289 chp->ch_drive[drive].state = 0; 290 } 291 chp->ch_flags &= ~WDCF_TH_RESET; 292 chp->ch_queue->queue_freeze--; 293 wdcstart(chp); 294 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 295 chp->ch_queue->queue_freeze == 1) { 296 /* 297 * caller has bumped queue_freeze, decrease it 298 */ 299 chp->ch_queue->queue_freeze--; 300 xfer = chp->ch_queue->sc_xfer.tqh_first; 301 #ifdef DIAGNOSTIC 302 if (xfer == NULL) 303 panic("channel active with no xfer ?"); 304 #endif 305 xfer->c_start(chp, xfer); 306 } else if (chp->ch_queue->queue_freeze > 1) { 307 panic("queue_freeze"); 308 } 309 splx(s); 310 } 311 chp->thread = NULL; 312 wakeup(&chp->ch_flags); 313 kthread_exit(0); 314 } 315 316 void 317 atabusconfig(atabus_sc) 318 struct atabus_softc *atabus_sc; 319 { 320 struct channel_softc *chp = atabus_sc->sc_chan; 321 int i, error, need_delref = 0; 322 struct ataparams params; 323 struct atabus_initq *atabus_initq = NULL; 324 u_int8_t st0 = 0, st1 = 0; 325 326 if ((error = wdc_addref(chp)) != 0) { 327 aprint_error("%s: unable to enable controller\n", 328 chp->wdc->sc_dev.dv_xname); 329 goto out; 330 } 331 need_delref = 1; 332 333 if (__wdcprobe(chp, 0) == 0) 334 /* If no drives, abort attach here. */ 335 goto out; 336 337 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 338 for (i = 0; i < mstohz(3000); i++) { 339 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 340 chp->wdc->select(chp,0); 341 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 342 WDSD_IBM); 343 delay(10); /* 400ns delay */ 344 st0 = bus_space_read_1(chp->cmd_iot, 345 chp->cmd_iohs[wd_status], 0); 346 347 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 348 chp->wdc->select(chp,1); 349 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 350 WDSD_IBM | 0x10); 351 delay(10); /* 400ns delay */ 352 st1 = bus_space_read_1(chp->cmd_iot, 353 chp->cmd_iohs[wd_status], 0); 354 355 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 356 == 0 || 357 (st0 & WDCS_DRDY)) && 358 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 359 == 0 || 360 (st1 & WDCS_DRDY))) 361 break; 362 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 363 } 364 if ((st0 & WDCS_DRDY) == 0) 365 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 366 if ((st1 & WDCS_DRDY) == 0) 367 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 368 369 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 370 chp->wdc->sc_dev.dv_xname, 371 chp->channel, st0, st1), DEBUG_PROBE); 372 373 /* Wait a bit, some devices are weird just after a reset. */ 374 delay(5000); 375 376 for (i = 0; i < 2; i++) { 377 chp->ch_drive[i].chnl_softc = chp; 378 chp->ch_drive[i].drive = i; 379 /* 380 * Init error counter so that an error withing the first xfers 381 * will trigger a downgrade 382 */ 383 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 384 385 /* If controller can't do 16bit flag the drives as 32bit */ 386 if ((chp->wdc->cap & 387 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 388 WDC_CAPABILITY_DATA32) 389 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 390 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 391 continue; 392 393 /* Shortcut in case we've been shutdown */ 394 if (chp->ch_flags & WDCF_SHUTDOWN) 395 goto out; 396 397 /* issue an identify, to try to detect ghosts */ 398 error = ata_get_params(&chp->ch_drive[i], 399 AT_WAIT | AT_POLL, ¶ms); 400 if (error != CMD_OK) { 401 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 402 403 /* Shortcut in case we've been shutdown */ 404 if (chp->ch_flags & WDCF_SHUTDOWN) 405 goto out; 406 407 error = ata_get_params(&chp->ch_drive[i], 408 AT_WAIT | AT_POLL, ¶ms); 409 } 410 if (error == CMD_OK) { 411 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 412 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 413 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 414 } else { 415 chp->ch_drive[i].drive_flags &= 416 ~(DRIVE_ATA | DRIVE_ATAPI); 417 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 418 chp->wdc->sc_dev.dv_xname, 419 chp->channel, i, error), DEBUG_PROBE); 420 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 421 continue; 422 /* 423 * Pre-ATA drive ? 424 * Test registers writability (Error register not 425 * writable, but cyllo is), then try an ATA command. 426 */ 427 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 428 chp->wdc->select(chp,i); 429 bus_space_write_1(chp->cmd_iot, 430 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 431 delay(10); /* 400ns delay */ 432 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 433 0, 0x58); 434 bus_space_write_1(chp->cmd_iot, 435 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 436 if (bus_space_read_1(chp->cmd_iot, 437 chp->cmd_iohs[wd_error], 0) == 0x58 || 438 bus_space_read_1(chp->cmd_iot, 439 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 440 WDCDEBUG_PRINT(("%s:%d:%d: register " 441 "writability failed\n", 442 chp->wdc->sc_dev.dv_xname, 443 chp->channel, i), DEBUG_PROBE); 444 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 445 continue; 446 } 447 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 448 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 449 chp->wdc->sc_dev.dv_xname, 450 chp->channel, i), DEBUG_PROBE); 451 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 452 continue; 453 } 454 bus_space_write_1(chp->cmd_iot, 455 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 456 delay(10); /* 400ns delay */ 457 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 458 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 459 chp->wdc->sc_dev.dv_xname, 460 chp->channel, i), DEBUG_PROBE); 461 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 462 } else { 463 chp->ch_drive[0].drive_flags &= 464 ~(DRIVE_ATA | DRIVE_ATAPI); 465 chp->ch_drive[1].drive_flags &= 466 ~(DRIVE_ATA | DRIVE_ATAPI); 467 } 468 } 469 } 470 471 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 472 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 473 DEBUG_PROBE); 474 475 /* If no drives, abort here */ 476 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 477 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 478 goto out; 479 480 /* Make sure the devices probe in atabus order to avoid jitter. */ 481 simple_lock(&atabus_interlock); 482 while(1) { 483 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 484 if (atabus_initq->atabus_sc == atabus_sc) 485 break; 486 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 487 &atabus_interlock); 488 } 489 simple_unlock(&atabus_interlock); 490 491 /* 492 * Attach an ATAPI bus, if needed. 493 */ 494 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 495 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 496 #if NATAPIBUS > 0 497 wdc_atapibus_attach(atabus_sc); 498 #else 499 /* 500 * Fake the autoconfig "not configured" message 501 */ 502 aprint_normal("atapibus at %s not configured\n", 503 chp->wdc->sc_dev.dv_xname); 504 chp->atapibus = NULL; 505 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 506 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 507 #endif 508 } 509 510 for (i = 0; i < 2; i++) { 511 struct ata_device adev; 512 if ((chp->ch_drive[i].drive_flags & 513 (DRIVE_ATA | DRIVE_OLD)) == 0) { 514 continue; 515 } 516 memset(&adev, 0, sizeof(struct ata_device)); 517 adev.adev_bustype = &wdc_ata_bustype; 518 adev.adev_channel = chp->channel; 519 adev.adev_openings = 1; 520 adev.adev_drv_data = &chp->ch_drive[i]; 521 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 522 &adev, wdprint); 523 if (chp->ata_drives[i] != NULL) 524 wdc_probe_caps(&chp->ch_drive[i]); 525 else 526 chp->ch_drive[i].drive_flags &= 527 ~(DRIVE_ATA | DRIVE_OLD); 528 } 529 530 /* now that we know the drives, the controller can set its modes */ 531 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 532 chp->wdc->set_modes(chp); 533 wdc_print_modes(chp); 534 } 535 #if NATARAID > 0 536 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 537 for (i = 0; i < 2; i++) 538 if (chp->ata_drives[i] != NULL) 539 ata_raid_check_component(chp->ata_drives[i]); 540 #endif /* NATARAID > 0 */ 541 542 /* 543 * reset drive_flags for unattached devices, reset state for attached 544 * ones 545 */ 546 for (i = 0; i < 2; i++) { 547 if (chp->ch_drive[i].drv_softc == NULL) 548 chp->ch_drive[i].drive_flags = 0; 549 else 550 chp->ch_drive[i].state = 0; 551 } 552 553 out: 554 if (atabus_initq == NULL) { 555 simple_lock(&atabus_interlock); 556 while(1) { 557 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 558 if (atabus_initq->atabus_sc == atabus_sc) 559 break; 560 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 561 &atabus_interlock); 562 } 563 simple_unlock(&atabus_interlock); 564 } 565 simple_lock(&atabus_interlock); 566 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 567 simple_unlock(&atabus_interlock); 568 569 free(atabus_initq, M_DEVBUF); 570 wakeup(&atabus_initq_head); 571 572 config_pending_decr(); 573 if (need_delref) 574 wdc_delref(chp); 575 } 576 577 578 int 579 wdprint(aux, pnp) 580 void *aux; 581 const char *pnp; 582 { 583 struct ata_device *adev = aux; 584 if (pnp) 585 aprint_normal("wd at %s", pnp); 586 aprint_normal(" drive %d", adev->adev_drv_data->drive); 587 return (UNCONF); 588 } 589 590 /* Test to see controller with at last one attached drive is there. 591 * Returns a bit for each possible drive found (0x01 for drive 0, 592 * 0x02 for drive 1). 593 * Logic: 594 * - If a status register is at 0xff, assume there is no drive here 595 * (ISA has pull-up resistors). Similarly if the status register has 596 * the value we last wrote to the bus (for IDE interfaces without pullups). 597 * If no drive at all -> return. 598 * - reset the controller, wait for it to complete (may take up to 31s !). 599 * If timeout -> return. 600 * - test ATA/ATAPI signatures. If at last one drive found -> return. 601 * - try an ATA command on the master. 602 */ 603 604 int 605 wdcprobe(chp) 606 struct channel_softc *chp; 607 { 608 return __wdcprobe(chp, 1); 609 } 610 611 int 612 __wdcprobe(chp, poll) 613 struct channel_softc *chp; 614 int poll; 615 { 616 u_int8_t st0, st1, sc, sn, cl, ch; 617 u_int8_t ret_value = 0x03; 618 u_int8_t drive; 619 int s; 620 621 /* 622 * Sanity check to see if the wdc channel responds at all. 623 */ 624 625 if (chp->wdc == NULL || 626 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 627 628 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 629 chp->wdc->select(chp,0); 630 631 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 632 WDSD_IBM); 633 delay(10); /* 400ns delay */ 634 st0 = bus_space_read_1(chp->cmd_iot, 635 chp->cmd_iohs[wd_status], 0); 636 637 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 638 chp->wdc->select(chp,1); 639 640 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 641 WDSD_IBM | 0x10); 642 delay(10); /* 400ns delay */ 643 st1 = bus_space_read_1(chp->cmd_iot, 644 chp->cmd_iohs[wd_status], 0); 645 646 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 647 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 648 chp->channel, st0, st1), DEBUG_PROBE); 649 650 if (st0 == 0xff || st0 == WDSD_IBM) 651 ret_value &= ~0x01; 652 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 653 ret_value &= ~0x02; 654 /* Register writability test, drive 0. */ 655 if (ret_value & 0x01) { 656 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 657 chp->wdc->select(chp,0); 658 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 659 0, WDSD_IBM); 660 bus_space_write_1(chp->cmd_iot, 661 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 662 if (bus_space_read_1(chp->cmd_iot, 663 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 664 ret_value &= ~0x01; 665 bus_space_write_1(chp->cmd_iot, 666 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 667 if (bus_space_read_1(chp->cmd_iot, 668 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 669 ret_value &= ~0x01; 670 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 671 0, 0x01); 672 if (bus_space_read_1(chp->cmd_iot, 673 chp->cmd_iohs[wd_sector], 0) != 0x01) 674 ret_value &= ~0x01; 675 bus_space_write_1(chp->cmd_iot, 676 chp->cmd_iohs[wd_sector], 0, 0x02); 677 if (bus_space_read_1(chp->cmd_iot, 678 chp->cmd_iohs[wd_sector], 0) != 0x02) 679 ret_value &= ~0x01; 680 if (bus_space_read_1(chp->cmd_iot, 681 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 682 ret_value &= ~0x01; 683 } 684 /* Register writability test, drive 1. */ 685 if (ret_value & 0x02) { 686 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 687 chp->wdc->select(chp,1); 688 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 689 0, WDSD_IBM | 0x10); 690 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 691 0, 0x02); 692 if (bus_space_read_1(chp->cmd_iot, 693 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 694 ret_value &= ~0x02; 695 bus_space_write_1(chp->cmd_iot, 696 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 697 if (bus_space_read_1(chp->cmd_iot, 698 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 699 ret_value &= ~0x02; 700 bus_space_write_1(chp->cmd_iot, 701 chp->cmd_iohs[wd_sector], 0, 0x01); 702 if (bus_space_read_1(chp->cmd_iot, 703 chp->cmd_iohs[wd_sector], 0) != 0x01) 704 ret_value &= ~0x02; 705 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 706 0, 0x02); 707 if (bus_space_read_1(chp->cmd_iot, 708 chp->cmd_iohs[wd_sector], 0) != 0x02) 709 ret_value &= ~0x02; 710 if (bus_space_read_1(chp->cmd_iot, 711 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 712 ret_value &= ~0x02; 713 } 714 715 if (ret_value == 0) 716 return 0; 717 } 718 719 s = splbio(); 720 721 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 722 chp->wdc->select(chp,0); 723 /* assert SRST, wait for reset to complete */ 724 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 725 delay(10); /* 400ns delay */ 726 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 727 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 728 DELAY(2000); 729 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 730 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 731 delay(10); /* 400ns delay */ 732 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 733 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 734 chp->wdc->irqack(chp); 735 splx(s); 736 737 ret_value = __wdcwait_reset(chp, ret_value, poll); 738 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 739 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 740 ret_value), DEBUG_PROBE); 741 742 /* if reset failed, there's nothing here */ 743 if (ret_value == 0) 744 return 0; 745 746 /* 747 * Test presence of drives. First test register signatures looking for 748 * ATAPI devices. If it's not an ATAPI and reset said there may be 749 * something here assume it's ATA or OLD. Ghost will be killed later in 750 * attach routine. 751 */ 752 for (drive = 0; drive < 2; drive++) { 753 if ((ret_value & (0x01 << drive)) == 0) 754 continue; 755 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 756 chp->wdc->select(chp,drive); 757 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 758 WDSD_IBM | (drive << 4)); 759 delay(10); /* 400ns delay */ 760 /* Save registers contents */ 761 sc = bus_space_read_1(chp->cmd_iot, 762 chp->cmd_iohs[wd_seccnt], 0); 763 sn = bus_space_read_1(chp->cmd_iot, 764 chp->cmd_iohs[wd_sector], 0); 765 cl = bus_space_read_1(chp->cmd_iot, 766 chp->cmd_iohs[wd_cyl_lo], 0); 767 ch = bus_space_read_1(chp->cmd_iot, 768 chp->cmd_iohs[wd_cyl_hi], 0); 769 770 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 771 "cl=0x%x ch=0x%x\n", 772 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 773 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 774 /* 775 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 776 * we get wrong values here, so ignore it. 777 */ 778 if (cl == 0x14 && ch == 0xeb) { 779 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 780 } else { 781 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 782 if (chp->wdc == NULL || 783 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 784 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 785 } 786 } 787 return (ret_value); 788 } 789 790 void 791 wdcattach(chp) 792 struct channel_softc *chp; 793 { 794 static int inited = 0; 795 796 if (chp->ch_flags & WDCF_DISABLED) 797 return; 798 799 /* initialise global data */ 800 callout_init(&chp->ch_callout); 801 if (inited == 0) { 802 /* Initialize the wdc_xfer pool. */ 803 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 804 0, 0, "wdcspl", NULL); 805 inited++; 806 } 807 TAILQ_INIT(&chp->ch_queue->sc_xfer); 808 chp->ch_queue->queue_freeze = 0; 809 810 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 811 } 812 813 /* 814 * Call activate routine of underlying devices. 815 */ 816 int 817 atabusactivate(self, act) 818 struct device *self; 819 enum devact act; 820 { 821 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 822 struct channel_softc *chp = atabus_sc->sc_chan; 823 struct device *sc = 0; 824 int s, i, error = 0; 825 826 s = splbio(); 827 switch (act) { 828 case DVACT_ACTIVATE: 829 error = EOPNOTSUPP; 830 break; 831 832 case DVACT_DEACTIVATE: 833 /* 834 * We might call deactivate routine for 835 * the children of atapibus twice (once via 836 * atapibus, once directly), but since 837 * config_deactivate maintains DVF_ACTIVE flag, 838 * it's safe. 839 */ 840 sc = chp->atapibus; 841 if (sc != NULL) { 842 error = config_deactivate(sc); 843 if (error != 0) 844 goto out; 845 } 846 847 for (i = 0; i < 2; i++) { 848 sc = chp->ch_drive[i].drv_softc; 849 WDCDEBUG_PRINT(("atabusactivate: %s:" 850 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 851 sc == NULL ? "nodrv" : sc->dv_xname), 852 DEBUG_DETACH); 853 if (sc != NULL) { 854 error = config_deactivate(sc); 855 if (error != 0) 856 goto out; 857 } 858 } 859 break; 860 } 861 862 out: 863 splx(s); 864 865 #ifdef WDCDEBUG 866 if (sc && error != 0) 867 WDCDEBUG_PRINT(("atabusactivate: %s: " 868 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 869 error, sc->dv_xname), DEBUG_DETACH); 870 #endif 871 return (error); 872 } 873 874 int wdcactivate(self, act) 875 struct device *self; 876 enum devact act; 877 { 878 struct wdc_softc *wdc = (struct wdc_softc *)self; 879 int s, i, error = 0; 880 881 s = splbio(); 882 switch (act) { 883 case DVACT_ACTIVATE: 884 error = EOPNOTSUPP; 885 break; 886 887 case DVACT_DEACTIVATE: 888 for (i = 0; i < wdc->nchannels; i++) { 889 error = config_deactivate(wdc->channels[i]->atabus); 890 if (error) 891 break; 892 } 893 break; 894 } 895 splx(s); 896 return (error); 897 } 898 899 900 int 901 atabusdetach(self, flags) 902 struct device *self; 903 int flags; 904 { 905 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 906 struct channel_softc *chp = atabus_sc->sc_chan; 907 struct device *sc = 0; 908 int i, error = 0; 909 910 /* shutdown channel */ 911 chp->ch_flags |= WDCF_SHUTDOWN; 912 wakeup(&chp->thread); 913 while (chp->thread != NULL) 914 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 915 916 /* 917 * Detach atapibus and its children. 918 */ 919 sc = chp->atapibus; 920 if (sc != NULL) { 921 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 922 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 923 error = config_detach(sc, flags); 924 if (error != 0) 925 goto out; 926 } 927 928 /* 929 * Detach our other children. 930 */ 931 for (i = 0; i < 2; i++) { 932 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 933 continue; 934 sc = chp->ch_drive[i].drv_softc; 935 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 936 atabus_sc->sc_dev.dv_xname, 937 sc == NULL ? "nodrv" : sc->dv_xname), 938 DEBUG_DETACH); 939 if (sc != NULL) { 940 error = config_detach(sc, flags); 941 if (error != 0) 942 goto out; 943 } 944 } 945 946 wdc_kill_pending(chp); 947 948 out: 949 #ifdef WDCDEBUG 950 if (sc && error != 0) 951 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 952 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 953 DEBUG_DETACH); 954 #endif 955 return (error); 956 } 957 958 int 959 wdcdetach(self, flags) 960 struct device *self; 961 int flags; 962 { 963 struct wdc_softc *wdc = (struct wdc_softc *)self; 964 struct channel_softc *chp; 965 int i, error = 0; 966 967 for (i = 0; i < wdc->nchannels; i++) { 968 chp = wdc->channels[i]; 969 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 970 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 971 error = config_detach(chp->atabus, flags); 972 if (error) 973 break; 974 } 975 return (error); 976 } 977 978 /* 979 * Start I/O on a controller, for the given channel. 980 * The first xfer may be not for our channel if the channel queues 981 * are shared. 982 */ 983 void 984 wdcstart(chp) 985 struct channel_softc *chp; 986 { 987 struct wdc_xfer *xfer; 988 989 #ifdef WDC_DIAGNOSTIC 990 int spl1, spl2; 991 992 spl1 = splbio(); 993 spl2 = splbio(); 994 if (spl2 != spl1) { 995 printf("wdcstart: not at splbio()\n"); 996 panic("wdcstart"); 997 } 998 splx(spl2); 999 splx(spl1); 1000 #endif /* WDC_DIAGNOSTIC */ 1001 1002 /* is there a xfer ? */ 1003 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 1004 return; 1005 1006 /* adjust chp, in case we have a shared queue */ 1007 chp = xfer->chp; 1008 1009 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 1010 return; /* channel aleady active */ 1011 } 1012 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 1013 return; /* queue froozen */ 1014 } 1015 #ifdef DIAGNOSTIC 1016 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 1017 panic("wdcstart: channel waiting for irq"); 1018 #endif 1019 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 1020 if (!(*chp->wdc->claim_hw)(chp, 0)) 1021 return; 1022 1023 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1024 chp->channel, xfer->drive), DEBUG_XFERS); 1025 chp->ch_flags |= WDCF_ACTIVE; 1026 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1027 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1028 chp->ch_drive[xfer->drive].state = 0; 1029 } 1030 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1031 KASSERT(xfer->c_flags & C_POLL); 1032 xfer->c_start(chp, xfer); 1033 } 1034 1035 /* restart an interrupted I/O */ 1036 void 1037 wdcrestart(v) 1038 void *v; 1039 { 1040 struct channel_softc *chp = v; 1041 int s; 1042 1043 s = splbio(); 1044 wdcstart(chp); 1045 splx(s); 1046 } 1047 1048 1049 /* 1050 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1051 * errors on the current operation, mark it done if necessary, and start the 1052 * next request. Also check for a partially done transfer, and continue with 1053 * the next chunk if so. 1054 */ 1055 int 1056 wdcintr(arg) 1057 void *arg; 1058 { 1059 struct channel_softc *chp = arg; 1060 struct wdc_xfer *xfer; 1061 int ret; 1062 1063 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1064 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1065 DEBUG_INTR); 1066 return (0); 1067 } 1068 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1069 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1070 /* try to clear the pending interrupt anyway */ 1071 (void)bus_space_read_1(chp->cmd_iot, 1072 chp->cmd_iohs[wd_status], 0); 1073 return (0); 1074 } 1075 1076 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1077 xfer = chp->ch_queue->sc_xfer.tqh_first; 1078 if (chp->ch_flags & WDCF_DMA_WAIT) { 1079 chp->wdc->dma_status = 1080 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1081 xfer->drive, 0); 1082 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1083 /* IRQ not for us, not detected by DMA engine */ 1084 return 0; 1085 } 1086 chp->ch_flags &= ~WDCF_DMA_WAIT; 1087 } 1088 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1089 ret = xfer->c_intr(chp, xfer, 1); 1090 if (ret == 0) /* irq was not for us, still waiting for irq */ 1091 chp->ch_flags |= WDCF_IRQ_WAIT; 1092 return (ret); 1093 } 1094 1095 /* Put all disk in RESET state */ 1096 void 1097 wdc_reset_channel(drvp, flags) 1098 struct ata_drive_datas *drvp; 1099 int flags; 1100 { 1101 struct channel_softc *chp = drvp->chnl_softc; 1102 int drive; 1103 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1104 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1105 DEBUG_FUNCS); 1106 if ((flags & AT_POLL) == 0) { 1107 if (chp->ch_flags & WDCF_TH_RESET) { 1108 /* no need to schedule a reset more than one time */ 1109 return; 1110 } 1111 chp->ch_flags |= WDCF_TH_RESET; 1112 chp->ch_queue->queue_freeze++; 1113 wakeup(&chp->thread); 1114 return; 1115 } 1116 (void) wdcreset(chp, RESET_POLL); 1117 for (drive = 0; drive < 2; drive++) { 1118 chp->ch_drive[drive].state = 0; 1119 } 1120 } 1121 1122 int 1123 wdcreset(chp, poll) 1124 struct channel_softc *chp; 1125 int poll; 1126 { 1127 int drv_mask1, drv_mask2; 1128 int s = 0; 1129 1130 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1131 chp->wdc->select(chp,0); 1132 if (poll != RESET_SLEEP) 1133 s = splbio(); 1134 /* master */ 1135 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1136 delay(10); /* 400ns delay */ 1137 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1138 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1139 delay(2000); 1140 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1141 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1142 WDCTL_4BIT | WDCTL_IDS); 1143 delay(10); /* 400ns delay */ 1144 if (poll != RESET_SLEEP) { 1145 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1146 chp->wdc->irqack(chp); 1147 splx(s); 1148 } 1149 1150 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1151 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1152 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1153 (poll == RESET_SLEEP) ? 0 : 1); 1154 if (drv_mask2 != drv_mask1) { 1155 printf("%s channel %d: reset failed for", 1156 chp->wdc->sc_dev.dv_xname, chp->channel); 1157 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1158 printf(" drive 0"); 1159 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1160 printf(" drive 1"); 1161 printf("\n"); 1162 } 1163 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1164 return (drv_mask1 != drv_mask2) ? 1 : 0; 1165 } 1166 1167 static int 1168 __wdcwait_reset(chp, drv_mask, poll) 1169 struct channel_softc *chp; 1170 int drv_mask; 1171 { 1172 int timeout, nloop; 1173 u_int8_t st0 = 0, st1 = 0; 1174 #ifdef WDCDEBUG 1175 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1176 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1177 #endif 1178 1179 if (poll) 1180 nloop = WDCNDELAY_RST; 1181 else 1182 nloop = WDC_RESET_WAIT * hz / 1000; 1183 /* wait for BSY to deassert */ 1184 for (timeout = 0; timeout < nloop; timeout++) { 1185 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1186 chp->wdc->select(chp,0); 1187 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1188 WDSD_IBM); /* master */ 1189 delay(10); 1190 st0 = bus_space_read_1(chp->cmd_iot, 1191 chp->cmd_iohs[wd_status], 0); 1192 #ifdef WDCDEBUG 1193 sc0 = bus_space_read_1(chp->cmd_iot, 1194 chp->cmd_iohs[wd_seccnt], 0); 1195 sn0 = bus_space_read_1(chp->cmd_iot, 1196 chp->cmd_iohs[wd_sector], 0); 1197 cl0 = bus_space_read_1(chp->cmd_iot, 1198 chp->cmd_iohs[wd_cyl_lo], 0); 1199 ch0 = bus_space_read_1(chp->cmd_iot, 1200 chp->cmd_iohs[wd_cyl_hi], 0); 1201 #endif 1202 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1203 chp->wdc->select(chp,1); 1204 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1205 WDSD_IBM | 0x10); /* slave */ 1206 delay(10); 1207 st1 = bus_space_read_1(chp->cmd_iot, 1208 chp->cmd_iohs[wd_status], 0); 1209 #ifdef WDCDEBUG 1210 sc1 = bus_space_read_1(chp->cmd_iot, 1211 chp->cmd_iohs[wd_seccnt], 0); 1212 sn1 = bus_space_read_1(chp->cmd_iot, 1213 chp->cmd_iohs[wd_sector], 0); 1214 cl1 = bus_space_read_1(chp->cmd_iot, 1215 chp->cmd_iohs[wd_cyl_lo], 0); 1216 ch1 = bus_space_read_1(chp->cmd_iot, 1217 chp->cmd_iohs[wd_cyl_hi], 0); 1218 #endif 1219 1220 if ((drv_mask & 0x01) == 0) { 1221 /* no master */ 1222 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1223 /* No master, slave is ready, it's done */ 1224 goto end; 1225 } 1226 } else if ((drv_mask & 0x02) == 0) { 1227 /* no slave */ 1228 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1229 /* No slave, master is ready, it's done */ 1230 goto end; 1231 } 1232 } else { 1233 /* Wait for both master and slave to be ready */ 1234 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1235 goto end; 1236 } 1237 } 1238 if (poll) 1239 delay(WDCDELAY); 1240 else 1241 tsleep(&nloop, PRIBIO, "atarst", 1); 1242 } 1243 /* Reset timed out. Maybe it's because drv_mask was not right */ 1244 if (st0 & WDCS_BSY) 1245 drv_mask &= ~0x01; 1246 if (st1 & WDCS_BSY) 1247 drv_mask &= ~0x02; 1248 end: 1249 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1250 "cl=0x%x ch=0x%x\n", 1251 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1252 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1253 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1254 "cl=0x%x ch=0x%x\n", 1255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1256 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1257 1258 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1259 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1260 st0, st1), DEBUG_PROBE); 1261 1262 return drv_mask; 1263 } 1264 1265 /* 1266 * Wait for a drive to be !BSY, and have mask in its status register. 1267 * return -1 for a timeout after "timeout" ms. 1268 */ 1269 int 1270 __wdcwait(chp, mask, bits, timeout) 1271 struct channel_softc *chp; 1272 int mask, bits, timeout; 1273 { 1274 u_char status; 1275 int time = 0; 1276 1277 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1278 :"none", chp->channel), DEBUG_STATUS); 1279 chp->ch_error = 0; 1280 1281 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1282 1283 for (;;) { 1284 chp->ch_status = status = 1285 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1286 if ((status & (WDCS_BSY | mask)) == bits) 1287 break; 1288 if (++time > timeout) { 1289 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1290 "status %x error %x (mask 0x%x bits 0x%x)\n", 1291 time, status, 1292 bus_space_read_1(chp->cmd_iot, 1293 chp->cmd_iohs[wd_error], 0), mask, bits), 1294 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1295 return(WDCWAIT_TOUT); 1296 } 1297 delay(WDCDELAY); 1298 } 1299 #ifdef WDCDEBUG 1300 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1301 printf("__wdcwait: did busy-wait, time=%d\n", time); 1302 #endif 1303 if (status & WDCS_ERR) 1304 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1305 chp->cmd_iohs[wd_error], 0); 1306 #ifdef WDCNDELAY_DEBUG 1307 /* After autoconfig, there should be no long delays. */ 1308 if (!cold && time > WDCNDELAY_DEBUG) { 1309 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1310 if (xfer == NULL) 1311 printf("%s channel %d: warning: busy-wait took %dus\n", 1312 chp->wdc->sc_dev.dv_xname, chp->channel, 1313 WDCDELAY * time); 1314 else 1315 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1316 chp->wdc->sc_dev.dv_xname, chp->channel, 1317 xfer->drive, 1318 WDCDELAY * time); 1319 } 1320 #endif 1321 return(WDCWAIT_OK); 1322 } 1323 1324 /* 1325 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1326 * thread if possible 1327 */ 1328 int 1329 wdcwait(chp, mask, bits, timeout, flags) 1330 struct channel_softc *chp; 1331 int mask, bits, timeout, flags; 1332 { 1333 int error, i, timeout_hz = mstohz(timeout); 1334 1335 if (timeout_hz == 0 || 1336 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1337 error = __wdcwait(chp, mask, bits, timeout); 1338 else { 1339 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1340 if (error != 0) { 1341 if ((chp->ch_flags & WDCF_TH_RUN) || 1342 (flags & AT_WAIT)) { 1343 /* 1344 * we're running in the channel thread 1345 * or some userland thread context 1346 */ 1347 for (i = 0; i < timeout_hz; i++) { 1348 if (__wdcwait(chp, mask, bits, 1349 WDCDELAY_POLL) == 0) { 1350 error = 0; 1351 break; 1352 } 1353 tsleep(&chp, PRIBIO, "atapoll", 1); 1354 } 1355 } else { 1356 /* 1357 * we're probably in interrupt context, 1358 * ask the thread to come back here 1359 */ 1360 #ifdef DIAGNOSTIC 1361 if (chp->ch_queue->queue_freeze > 0) 1362 panic("wdcwait: queue_freeze"); 1363 #endif 1364 chp->ch_queue->queue_freeze++; 1365 wakeup(&chp->thread); 1366 return(WDCWAIT_THR); 1367 } 1368 } 1369 } 1370 return(error); 1371 } 1372 1373 1374 /* 1375 * Busy-wait for DMA to complete 1376 */ 1377 int 1378 wdc_dmawait(chp, xfer, timeout) 1379 struct channel_softc *chp; 1380 struct wdc_xfer *xfer; 1381 int timeout; 1382 { 1383 int time; 1384 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1385 chp->wdc->dma_status = 1386 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1387 chp->channel, xfer->drive, 0); 1388 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1389 return 0; 1390 delay(WDCDELAY); 1391 } 1392 /* timeout, force a DMA halt */ 1393 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1394 chp->channel, xfer->drive, 1); 1395 return 1; 1396 } 1397 1398 void 1399 wdctimeout(arg) 1400 void *arg; 1401 { 1402 struct channel_softc *chp = (struct channel_softc *)arg; 1403 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1404 int s; 1405 1406 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1407 1408 s = splbio(); 1409 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1410 __wdcerror(chp, "lost interrupt"); 1411 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1412 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1413 xfer->c_bcount, 1414 xfer->c_skip); 1415 if (chp->ch_flags & WDCF_DMA_WAIT) { 1416 chp->wdc->dma_status = 1417 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1418 chp->channel, xfer->drive, 1); 1419 chp->ch_flags &= ~WDCF_DMA_WAIT; 1420 } 1421 /* 1422 * Call the interrupt routine. If we just missed an interrupt, 1423 * it will do what's needed. Else, it will take the needed 1424 * action (reset the device). 1425 * Before that we need to reinstall the timeout callback, 1426 * in case it will miss another irq while in this transfer 1427 * We arbitray chose it to be 1s 1428 */ 1429 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1430 xfer->c_flags |= C_TIMEOU; 1431 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1432 xfer->c_intr(chp, xfer, 1); 1433 } else 1434 __wdcerror(chp, "missing untimeout"); 1435 splx(s); 1436 } 1437 1438 /* 1439 * Probe drive's capabilities, for use by the controller later 1440 * Assumes drvp points to an existing drive. 1441 * XXX this should be a controller-indep function 1442 */ 1443 void 1444 wdc_probe_caps(drvp) 1445 struct ata_drive_datas *drvp; 1446 { 1447 struct ataparams params, params2; 1448 struct channel_softc *chp = drvp->chnl_softc; 1449 struct device *drv_dev = drvp->drv_softc; 1450 struct wdc_softc *wdc = chp->wdc; 1451 int i, printed; 1452 char *sep = ""; 1453 int cf_flags; 1454 1455 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1456 /* IDENTIFY failed. Can't tell more about the device */ 1457 return; 1458 } 1459 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1460 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1461 /* 1462 * Controller claims 16 and 32 bit transfers. 1463 * Re-do an IDENTIFY with 32-bit transfers, 1464 * and compare results. 1465 */ 1466 drvp->drive_flags |= DRIVE_CAP32; 1467 ata_get_params(drvp, AT_WAIT, ¶ms2); 1468 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1469 /* Not good. fall back to 16bits */ 1470 drvp->drive_flags &= ~DRIVE_CAP32; 1471 } else { 1472 aprint_normal("%s: 32-bit data port\n", 1473 drv_dev->dv_xname); 1474 } 1475 } 1476 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1477 if (params.atap_ata_major > 0x01 && 1478 params.atap_ata_major != 0xffff) { 1479 for (i = 14; i > 0; i--) { 1480 if (params.atap_ata_major & (1 << i)) { 1481 aprint_normal("%s: ATA version %d\n", 1482 drv_dev->dv_xname, i); 1483 drvp->ata_vers = i; 1484 break; 1485 } 1486 } 1487 } 1488 #endif 1489 1490 /* An ATAPI device is at last PIO mode 3 */ 1491 if (drvp->drive_flags & DRIVE_ATAPI) 1492 drvp->PIO_mode = 3; 1493 1494 /* 1495 * It's not in the specs, but it seems that some drive 1496 * returns 0xffff in atap_extensions when this field is invalid 1497 */ 1498 if (params.atap_extensions != 0xffff && 1499 (params.atap_extensions & WDC_EXT_MODES)) { 1500 printed = 0; 1501 /* 1502 * XXX some drives report something wrong here (they claim to 1503 * support PIO mode 8 !). As mode is coded on 3 bits in 1504 * SET FEATURE, limit it to 7 (so limit i to 4). 1505 * If higher mode than 7 is found, abort. 1506 */ 1507 for (i = 7; i >= 0; i--) { 1508 if ((params.atap_piomode_supp & (1 << i)) == 0) 1509 continue; 1510 if (i > 4) 1511 return; 1512 /* 1513 * See if mode is accepted. 1514 * If the controller can't set its PIO mode, 1515 * assume the defaults are good, so don't try 1516 * to set it 1517 */ 1518 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1519 /* 1520 * It's OK to pool here, it's fast enouth 1521 * to not bother waiting for interrupt 1522 */ 1523 if (ata_set_mode(drvp, 0x08 | (i + 3), 1524 AT_WAIT) != CMD_OK) 1525 continue; 1526 if (!printed) { 1527 aprint_normal("%s: drive supports PIO mode %d", 1528 drv_dev->dv_xname, i + 3); 1529 sep = ","; 1530 printed = 1; 1531 } 1532 /* 1533 * If controller's driver can't set its PIO mode, 1534 * get the highter one for the drive. 1535 */ 1536 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1537 wdc->PIO_cap >= i + 3) { 1538 drvp->PIO_mode = i + 3; 1539 drvp->PIO_cap = i + 3; 1540 break; 1541 } 1542 } 1543 if (!printed) { 1544 /* 1545 * We didn't find a valid PIO mode. 1546 * Assume the values returned for DMA are buggy too 1547 */ 1548 return; 1549 } 1550 drvp->drive_flags |= DRIVE_MODE; 1551 printed = 0; 1552 for (i = 7; i >= 0; i--) { 1553 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1554 continue; 1555 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1556 (wdc->cap & WDC_CAPABILITY_MODE)) 1557 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1558 != CMD_OK) 1559 continue; 1560 if (!printed) { 1561 aprint_normal("%s DMA mode %d", sep, i); 1562 sep = ","; 1563 printed = 1; 1564 } 1565 if (wdc->cap & WDC_CAPABILITY_DMA) { 1566 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1567 wdc->DMA_cap < i) 1568 continue; 1569 drvp->DMA_mode = i; 1570 drvp->DMA_cap = i; 1571 drvp->drive_flags |= DRIVE_DMA; 1572 } 1573 break; 1574 } 1575 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1576 printed = 0; 1577 for (i = 7; i >= 0; i--) { 1578 if ((params.atap_udmamode_supp & (1 << i)) 1579 == 0) 1580 continue; 1581 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1582 (wdc->cap & WDC_CAPABILITY_UDMA)) 1583 if (ata_set_mode(drvp, 0x40 | i, 1584 AT_WAIT) != CMD_OK) 1585 continue; 1586 if (!printed) { 1587 aprint_normal("%s Ultra-DMA mode %d", 1588 sep, i); 1589 if (i == 2) 1590 aprint_normal(" (Ultra/33)"); 1591 else if (i == 4) 1592 aprint_normal(" (Ultra/66)"); 1593 else if (i == 5) 1594 aprint_normal(" (Ultra/100)"); 1595 else if (i == 6) 1596 aprint_normal(" (Ultra/133)"); 1597 sep = ","; 1598 printed = 1; 1599 } 1600 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1601 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1602 wdc->UDMA_cap < i) 1603 continue; 1604 drvp->UDMA_mode = i; 1605 drvp->UDMA_cap = i; 1606 drvp->drive_flags |= DRIVE_UDMA; 1607 } 1608 break; 1609 } 1610 } 1611 aprint_normal("\n"); 1612 } 1613 1614 /* Try to guess ATA version here, if it didn't get reported */ 1615 if (drvp->ata_vers == 0) { 1616 if (drvp->drive_flags & DRIVE_UDMA) 1617 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1618 else if (drvp->PIO_cap > 2) 1619 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1620 } 1621 cf_flags = drv_dev->dv_cfdata->cf_flags; 1622 if (cf_flags & ATA_CONFIG_PIO_SET) { 1623 drvp->PIO_mode = 1624 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1625 drvp->drive_flags |= DRIVE_MODE; 1626 } 1627 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1628 /* don't care about DMA modes */ 1629 return; 1630 } 1631 if (cf_flags & ATA_CONFIG_DMA_SET) { 1632 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1633 ATA_CONFIG_DMA_DISABLE) { 1634 drvp->drive_flags &= ~DRIVE_DMA; 1635 } else { 1636 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1637 ATA_CONFIG_DMA_OFF; 1638 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1639 } 1640 } 1641 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1642 /* don't care about UDMA modes */ 1643 return; 1644 } 1645 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1646 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1647 ATA_CONFIG_UDMA_DISABLE) { 1648 drvp->drive_flags &= ~DRIVE_UDMA; 1649 } else { 1650 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1651 ATA_CONFIG_UDMA_OFF; 1652 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1653 } 1654 } 1655 } 1656 1657 /* 1658 * downgrade the transfer mode of a drive after an error. return 1 if 1659 * downgrade was possible, 0 otherwise. 1660 */ 1661 int 1662 wdc_downgrade_mode(drvp, flags) 1663 struct ata_drive_datas *drvp; 1664 { 1665 struct channel_softc *chp = drvp->chnl_softc; 1666 struct device *drv_dev = drvp->drv_softc; 1667 struct wdc_softc *wdc = chp->wdc; 1668 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1669 1670 /* if drive or controller don't know its mode, we can't do much */ 1671 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1672 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1673 return 0; 1674 /* current drive mode was set by a config flag, let it this way */ 1675 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1676 (cf_flags & ATA_CONFIG_DMA_SET) || 1677 (cf_flags & ATA_CONFIG_UDMA_SET)) 1678 return 0; 1679 1680 /* 1681 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1682 * Maybe we didn't properly notice the cable type 1683 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1684 * It helps in some cases. 1685 */ 1686 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1687 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1688 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1689 drv_dev->dv_xname, drvp->UDMA_mode); 1690 } 1691 1692 /* 1693 * If we were using ultra-DMA, don't downgrade to multiword DMA 1694 * if we noticed a CRC error. It has been noticed that CRC errors 1695 * in ultra-DMA lead to silent data corruption in multiword DMA. 1696 * Data corruption is less likely to occur in PIO mode. 1697 */ 1698 else if ((drvp->drive_flags & DRIVE_UDMA) && 1699 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1700 drvp->drive_flags &= ~DRIVE_UDMA; 1701 drvp->drive_flags |= DRIVE_DMA; 1702 drvp->DMA_mode = drvp->DMA_cap; 1703 printf("%s: transfer error, downgrading to DMA mode %d\n", 1704 drv_dev->dv_xname, drvp->DMA_mode); 1705 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1706 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1707 drvp->PIO_mode = drvp->PIO_cap; 1708 printf("%s: transfer error, downgrading to PIO mode %d\n", 1709 drv_dev->dv_xname, drvp->PIO_mode); 1710 } else /* already using PIO, can't downgrade */ 1711 return 0; 1712 1713 wdc->set_modes(chp); 1714 wdc_print_modes(chp); 1715 /* reset the channel, which will shedule all drives for setup */ 1716 wdc_reset_channel(drvp, flags); 1717 return 1; 1718 } 1719 1720 int 1721 wdc_exec_command(drvp, wdc_c) 1722 struct ata_drive_datas *drvp; 1723 struct wdc_command *wdc_c; 1724 { 1725 struct channel_softc *chp = drvp->chnl_softc; 1726 struct wdc_xfer *xfer; 1727 int s, ret; 1728 1729 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1730 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1731 DEBUG_FUNCS); 1732 1733 /* set up an xfer and queue. Wait for completion */ 1734 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1735 WDC_NOSLEEP); 1736 if (xfer == NULL) { 1737 return WDC_TRY_AGAIN; 1738 } 1739 1740 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1741 wdc_c->flags |= AT_POLL; 1742 if (wdc_c->flags & AT_POLL) 1743 xfer->c_flags |= C_POLL; 1744 xfer->drive = drvp->drive; 1745 xfer->databuf = wdc_c->data; 1746 xfer->c_bcount = wdc_c->bcount; 1747 xfer->cmd = wdc_c; 1748 xfer->c_start = __wdccommand_start; 1749 xfer->c_intr = __wdccommand_intr; 1750 xfer->c_kill_xfer = __wdccommand_done; 1751 1752 s = splbio(); 1753 wdc_exec_xfer(chp, xfer); 1754 #ifdef DIAGNOSTIC 1755 if ((wdc_c->flags & AT_POLL) != 0 && 1756 (wdc_c->flags & AT_DONE) == 0) 1757 panic("wdc_exec_command: polled command not done"); 1758 #endif 1759 if (wdc_c->flags & AT_DONE) { 1760 ret = WDC_COMPLETE; 1761 } else { 1762 if (wdc_c->flags & AT_WAIT) { 1763 while ((wdc_c->flags & AT_DONE) == 0) { 1764 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1765 } 1766 ret = WDC_COMPLETE; 1767 } else { 1768 ret = WDC_QUEUED; 1769 } 1770 } 1771 splx(s); 1772 return ret; 1773 } 1774 1775 void 1776 __wdccommand_start(chp, xfer) 1777 struct channel_softc *chp; 1778 struct wdc_xfer *xfer; 1779 { 1780 int drive = xfer->drive; 1781 struct wdc_command *wdc_c = xfer->cmd; 1782 1783 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1784 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1785 DEBUG_FUNCS); 1786 1787 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1788 chp->wdc->select(chp,drive); 1789 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1790 WDSD_IBM | (drive << 4)); 1791 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1792 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1793 case WDCWAIT_OK: 1794 break; 1795 case WDCWAIT_TOUT: 1796 wdc_c->flags |= AT_TIMEOU; 1797 __wdccommand_done(chp, xfer); 1798 return; 1799 case WDCWAIT_THR: 1800 return; 1801 } 1802 if (wdc_c->flags & AT_POLL) { 1803 /* polled command, disable interrupts */ 1804 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1805 WDCTL_4BIT | WDCTL_IDS); 1806 } 1807 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1808 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1809 1810 if ((wdc_c->flags & AT_POLL) == 0) { 1811 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1812 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1813 wdctimeout, chp); 1814 return; 1815 } 1816 /* 1817 * Polled command. Wait for drive ready or drq. Done in intr(). 1818 * Wait for at last 400ns for status bit to be valid. 1819 */ 1820 delay(10); /* 400ns delay */ 1821 __wdccommand_intr(chp, xfer, 0); 1822 } 1823 1824 int 1825 __wdccommand_intr(chp, xfer, irq) 1826 struct channel_softc *chp; 1827 struct wdc_xfer *xfer; 1828 int irq; 1829 { 1830 struct wdc_command *wdc_c = xfer->cmd; 1831 int bcount = wdc_c->bcount; 1832 char *data = wdc_c->data; 1833 int wflags; 1834 1835 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1836 /* both wait and poll, we can tsleep here */ 1837 wflags = AT_WAIT | AT_POLL; 1838 } else { 1839 wflags = AT_POLL; 1840 } 1841 1842 again: 1843 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1844 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1845 /* 1846 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1847 * Reselect again, it doesn't hurt for others commands, and the time 1848 * penalty for the extra regiter write is acceptable, 1849 * wdc_exec_command() isn't called often (mosly for autoconfig) 1850 */ 1851 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1852 WDSD_IBM | (xfer->drive << 4)); 1853 if ((wdc_c->flags & AT_XFDONE) != 0) { 1854 /* 1855 * We have completed a data xfer. The drive should now be 1856 * in its initial state 1857 */ 1858 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1859 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1860 wflags) == WDCWAIT_TOUT) { 1861 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1862 return 0; /* IRQ was not for us */ 1863 wdc_c->flags |= AT_TIMEOU; 1864 } 1865 goto out; 1866 } 1867 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1868 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1869 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1870 return 0; /* IRQ was not for us */ 1871 wdc_c->flags |= AT_TIMEOU; 1872 goto out; 1873 } 1874 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1875 chp->wdc->irqack(chp); 1876 if (wdc_c->flags & AT_READ) { 1877 if ((chp->ch_status & WDCS_DRQ) == 0) { 1878 wdc_c->flags |= AT_TIMEOU; 1879 goto out; 1880 } 1881 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1882 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1883 0, (u_int32_t*)data, bcount >> 2); 1884 data += bcount & 0xfffffffc; 1885 bcount = bcount & 0x03; 1886 } 1887 if (bcount > 0) 1888 bus_space_read_multi_2(chp->cmd_iot, 1889 chp->cmd_iohs[wd_data], 0, 1890 (u_int16_t *)data, bcount >> 1); 1891 /* at this point the drive should be in its initial state */ 1892 wdc_c->flags |= AT_XFDONE; 1893 /* XXX should read status register here ? */ 1894 } else if (wdc_c->flags & AT_WRITE) { 1895 if ((chp->ch_status & WDCS_DRQ) == 0) { 1896 wdc_c->flags |= AT_TIMEOU; 1897 goto out; 1898 } 1899 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1900 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1901 0, (u_int32_t*)data, bcount >> 2); 1902 data += bcount & 0xfffffffc; 1903 bcount = bcount & 0x03; 1904 } 1905 if (bcount > 0) 1906 bus_space_write_multi_2(chp->cmd_iot, 1907 chp->cmd_iohs[wd_data], 0, 1908 (u_int16_t *)data, bcount >> 1); 1909 wdc_c->flags |= AT_XFDONE; 1910 if ((wdc_c->flags & AT_POLL) == 0) { 1911 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1912 callout_reset(&chp->ch_callout, 1913 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1914 return 1; 1915 } else { 1916 goto again; 1917 } 1918 } 1919 out: 1920 __wdccommand_done(chp, xfer); 1921 return 1; 1922 } 1923 1924 void 1925 __wdccommand_done(chp, xfer) 1926 struct channel_softc *chp; 1927 struct wdc_xfer *xfer; 1928 { 1929 struct wdc_command *wdc_c = xfer->cmd; 1930 1931 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1932 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1933 1934 callout_stop(&chp->ch_callout); 1935 1936 if (chp->ch_status & WDCS_DWF) 1937 wdc_c->flags |= AT_DF; 1938 if (chp->ch_status & WDCS_ERR) { 1939 wdc_c->flags |= AT_ERROR; 1940 wdc_c->r_error = chp->ch_error; 1941 } 1942 wdc_c->flags |= AT_DONE; 1943 if ((wdc_c->flags & AT_READREG) != 0 && 1944 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1945 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1946 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1947 chp->cmd_iohs[wd_sdh], 0); 1948 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1949 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1950 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1951 chp->cmd_iohs[wd_cyl_lo], 0); 1952 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1953 chp->cmd_iohs[wd_sector], 0); 1954 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1955 chp->cmd_iohs[wd_seccnt], 0); 1956 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1957 chp->cmd_iohs[wd_error], 0); 1958 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1959 chp->cmd_iohs[wd_precomp], 0); 1960 } 1961 1962 if (wdc_c->flags & AT_POLL) { 1963 /* enable interrupts */ 1964 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1965 WDCTL_4BIT); 1966 } 1967 wdc_free_xfer(chp, xfer); 1968 if (wdc_c->flags & AT_WAIT) 1969 wakeup(wdc_c); 1970 else if (wdc_c->callback) 1971 wdc_c->callback(wdc_c->callback_arg); 1972 wdcstart(chp); 1973 return; 1974 } 1975 1976 /* 1977 * Send a command. The drive should be ready. 1978 * Assumes interrupts are blocked. 1979 */ 1980 void 1981 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1982 struct channel_softc *chp; 1983 u_int8_t drive; 1984 u_int8_t command; 1985 u_int16_t cylin; 1986 u_int8_t head, sector, count, precomp; 1987 { 1988 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1989 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1990 chp->channel, drive, command, cylin, head, sector, count, precomp), 1991 DEBUG_FUNCS); 1992 1993 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1994 chp->wdc->select(chp,drive); 1995 1996 /* Select drive, head, and addressing mode. */ 1997 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1998 WDSD_IBM | (drive << 4) | head); 1999 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 2000 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 2001 precomp); 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 2003 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 2004 0, cylin >> 8); 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 2006 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2007 2008 /* Send command. */ 2009 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2010 return; 2011 } 2012 2013 /* 2014 * Send a 48-bit addressing command. The drive should be ready. 2015 * Assumes interrupts are blocked. 2016 */ 2017 void 2018 wdccommandext(chp, drive, command, blkno, count) 2019 struct channel_softc *chp; 2020 u_int8_t drive; 2021 u_int8_t command; 2022 u_int64_t blkno; 2023 u_int16_t count; 2024 { 2025 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2026 "count=%d\n", chp->wdc->sc_dev.dv_xname, 2027 chp->channel, drive, command, (u_int32_t) blkno, count), 2028 DEBUG_FUNCS); 2029 2030 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2031 chp->wdc->select(chp,drive); 2032 2033 /* Select drive, head, and addressing mode. */ 2034 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2035 (drive << 4) | WDSD_LBA); 2036 2037 /* previous */ 2038 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2039 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 2040 0, count >> 8); 2041 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2042 0, blkno >> 40); 2043 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2044 0, blkno >> 32); 2045 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 2046 0, blkno >> 24); 2047 2048 /* current */ 2049 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2050 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2051 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2052 0, blkno >> 16); 2053 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2054 0, blkno >> 8); 2055 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2056 2057 /* Send command. */ 2058 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2059 return; 2060 } 2061 2062 /* 2063 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2064 * tested by the caller. 2065 */ 2066 void 2067 wdccommandshort(chp, drive, command) 2068 struct channel_softc *chp; 2069 int drive; 2070 int command; 2071 { 2072 2073 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2074 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2075 DEBUG_FUNCS); 2076 2077 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2078 chp->wdc->select(chp,drive); 2079 2080 /* Select drive. */ 2081 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2082 WDSD_IBM | (drive << 4)); 2083 2084 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2085 } 2086 2087 /* Add a command to the queue and start controller. Must be called at splbio */ 2088 2089 void 2090 wdc_exec_xfer(chp, xfer) 2091 struct channel_softc *chp; 2092 struct wdc_xfer *xfer; 2093 { 2094 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2095 chp->channel, xfer->drive), DEBUG_XFERS); 2096 2097 /* complete xfer setup */ 2098 xfer->chp = chp; 2099 2100 /* 2101 * If we are a polled command, and the list is not empty, 2102 * we are doing a dump. Drop the list to allow the polled command 2103 * to complete, we're going to reboot soon anyway. 2104 */ 2105 if ((xfer->c_flags & C_POLL) != 0 && 2106 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2107 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2108 } 2109 /* insert at the end of command list */ 2110 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2111 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2112 chp->ch_flags), DEBUG_XFERS); 2113 wdcstart(chp); 2114 } 2115 2116 struct wdc_xfer * 2117 wdc_get_xfer(flags) 2118 int flags; 2119 { 2120 struct wdc_xfer *xfer; 2121 int s; 2122 2123 s = splbio(); 2124 xfer = pool_get(&wdc_xfer_pool, 2125 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2126 splx(s); 2127 if (xfer != NULL) { 2128 memset(xfer, 0, sizeof(struct wdc_xfer)); 2129 } 2130 return xfer; 2131 } 2132 2133 void 2134 wdc_free_xfer(chp, xfer) 2135 struct channel_softc *chp; 2136 struct wdc_xfer *xfer; 2137 { 2138 struct wdc_softc *wdc = chp->wdc; 2139 int s; 2140 2141 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2142 (*wdc->free_hw)(chp); 2143 s = splbio(); 2144 chp->ch_flags &= ~WDCF_ACTIVE; 2145 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2146 pool_put(&wdc_xfer_pool, xfer); 2147 splx(s); 2148 } 2149 2150 /* 2151 * Kill off all pending xfers for a channel_softc. 2152 * 2153 * Must be called at splbio(). 2154 */ 2155 void 2156 wdc_kill_pending(chp) 2157 struct channel_softc *chp; 2158 { 2159 struct wdc_xfer *xfer; 2160 2161 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2162 chp = xfer->chp; 2163 (*xfer->c_kill_xfer)(chp, xfer); 2164 } 2165 } 2166 2167 static void 2168 __wdcerror(chp, msg) 2169 struct channel_softc *chp; 2170 char *msg; 2171 { 2172 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2173 2174 if (xfer == NULL) 2175 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2176 msg); 2177 else 2178 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2179 chp->channel, xfer->drive, msg); 2180 } 2181 2182 /* 2183 * the bit bucket 2184 */ 2185 void 2186 wdcbit_bucket(chp, size) 2187 struct channel_softc *chp; 2188 int size; 2189 { 2190 2191 for (; size >= 2; size -= 2) 2192 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2193 if (size) 2194 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2195 } 2196 2197 int 2198 wdc_addref(chp) 2199 struct channel_softc *chp; 2200 { 2201 struct wdc_softc *wdc = chp->wdc; 2202 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2203 int s, error = 0; 2204 2205 s = splbio(); 2206 if (adapt->adapt_refcnt++ == 0 && 2207 adapt->adapt_enable != NULL) { 2208 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2209 if (error) 2210 adapt->adapt_refcnt--; 2211 } 2212 splx(s); 2213 return (error); 2214 } 2215 2216 void 2217 wdc_delref(chp) 2218 struct channel_softc *chp; 2219 { 2220 struct wdc_softc *wdc = chp->wdc; 2221 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2222 int s; 2223 2224 s = splbio(); 2225 if (adapt->adapt_refcnt-- == 1 && 2226 adapt->adapt_enable != NULL) 2227 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2228 splx(s); 2229 } 2230 2231 void 2232 wdc_print_modes(struct channel_softc *chp) 2233 { 2234 int drive; 2235 struct ata_drive_datas *drvp; 2236 2237 for (drive = 0; drive < 2; drive++) { 2238 drvp = &chp->ch_drive[drive]; 2239 if ((drvp->drive_flags & DRIVE) == 0) 2240 continue; 2241 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2242 drvp->drv_softc->dv_xname, 2243 chp->wdc->sc_dev.dv_xname, 2244 chp->channel, drive, drvp->PIO_mode); 2245 if (drvp->drive_flags & DRIVE_DMA) 2246 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2247 if (drvp->drive_flags & DRIVE_UDMA) { 2248 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2249 if (drvp->UDMA_mode == 2) 2250 aprint_normal(" (Ultra/33)"); 2251 else if (drvp->UDMA_mode == 4) 2252 aprint_normal(" (Ultra/66)"); 2253 else if (drvp->UDMA_mode == 5) 2254 aprint_normal(" (Ultra/100)"); 2255 else if (drvp->UDMA_mode == 6) 2256 aprint_normal(" (Ultra/133)"); 2257 } 2258 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2259 aprint_normal(" (using DMA data transfers)"); 2260 aprint_normal("\n"); 2261 } 2262 } 2263
Indexes created Thu Sep 25 06:09:39 GMT 2025