wdc.c revision 1.160
1 /* $NetBSD: wdc.c,v 1.160 2003/12/14 18:51:10 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.160 2003/12/14 18:51:10 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "locators.h" 107 108 #include "ataraid.h" 109 #include "atapibus.h" 110 #include "wd.h" 111 112 #if NATARAID > 0 113 #include <dev/ata/ata_raidvar.h> 114 #endif 115 116 #define WDCDELAY 100 /* 100 microseconds */ 117 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 118 #if 0 119 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 120 #define WDCNDELAY_DEBUG 50 121 #endif 122 123 /* When polling wait that much and then tsleep for 1/hz seconds */ 124 #define WDCDELAY_POLL 1 /* ms */ 125 126 /* timeout for the control commands */ 127 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 128 129 struct pool wdc_xfer_pool; 130 131 #if NWD > 0 132 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 133 #else 134 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 135 const struct ata_bustype wdc_ata_bustype = { 136 SCSIPI_BUSTYPE_ATA, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL 144 }; 145 #endif 146 147 int atabusmatch __P((struct device *, struct cfdata *, void *)); 148 void atabusattach __P((struct device *, struct device *, void *)); 149 void atabus_create_thread __P((void *)); 150 void atabus_thread __P((void *)); 151 void atabusconfig __P((struct atabus_softc *)); 152 int atabusactivate __P((struct device *, enum devact)); 153 int atabusdetach __P((struct device *, int flags)); 154 int atabusprint __P((void *, const char *)); 155 156 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 157 atabusmatch, atabusattach, atabusdetach, atabusactivate); 158 159 struct atabus_initq { 160 struct atabus_softc *atabus_sc; 161 TAILQ_ENTRY(atabus_initq) atabus_initq; 162 }; 163 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 164 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 165 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 166 167 int wdcprobe1 __P((struct channel_softc*, int)); 168 static void __wdcerror __P((struct channel_softc*, char *)); 169 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 170 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 171 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 172 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 173 int __wdcwait __P((struct channel_softc *, int, int, int)); 174 int wdprint __P((void *, const char *)); 175 void wdc_finish_attach __P((struct device *)); 176 void wdc_channel_attach __P((struct channel_softc *)); 177 178 #define DEBUG_INTR 0x01 179 #define DEBUG_XFERS 0x02 180 #define DEBUG_STATUS 0x04 181 #define DEBUG_FUNCS 0x08 182 #define DEBUG_PROBE 0x10 183 #define DEBUG_DETACH 0x20 184 #define DEBUG_DELAY 0x40 185 #ifdef WDCDEBUG 186 int wdcdebug_mask = 0; 187 int wdc_nxfer = 0; 188 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 189 #else 190 #define WDCDEBUG_PRINT(args, level) 191 #endif 192 193 int 194 atabusprint(aux, pnp) 195 void *aux; 196 const char *pnp; 197 { 198 struct channel_softc *chan = aux; 199 if (pnp) 200 aprint_normal("atabus at %s", pnp); 201 aprint_normal(" channel %d", chan->channel); 202 return (UNCONF); 203 } 204 205 int 206 atabusmatch(parent, cf, aux) 207 struct device *parent; 208 struct cfdata *cf; 209 void *aux; 210 { 211 struct channel_softc *chp = aux; 212 213 if (chp == NULL) 214 return (0); 215 216 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 217 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 218 return (0); 219 220 return (1); 221 } 222 223 void 224 atabusattach(parent, self, aux) 225 struct device *parent, *self; 226 void *aux; 227 { 228 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 229 struct channel_softc *chp = aux; 230 struct atabus_initq *atabus_initq; 231 232 atabus_sc->sc_chan = chp; 233 234 aprint_normal("\n"); 235 aprint_naive("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) { 272 s = splbio(); 273 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 274 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 275 chp->ch_queue->queue_freeze == 0)) { 276 chp->ch_flags &= ~WDCF_TH_RUN; 277 tsleep(&chp->thread, PRIBIO, "atath", 0); 278 chp->ch_flags |= WDCF_TH_RUN; 279 } 280 splx(s); 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 break; 283 s = splbio(); 284 if (chp->ch_flags & WDCF_TH_RESET) { 285 int drive; 286 (void) wdcreset(chp, RESET_SLEEP); 287 for (drive = 0; drive < 2; drive++) { 288 chp->ch_drive[drive].state = 0; 289 } 290 chp->ch_flags &= ~WDCF_TH_RESET; 291 chp->ch_queue->queue_freeze--; 292 wdcstart(chp); 293 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 294 chp->ch_queue->queue_freeze == 1) { 295 /* 296 * caller has bumped queue_freeze, decrease it 297 */ 298 chp->ch_queue->queue_freeze--; 299 xfer = chp->ch_queue->sc_xfer.tqh_first; 300 #ifdef DIAGNOSTIC 301 if (xfer == NULL) 302 panic("channel active with no xfer ?"); 303 #endif 304 xfer->c_start(chp, xfer); 305 } else if (chp->ch_queue->queue_freeze > 1) { 306 panic("queue_freeze"); 307 } 308 splx(s); 309 } 310 chp->thread = NULL; 311 wakeup(&chp->ch_flags); 312 kthread_exit(0); 313 } 314 315 void 316 atabusconfig(atabus_sc) 317 struct atabus_softc *atabus_sc; 318 { 319 struct channel_softc *chp = atabus_sc->sc_chan; 320 int i, error, need_delref = 0; 321 struct ataparams params; 322 struct atabus_initq *atabus_initq = NULL; 323 u_int8_t st0 = 0, st1 = 0; 324 325 if ((error = wdc_addref(chp)) != 0) { 326 aprint_error("%s: unable to enable controller\n", 327 chp->wdc->sc_dev.dv_xname); 328 goto out; 329 } 330 need_delref = 1; 331 332 if (wdcprobe1(chp, 0) == 0) 333 /* If no drives, abort attach here. */ 334 goto out; 335 336 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 337 for (i = 0; i < mstohz(3000); i++) { 338 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 339 chp->wdc->select(chp,0); 340 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 341 WDSD_IBM); 342 delay(10); /* 400ns delay */ 343 st0 = bus_space_read_1(chp->cmd_iot, 344 chp->cmd_iohs[wd_status], 0); 345 346 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 347 chp->wdc->select(chp,1); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 349 WDSD_IBM | 0x10); 350 delay(10); /* 400ns delay */ 351 st1 = bus_space_read_1(chp->cmd_iot, 352 chp->cmd_iohs[wd_status], 0); 353 354 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 355 == 0 || 356 (st0 & WDCS_DRDY)) && 357 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 358 == 0 || 359 (st1 & WDCS_DRDY))) 360 break; 361 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 362 } 363 if ((st0 & WDCS_DRDY) == 0) 364 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 365 if ((st1 & WDCS_DRDY) == 0) 366 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 367 368 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 369 chp->wdc->sc_dev.dv_xname, 370 chp->channel, st0, st1), DEBUG_PROBE); 371 372 /* Wait a bit, some devices are weird just after a reset. */ 373 delay(5000); 374 375 for (i = 0; i < 2; i++) { 376 chp->ch_drive[i].chnl_softc = chp; 377 chp->ch_drive[i].drive = i; 378 /* 379 * Init error counter so that an error withing the first xfers 380 * will trigger a downgrade 381 */ 382 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 383 384 /* If controller can't do 16bit flag the drives as 32bit */ 385 if ((chp->wdc->cap & 386 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 387 WDC_CAPABILITY_DATA32) 388 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 389 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 390 continue; 391 392 /* Shortcut in case we've been shutdown */ 393 if (chp->ch_flags & WDCF_SHUTDOWN) 394 goto out; 395 396 /* issue an identify, to try to detect ghosts */ 397 error = ata_get_params(&chp->ch_drive[i], 398 AT_WAIT | AT_POLL, ¶ms); 399 if (error != CMD_OK) { 400 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 401 402 /* Shortcut in case we've been shutdown */ 403 if (chp->ch_flags & WDCF_SHUTDOWN) 404 goto out; 405 406 error = ata_get_params(&chp->ch_drive[i], 407 AT_WAIT | AT_POLL, ¶ms); 408 } 409 if (error == CMD_OK) { 410 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 411 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 412 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 413 } else { 414 chp->ch_drive[i].drive_flags &= 415 ~(DRIVE_ATA | DRIVE_ATAPI); 416 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 417 chp->wdc->sc_dev.dv_xname, 418 chp->channel, i, error), DEBUG_PROBE); 419 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 420 continue; 421 /* 422 * Pre-ATA drive ? 423 * Test registers writability (Error register not 424 * writable, but cyllo is), then try an ATA command. 425 */ 426 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 427 chp->wdc->select(chp,i); 428 bus_space_write_1(chp->cmd_iot, 429 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 430 delay(10); /* 400ns delay */ 431 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 432 0, 0x58); 433 bus_space_write_1(chp->cmd_iot, 434 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 435 if (bus_space_read_1(chp->cmd_iot, 436 chp->cmd_iohs[wd_error], 0) == 0x58 || 437 bus_space_read_1(chp->cmd_iot, 438 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 439 WDCDEBUG_PRINT(("%s:%d:%d: register " 440 "writability failed\n", 441 chp->wdc->sc_dev.dv_xname, 442 chp->channel, i), DEBUG_PROBE); 443 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 444 continue; 445 } 446 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 447 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 448 chp->wdc->sc_dev.dv_xname, 449 chp->channel, i), DEBUG_PROBE); 450 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 451 continue; 452 } 453 bus_space_write_1(chp->cmd_iot, 454 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 455 delay(10); /* 400ns delay */ 456 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 457 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 458 chp->wdc->sc_dev.dv_xname, 459 chp->channel, i), DEBUG_PROBE); 460 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 461 } else { 462 chp->ch_drive[0].drive_flags &= 463 ~(DRIVE_ATA | DRIVE_ATAPI); 464 chp->ch_drive[1].drive_flags &= 465 ~(DRIVE_ATA | DRIVE_ATAPI); 466 } 467 } 468 } 469 470 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 471 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 472 DEBUG_PROBE); 473 474 /* If no drives, abort here */ 475 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 476 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 477 goto out; 478 479 /* Make sure the devices probe in atabus order to avoid jitter. */ 480 simple_lock(&atabus_interlock); 481 while(1) { 482 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 483 if (atabus_initq->atabus_sc == atabus_sc) 484 break; 485 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 486 &atabus_interlock); 487 } 488 simple_unlock(&atabus_interlock); 489 490 /* 491 * Attach an ATAPI bus, if needed. 492 */ 493 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 494 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 495 #if NATAPIBUS > 0 496 wdc_atapibus_attach(atabus_sc); 497 #else 498 /* 499 * Fake the autoconfig "not configured" message 500 */ 501 aprint_normal("atapibus at %s not configured\n", 502 chp->wdc->sc_dev.dv_xname); 503 chp->atapibus = NULL; 504 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 505 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 506 #endif 507 } 508 509 for (i = 0; i < 2; i++) { 510 struct ata_device adev; 511 if ((chp->ch_drive[i].drive_flags & 512 (DRIVE_ATA | DRIVE_OLD)) == 0) { 513 continue; 514 } 515 memset(&adev, 0, sizeof(struct ata_device)); 516 adev.adev_bustype = &wdc_ata_bustype; 517 adev.adev_channel = chp->channel; 518 adev.adev_openings = 1; 519 adev.adev_drv_data = &chp->ch_drive[i]; 520 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 521 &adev, wdprint); 522 if (chp->ata_drives[i] != NULL) 523 wdc_probe_caps(&chp->ch_drive[i]); 524 else 525 chp->ch_drive[i].drive_flags &= 526 ~(DRIVE_ATA | DRIVE_OLD); 527 } 528 529 /* now that we know the drives, the controller can set its modes */ 530 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 531 chp->wdc->set_modes(chp); 532 wdc_print_modes(chp); 533 } 534 #if NATARAID > 0 535 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 536 for (i = 0; i < 2; i++) 537 if (chp->ata_drives[i] != NULL) 538 ata_raid_check_component(chp->ata_drives[i]); 539 #endif /* NATARAID > 0 */ 540 541 /* 542 * reset drive_flags for unattached devices, reset state for attached 543 * ones 544 */ 545 for (i = 0; i < 2; i++) { 546 if (chp->ch_drive[i].drv_softc == NULL) 547 chp->ch_drive[i].drive_flags = 0; 548 else 549 chp->ch_drive[i].state = 0; 550 } 551 552 out: 553 if (atabus_initq == NULL) { 554 simple_lock(&atabus_interlock); 555 while(1) { 556 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 557 if (atabus_initq->atabus_sc == atabus_sc) 558 break; 559 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 560 &atabus_interlock); 561 } 562 simple_unlock(&atabus_interlock); 563 } 564 simple_lock(&atabus_interlock); 565 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 566 simple_unlock(&atabus_interlock); 567 568 free(atabus_initq, M_DEVBUF); 569 wakeup(&atabus_initq_head); 570 571 config_pending_decr(); 572 if (need_delref) 573 wdc_delref(chp); 574 } 575 576 577 int 578 wdprint(aux, pnp) 579 void *aux; 580 const char *pnp; 581 { 582 struct ata_device *adev = aux; 583 if (pnp) 584 aprint_normal("wd at %s", pnp); 585 aprint_normal(" drive %d", adev->adev_drv_data->drive); 586 return (UNCONF); 587 } 588 589 /* Test to see controller with at last one attached drive is there. 590 * Returns a bit for each possible drive found (0x01 for drive 0, 591 * 0x02 for drive 1). 592 * Logic: 593 * - If a status register is at 0xff, assume there is no drive here 594 * (ISA has pull-up resistors). Similarly if the status register has 595 * the value we last wrote to the bus (for IDE interfaces without pullups). 596 * If no drive at all -> return. 597 * - reset the controller, wait for it to complete (may take up to 31s !). 598 * If timeout -> return. 599 * - test ATA/ATAPI signatures. If at last one drive found -> return. 600 * - try an ATA command on the master. 601 */ 602 603 int 604 wdcprobe(chp) 605 struct channel_softc *chp; 606 { 607 return wdcprobe1(chp, 1); 608 } 609 610 int 611 wdcprobe1(chp, poll) 612 struct channel_softc *chp; 613 int poll; 614 { 615 u_int8_t st0, st1, sc, sn, cl, ch; 616 u_int8_t ret_value = 0x03; 617 u_int8_t drive; 618 int s; 619 620 /* 621 * Sanity check to see if the wdc channel responds at all. 622 */ 623 624 if (chp->wdc == NULL || 625 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 626 627 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 628 chp->wdc->select(chp,0); 629 630 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 631 WDSD_IBM); 632 delay(10); /* 400ns delay */ 633 st0 = bus_space_read_1(chp->cmd_iot, 634 chp->cmd_iohs[wd_status], 0); 635 636 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 637 chp->wdc->select(chp,1); 638 639 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 640 WDSD_IBM | 0x10); 641 delay(10); /* 400ns delay */ 642 st1 = bus_space_read_1(chp->cmd_iot, 643 chp->cmd_iohs[wd_status], 0); 644 645 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 646 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 647 chp->channel, st0, st1), DEBUG_PROBE); 648 649 if (st0 == 0xff || st0 == WDSD_IBM) 650 ret_value &= ~0x01; 651 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 652 ret_value &= ~0x02; 653 /* Register writability test, drive 0. */ 654 if (ret_value & 0x01) { 655 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 656 chp->wdc->select(chp,0); 657 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 658 0, WDSD_IBM); 659 bus_space_write_1(chp->cmd_iot, 660 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 661 if (bus_space_read_1(chp->cmd_iot, 662 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 663 ret_value &= ~0x01; 664 bus_space_write_1(chp->cmd_iot, 665 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 666 if (bus_space_read_1(chp->cmd_iot, 667 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 668 ret_value &= ~0x01; 669 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 670 0, 0x01); 671 if (bus_space_read_1(chp->cmd_iot, 672 chp->cmd_iohs[wd_sector], 0) != 0x01) 673 ret_value &= ~0x01; 674 bus_space_write_1(chp->cmd_iot, 675 chp->cmd_iohs[wd_sector], 0, 0x02); 676 if (bus_space_read_1(chp->cmd_iot, 677 chp->cmd_iohs[wd_sector], 0) != 0x02) 678 ret_value &= ~0x01; 679 if (bus_space_read_1(chp->cmd_iot, 680 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 681 ret_value &= ~0x01; 682 } 683 /* Register writability test, drive 1. */ 684 if (ret_value & 0x02) { 685 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 686 chp->wdc->select(chp,1); 687 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 688 0, WDSD_IBM | 0x10); 689 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 690 0, 0x02); 691 if (bus_space_read_1(chp->cmd_iot, 692 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 693 ret_value &= ~0x02; 694 bus_space_write_1(chp->cmd_iot, 695 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 696 if (bus_space_read_1(chp->cmd_iot, 697 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 698 ret_value &= ~0x02; 699 bus_space_write_1(chp->cmd_iot, 700 chp->cmd_iohs[wd_sector], 0, 0x01); 701 if (bus_space_read_1(chp->cmd_iot, 702 chp->cmd_iohs[wd_sector], 0) != 0x01) 703 ret_value &= ~0x02; 704 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 705 0, 0x02); 706 if (bus_space_read_1(chp->cmd_iot, 707 chp->cmd_iohs[wd_sector], 0) != 0x02) 708 ret_value &= ~0x02; 709 if (bus_space_read_1(chp->cmd_iot, 710 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 711 ret_value &= ~0x02; 712 } 713 714 if (ret_value == 0) 715 return 0; 716 } 717 718 s = splbio(); 719 720 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 721 chp->wdc->select(chp,0); 722 /* assert SRST, wait for reset to complete */ 723 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 724 delay(10); /* 400ns delay */ 725 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 726 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 727 DELAY(2000); 728 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 729 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 730 delay(10); /* 400ns delay */ 731 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 732 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_IRQACK)) 733 chp->wdc->irqack(chp); 734 splx(s); 735 736 ret_value = __wdcwait_reset(chp, ret_value, poll); 737 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 738 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 739 ret_value), DEBUG_PROBE); 740 741 /* if reset failed, there's nothing here */ 742 if (ret_value == 0) 743 return 0; 744 745 /* 746 * Test presence of drives. First test register signatures looking for 747 * ATAPI devices. If it's not an ATAPI and reset said there may be 748 * something here assume it's ATA or OLD. Ghost will be killed later in 749 * attach routine. 750 */ 751 for (drive = 0; drive < 2; drive++) { 752 if ((ret_value & (0x01 << drive)) == 0) 753 continue; 754 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 755 chp->wdc->select(chp,drive); 756 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 757 WDSD_IBM | (drive << 4)); 758 delay(10); /* 400ns delay */ 759 /* Save registers contents */ 760 sc = bus_space_read_1(chp->cmd_iot, 761 chp->cmd_iohs[wd_seccnt], 0); 762 sn = bus_space_read_1(chp->cmd_iot, 763 chp->cmd_iohs[wd_sector], 0); 764 cl = bus_space_read_1(chp->cmd_iot, 765 chp->cmd_iohs[wd_cyl_lo], 0); 766 ch = bus_space_read_1(chp->cmd_iot, 767 chp->cmd_iohs[wd_cyl_hi], 0); 768 769 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 770 "cl=0x%x ch=0x%x\n", 771 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 772 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 773 /* 774 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 775 * we get wrong values here, so ignore it. 776 */ 777 if (cl == 0x14 && ch == 0xeb) { 778 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 779 } else { 780 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 781 if (chp->wdc == NULL || 782 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 783 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 784 } 785 } 786 return (ret_value); 787 } 788 789 void 790 wdcattach(chp) 791 struct channel_softc *chp; 792 { 793 static int inited = 0; 794 795 if (chp->ch_flags & WDCF_DISABLED) 796 return; 797 798 /* initialise global data */ 799 callout_init(&chp->ch_callout); 800 if (inited == 0) { 801 /* Initialize the wdc_xfer pool. */ 802 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 803 0, 0, "wdcspl", NULL); 804 inited++; 805 } 806 TAILQ_INIT(&chp->ch_queue->sc_xfer); 807 chp->ch_queue->queue_freeze = 0; 808 809 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 810 } 811 812 /* 813 * Call activate routine of underlying devices. 814 */ 815 int 816 atabusactivate(self, act) 817 struct device *self; 818 enum devact act; 819 { 820 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 821 struct channel_softc *chp = atabus_sc->sc_chan; 822 struct device *sc = 0; 823 int s, i, error = 0; 824 825 s = splbio(); 826 switch (act) { 827 case DVACT_ACTIVATE: 828 error = EOPNOTSUPP; 829 break; 830 831 case DVACT_DEACTIVATE: 832 /* 833 * We might call deactivate routine for 834 * the children of atapibus twice (once via 835 * atapibus, once directly), but since 836 * config_deactivate maintains DVF_ACTIVE flag, 837 * it's safe. 838 */ 839 sc = chp->atapibus; 840 if (sc != NULL) { 841 error = config_deactivate(sc); 842 if (error != 0) 843 goto out; 844 } 845 846 for (i = 0; i < 2; i++) { 847 sc = chp->ch_drive[i].drv_softc; 848 WDCDEBUG_PRINT(("atabusactivate: %s:" 849 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 850 sc == NULL ? "nodrv" : sc->dv_xname), 851 DEBUG_DETACH); 852 if (sc != NULL) { 853 error = config_deactivate(sc); 854 if (error != 0) 855 goto out; 856 } 857 } 858 break; 859 } 860 861 out: 862 splx(s); 863 864 #ifdef WDCDEBUG 865 if (sc && error != 0) 866 WDCDEBUG_PRINT(("atabusactivate: %s: " 867 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 868 error, sc->dv_xname), DEBUG_DETACH); 869 #endif 870 return (error); 871 } 872 873 int wdcactivate(self, act) 874 struct device *self; 875 enum devact act; 876 { 877 struct wdc_softc *wdc = (struct wdc_softc *)self; 878 int s, i, error = 0; 879 880 s = splbio(); 881 switch (act) { 882 case DVACT_ACTIVATE: 883 error = EOPNOTSUPP; 884 break; 885 886 case DVACT_DEACTIVATE: 887 for (i = 0; i < wdc->nchannels; i++) { 888 error = config_deactivate(wdc->channels[i]->atabus); 889 if (error) 890 break; 891 } 892 break; 893 } 894 splx(s); 895 return (error); 896 } 897 898 899 int 900 atabusdetach(self, flags) 901 struct device *self; 902 int flags; 903 { 904 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 905 struct channel_softc *chp = atabus_sc->sc_chan; 906 struct device *sc = 0; 907 int i, error = 0; 908 909 /* shutdown channel */ 910 chp->ch_flags |= WDCF_SHUTDOWN; 911 wakeup(&chp->thread); 912 while (chp->thread != NULL) 913 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 914 915 /* 916 * Detach atapibus and its children. 917 */ 918 sc = chp->atapibus; 919 if (sc != NULL) { 920 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 921 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 922 error = config_detach(sc, flags); 923 if (error != 0) 924 goto out; 925 } 926 927 /* 928 * Detach our other children. 929 */ 930 for (i = 0; i < 2; i++) { 931 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 932 continue; 933 sc = chp->ch_drive[i].drv_softc; 934 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 935 atabus_sc->sc_dev.dv_xname, 936 sc == NULL ? "nodrv" : sc->dv_xname), 937 DEBUG_DETACH); 938 if (sc != NULL) { 939 error = config_detach(sc, flags); 940 if (error != 0) 941 goto out; 942 } 943 } 944 945 wdc_kill_pending(chp); 946 947 out: 948 #ifdef WDCDEBUG 949 if (sc && error != 0) 950 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 951 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 952 DEBUG_DETACH); 953 #endif 954 return (error); 955 } 956 957 int 958 wdcdetach(self, flags) 959 struct device *self; 960 int flags; 961 { 962 struct wdc_softc *wdc = (struct wdc_softc *)self; 963 struct channel_softc *chp; 964 int i, error = 0; 965 966 for (i = 0; i < wdc->nchannels; i++) { 967 chp = wdc->channels[i]; 968 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 969 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 970 error = config_detach(chp->atabus, flags); 971 if (error) 972 break; 973 } 974 return (error); 975 } 976 977 /* 978 * Start I/O on a controller, for the given channel. 979 * The first xfer may be not for our channel if the channel queues 980 * are shared. 981 */ 982 void 983 wdcstart(chp) 984 struct channel_softc *chp; 985 { 986 struct wdc_xfer *xfer; 987 988 #ifdef WDC_DIAGNOSTIC 989 int spl1, spl2; 990 991 spl1 = splbio(); 992 spl2 = splbio(); 993 if (spl2 != spl1) { 994 printf("wdcstart: not at splbio()\n"); 995 panic("wdcstart"); 996 } 997 splx(spl2); 998 splx(spl1); 999 #endif /* WDC_DIAGNOSTIC */ 1000 1001 /* is there a xfer ? */ 1002 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 1003 return; 1004 1005 /* adjust chp, in case we have a shared queue */ 1006 chp = xfer->chp; 1007 1008 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 1009 return; /* channel aleady active */ 1010 } 1011 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 1012 return; /* queue froozen */ 1013 } 1014 #ifdef DIAGNOSTIC 1015 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 1016 panic("wdcstart: channel waiting for irq"); 1017 #endif 1018 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 1019 if (!(*chp->wdc->claim_hw)(chp, 0)) 1020 return; 1021 1022 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1023 chp->channel, xfer->drive), DEBUG_XFERS); 1024 chp->ch_flags |= WDCF_ACTIVE; 1025 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1026 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1027 chp->ch_drive[xfer->drive].state = 0; 1028 } 1029 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1030 KASSERT(xfer->c_flags & C_POLL); 1031 xfer->c_start(chp, xfer); 1032 } 1033 1034 /* restart an interrupted I/O */ 1035 void 1036 wdcrestart(v) 1037 void *v; 1038 { 1039 struct channel_softc *chp = v; 1040 int s; 1041 1042 s = splbio(); 1043 wdcstart(chp); 1044 splx(s); 1045 } 1046 1047 1048 /* 1049 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1050 * errors on the current operation, mark it done if necessary, and start the 1051 * next request. Also check for a partially done transfer, and continue with 1052 * the next chunk if so. 1053 */ 1054 int 1055 wdcintr(arg) 1056 void *arg; 1057 { 1058 struct channel_softc *chp = arg; 1059 struct wdc_xfer *xfer; 1060 int ret; 1061 1062 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1063 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1064 DEBUG_INTR); 1065 return (0); 1066 } 1067 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1068 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1069 /* try to clear the pending interrupt anyway */ 1070 (void)bus_space_read_1(chp->cmd_iot, 1071 chp->cmd_iohs[wd_status], 0); 1072 return (0); 1073 } 1074 1075 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1076 xfer = chp->ch_queue->sc_xfer.tqh_first; 1077 if (chp->ch_flags & WDCF_DMA_WAIT) { 1078 chp->wdc->dma_status = 1079 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1080 xfer->drive, 0); 1081 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1082 /* IRQ not for us, not detected by DMA engine */ 1083 return 0; 1084 } 1085 chp->ch_flags &= ~WDCF_DMA_WAIT; 1086 } 1087 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1088 ret = xfer->c_intr(chp, xfer, 1); 1089 if (ret == 0) /* irq was not for us, still waiting for irq */ 1090 chp->ch_flags |= WDCF_IRQ_WAIT; 1091 return (ret); 1092 } 1093 1094 /* Put all disk in RESET state */ 1095 void 1096 wdc_reset_channel(drvp, flags) 1097 struct ata_drive_datas *drvp; 1098 int flags; 1099 { 1100 struct channel_softc *chp = drvp->chnl_softc; 1101 int drive; 1102 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1103 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1104 DEBUG_FUNCS); 1105 if ((flags & AT_POLL) == 0) { 1106 if (chp->ch_flags & WDCF_TH_RESET) { 1107 /* no need to schedule a reset more than one time */ 1108 return; 1109 } 1110 chp->ch_flags |= WDCF_TH_RESET; 1111 chp->ch_queue->queue_freeze++; 1112 wakeup(&chp->thread); 1113 return; 1114 } 1115 (void) wdcreset(chp, RESET_POLL); 1116 for (drive = 0; drive < 2; drive++) { 1117 chp->ch_drive[drive].state = 0; 1118 } 1119 } 1120 1121 int 1122 wdcreset(chp, poll) 1123 struct channel_softc *chp; 1124 int poll; 1125 { 1126 int drv_mask1, drv_mask2; 1127 int s = 0; 1128 1129 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1130 chp->wdc->select(chp,0); 1131 if (poll != RESET_SLEEP) 1132 s = splbio(); 1133 /* master */ 1134 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1135 delay(10); /* 400ns delay */ 1136 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1137 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1138 delay(2000); 1139 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1140 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1141 WDCTL_4BIT | WDCTL_IDS); 1142 delay(10); /* 400ns delay */ 1143 if (poll != RESET_SLEEP) { 1144 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1145 chp->wdc->irqack(chp); 1146 splx(s); 1147 } 1148 1149 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1150 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1151 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1152 (poll == RESET_SLEEP) ? 0 : 1); 1153 if (drv_mask2 != drv_mask1) { 1154 printf("%s channel %d: reset failed for", 1155 chp->wdc->sc_dev.dv_xname, chp->channel); 1156 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1157 printf(" drive 0"); 1158 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1159 printf(" drive 1"); 1160 printf("\n"); 1161 } 1162 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1163 return (drv_mask1 != drv_mask2) ? 1 : 0; 1164 } 1165 1166 static int 1167 __wdcwait_reset(chp, drv_mask, poll) 1168 struct channel_softc *chp; 1169 int drv_mask; 1170 { 1171 int timeout, nloop; 1172 u_int8_t st0 = 0, st1 = 0; 1173 #ifdef WDCDEBUG 1174 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1175 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1176 #endif 1177 1178 if (poll) 1179 nloop = WDCNDELAY_RST; 1180 else 1181 nloop = WDC_RESET_WAIT * hz / 1000; 1182 /* wait for BSY to deassert */ 1183 for (timeout = 0; timeout < nloop; timeout++) { 1184 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1185 chp->wdc->select(chp,0); 1186 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1187 WDSD_IBM); /* master */ 1188 delay(10); 1189 st0 = bus_space_read_1(chp->cmd_iot, 1190 chp->cmd_iohs[wd_status], 0); 1191 #ifdef WDCDEBUG 1192 sc0 = bus_space_read_1(chp->cmd_iot, 1193 chp->cmd_iohs[wd_seccnt], 0); 1194 sn0 = bus_space_read_1(chp->cmd_iot, 1195 chp->cmd_iohs[wd_sector], 0); 1196 cl0 = bus_space_read_1(chp->cmd_iot, 1197 chp->cmd_iohs[wd_cyl_lo], 0); 1198 ch0 = bus_space_read_1(chp->cmd_iot, 1199 chp->cmd_iohs[wd_cyl_hi], 0); 1200 #endif 1201 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1202 chp->wdc->select(chp,1); 1203 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1204 WDSD_IBM | 0x10); /* slave */ 1205 delay(10); 1206 st1 = bus_space_read_1(chp->cmd_iot, 1207 chp->cmd_iohs[wd_status], 0); 1208 #ifdef WDCDEBUG 1209 sc1 = bus_space_read_1(chp->cmd_iot, 1210 chp->cmd_iohs[wd_seccnt], 0); 1211 sn1 = bus_space_read_1(chp->cmd_iot, 1212 chp->cmd_iohs[wd_sector], 0); 1213 cl1 = bus_space_read_1(chp->cmd_iot, 1214 chp->cmd_iohs[wd_cyl_lo], 0); 1215 ch1 = bus_space_read_1(chp->cmd_iot, 1216 chp->cmd_iohs[wd_cyl_hi], 0); 1217 #endif 1218 1219 if ((drv_mask & 0x01) == 0) { 1220 /* no master */ 1221 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1222 /* No master, slave is ready, it's done */ 1223 goto end; 1224 } 1225 } else if ((drv_mask & 0x02) == 0) { 1226 /* no slave */ 1227 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1228 /* No slave, master is ready, it's done */ 1229 goto end; 1230 } 1231 } else { 1232 /* Wait for both master and slave to be ready */ 1233 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1234 goto end; 1235 } 1236 } 1237 if (poll) 1238 delay(WDCDELAY); 1239 else 1240 tsleep(&nloop, PRIBIO, "atarst", 1); 1241 } 1242 /* Reset timed out. Maybe it's because drv_mask was not right */ 1243 if (st0 & WDCS_BSY) 1244 drv_mask &= ~0x01; 1245 if (st1 & WDCS_BSY) 1246 drv_mask &= ~0x02; 1247 end: 1248 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1249 "cl=0x%x ch=0x%x\n", 1250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1251 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1252 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1253 "cl=0x%x ch=0x%x\n", 1254 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1255 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1256 1257 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1258 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1259 st0, st1), DEBUG_PROBE); 1260 1261 return drv_mask; 1262 } 1263 1264 /* 1265 * Wait for a drive to be !BSY, and have mask in its status register. 1266 * return -1 for a timeout after "timeout" ms. 1267 */ 1268 int 1269 __wdcwait(chp, mask, bits, timeout) 1270 struct channel_softc *chp; 1271 int mask, bits, timeout; 1272 { 1273 u_char status; 1274 int time = 0; 1275 1276 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1277 :"none", chp->channel), DEBUG_STATUS); 1278 chp->ch_error = 0; 1279 1280 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1281 1282 for (;;) { 1283 chp->ch_status = status = 1284 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1285 if ((status & (WDCS_BSY | mask)) == bits) 1286 break; 1287 if (++time > timeout) { 1288 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1289 "status %x error %x (mask 0x%x bits 0x%x)\n", 1290 time, status, 1291 bus_space_read_1(chp->cmd_iot, 1292 chp->cmd_iohs[wd_error], 0), mask, bits), 1293 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1294 return(WDCWAIT_TOUT); 1295 } 1296 delay(WDCDELAY); 1297 } 1298 #ifdef WDCDEBUG 1299 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1300 printf("__wdcwait: did busy-wait, time=%d\n", time); 1301 #endif 1302 if (status & WDCS_ERR) 1303 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1304 chp->cmd_iohs[wd_error], 0); 1305 #ifdef WDCNDELAY_DEBUG 1306 /* After autoconfig, there should be no long delays. */ 1307 if (!cold && time > WDCNDELAY_DEBUG) { 1308 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1309 if (xfer == NULL) 1310 printf("%s channel %d: warning: busy-wait took %dus\n", 1311 chp->wdc->sc_dev.dv_xname, chp->channel, 1312 WDCDELAY * time); 1313 else 1314 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1315 chp->wdc->sc_dev.dv_xname, chp->channel, 1316 xfer->drive, 1317 WDCDELAY * time); 1318 } 1319 #endif 1320 return(WDCWAIT_OK); 1321 } 1322 1323 /* 1324 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1325 * thread if possible 1326 */ 1327 int 1328 wdcwait(chp, mask, bits, timeout, flags) 1329 struct channel_softc *chp; 1330 int mask, bits, timeout, flags; 1331 { 1332 int error, i, timeout_hz = mstohz(timeout); 1333 1334 if (timeout_hz == 0 || 1335 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1336 error = __wdcwait(chp, mask, bits, timeout); 1337 else { 1338 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1339 if (error != 0) { 1340 if ((chp->ch_flags & WDCF_TH_RUN) || 1341 (flags & AT_WAIT)) { 1342 /* 1343 * we're running in the channel thread 1344 * or some userland thread context 1345 */ 1346 for (i = 0; i < timeout_hz; i++) { 1347 if (__wdcwait(chp, mask, bits, 1348 WDCDELAY_POLL) == 0) { 1349 error = 0; 1350 break; 1351 } 1352 tsleep(&chp, PRIBIO, "atapoll", 1); 1353 } 1354 } else { 1355 /* 1356 * we're probably in interrupt context, 1357 * ask the thread to come back here 1358 */ 1359 #ifdef DIAGNOSTIC 1360 if (chp->ch_queue->queue_freeze > 0) 1361 panic("wdcwait: queue_freeze"); 1362 #endif 1363 chp->ch_queue->queue_freeze++; 1364 wakeup(&chp->thread); 1365 return(WDCWAIT_THR); 1366 } 1367 } 1368 } 1369 return(error); 1370 } 1371 1372 1373 /* 1374 * Busy-wait for DMA to complete 1375 */ 1376 int 1377 wdc_dmawait(chp, xfer, timeout) 1378 struct channel_softc *chp; 1379 struct wdc_xfer *xfer; 1380 int timeout; 1381 { 1382 int time; 1383 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1384 chp->wdc->dma_status = 1385 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1386 chp->channel, xfer->drive, 0); 1387 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1388 return 0; 1389 delay(WDCDELAY); 1390 } 1391 /* timeout, force a DMA halt */ 1392 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1393 chp->channel, xfer->drive, 1); 1394 return 1; 1395 } 1396 1397 void 1398 wdctimeout(arg) 1399 void *arg; 1400 { 1401 struct channel_softc *chp = (struct channel_softc *)arg; 1402 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1403 int s; 1404 1405 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1406 1407 s = splbio(); 1408 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1409 __wdcerror(chp, "lost interrupt"); 1410 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1411 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1412 xfer->c_bcount, 1413 xfer->c_skip); 1414 if (chp->ch_flags & WDCF_DMA_WAIT) { 1415 chp->wdc->dma_status = 1416 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1417 chp->channel, xfer->drive, 1); 1418 chp->ch_flags &= ~WDCF_DMA_WAIT; 1419 } 1420 /* 1421 * Call the interrupt routine. If we just missed an interrupt, 1422 * it will do what's needed. Else, it will take the needed 1423 * action (reset the device). 1424 * Before that we need to reinstall the timeout callback, 1425 * in case it will miss another irq while in this transfer 1426 * We arbitray chose it to be 1s 1427 */ 1428 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1429 xfer->c_flags |= C_TIMEOU; 1430 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1431 xfer->c_intr(chp, xfer, 1); 1432 } else 1433 __wdcerror(chp, "missing untimeout"); 1434 splx(s); 1435 } 1436 1437 /* 1438 * Probe drive's capabilities, for use by the controller later 1439 * Assumes drvp points to an existing drive. 1440 * XXX this should be a controller-indep function 1441 */ 1442 void 1443 wdc_probe_caps(drvp) 1444 struct ata_drive_datas *drvp; 1445 { 1446 struct ataparams params, params2; 1447 struct channel_softc *chp = drvp->chnl_softc; 1448 struct device *drv_dev = drvp->drv_softc; 1449 struct wdc_softc *wdc = chp->wdc; 1450 int i, printed; 1451 char *sep = ""; 1452 int cf_flags; 1453 1454 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1455 /* IDENTIFY failed. Can't tell more about the device */ 1456 return; 1457 } 1458 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1459 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1460 /* 1461 * Controller claims 16 and 32 bit transfers. 1462 * Re-do an IDENTIFY with 32-bit transfers, 1463 * and compare results. 1464 */ 1465 drvp->drive_flags |= DRIVE_CAP32; 1466 ata_get_params(drvp, AT_WAIT, ¶ms2); 1467 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1468 /* Not good. fall back to 16bits */ 1469 drvp->drive_flags &= ~DRIVE_CAP32; 1470 } else { 1471 aprint_normal("%s: 32-bit data port\n", 1472 drv_dev->dv_xname); 1473 } 1474 } 1475 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1476 if (params.atap_ata_major > 0x01 && 1477 params.atap_ata_major != 0xffff) { 1478 for (i = 14; i > 0; i--) { 1479 if (params.atap_ata_major & (1 << i)) { 1480 aprint_normal("%s: ATA version %d\n", 1481 drv_dev->dv_xname, i); 1482 drvp->ata_vers = i; 1483 break; 1484 } 1485 } 1486 } 1487 #endif 1488 1489 /* An ATAPI device is at last PIO mode 3 */ 1490 if (drvp->drive_flags & DRIVE_ATAPI) 1491 drvp->PIO_mode = 3; 1492 1493 /* 1494 * It's not in the specs, but it seems that some drive 1495 * returns 0xffff in atap_extensions when this field is invalid 1496 */ 1497 if (params.atap_extensions != 0xffff && 1498 (params.atap_extensions & WDC_EXT_MODES)) { 1499 printed = 0; 1500 /* 1501 * XXX some drives report something wrong here (they claim to 1502 * support PIO mode 8 !). As mode is coded on 3 bits in 1503 * SET FEATURE, limit it to 7 (so limit i to 4). 1504 * If higher mode than 7 is found, abort. 1505 */ 1506 for (i = 7; i >= 0; i--) { 1507 if ((params.atap_piomode_supp & (1 << i)) == 0) 1508 continue; 1509 if (i > 4) 1510 return; 1511 /* 1512 * See if mode is accepted. 1513 * If the controller can't set its PIO mode, 1514 * assume the defaults are good, so don't try 1515 * to set it 1516 */ 1517 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1518 /* 1519 * It's OK to pool here, it's fast enouth 1520 * to not bother waiting for interrupt 1521 */ 1522 if (ata_set_mode(drvp, 0x08 | (i + 3), 1523 AT_WAIT) != CMD_OK) 1524 continue; 1525 if (!printed) { 1526 aprint_normal("%s: drive supports PIO mode %d", 1527 drv_dev->dv_xname, i + 3); 1528 sep = ","; 1529 printed = 1; 1530 } 1531 /* 1532 * If controller's driver can't set its PIO mode, 1533 * get the highter one for the drive. 1534 */ 1535 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1536 wdc->PIO_cap >= i + 3) { 1537 drvp->PIO_mode = i + 3; 1538 drvp->PIO_cap = i + 3; 1539 break; 1540 } 1541 } 1542 if (!printed) { 1543 /* 1544 * We didn't find a valid PIO mode. 1545 * Assume the values returned for DMA are buggy too 1546 */ 1547 return; 1548 } 1549 drvp->drive_flags |= DRIVE_MODE; 1550 printed = 0; 1551 for (i = 7; i >= 0; i--) { 1552 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1553 continue; 1554 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1555 (wdc->cap & WDC_CAPABILITY_MODE)) 1556 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1557 != CMD_OK) 1558 continue; 1559 if (!printed) { 1560 aprint_normal("%s DMA mode %d", sep, i); 1561 sep = ","; 1562 printed = 1; 1563 } 1564 if (wdc->cap & WDC_CAPABILITY_DMA) { 1565 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1566 wdc->DMA_cap < i) 1567 continue; 1568 drvp->DMA_mode = i; 1569 drvp->DMA_cap = i; 1570 drvp->drive_flags |= DRIVE_DMA; 1571 } 1572 break; 1573 } 1574 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1575 printed = 0; 1576 for (i = 7; i >= 0; i--) { 1577 if ((params.atap_udmamode_supp & (1 << i)) 1578 == 0) 1579 continue; 1580 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1581 (wdc->cap & WDC_CAPABILITY_UDMA)) 1582 if (ata_set_mode(drvp, 0x40 | i, 1583 AT_WAIT) != CMD_OK) 1584 continue; 1585 if (!printed) { 1586 aprint_normal("%s Ultra-DMA mode %d", 1587 sep, i); 1588 if (i == 2) 1589 aprint_normal(" (Ultra/33)"); 1590 else if (i == 4) 1591 aprint_normal(" (Ultra/66)"); 1592 else if (i == 5) 1593 aprint_normal(" (Ultra/100)"); 1594 else if (i == 6) 1595 aprint_normal(" (Ultra/133)"); 1596 sep = ","; 1597 printed = 1; 1598 } 1599 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1600 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1601 wdc->UDMA_cap < i) 1602 continue; 1603 drvp->UDMA_mode = i; 1604 drvp->UDMA_cap = i; 1605 drvp->drive_flags |= DRIVE_UDMA; 1606 } 1607 break; 1608 } 1609 } 1610 aprint_normal("\n"); 1611 } 1612 1613 /* Try to guess ATA version here, if it didn't get reported */ 1614 if (drvp->ata_vers == 0) { 1615 if (drvp->drive_flags & DRIVE_UDMA) 1616 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1617 else if (drvp->PIO_cap > 2) 1618 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1619 } 1620 cf_flags = drv_dev->dv_cfdata->cf_flags; 1621 if (cf_flags & ATA_CONFIG_PIO_SET) { 1622 drvp->PIO_mode = 1623 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1624 drvp->drive_flags |= DRIVE_MODE; 1625 } 1626 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1627 /* don't care about DMA modes */ 1628 return; 1629 } 1630 if (cf_flags & ATA_CONFIG_DMA_SET) { 1631 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1632 ATA_CONFIG_DMA_DISABLE) { 1633 drvp->drive_flags &= ~DRIVE_DMA; 1634 } else { 1635 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1636 ATA_CONFIG_DMA_OFF; 1637 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1638 } 1639 } 1640 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1641 /* don't care about UDMA modes */ 1642 return; 1643 } 1644 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1645 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1646 ATA_CONFIG_UDMA_DISABLE) { 1647 drvp->drive_flags &= ~DRIVE_UDMA; 1648 } else { 1649 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1650 ATA_CONFIG_UDMA_OFF; 1651 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1652 } 1653 } 1654 } 1655 1656 /* 1657 * downgrade the transfer mode of a drive after an error. return 1 if 1658 * downgrade was possible, 0 otherwise. 1659 */ 1660 int 1661 wdc_downgrade_mode(drvp, flags) 1662 struct ata_drive_datas *drvp; 1663 { 1664 struct channel_softc *chp = drvp->chnl_softc; 1665 struct device *drv_dev = drvp->drv_softc; 1666 struct wdc_softc *wdc = chp->wdc; 1667 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1668 1669 /* if drive or controller don't know its mode, we can't do much */ 1670 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1671 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1672 return 0; 1673 /* current drive mode was set by a config flag, let it this way */ 1674 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1675 (cf_flags & ATA_CONFIG_DMA_SET) || 1676 (cf_flags & ATA_CONFIG_UDMA_SET)) 1677 return 0; 1678 1679 /* 1680 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1681 * Maybe we didn't properly notice the cable type 1682 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1683 * It helps in some cases. 1684 */ 1685 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1686 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1687 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1688 drv_dev->dv_xname, drvp->UDMA_mode); 1689 } 1690 1691 /* 1692 * If we were using ultra-DMA, don't downgrade to multiword DMA 1693 * if we noticed a CRC error. It has been noticed that CRC errors 1694 * in ultra-DMA lead to silent data corruption in multiword DMA. 1695 * Data corruption is less likely to occur in PIO mode. 1696 */ 1697 else if ((drvp->drive_flags & DRIVE_UDMA) && 1698 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1699 drvp->drive_flags &= ~DRIVE_UDMA; 1700 drvp->drive_flags |= DRIVE_DMA; 1701 drvp->DMA_mode = drvp->DMA_cap; 1702 printf("%s: transfer error, downgrading to DMA mode %d\n", 1703 drv_dev->dv_xname, drvp->DMA_mode); 1704 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1705 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1706 drvp->PIO_mode = drvp->PIO_cap; 1707 printf("%s: transfer error, downgrading to PIO mode %d\n", 1708 drv_dev->dv_xname, drvp->PIO_mode); 1709 } else /* already using PIO, can't downgrade */ 1710 return 0; 1711 1712 wdc->set_modes(chp); 1713 wdc_print_modes(chp); 1714 /* reset the channel, which will shedule all drives for setup */ 1715 wdc_reset_channel(drvp, flags); 1716 return 1; 1717 } 1718 1719 int 1720 wdc_exec_command(drvp, wdc_c) 1721 struct ata_drive_datas *drvp; 1722 struct wdc_command *wdc_c; 1723 { 1724 struct channel_softc *chp = drvp->chnl_softc; 1725 struct wdc_xfer *xfer; 1726 int s, ret; 1727 1728 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1729 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1730 DEBUG_FUNCS); 1731 1732 /* set up an xfer and queue. Wait for completion */ 1733 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1734 WDC_NOSLEEP); 1735 if (xfer == NULL) { 1736 return WDC_TRY_AGAIN; 1737 } 1738 1739 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1740 wdc_c->flags |= AT_POLL; 1741 if (wdc_c->flags & AT_POLL) 1742 xfer->c_flags |= C_POLL; 1743 xfer->drive = drvp->drive; 1744 xfer->databuf = wdc_c->data; 1745 xfer->c_bcount = wdc_c->bcount; 1746 xfer->cmd = wdc_c; 1747 xfer->c_start = __wdccommand_start; 1748 xfer->c_intr = __wdccommand_intr; 1749 xfer->c_kill_xfer = __wdccommand_done; 1750 1751 s = splbio(); 1752 wdc_exec_xfer(chp, xfer); 1753 #ifdef DIAGNOSTIC 1754 if ((wdc_c->flags & AT_POLL) != 0 && 1755 (wdc_c->flags & AT_DONE) == 0) 1756 panic("wdc_exec_command: polled command not done"); 1757 #endif 1758 if (wdc_c->flags & AT_DONE) { 1759 ret = WDC_COMPLETE; 1760 } else { 1761 if (wdc_c->flags & AT_WAIT) { 1762 while ((wdc_c->flags & AT_DONE) == 0) { 1763 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1764 } 1765 ret = WDC_COMPLETE; 1766 } else { 1767 ret = WDC_QUEUED; 1768 } 1769 } 1770 splx(s); 1771 return ret; 1772 } 1773 1774 void 1775 __wdccommand_start(chp, xfer) 1776 struct channel_softc *chp; 1777 struct wdc_xfer *xfer; 1778 { 1779 int drive = xfer->drive; 1780 struct wdc_command *wdc_c = xfer->cmd; 1781 1782 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1783 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1784 DEBUG_FUNCS); 1785 1786 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1787 chp->wdc->select(chp,drive); 1788 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1789 WDSD_IBM | (drive << 4)); 1790 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1791 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1792 case WDCWAIT_OK: 1793 break; 1794 case WDCWAIT_TOUT: 1795 wdc_c->flags |= AT_TIMEOU; 1796 __wdccommand_done(chp, xfer); 1797 return; 1798 case WDCWAIT_THR: 1799 return; 1800 } 1801 if (wdc_c->flags & AT_POLL) { 1802 /* polled command, disable interrupts */ 1803 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1804 WDCTL_4BIT | WDCTL_IDS); 1805 } 1806 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1807 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1808 1809 if ((wdc_c->flags & AT_POLL) == 0) { 1810 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1811 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1812 wdctimeout, chp); 1813 return; 1814 } 1815 /* 1816 * Polled command. Wait for drive ready or drq. Done in intr(). 1817 * Wait for at last 400ns for status bit to be valid. 1818 */ 1819 delay(10); /* 400ns delay */ 1820 __wdccommand_intr(chp, xfer, 0); 1821 } 1822 1823 int 1824 __wdccommand_intr(chp, xfer, irq) 1825 struct channel_softc *chp; 1826 struct wdc_xfer *xfer; 1827 int irq; 1828 { 1829 struct wdc_command *wdc_c = xfer->cmd; 1830 int bcount = wdc_c->bcount; 1831 char *data = wdc_c->data; 1832 int wflags; 1833 1834 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1835 /* both wait and poll, we can tsleep here */ 1836 wflags = AT_WAIT | AT_POLL; 1837 } else { 1838 wflags = AT_POLL; 1839 } 1840 1841 again: 1842 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1843 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1844 /* 1845 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1846 * Reselect again, it doesn't hurt for others commands, and the time 1847 * penalty for the extra regiter write is acceptable, 1848 * wdc_exec_command() isn't called often (mosly for autoconfig) 1849 */ 1850 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1851 WDSD_IBM | (xfer->drive << 4)); 1852 if ((wdc_c->flags & AT_XFDONE) != 0) { 1853 /* 1854 * We have completed a data xfer. The drive should now be 1855 * in its initial state 1856 */ 1857 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1858 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1859 wflags) == WDCWAIT_TOUT) { 1860 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1861 return 0; /* IRQ was not for us */ 1862 wdc_c->flags |= AT_TIMEOU; 1863 } 1864 goto out; 1865 } 1866 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1867 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1868 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1869 return 0; /* IRQ was not for us */ 1870 wdc_c->flags |= AT_TIMEOU; 1871 goto out; 1872 } 1873 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1874 chp->wdc->irqack(chp); 1875 if (wdc_c->flags & AT_READ) { 1876 if ((chp->ch_status & WDCS_DRQ) == 0) { 1877 wdc_c->flags |= AT_TIMEOU; 1878 goto out; 1879 } 1880 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1881 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1882 0, (u_int32_t*)data, bcount >> 2); 1883 data += bcount & 0xfffffffc; 1884 bcount = bcount & 0x03; 1885 } 1886 if (bcount > 0) 1887 bus_space_read_multi_2(chp->cmd_iot, 1888 chp->cmd_iohs[wd_data], 0, 1889 (u_int16_t *)data, bcount >> 1); 1890 /* at this point the drive should be in its initial state */ 1891 wdc_c->flags |= AT_XFDONE; 1892 /* XXX should read status register here ? */ 1893 } else if (wdc_c->flags & AT_WRITE) { 1894 if ((chp->ch_status & WDCS_DRQ) == 0) { 1895 wdc_c->flags |= AT_TIMEOU; 1896 goto out; 1897 } 1898 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1899 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1900 0, (u_int32_t*)data, bcount >> 2); 1901 data += bcount & 0xfffffffc; 1902 bcount = bcount & 0x03; 1903 } 1904 if (bcount > 0) 1905 bus_space_write_multi_2(chp->cmd_iot, 1906 chp->cmd_iohs[wd_data], 0, 1907 (u_int16_t *)data, bcount >> 1); 1908 wdc_c->flags |= AT_XFDONE; 1909 if ((wdc_c->flags & AT_POLL) == 0) { 1910 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1911 callout_reset(&chp->ch_callout, 1912 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1913 return 1; 1914 } else { 1915 goto again; 1916 } 1917 } 1918 out: 1919 __wdccommand_done(chp, xfer); 1920 return 1; 1921 } 1922 1923 void 1924 __wdccommand_done(chp, xfer) 1925 struct channel_softc *chp; 1926 struct wdc_xfer *xfer; 1927 { 1928 struct wdc_command *wdc_c = xfer->cmd; 1929 1930 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1931 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1932 1933 callout_stop(&chp->ch_callout); 1934 1935 if (chp->ch_status & WDCS_DWF) 1936 wdc_c->flags |= AT_DF; 1937 if (chp->ch_status & WDCS_ERR) { 1938 wdc_c->flags |= AT_ERROR; 1939 wdc_c->r_error = chp->ch_error; 1940 } 1941 wdc_c->flags |= AT_DONE; 1942 if ((wdc_c->flags & AT_READREG) != 0 && 1943 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1944 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1945 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1946 chp->cmd_iohs[wd_sdh], 0); 1947 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1948 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1949 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1950 chp->cmd_iohs[wd_cyl_lo], 0); 1951 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1952 chp->cmd_iohs[wd_sector], 0); 1953 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1954 chp->cmd_iohs[wd_seccnt], 0); 1955 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1956 chp->cmd_iohs[wd_error], 0); 1957 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1958 chp->cmd_iohs[wd_precomp], 0); 1959 } 1960 1961 if (wdc_c->flags & AT_POLL) { 1962 /* enable interrupts */ 1963 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1964 WDCTL_4BIT); 1965 } 1966 wdc_free_xfer(chp, xfer); 1967 if (wdc_c->flags & AT_WAIT) 1968 wakeup(wdc_c); 1969 else if (wdc_c->callback) 1970 wdc_c->callback(wdc_c->callback_arg); 1971 wdcstart(chp); 1972 return; 1973 } 1974 1975 /* 1976 * Send a command. The drive should be ready. 1977 * Assumes interrupts are blocked. 1978 */ 1979 void 1980 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1981 struct channel_softc *chp; 1982 u_int8_t drive; 1983 u_int8_t command; 1984 u_int16_t cylin; 1985 u_int8_t head, sector, count, precomp; 1986 { 1987 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1988 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1989 chp->channel, drive, command, cylin, head, sector, count, precomp), 1990 DEBUG_FUNCS); 1991 1992 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1993 chp->wdc->select(chp,drive); 1994 1995 /* Select drive, head, and addressing mode. */ 1996 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1997 WDSD_IBM | (drive << 4) | head); 1998 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1999 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 2000 precomp); 2001 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 2003 0, cylin >> 8); 2004 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2006 2007 /* Send command. */ 2008 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2009 return; 2010 } 2011 2012 /* 2013 * Send a 48-bit addressing command. The drive should be ready. 2014 * Assumes interrupts are blocked. 2015 */ 2016 void 2017 wdccommandext(chp, drive, command, blkno, count) 2018 struct channel_softc *chp; 2019 u_int8_t drive; 2020 u_int8_t command; 2021 u_int64_t blkno; 2022 u_int16_t count; 2023 { 2024 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2025 "count=%d\n", chp->wdc->sc_dev.dv_xname, 2026 chp->channel, drive, command, (u_int32_t) blkno, count), 2027 DEBUG_FUNCS); 2028 2029 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2030 chp->wdc->select(chp,drive); 2031 2032 /* Select drive, head, and addressing mode. */ 2033 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2034 (drive << 4) | WDSD_LBA); 2035 2036 /* previous */ 2037 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2038 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 2039 0, count >> 8); 2040 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2041 0, blkno >> 40); 2042 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2043 0, blkno >> 32); 2044 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 2045 0, blkno >> 24); 2046 2047 /* current */ 2048 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2049 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2050 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2051 0, blkno >> 16); 2052 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2053 0, blkno >> 8); 2054 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2055 2056 /* Send command. */ 2057 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2058 return; 2059 } 2060 2061 /* 2062 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2063 * tested by the caller. 2064 */ 2065 void 2066 wdccommandshort(chp, drive, command) 2067 struct channel_softc *chp; 2068 int drive; 2069 int command; 2070 { 2071 2072 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2073 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2074 DEBUG_FUNCS); 2075 2076 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2077 chp->wdc->select(chp,drive); 2078 2079 /* Select drive. */ 2080 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2081 WDSD_IBM | (drive << 4)); 2082 2083 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2084 } 2085 2086 /* Add a command to the queue and start controller. Must be called at splbio */ 2087 2088 void 2089 wdc_exec_xfer(chp, xfer) 2090 struct channel_softc *chp; 2091 struct wdc_xfer *xfer; 2092 { 2093 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2094 chp->channel, xfer->drive), DEBUG_XFERS); 2095 2096 /* complete xfer setup */ 2097 xfer->chp = chp; 2098 2099 /* 2100 * If we are a polled command, and the list is not empty, 2101 * we are doing a dump. Drop the list to allow the polled command 2102 * to complete, we're going to reboot soon anyway. 2103 */ 2104 if ((xfer->c_flags & C_POLL) != 0 && 2105 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2106 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2107 } 2108 /* insert at the end of command list */ 2109 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2110 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2111 chp->ch_flags), DEBUG_XFERS); 2112 wdcstart(chp); 2113 } 2114 2115 struct wdc_xfer * 2116 wdc_get_xfer(flags) 2117 int flags; 2118 { 2119 struct wdc_xfer *xfer; 2120 int s; 2121 2122 s = splbio(); 2123 xfer = pool_get(&wdc_xfer_pool, 2124 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2125 splx(s); 2126 if (xfer != NULL) { 2127 memset(xfer, 0, sizeof(struct wdc_xfer)); 2128 } 2129 return xfer; 2130 } 2131 2132 void 2133 wdc_free_xfer(chp, xfer) 2134 struct channel_softc *chp; 2135 struct wdc_xfer *xfer; 2136 { 2137 struct wdc_softc *wdc = chp->wdc; 2138 int s; 2139 2140 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2141 (*wdc->free_hw)(chp); 2142 s = splbio(); 2143 chp->ch_flags &= ~WDCF_ACTIVE; 2144 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2145 pool_put(&wdc_xfer_pool, xfer); 2146 splx(s); 2147 } 2148 2149 /* 2150 * Kill off all pending xfers for a channel_softc. 2151 * 2152 * Must be called at splbio(). 2153 */ 2154 void 2155 wdc_kill_pending(chp) 2156 struct channel_softc *chp; 2157 { 2158 struct wdc_xfer *xfer; 2159 2160 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2161 chp = xfer->chp; 2162 (*xfer->c_kill_xfer)(chp, xfer); 2163 } 2164 } 2165 2166 static void 2167 __wdcerror(chp, msg) 2168 struct channel_softc *chp; 2169 char *msg; 2170 { 2171 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2172 2173 if (xfer == NULL) 2174 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2175 msg); 2176 else 2177 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2178 chp->channel, xfer->drive, msg); 2179 } 2180 2181 /* 2182 * the bit bucket 2183 */ 2184 void 2185 wdcbit_bucket(chp, size) 2186 struct channel_softc *chp; 2187 int size; 2188 { 2189 2190 for (; size >= 2; size -= 2) 2191 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2192 if (size) 2193 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2194 } 2195 2196 int 2197 wdc_addref(chp) 2198 struct channel_softc *chp; 2199 { 2200 struct wdc_softc *wdc = chp->wdc; 2201 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2202 int s, error = 0; 2203 2204 s = splbio(); 2205 if (adapt->adapt_refcnt++ == 0 && 2206 adapt->adapt_enable != NULL) { 2207 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2208 if (error) 2209 adapt->adapt_refcnt--; 2210 } 2211 splx(s); 2212 return (error); 2213 } 2214 2215 void 2216 wdc_delref(chp) 2217 struct channel_softc *chp; 2218 { 2219 struct wdc_softc *wdc = chp->wdc; 2220 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2221 int s; 2222 2223 s = splbio(); 2224 if (adapt->adapt_refcnt-- == 1 && 2225 adapt->adapt_enable != NULL) 2226 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2227 splx(s); 2228 } 2229 2230 void 2231 wdc_print_modes(struct channel_softc *chp) 2232 { 2233 int drive; 2234 struct ata_drive_datas *drvp; 2235 2236 for (drive = 0; drive < 2; drive++) { 2237 drvp = &chp->ch_drive[drive]; 2238 if ((drvp->drive_flags & DRIVE) == 0) 2239 continue; 2240 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2241 drvp->drv_softc->dv_xname, 2242 chp->wdc->sc_dev.dv_xname, 2243 chp->channel, drive, drvp->PIO_mode); 2244 if (drvp->drive_flags & DRIVE_DMA) 2245 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2246 if (drvp->drive_flags & DRIVE_UDMA) { 2247 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2248 if (drvp->UDMA_mode == 2) 2249 aprint_normal(" (Ultra/33)"); 2250 else if (drvp->UDMA_mode == 4) 2251 aprint_normal(" (Ultra/66)"); 2252 else if (drvp->UDMA_mode == 5) 2253 aprint_normal(" (Ultra/100)"); 2254 else if (drvp->UDMA_mode == 6) 2255 aprint_normal(" (Ultra/133)"); 2256 } 2257 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2258 aprint_normal(" (using DMA data transfers)"); 2259 aprint_normal("\n"); 2260 } 2261 } 2262
Indexes created Fri Sep 26 08:10:20 GMT 2025