wdc.c revision 1.161
1 /* $NetBSD: wdc.c,v 1.161 2003/12/15 00:27:13 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.161 2003/12/15 00:27:13 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/kthread.h> 83 #include <sys/conf.h> 84 #include <sys/buf.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/pool.h> 88 #include <sys/syslog.h> 89 #include <sys/proc.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "locators.h" 107 108 #include "ataraid.h" 109 #include "atapibus.h" 110 #include "wd.h" 111 112 #if NATARAID > 0 113 #include <dev/ata/ata_raidvar.h> 114 #endif 115 116 #define WDCDELAY 100 /* 100 microseconds */ 117 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 118 #if 0 119 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 120 #define WDCNDELAY_DEBUG 50 121 #endif 122 123 /* When polling wait that much and then tsleep for 1/hz seconds */ 124 #define WDCDELAY_POLL 1 /* ms */ 125 126 /* timeout for the control commands */ 127 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 128 129 struct pool wdc_xfer_pool; 130 131 #if NWD > 0 132 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 133 #else 134 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 135 const struct ata_bustype wdc_ata_bustype = { 136 SCSIPI_BUSTYPE_ATA, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL, 143 NULL 144 }; 145 #endif 146 147 int atabusmatch __P((struct device *, struct cfdata *, void *)); 148 void atabusattach __P((struct device *, struct device *, void *)); 149 void atabus_create_thread __P((void *)); 150 void atabus_thread __P((void *)); 151 void atabusconfig __P((struct atabus_softc *)); 152 int atabusactivate __P((struct device *, enum devact)); 153 int atabusdetach __P((struct device *, int flags)); 154 int atabusprint __P((void *, const char *)); 155 156 CFATTACH_DECL(atabus, sizeof(struct atabus_softc), 157 atabusmatch, atabusattach, atabusdetach, atabusactivate); 158 159 struct atabus_initq { 160 struct atabus_softc *atabus_sc; 161 TAILQ_ENTRY(atabus_initq) atabus_initq; 162 }; 163 static TAILQ_HEAD(, atabus_initq) atabus_initq_head = 164 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 165 static struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 166 167 int wdcprobe1 __P((struct channel_softc*, int)); 168 static void __wdcerror __P((struct channel_softc*, char *)); 169 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 170 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 171 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 172 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 173 int __wdcwait __P((struct channel_softc *, int, int, int)); 174 int wdprint __P((void *, const char *)); 175 void wdc_finish_attach __P((struct device *)); 176 void wdc_channel_attach __P((struct channel_softc *)); 177 178 #define DEBUG_INTR 0x01 179 #define DEBUG_XFERS 0x02 180 #define DEBUG_STATUS 0x04 181 #define DEBUG_FUNCS 0x08 182 #define DEBUG_PROBE 0x10 183 #define DEBUG_DETACH 0x20 184 #define DEBUG_DELAY 0x40 185 #ifdef WDCDEBUG 186 int wdcdebug_mask = 0; 187 int wdc_nxfer = 0; 188 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 189 #else 190 #define WDCDEBUG_PRINT(args, level) 191 #endif 192 193 int 194 atabusprint(aux, pnp) 195 void *aux; 196 const char *pnp; 197 { 198 struct channel_softc *chan = aux; 199 if (pnp) 200 aprint_normal("atabus at %s", pnp); 201 aprint_normal(" channel %d", chan->channel); 202 return (UNCONF); 203 } 204 205 int 206 atabusmatch(parent, cf, aux) 207 struct device *parent; 208 struct cfdata *cf; 209 void *aux; 210 { 211 struct channel_softc *chp = aux; 212 213 if (chp == NULL) 214 return (0); 215 216 if (cf->cf_loc[ATACF_CHANNEL] != chp->channel && 217 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT) 218 return (0); 219 220 return (1); 221 } 222 223 void 224 atabusattach(parent, self, aux) 225 struct device *parent, *self; 226 void *aux; 227 { 228 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 229 struct channel_softc *chp = aux; 230 struct atabus_initq *atabus_initq; 231 232 atabus_sc->sc_chan = chp; 233 234 aprint_normal("\n"); 235 aprint_naive("\n"); 236 atabus_initq = malloc(sizeof(struct atabus_initq), M_DEVBUF, M_NOWAIT); 237 atabus_initq->atabus_sc = atabus_sc; 238 TAILQ_INSERT_TAIL(&atabus_initq_head, atabus_initq, atabus_initq); 239 config_pending_incr(); 240 kthread_create(atabus_create_thread, atabus_sc); 241 242 } 243 244 void 245 atabus_create_thread(arg) 246 void *arg; 247 { 248 struct atabus_softc *atabus_sc = arg; 249 struct channel_softc *chp = atabus_sc->sc_chan; 250 int error; 251 252 if ((error = kthread_create1(atabus_thread, atabus_sc, &chp->thread, 253 "%s", atabus_sc->sc_dev.dv_xname)) != 0) 254 printf("unable to create kernel thread for %s: error %d\n", 255 atabus_sc->sc_dev.dv_xname, error); 256 } 257 258 void 259 atabus_thread(arg) 260 void *arg; 261 { 262 struct atabus_softc *atabus_sc = arg; 263 struct channel_softc *chp = atabus_sc->sc_chan; 264 struct wdc_xfer *xfer; 265 int s; 266 267 s = splbio(); 268 chp->ch_flags |= WDCF_TH_RUN; 269 splx(s); 270 atabusconfig(atabus_sc); 271 for(;;) { 272 s = splbio(); 273 if ((chp->ch_flags & (WDCF_TH_RESET | WDCF_SHUTDOWN)) == 0 && 274 ((chp->ch_flags & WDCF_ACTIVE) == 0 || 275 chp->ch_queue->queue_freeze == 0)) { 276 chp->ch_flags &= ~WDCF_TH_RUN; 277 tsleep(&chp->thread, PRIBIO, "atath", 0); 278 chp->ch_flags |= WDCF_TH_RUN; 279 } 280 splx(s); 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 break; 283 s = splbio(); 284 if (chp->ch_flags & WDCF_TH_RESET) { 285 int drive; 286 (void) wdcreset(chp, RESET_SLEEP); 287 for (drive = 0; drive < 2; drive++) { 288 chp->ch_drive[drive].state = 0; 289 } 290 chp->ch_flags &= ~WDCF_TH_RESET; 291 chp->ch_queue->queue_freeze--; 292 wdcstart(chp); 293 } else if ((chp->ch_flags & WDCF_ACTIVE) != 0 && 294 chp->ch_queue->queue_freeze == 1) { 295 /* 296 * caller has bumped queue_freeze, decrease it 297 */ 298 chp->ch_queue->queue_freeze--; 299 xfer = chp->ch_queue->sc_xfer.tqh_first; 300 #ifdef DIAGNOSTIC 301 if (xfer == NULL) 302 panic("channel active with no xfer ?"); 303 #endif 304 xfer->c_start(chp, xfer); 305 } else if (chp->ch_queue->queue_freeze > 1) { 306 panic("queue_freeze"); 307 } 308 splx(s); 309 } 310 chp->thread = NULL; 311 wakeup(&chp->ch_flags); 312 kthread_exit(0); 313 } 314 315 void 316 atabusconfig(atabus_sc) 317 struct atabus_softc *atabus_sc; 318 { 319 struct channel_softc *chp = atabus_sc->sc_chan; 320 int i, error, need_delref = 0; 321 struct ataparams params; 322 struct atabus_initq *atabus_initq = NULL; 323 u_int8_t st0 = 0, st1 = 0; 324 325 if ((error = wdc_addref(chp)) != 0) { 326 aprint_error("%s: unable to enable controller\n", 327 chp->wdc->sc_dev.dv_xname); 328 goto out; 329 } 330 need_delref = 1; 331 332 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_DRVPROBE) != 0) { 333 if ((*chp->wdc->drv_probe)(chp) == 0) { 334 /* If no drives, abort attach here. */ 335 goto out; 336 } 337 } else if (wdcprobe1(chp, 0) == 0) { 338 /* If no drives, abort attach here. */ 339 goto out; 340 } 341 342 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 343 for (i = 0; i < mstohz(3000); i++) { 344 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 345 chp->wdc->select(chp,0); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 347 WDSD_IBM); 348 delay(10); /* 400ns delay */ 349 st0 = bus_space_read_1(chp->cmd_iot, 350 chp->cmd_iohs[wd_status], 0); 351 352 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 353 chp->wdc->select(chp,1); 354 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 355 WDSD_IBM | 0x10); 356 delay(10); /* 400ns delay */ 357 st1 = bus_space_read_1(chp->cmd_iot, 358 chp->cmd_iohs[wd_status], 0); 359 360 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 361 == 0 || 362 (st0 & WDCS_DRDY)) && 363 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 364 == 0 || 365 (st1 & WDCS_DRDY))) 366 break; 367 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 368 } 369 if ((st0 & WDCS_DRDY) == 0) 370 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 371 if ((st1 & WDCS_DRDY) == 0) 372 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 373 374 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 375 chp->wdc->sc_dev.dv_xname, 376 chp->channel, st0, st1), DEBUG_PROBE); 377 378 /* Wait a bit, some devices are weird just after a reset. */ 379 delay(5000); 380 381 for (i = 0; i < 2; i++) { 382 chp->ch_drive[i].chnl_softc = chp; 383 chp->ch_drive[i].drive = i; 384 /* 385 * Init error counter so that an error withing the first xfers 386 * will trigger a downgrade 387 */ 388 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 389 390 /* If controller can't do 16bit flag the drives as 32bit */ 391 if ((chp->wdc->cap & 392 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 393 WDC_CAPABILITY_DATA32) 394 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 395 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 396 continue; 397 398 /* Shortcut in case we've been shutdown */ 399 if (chp->ch_flags & WDCF_SHUTDOWN) 400 goto out; 401 402 /* issue an identify, to try to detect ghosts */ 403 error = ata_get_params(&chp->ch_drive[i], 404 AT_WAIT | AT_POLL, ¶ms); 405 if (error != CMD_OK) { 406 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 407 408 /* Shortcut in case we've been shutdown */ 409 if (chp->ch_flags & WDCF_SHUTDOWN) 410 goto out; 411 412 error = ata_get_params(&chp->ch_drive[i], 413 AT_WAIT | AT_POLL, ¶ms); 414 } 415 if (error == CMD_OK) { 416 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 417 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 418 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 419 } else { 420 chp->ch_drive[i].drive_flags &= 421 ~(DRIVE_ATA | DRIVE_ATAPI); 422 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 423 chp->wdc->sc_dev.dv_xname, 424 chp->channel, i, error), DEBUG_PROBE); 425 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 426 continue; 427 /* 428 * Pre-ATA drive ? 429 * Test registers writability (Error register not 430 * writable, but cyllo is), then try an ATA command. 431 */ 432 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 433 chp->wdc->select(chp,i); 434 bus_space_write_1(chp->cmd_iot, 435 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 436 delay(10); /* 400ns delay */ 437 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 438 0, 0x58); 439 bus_space_write_1(chp->cmd_iot, 440 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 441 if (bus_space_read_1(chp->cmd_iot, 442 chp->cmd_iohs[wd_error], 0) == 0x58 || 443 bus_space_read_1(chp->cmd_iot, 444 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 445 WDCDEBUG_PRINT(("%s:%d:%d: register " 446 "writability failed\n", 447 chp->wdc->sc_dev.dv_xname, 448 chp->channel, i), DEBUG_PROBE); 449 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 450 continue; 451 } 452 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 453 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 454 chp->wdc->sc_dev.dv_xname, 455 chp->channel, i), DEBUG_PROBE); 456 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 457 continue; 458 } 459 bus_space_write_1(chp->cmd_iot, 460 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 461 delay(10); /* 400ns delay */ 462 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 463 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 464 chp->wdc->sc_dev.dv_xname, 465 chp->channel, i), DEBUG_PROBE); 466 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 467 } else { 468 chp->ch_drive[0].drive_flags &= 469 ~(DRIVE_ATA | DRIVE_ATAPI); 470 chp->ch_drive[1].drive_flags &= 471 ~(DRIVE_ATA | DRIVE_ATAPI); 472 } 473 } 474 } 475 476 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 477 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 478 DEBUG_PROBE); 479 480 /* If no drives, abort here */ 481 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 482 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 483 goto out; 484 485 /* Make sure the devices probe in atabus order to avoid jitter. */ 486 simple_lock(&atabus_interlock); 487 while(1) { 488 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 489 if (atabus_initq->atabus_sc == atabus_sc) 490 break; 491 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 492 &atabus_interlock); 493 } 494 simple_unlock(&atabus_interlock); 495 496 /* 497 * Attach an ATAPI bus, if needed. 498 */ 499 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 500 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 501 #if NATAPIBUS > 0 502 wdc_atapibus_attach(atabus_sc); 503 #else 504 /* 505 * Fake the autoconfig "not configured" message 506 */ 507 aprint_normal("atapibus at %s not configured\n", 508 chp->wdc->sc_dev.dv_xname); 509 chp->atapibus = NULL; 510 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 511 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 512 #endif 513 } 514 515 for (i = 0; i < 2; i++) { 516 struct ata_device adev; 517 if ((chp->ch_drive[i].drive_flags & 518 (DRIVE_ATA | DRIVE_OLD)) == 0) { 519 continue; 520 } 521 memset(&adev, 0, sizeof(struct ata_device)); 522 adev.adev_bustype = &wdc_ata_bustype; 523 adev.adev_channel = chp->channel; 524 adev.adev_openings = 1; 525 adev.adev_drv_data = &chp->ch_drive[i]; 526 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 527 &adev, wdprint); 528 if (chp->ata_drives[i] != NULL) 529 wdc_probe_caps(&chp->ch_drive[i]); 530 else 531 chp->ch_drive[i].drive_flags &= 532 ~(DRIVE_ATA | DRIVE_OLD); 533 } 534 535 /* now that we know the drives, the controller can set its modes */ 536 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 537 chp->wdc->set_modes(chp); 538 wdc_print_modes(chp); 539 } 540 #if NATARAID > 0 541 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 542 for (i = 0; i < 2; i++) 543 if (chp->ata_drives[i] != NULL) 544 ata_raid_check_component(chp->ata_drives[i]); 545 #endif /* NATARAID > 0 */ 546 547 /* 548 * reset drive_flags for unattached devices, reset state for attached 549 * ones 550 */ 551 for (i = 0; i < 2; i++) { 552 if (chp->ch_drive[i].drv_softc == NULL) 553 chp->ch_drive[i].drive_flags = 0; 554 else 555 chp->ch_drive[i].state = 0; 556 } 557 558 out: 559 if (atabus_initq == NULL) { 560 simple_lock(&atabus_interlock); 561 while(1) { 562 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 563 if (atabus_initq->atabus_sc == atabus_sc) 564 break; 565 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 566 &atabus_interlock); 567 } 568 simple_unlock(&atabus_interlock); 569 } 570 simple_lock(&atabus_interlock); 571 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 572 simple_unlock(&atabus_interlock); 573 574 free(atabus_initq, M_DEVBUF); 575 wakeup(&atabus_initq_head); 576 577 config_pending_decr(); 578 if (need_delref) 579 wdc_delref(chp); 580 } 581 582 583 int 584 wdprint(aux, pnp) 585 void *aux; 586 const char *pnp; 587 { 588 struct ata_device *adev = aux; 589 if (pnp) 590 aprint_normal("wd at %s", pnp); 591 aprint_normal(" drive %d", adev->adev_drv_data->drive); 592 return (UNCONF); 593 } 594 595 /* Test to see controller with at last one attached drive is there. 596 * Returns a bit for each possible drive found (0x01 for drive 0, 597 * 0x02 for drive 1). 598 * Logic: 599 * - If a status register is at 0xff, assume there is no drive here 600 * (ISA has pull-up resistors). Similarly if the status register has 601 * the value we last wrote to the bus (for IDE interfaces without pullups). 602 * If no drive at all -> return. 603 * - reset the controller, wait for it to complete (may take up to 31s !). 604 * If timeout -> return. 605 * - test ATA/ATAPI signatures. If at last one drive found -> return. 606 * - try an ATA command on the master. 607 */ 608 609 int 610 wdcprobe(chp) 611 struct channel_softc *chp; 612 { 613 return wdcprobe1(chp, 1); 614 } 615 616 int 617 wdcprobe1(chp, poll) 618 struct channel_softc *chp; 619 int poll; 620 { 621 u_int8_t st0, st1, sc, sn, cl, ch; 622 u_int8_t ret_value = 0x03; 623 u_int8_t drive; 624 int s; 625 626 /* 627 * Sanity check to see if the wdc channel responds at all. 628 */ 629 630 if (chp->wdc == NULL || 631 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 632 633 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 634 chp->wdc->select(chp,0); 635 636 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 637 WDSD_IBM); 638 delay(10); /* 400ns delay */ 639 st0 = bus_space_read_1(chp->cmd_iot, 640 chp->cmd_iohs[wd_status], 0); 641 642 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 643 chp->wdc->select(chp,1); 644 645 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 646 WDSD_IBM | 0x10); 647 delay(10); /* 400ns delay */ 648 st1 = bus_space_read_1(chp->cmd_iot, 649 chp->cmd_iohs[wd_status], 0); 650 651 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 652 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 653 chp->channel, st0, st1), DEBUG_PROBE); 654 655 if (st0 == 0xff || st0 == WDSD_IBM) 656 ret_value &= ~0x01; 657 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 658 ret_value &= ~0x02; 659 /* Register writability test, drive 0. */ 660 if (ret_value & 0x01) { 661 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 662 chp->wdc->select(chp,0); 663 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 664 0, WDSD_IBM); 665 bus_space_write_1(chp->cmd_iot, 666 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 667 if (bus_space_read_1(chp->cmd_iot, 668 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 669 ret_value &= ~0x01; 670 bus_space_write_1(chp->cmd_iot, 671 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 672 if (bus_space_read_1(chp->cmd_iot, 673 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 674 ret_value &= ~0x01; 675 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 676 0, 0x01); 677 if (bus_space_read_1(chp->cmd_iot, 678 chp->cmd_iohs[wd_sector], 0) != 0x01) 679 ret_value &= ~0x01; 680 bus_space_write_1(chp->cmd_iot, 681 chp->cmd_iohs[wd_sector], 0, 0x02); 682 if (bus_space_read_1(chp->cmd_iot, 683 chp->cmd_iohs[wd_sector], 0) != 0x02) 684 ret_value &= ~0x01; 685 if (bus_space_read_1(chp->cmd_iot, 686 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 687 ret_value &= ~0x01; 688 } 689 /* Register writability test, drive 1. */ 690 if (ret_value & 0x02) { 691 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 692 chp->wdc->select(chp,1); 693 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 694 0, WDSD_IBM | 0x10); 695 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 696 0, 0x02); 697 if (bus_space_read_1(chp->cmd_iot, 698 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 699 ret_value &= ~0x02; 700 bus_space_write_1(chp->cmd_iot, 701 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 702 if (bus_space_read_1(chp->cmd_iot, 703 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 704 ret_value &= ~0x02; 705 bus_space_write_1(chp->cmd_iot, 706 chp->cmd_iohs[wd_sector], 0, 0x01); 707 if (bus_space_read_1(chp->cmd_iot, 708 chp->cmd_iohs[wd_sector], 0) != 0x01) 709 ret_value &= ~0x02; 710 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 711 0, 0x02); 712 if (bus_space_read_1(chp->cmd_iot, 713 chp->cmd_iohs[wd_sector], 0) != 0x02) 714 ret_value &= ~0x02; 715 if (bus_space_read_1(chp->cmd_iot, 716 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 717 ret_value &= ~0x02; 718 } 719 720 if (ret_value == 0) 721 return 0; 722 } 723 724 s = splbio(); 725 726 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 727 chp->wdc->select(chp,0); 728 /* assert SRST, wait for reset to complete */ 729 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 730 delay(10); /* 400ns delay */ 731 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 732 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 733 DELAY(2000); 734 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 735 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 736 delay(10); /* 400ns delay */ 737 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 738 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_IRQACK)) 739 chp->wdc->irqack(chp); 740 splx(s); 741 742 ret_value = __wdcwait_reset(chp, ret_value, poll); 743 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 744 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 745 ret_value), DEBUG_PROBE); 746 747 /* if reset failed, there's nothing here */ 748 if (ret_value == 0) 749 return 0; 750 751 /* 752 * Test presence of drives. First test register signatures looking for 753 * ATAPI devices. If it's not an ATAPI and reset said there may be 754 * something here assume it's ATA or OLD. Ghost will be killed later in 755 * attach routine. 756 */ 757 for (drive = 0; drive < 2; drive++) { 758 if ((ret_value & (0x01 << drive)) == 0) 759 continue; 760 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 761 chp->wdc->select(chp,drive); 762 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 763 WDSD_IBM | (drive << 4)); 764 delay(10); /* 400ns delay */ 765 /* Save registers contents */ 766 sc = bus_space_read_1(chp->cmd_iot, 767 chp->cmd_iohs[wd_seccnt], 0); 768 sn = bus_space_read_1(chp->cmd_iot, 769 chp->cmd_iohs[wd_sector], 0); 770 cl = bus_space_read_1(chp->cmd_iot, 771 chp->cmd_iohs[wd_cyl_lo], 0); 772 ch = bus_space_read_1(chp->cmd_iot, 773 chp->cmd_iohs[wd_cyl_hi], 0); 774 775 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 776 "cl=0x%x ch=0x%x\n", 777 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 778 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 779 /* 780 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 781 * we get wrong values here, so ignore it. 782 */ 783 if (cl == 0x14 && ch == 0xeb) { 784 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 785 } else { 786 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 787 if (chp->wdc == NULL || 788 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 789 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 790 } 791 } 792 return (ret_value); 793 } 794 795 void 796 wdcattach(chp) 797 struct channel_softc *chp; 798 { 799 static int inited = 0; 800 801 if (chp->ch_flags & WDCF_DISABLED) 802 return; 803 804 /* initialise global data */ 805 callout_init(&chp->ch_callout); 806 if (inited == 0) { 807 /* Initialize the wdc_xfer pool. */ 808 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 809 0, 0, "wdcspl", NULL); 810 inited++; 811 } 812 TAILQ_INIT(&chp->ch_queue->sc_xfer); 813 chp->ch_queue->queue_freeze = 0; 814 815 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 816 } 817 818 /* 819 * Call activate routine of underlying devices. 820 */ 821 int 822 atabusactivate(self, act) 823 struct device *self; 824 enum devact act; 825 { 826 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 827 struct channel_softc *chp = atabus_sc->sc_chan; 828 struct device *sc = 0; 829 int s, i, error = 0; 830 831 s = splbio(); 832 switch (act) { 833 case DVACT_ACTIVATE: 834 error = EOPNOTSUPP; 835 break; 836 837 case DVACT_DEACTIVATE: 838 /* 839 * We might call deactivate routine for 840 * the children of atapibus twice (once via 841 * atapibus, once directly), but since 842 * config_deactivate maintains DVF_ACTIVE flag, 843 * it's safe. 844 */ 845 sc = chp->atapibus; 846 if (sc != NULL) { 847 error = config_deactivate(sc); 848 if (error != 0) 849 goto out; 850 } 851 852 for (i = 0; i < 2; i++) { 853 sc = chp->ch_drive[i].drv_softc; 854 WDCDEBUG_PRINT(("atabusactivate: %s:" 855 " deactivating %s\n", atabus_sc->sc_dev.dv_xname, 856 sc == NULL ? "nodrv" : sc->dv_xname), 857 DEBUG_DETACH); 858 if (sc != NULL) { 859 error = config_deactivate(sc); 860 if (error != 0) 861 goto out; 862 } 863 } 864 break; 865 } 866 867 out: 868 splx(s); 869 870 #ifdef WDCDEBUG 871 if (sc && error != 0) 872 WDCDEBUG_PRINT(("atabusactivate: %s: " 873 "error %d deactivating %s\n", atabus_sc->sc_dev.dv_xname, 874 error, sc->dv_xname), DEBUG_DETACH); 875 #endif 876 return (error); 877 } 878 879 int wdcactivate(self, act) 880 struct device *self; 881 enum devact act; 882 { 883 struct wdc_softc *wdc = (struct wdc_softc *)self; 884 int s, i, error = 0; 885 886 s = splbio(); 887 switch (act) { 888 case DVACT_ACTIVATE: 889 error = EOPNOTSUPP; 890 break; 891 892 case DVACT_DEACTIVATE: 893 for (i = 0; i < wdc->nchannels; i++) { 894 error = config_deactivate(wdc->channels[i]->atabus); 895 if (error) 896 break; 897 } 898 break; 899 } 900 splx(s); 901 return (error); 902 } 903 904 905 int 906 atabusdetach(self, flags) 907 struct device *self; 908 int flags; 909 { 910 struct atabus_softc *atabus_sc = (struct atabus_softc *)self; 911 struct channel_softc *chp = atabus_sc->sc_chan; 912 struct device *sc = 0; 913 int i, error = 0; 914 915 /* shutdown channel */ 916 chp->ch_flags |= WDCF_SHUTDOWN; 917 wakeup(&chp->thread); 918 while (chp->thread != NULL) 919 tsleep(&chp->ch_flags, PRIBIO, "atadown", 0); 920 921 /* 922 * Detach atapibus and its children. 923 */ 924 sc = chp->atapibus; 925 if (sc != NULL) { 926 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 927 atabus_sc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 928 error = config_detach(sc, flags); 929 if (error != 0) 930 goto out; 931 } 932 933 /* 934 * Detach our other children. 935 */ 936 for (i = 0; i < 2; i++) { 937 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 938 continue; 939 sc = chp->ch_drive[i].drv_softc; 940 WDCDEBUG_PRINT(("atabusdetach: %s: detaching %s\n", 941 atabus_sc->sc_dev.dv_xname, 942 sc == NULL ? "nodrv" : sc->dv_xname), 943 DEBUG_DETACH); 944 if (sc != NULL) { 945 error = config_detach(sc, flags); 946 if (error != 0) 947 goto out; 948 } 949 } 950 951 wdc_kill_pending(chp); 952 953 out: 954 #ifdef WDCDEBUG 955 if (sc && error != 0) 956 WDCDEBUG_PRINT(("atabusdetach: %s: error %d detaching %s\n", 957 atabus_sc->sc_dev.dv_xname, error, sc->dv_xname), 958 DEBUG_DETACH); 959 #endif 960 return (error); 961 } 962 963 int 964 wdcdetach(self, flags) 965 struct device *self; 966 int flags; 967 { 968 struct wdc_softc *wdc = (struct wdc_softc *)self; 969 struct channel_softc *chp; 970 int i, error = 0; 971 972 for (i = 0; i < wdc->nchannels; i++) { 973 chp = wdc->channels[i]; 974 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 975 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 976 error = config_detach(chp->atabus, flags); 977 if (error) 978 break; 979 } 980 return (error); 981 } 982 983 /* 984 * Start I/O on a controller, for the given channel. 985 * The first xfer may be not for our channel if the channel queues 986 * are shared. 987 */ 988 void 989 wdcstart(chp) 990 struct channel_softc *chp; 991 { 992 struct wdc_xfer *xfer; 993 994 #ifdef WDC_DIAGNOSTIC 995 int spl1, spl2; 996 997 spl1 = splbio(); 998 spl2 = splbio(); 999 if (spl2 != spl1) { 1000 printf("wdcstart: not at splbio()\n"); 1001 panic("wdcstart"); 1002 } 1003 splx(spl2); 1004 splx(spl1); 1005 #endif /* WDC_DIAGNOSTIC */ 1006 1007 /* is there a xfer ? */ 1008 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 1009 return; 1010 1011 /* adjust chp, in case we have a shared queue */ 1012 chp = xfer->chp; 1013 1014 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 1015 return; /* channel aleady active */ 1016 } 1017 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 1018 return; /* queue froozen */ 1019 } 1020 #ifdef DIAGNOSTIC 1021 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 1022 panic("wdcstart: channel waiting for irq"); 1023 #endif 1024 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 1025 if (!(*chp->wdc->claim_hw)(chp, 0)) 1026 return; 1027 1028 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 1029 chp->channel, xfer->drive), DEBUG_XFERS); 1030 chp->ch_flags |= WDCF_ACTIVE; 1031 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 1032 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 1033 chp->ch_drive[xfer->drive].state = 0; 1034 } 1035 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1036 KASSERT(xfer->c_flags & C_POLL); 1037 xfer->c_start(chp, xfer); 1038 } 1039 1040 /* restart an interrupted I/O */ 1041 void 1042 wdcrestart(v) 1043 void *v; 1044 { 1045 struct channel_softc *chp = v; 1046 int s; 1047 1048 s = splbio(); 1049 wdcstart(chp); 1050 splx(s); 1051 } 1052 1053 1054 /* 1055 * Interrupt routine for the controller. Acknowledge the interrupt, check for 1056 * errors on the current operation, mark it done if necessary, and start the 1057 * next request. Also check for a partially done transfer, and continue with 1058 * the next chunk if so. 1059 */ 1060 int 1061 wdcintr(arg) 1062 void *arg; 1063 { 1064 struct channel_softc *chp = arg; 1065 struct wdc_xfer *xfer; 1066 int ret; 1067 1068 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 1069 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 1070 DEBUG_INTR); 1071 return (0); 1072 } 1073 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 1074 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 1075 /* try to clear the pending interrupt anyway */ 1076 (void)bus_space_read_1(chp->cmd_iot, 1077 chp->cmd_iohs[wd_status], 0); 1078 return (0); 1079 } 1080 1081 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 1082 xfer = chp->ch_queue->sc_xfer.tqh_first; 1083 if (chp->ch_flags & WDCF_DMA_WAIT) { 1084 chp->wdc->dma_status = 1085 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 1086 xfer->drive, 0); 1087 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 1088 /* IRQ not for us, not detected by DMA engine */ 1089 return 0; 1090 } 1091 chp->ch_flags &= ~WDCF_DMA_WAIT; 1092 } 1093 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1094 ret = xfer->c_intr(chp, xfer, 1); 1095 if (ret == 0) /* irq was not for us, still waiting for irq */ 1096 chp->ch_flags |= WDCF_IRQ_WAIT; 1097 return (ret); 1098 } 1099 1100 /* Put all disk in RESET state */ 1101 void 1102 wdc_reset_channel(drvp, flags) 1103 struct ata_drive_datas *drvp; 1104 int flags; 1105 { 1106 struct channel_softc *chp = drvp->chnl_softc; 1107 int drive; 1108 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 1109 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1110 DEBUG_FUNCS); 1111 if ((flags & AT_POLL) == 0) { 1112 if (chp->ch_flags & WDCF_TH_RESET) { 1113 /* no need to schedule a reset more than one time */ 1114 return; 1115 } 1116 chp->ch_flags |= WDCF_TH_RESET; 1117 chp->ch_queue->queue_freeze++; 1118 wakeup(&chp->thread); 1119 return; 1120 } 1121 (void) wdcreset(chp, RESET_POLL); 1122 for (drive = 0; drive < 2; drive++) { 1123 chp->ch_drive[drive].state = 0; 1124 } 1125 } 1126 1127 int 1128 wdcreset(chp, poll) 1129 struct channel_softc *chp; 1130 int poll; 1131 { 1132 int drv_mask1, drv_mask2; 1133 int s = 0; 1134 1135 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1136 chp->wdc->select(chp,0); 1137 if (poll != RESET_SLEEP) 1138 s = splbio(); 1139 /* master */ 1140 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1141 delay(10); /* 400ns delay */ 1142 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1143 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1144 delay(2000); 1145 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1146 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1147 WDCTL_4BIT | WDCTL_IDS); 1148 delay(10); /* 400ns delay */ 1149 if (poll != RESET_SLEEP) { 1150 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1151 chp->wdc->irqack(chp); 1152 splx(s); 1153 } 1154 1155 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1156 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1157 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1158 (poll == RESET_SLEEP) ? 0 : 1); 1159 if (drv_mask2 != drv_mask1) { 1160 printf("%s channel %d: reset failed for", 1161 chp->wdc->sc_dev.dv_xname, chp->channel); 1162 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1163 printf(" drive 0"); 1164 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1165 printf(" drive 1"); 1166 printf("\n"); 1167 } 1168 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1169 return (drv_mask1 != drv_mask2) ? 1 : 0; 1170 } 1171 1172 static int 1173 __wdcwait_reset(chp, drv_mask, poll) 1174 struct channel_softc *chp; 1175 int drv_mask; 1176 { 1177 int timeout, nloop; 1178 u_int8_t st0 = 0, st1 = 0; 1179 #ifdef WDCDEBUG 1180 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1181 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1182 #endif 1183 1184 if (poll) 1185 nloop = WDCNDELAY_RST; 1186 else 1187 nloop = WDC_RESET_WAIT * hz / 1000; 1188 /* wait for BSY to deassert */ 1189 for (timeout = 0; timeout < nloop; timeout++) { 1190 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1191 chp->wdc->select(chp,0); 1192 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1193 WDSD_IBM); /* master */ 1194 delay(10); 1195 st0 = bus_space_read_1(chp->cmd_iot, 1196 chp->cmd_iohs[wd_status], 0); 1197 #ifdef WDCDEBUG 1198 sc0 = bus_space_read_1(chp->cmd_iot, 1199 chp->cmd_iohs[wd_seccnt], 0); 1200 sn0 = bus_space_read_1(chp->cmd_iot, 1201 chp->cmd_iohs[wd_sector], 0); 1202 cl0 = bus_space_read_1(chp->cmd_iot, 1203 chp->cmd_iohs[wd_cyl_lo], 0); 1204 ch0 = bus_space_read_1(chp->cmd_iot, 1205 chp->cmd_iohs[wd_cyl_hi], 0); 1206 #endif 1207 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 1208 chp->wdc->select(chp,1); 1209 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1210 WDSD_IBM | 0x10); /* slave */ 1211 delay(10); 1212 st1 = bus_space_read_1(chp->cmd_iot, 1213 chp->cmd_iohs[wd_status], 0); 1214 #ifdef WDCDEBUG 1215 sc1 = bus_space_read_1(chp->cmd_iot, 1216 chp->cmd_iohs[wd_seccnt], 0); 1217 sn1 = bus_space_read_1(chp->cmd_iot, 1218 chp->cmd_iohs[wd_sector], 0); 1219 cl1 = bus_space_read_1(chp->cmd_iot, 1220 chp->cmd_iohs[wd_cyl_lo], 0); 1221 ch1 = bus_space_read_1(chp->cmd_iot, 1222 chp->cmd_iohs[wd_cyl_hi], 0); 1223 #endif 1224 1225 if ((drv_mask & 0x01) == 0) { 1226 /* no master */ 1227 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1228 /* No master, slave is ready, it's done */ 1229 goto end; 1230 } 1231 } else if ((drv_mask & 0x02) == 0) { 1232 /* no slave */ 1233 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1234 /* No slave, master is ready, it's done */ 1235 goto end; 1236 } 1237 } else { 1238 /* Wait for both master and slave to be ready */ 1239 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1240 goto end; 1241 } 1242 } 1243 if (poll) 1244 delay(WDCDELAY); 1245 else 1246 tsleep(&nloop, PRIBIO, "atarst", 1); 1247 } 1248 /* Reset timed out. Maybe it's because drv_mask was not right */ 1249 if (st0 & WDCS_BSY) 1250 drv_mask &= ~0x01; 1251 if (st1 & WDCS_BSY) 1252 drv_mask &= ~0x02; 1253 end: 1254 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1255 "cl=0x%x ch=0x%x\n", 1256 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1257 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1258 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1259 "cl=0x%x ch=0x%x\n", 1260 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 1261 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1262 1263 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1264 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1265 st0, st1), DEBUG_PROBE); 1266 1267 return drv_mask; 1268 } 1269 1270 /* 1271 * Wait for a drive to be !BSY, and have mask in its status register. 1272 * return -1 for a timeout after "timeout" ms. 1273 */ 1274 int 1275 __wdcwait(chp, mask, bits, timeout) 1276 struct channel_softc *chp; 1277 int mask, bits, timeout; 1278 { 1279 u_char status; 1280 int time = 0; 1281 1282 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1283 :"none", chp->channel), DEBUG_STATUS); 1284 chp->ch_error = 0; 1285 1286 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1287 1288 for (;;) { 1289 chp->ch_status = status = 1290 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1291 if ((status & (WDCS_BSY | mask)) == bits) 1292 break; 1293 if (++time > timeout) { 1294 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1295 "status %x error %x (mask 0x%x bits 0x%x)\n", 1296 time, status, 1297 bus_space_read_1(chp->cmd_iot, 1298 chp->cmd_iohs[wd_error], 0), mask, bits), 1299 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1300 return(WDCWAIT_TOUT); 1301 } 1302 delay(WDCDELAY); 1303 } 1304 #ifdef WDCDEBUG 1305 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1306 printf("__wdcwait: did busy-wait, time=%d\n", time); 1307 #endif 1308 if (status & WDCS_ERR) 1309 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1310 chp->cmd_iohs[wd_error], 0); 1311 #ifdef WDCNDELAY_DEBUG 1312 /* After autoconfig, there should be no long delays. */ 1313 if (!cold && time > WDCNDELAY_DEBUG) { 1314 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1315 if (xfer == NULL) 1316 printf("%s channel %d: warning: busy-wait took %dus\n", 1317 chp->wdc->sc_dev.dv_xname, chp->channel, 1318 WDCDELAY * time); 1319 else 1320 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1321 chp->wdc->sc_dev.dv_xname, chp->channel, 1322 xfer->drive, 1323 WDCDELAY * time); 1324 } 1325 #endif 1326 return(WDCWAIT_OK); 1327 } 1328 1329 /* 1330 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1331 * thread if possible 1332 */ 1333 int 1334 wdcwait(chp, mask, bits, timeout, flags) 1335 struct channel_softc *chp; 1336 int mask, bits, timeout, flags; 1337 { 1338 int error, i, timeout_hz = mstohz(timeout); 1339 1340 if (timeout_hz == 0 || 1341 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1342 error = __wdcwait(chp, mask, bits, timeout); 1343 else { 1344 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1345 if (error != 0) { 1346 if ((chp->ch_flags & WDCF_TH_RUN) || 1347 (flags & AT_WAIT)) { 1348 /* 1349 * we're running in the channel thread 1350 * or some userland thread context 1351 */ 1352 for (i = 0; i < timeout_hz; i++) { 1353 if (__wdcwait(chp, mask, bits, 1354 WDCDELAY_POLL) == 0) { 1355 error = 0; 1356 break; 1357 } 1358 tsleep(&chp, PRIBIO, "atapoll", 1); 1359 } 1360 } else { 1361 /* 1362 * we're probably in interrupt context, 1363 * ask the thread to come back here 1364 */ 1365 #ifdef DIAGNOSTIC 1366 if (chp->ch_queue->queue_freeze > 0) 1367 panic("wdcwait: queue_freeze"); 1368 #endif 1369 chp->ch_queue->queue_freeze++; 1370 wakeup(&chp->thread); 1371 return(WDCWAIT_THR); 1372 } 1373 } 1374 } 1375 return(error); 1376 } 1377 1378 1379 /* 1380 * Busy-wait for DMA to complete 1381 */ 1382 int 1383 wdc_dmawait(chp, xfer, timeout) 1384 struct channel_softc *chp; 1385 struct wdc_xfer *xfer; 1386 int timeout; 1387 { 1388 int time; 1389 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1390 chp->wdc->dma_status = 1391 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1392 chp->channel, xfer->drive, 0); 1393 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1394 return 0; 1395 delay(WDCDELAY); 1396 } 1397 /* timeout, force a DMA halt */ 1398 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1399 chp->channel, xfer->drive, 1); 1400 return 1; 1401 } 1402 1403 void 1404 wdctimeout(arg) 1405 void *arg; 1406 { 1407 struct channel_softc *chp = (struct channel_softc *)arg; 1408 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1409 int s; 1410 1411 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1412 1413 s = splbio(); 1414 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1415 __wdcerror(chp, "lost interrupt"); 1416 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1417 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1418 xfer->c_bcount, 1419 xfer->c_skip); 1420 if (chp->ch_flags & WDCF_DMA_WAIT) { 1421 chp->wdc->dma_status = 1422 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1423 chp->channel, xfer->drive, 1); 1424 chp->ch_flags &= ~WDCF_DMA_WAIT; 1425 } 1426 /* 1427 * Call the interrupt routine. If we just missed an interrupt, 1428 * it will do what's needed. Else, it will take the needed 1429 * action (reset the device). 1430 * Before that we need to reinstall the timeout callback, 1431 * in case it will miss another irq while in this transfer 1432 * We arbitray chose it to be 1s 1433 */ 1434 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1435 xfer->c_flags |= C_TIMEOU; 1436 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1437 xfer->c_intr(chp, xfer, 1); 1438 } else 1439 __wdcerror(chp, "missing untimeout"); 1440 splx(s); 1441 } 1442 1443 /* 1444 * Probe drive's capabilities, for use by the controller later 1445 * Assumes drvp points to an existing drive. 1446 * XXX this should be a controller-indep function 1447 */ 1448 void 1449 wdc_probe_caps(drvp) 1450 struct ata_drive_datas *drvp; 1451 { 1452 struct ataparams params, params2; 1453 struct channel_softc *chp = drvp->chnl_softc; 1454 struct device *drv_dev = drvp->drv_softc; 1455 struct wdc_softc *wdc = chp->wdc; 1456 int i, printed; 1457 char *sep = ""; 1458 int cf_flags; 1459 1460 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1461 /* IDENTIFY failed. Can't tell more about the device */ 1462 return; 1463 } 1464 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1465 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1466 /* 1467 * Controller claims 16 and 32 bit transfers. 1468 * Re-do an IDENTIFY with 32-bit transfers, 1469 * and compare results. 1470 */ 1471 drvp->drive_flags |= DRIVE_CAP32; 1472 ata_get_params(drvp, AT_WAIT, ¶ms2); 1473 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1474 /* Not good. fall back to 16bits */ 1475 drvp->drive_flags &= ~DRIVE_CAP32; 1476 } else { 1477 aprint_normal("%s: 32-bit data port\n", 1478 drv_dev->dv_xname); 1479 } 1480 } 1481 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1482 if (params.atap_ata_major > 0x01 && 1483 params.atap_ata_major != 0xffff) { 1484 for (i = 14; i > 0; i--) { 1485 if (params.atap_ata_major & (1 << i)) { 1486 aprint_normal("%s: ATA version %d\n", 1487 drv_dev->dv_xname, i); 1488 drvp->ata_vers = i; 1489 break; 1490 } 1491 } 1492 } 1493 #endif 1494 1495 /* An ATAPI device is at last PIO mode 3 */ 1496 if (drvp->drive_flags & DRIVE_ATAPI) 1497 drvp->PIO_mode = 3; 1498 1499 /* 1500 * It's not in the specs, but it seems that some drive 1501 * returns 0xffff in atap_extensions when this field is invalid 1502 */ 1503 if (params.atap_extensions != 0xffff && 1504 (params.atap_extensions & WDC_EXT_MODES)) { 1505 printed = 0; 1506 /* 1507 * XXX some drives report something wrong here (they claim to 1508 * support PIO mode 8 !). As mode is coded on 3 bits in 1509 * SET FEATURE, limit it to 7 (so limit i to 4). 1510 * If higher mode than 7 is found, abort. 1511 */ 1512 for (i = 7; i >= 0; i--) { 1513 if ((params.atap_piomode_supp & (1 << i)) == 0) 1514 continue; 1515 if (i > 4) 1516 return; 1517 /* 1518 * See if mode is accepted. 1519 * If the controller can't set its PIO mode, 1520 * assume the defaults are good, so don't try 1521 * to set it 1522 */ 1523 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1524 /* 1525 * It's OK to pool here, it's fast enouth 1526 * to not bother waiting for interrupt 1527 */ 1528 if (ata_set_mode(drvp, 0x08 | (i + 3), 1529 AT_WAIT) != CMD_OK) 1530 continue; 1531 if (!printed) { 1532 aprint_normal("%s: drive supports PIO mode %d", 1533 drv_dev->dv_xname, i + 3); 1534 sep = ","; 1535 printed = 1; 1536 } 1537 /* 1538 * If controller's driver can't set its PIO mode, 1539 * get the highter one for the drive. 1540 */ 1541 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1542 wdc->PIO_cap >= i + 3) { 1543 drvp->PIO_mode = i + 3; 1544 drvp->PIO_cap = i + 3; 1545 break; 1546 } 1547 } 1548 if (!printed) { 1549 /* 1550 * We didn't find a valid PIO mode. 1551 * Assume the values returned for DMA are buggy too 1552 */ 1553 return; 1554 } 1555 drvp->drive_flags |= DRIVE_MODE; 1556 printed = 0; 1557 for (i = 7; i >= 0; i--) { 1558 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1559 continue; 1560 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1561 (wdc->cap & WDC_CAPABILITY_MODE)) 1562 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1563 != CMD_OK) 1564 continue; 1565 if (!printed) { 1566 aprint_normal("%s DMA mode %d", sep, i); 1567 sep = ","; 1568 printed = 1; 1569 } 1570 if (wdc->cap & WDC_CAPABILITY_DMA) { 1571 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1572 wdc->DMA_cap < i) 1573 continue; 1574 drvp->DMA_mode = i; 1575 drvp->DMA_cap = i; 1576 drvp->drive_flags |= DRIVE_DMA; 1577 } 1578 break; 1579 } 1580 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1581 printed = 0; 1582 for (i = 7; i >= 0; i--) { 1583 if ((params.atap_udmamode_supp & (1 << i)) 1584 == 0) 1585 continue; 1586 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1587 (wdc->cap & WDC_CAPABILITY_UDMA)) 1588 if (ata_set_mode(drvp, 0x40 | i, 1589 AT_WAIT) != CMD_OK) 1590 continue; 1591 if (!printed) { 1592 aprint_normal("%s Ultra-DMA mode %d", 1593 sep, i); 1594 if (i == 2) 1595 aprint_normal(" (Ultra/33)"); 1596 else if (i == 4) 1597 aprint_normal(" (Ultra/66)"); 1598 else if (i == 5) 1599 aprint_normal(" (Ultra/100)"); 1600 else if (i == 6) 1601 aprint_normal(" (Ultra/133)"); 1602 sep = ","; 1603 printed = 1; 1604 } 1605 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1606 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1607 wdc->UDMA_cap < i) 1608 continue; 1609 drvp->UDMA_mode = i; 1610 drvp->UDMA_cap = i; 1611 drvp->drive_flags |= DRIVE_UDMA; 1612 } 1613 break; 1614 } 1615 } 1616 aprint_normal("\n"); 1617 } 1618 1619 /* Try to guess ATA version here, if it didn't get reported */ 1620 if (drvp->ata_vers == 0) { 1621 if (drvp->drive_flags & DRIVE_UDMA) 1622 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1623 else if (drvp->PIO_cap > 2) 1624 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1625 } 1626 cf_flags = drv_dev->dv_cfdata->cf_flags; 1627 if (cf_flags & ATA_CONFIG_PIO_SET) { 1628 drvp->PIO_mode = 1629 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1630 drvp->drive_flags |= DRIVE_MODE; 1631 } 1632 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1633 /* don't care about DMA modes */ 1634 return; 1635 } 1636 if (cf_flags & ATA_CONFIG_DMA_SET) { 1637 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1638 ATA_CONFIG_DMA_DISABLE) { 1639 drvp->drive_flags &= ~DRIVE_DMA; 1640 } else { 1641 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1642 ATA_CONFIG_DMA_OFF; 1643 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1644 } 1645 } 1646 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1647 /* don't care about UDMA modes */ 1648 return; 1649 } 1650 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1651 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1652 ATA_CONFIG_UDMA_DISABLE) { 1653 drvp->drive_flags &= ~DRIVE_UDMA; 1654 } else { 1655 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1656 ATA_CONFIG_UDMA_OFF; 1657 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1658 } 1659 } 1660 } 1661 1662 /* 1663 * downgrade the transfer mode of a drive after an error. return 1 if 1664 * downgrade was possible, 0 otherwise. 1665 */ 1666 int 1667 wdc_downgrade_mode(drvp, flags) 1668 struct ata_drive_datas *drvp; 1669 { 1670 struct channel_softc *chp = drvp->chnl_softc; 1671 struct device *drv_dev = drvp->drv_softc; 1672 struct wdc_softc *wdc = chp->wdc; 1673 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1674 1675 /* if drive or controller don't know its mode, we can't do much */ 1676 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1677 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1678 return 0; 1679 /* current drive mode was set by a config flag, let it this way */ 1680 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1681 (cf_flags & ATA_CONFIG_DMA_SET) || 1682 (cf_flags & ATA_CONFIG_UDMA_SET)) 1683 return 0; 1684 1685 /* 1686 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1687 * Maybe we didn't properly notice the cable type 1688 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1689 * It helps in some cases. 1690 */ 1691 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1692 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1693 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1694 drv_dev->dv_xname, drvp->UDMA_mode); 1695 } 1696 1697 /* 1698 * If we were using ultra-DMA, don't downgrade to multiword DMA 1699 * if we noticed a CRC error. It has been noticed that CRC errors 1700 * in ultra-DMA lead to silent data corruption in multiword DMA. 1701 * Data corruption is less likely to occur in PIO mode. 1702 */ 1703 else if ((drvp->drive_flags & DRIVE_UDMA) && 1704 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1705 drvp->drive_flags &= ~DRIVE_UDMA; 1706 drvp->drive_flags |= DRIVE_DMA; 1707 drvp->DMA_mode = drvp->DMA_cap; 1708 printf("%s: transfer error, downgrading to DMA mode %d\n", 1709 drv_dev->dv_xname, drvp->DMA_mode); 1710 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1711 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1712 drvp->PIO_mode = drvp->PIO_cap; 1713 printf("%s: transfer error, downgrading to PIO mode %d\n", 1714 drv_dev->dv_xname, drvp->PIO_mode); 1715 } else /* already using PIO, can't downgrade */ 1716 return 0; 1717 1718 wdc->set_modes(chp); 1719 wdc_print_modes(chp); 1720 /* reset the channel, which will shedule all drives for setup */ 1721 wdc_reset_channel(drvp, flags); 1722 return 1; 1723 } 1724 1725 int 1726 wdc_exec_command(drvp, wdc_c) 1727 struct ata_drive_datas *drvp; 1728 struct wdc_command *wdc_c; 1729 { 1730 struct channel_softc *chp = drvp->chnl_softc; 1731 struct wdc_xfer *xfer; 1732 int s, ret; 1733 1734 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1735 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1736 DEBUG_FUNCS); 1737 1738 /* set up an xfer and queue. Wait for completion */ 1739 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1740 WDC_NOSLEEP); 1741 if (xfer == NULL) { 1742 return WDC_TRY_AGAIN; 1743 } 1744 1745 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1746 wdc_c->flags |= AT_POLL; 1747 if (wdc_c->flags & AT_POLL) 1748 xfer->c_flags |= C_POLL; 1749 xfer->drive = drvp->drive; 1750 xfer->databuf = wdc_c->data; 1751 xfer->c_bcount = wdc_c->bcount; 1752 xfer->cmd = wdc_c; 1753 xfer->c_start = __wdccommand_start; 1754 xfer->c_intr = __wdccommand_intr; 1755 xfer->c_kill_xfer = __wdccommand_done; 1756 1757 s = splbio(); 1758 wdc_exec_xfer(chp, xfer); 1759 #ifdef DIAGNOSTIC 1760 if ((wdc_c->flags & AT_POLL) != 0 && 1761 (wdc_c->flags & AT_DONE) == 0) 1762 panic("wdc_exec_command: polled command not done"); 1763 #endif 1764 if (wdc_c->flags & AT_DONE) { 1765 ret = WDC_COMPLETE; 1766 } else { 1767 if (wdc_c->flags & AT_WAIT) { 1768 while ((wdc_c->flags & AT_DONE) == 0) { 1769 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1770 } 1771 ret = WDC_COMPLETE; 1772 } else { 1773 ret = WDC_QUEUED; 1774 } 1775 } 1776 splx(s); 1777 return ret; 1778 } 1779 1780 void 1781 __wdccommand_start(chp, xfer) 1782 struct channel_softc *chp; 1783 struct wdc_xfer *xfer; 1784 { 1785 int drive = xfer->drive; 1786 struct wdc_command *wdc_c = xfer->cmd; 1787 1788 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1789 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1790 DEBUG_FUNCS); 1791 1792 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1793 chp->wdc->select(chp,drive); 1794 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1795 WDSD_IBM | (drive << 4)); 1796 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1797 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1798 case WDCWAIT_OK: 1799 break; 1800 case WDCWAIT_TOUT: 1801 wdc_c->flags |= AT_TIMEOU; 1802 __wdccommand_done(chp, xfer); 1803 return; 1804 case WDCWAIT_THR: 1805 return; 1806 } 1807 if (wdc_c->flags & AT_POLL) { 1808 /* polled command, disable interrupts */ 1809 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1810 WDCTL_4BIT | WDCTL_IDS); 1811 } 1812 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1813 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1814 1815 if ((wdc_c->flags & AT_POLL) == 0) { 1816 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1817 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1818 wdctimeout, chp); 1819 return; 1820 } 1821 /* 1822 * Polled command. Wait for drive ready or drq. Done in intr(). 1823 * Wait for at last 400ns for status bit to be valid. 1824 */ 1825 delay(10); /* 400ns delay */ 1826 __wdccommand_intr(chp, xfer, 0); 1827 } 1828 1829 int 1830 __wdccommand_intr(chp, xfer, irq) 1831 struct channel_softc *chp; 1832 struct wdc_xfer *xfer; 1833 int irq; 1834 { 1835 struct wdc_command *wdc_c = xfer->cmd; 1836 int bcount = wdc_c->bcount; 1837 char *data = wdc_c->data; 1838 int wflags; 1839 1840 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1841 /* both wait and poll, we can tsleep here */ 1842 wflags = AT_WAIT | AT_POLL; 1843 } else { 1844 wflags = AT_POLL; 1845 } 1846 1847 again: 1848 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1849 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1850 /* 1851 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1852 * Reselect again, it doesn't hurt for others commands, and the time 1853 * penalty for the extra regiter write is acceptable, 1854 * wdc_exec_command() isn't called often (mosly for autoconfig) 1855 */ 1856 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1857 WDSD_IBM | (xfer->drive << 4)); 1858 if ((wdc_c->flags & AT_XFDONE) != 0) { 1859 /* 1860 * We have completed a data xfer. The drive should now be 1861 * in its initial state 1862 */ 1863 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1864 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1865 wflags) == WDCWAIT_TOUT) { 1866 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1867 return 0; /* IRQ was not for us */ 1868 wdc_c->flags |= AT_TIMEOU; 1869 } 1870 goto out; 1871 } 1872 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1873 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1874 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1875 return 0; /* IRQ was not for us */ 1876 wdc_c->flags |= AT_TIMEOU; 1877 goto out; 1878 } 1879 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1880 chp->wdc->irqack(chp); 1881 if (wdc_c->flags & AT_READ) { 1882 if ((chp->ch_status & WDCS_DRQ) == 0) { 1883 wdc_c->flags |= AT_TIMEOU; 1884 goto out; 1885 } 1886 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1887 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1888 0, (u_int32_t*)data, bcount >> 2); 1889 data += bcount & 0xfffffffc; 1890 bcount = bcount & 0x03; 1891 } 1892 if (bcount > 0) 1893 bus_space_read_multi_2(chp->cmd_iot, 1894 chp->cmd_iohs[wd_data], 0, 1895 (u_int16_t *)data, bcount >> 1); 1896 /* at this point the drive should be in its initial state */ 1897 wdc_c->flags |= AT_XFDONE; 1898 /* XXX should read status register here ? */ 1899 } else if (wdc_c->flags & AT_WRITE) { 1900 if ((chp->ch_status & WDCS_DRQ) == 0) { 1901 wdc_c->flags |= AT_TIMEOU; 1902 goto out; 1903 } 1904 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1905 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1906 0, (u_int32_t*)data, bcount >> 2); 1907 data += bcount & 0xfffffffc; 1908 bcount = bcount & 0x03; 1909 } 1910 if (bcount > 0) 1911 bus_space_write_multi_2(chp->cmd_iot, 1912 chp->cmd_iohs[wd_data], 0, 1913 (u_int16_t *)data, bcount >> 1); 1914 wdc_c->flags |= AT_XFDONE; 1915 if ((wdc_c->flags & AT_POLL) == 0) { 1916 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1917 callout_reset(&chp->ch_callout, 1918 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1919 return 1; 1920 } else { 1921 goto again; 1922 } 1923 } 1924 out: 1925 __wdccommand_done(chp, xfer); 1926 return 1; 1927 } 1928 1929 void 1930 __wdccommand_done(chp, xfer) 1931 struct channel_softc *chp; 1932 struct wdc_xfer *xfer; 1933 { 1934 struct wdc_command *wdc_c = xfer->cmd; 1935 1936 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1937 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1938 1939 callout_stop(&chp->ch_callout); 1940 1941 if (chp->ch_status & WDCS_DWF) 1942 wdc_c->flags |= AT_DF; 1943 if (chp->ch_status & WDCS_ERR) { 1944 wdc_c->flags |= AT_ERROR; 1945 wdc_c->r_error = chp->ch_error; 1946 } 1947 wdc_c->flags |= AT_DONE; 1948 if ((wdc_c->flags & AT_READREG) != 0 && 1949 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1950 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1951 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1952 chp->cmd_iohs[wd_sdh], 0); 1953 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1954 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1955 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1956 chp->cmd_iohs[wd_cyl_lo], 0); 1957 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1958 chp->cmd_iohs[wd_sector], 0); 1959 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1960 chp->cmd_iohs[wd_seccnt], 0); 1961 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1962 chp->cmd_iohs[wd_error], 0); 1963 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1964 chp->cmd_iohs[wd_precomp], 0); 1965 } 1966 1967 if (wdc_c->flags & AT_POLL) { 1968 /* enable interrupts */ 1969 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1970 WDCTL_4BIT); 1971 } 1972 wdc_free_xfer(chp, xfer); 1973 if (wdc_c->flags & AT_WAIT) 1974 wakeup(wdc_c); 1975 else if (wdc_c->callback) 1976 wdc_c->callback(wdc_c->callback_arg); 1977 wdcstart(chp); 1978 return; 1979 } 1980 1981 /* 1982 * Send a command. The drive should be ready. 1983 * Assumes interrupts are blocked. 1984 */ 1985 void 1986 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1987 struct channel_softc *chp; 1988 u_int8_t drive; 1989 u_int8_t command; 1990 u_int16_t cylin; 1991 u_int8_t head, sector, count, precomp; 1992 { 1993 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1994 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1995 chp->channel, drive, command, cylin, head, sector, count, precomp), 1996 DEBUG_FUNCS); 1997 1998 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1999 chp->wdc->select(chp,drive); 2000 2001 /* Select drive, head, and addressing mode. */ 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2003 WDSD_IBM | (drive << 4) | head); 2004 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 2006 precomp); 2007 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 2008 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 2009 0, cylin >> 8); 2010 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 2011 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2012 2013 /* Send command. */ 2014 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2015 return; 2016 } 2017 2018 /* 2019 * Send a 48-bit addressing command. The drive should be ready. 2020 * Assumes interrupts are blocked. 2021 */ 2022 void 2023 wdccommandext(chp, drive, command, blkno, count) 2024 struct channel_softc *chp; 2025 u_int8_t drive; 2026 u_int8_t command; 2027 u_int64_t blkno; 2028 u_int16_t count; 2029 { 2030 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2031 "count=%d\n", chp->wdc->sc_dev.dv_xname, 2032 chp->channel, drive, command, (u_int32_t) blkno, count), 2033 DEBUG_FUNCS); 2034 2035 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2036 chp->wdc->select(chp,drive); 2037 2038 /* Select drive, head, and addressing mode. */ 2039 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2040 (drive << 4) | WDSD_LBA); 2041 2042 /* previous */ 2043 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2044 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 2045 0, count >> 8); 2046 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2047 0, blkno >> 40); 2048 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2049 0, blkno >> 32); 2050 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 2051 0, blkno >> 24); 2052 2053 /* current */ 2054 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2055 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2056 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2057 0, blkno >> 16); 2058 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2059 0, blkno >> 8); 2060 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2061 2062 /* Send command. */ 2063 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2064 return; 2065 } 2066 2067 /* 2068 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2069 * tested by the caller. 2070 */ 2071 void 2072 wdccommandshort(chp, drive, command) 2073 struct channel_softc *chp; 2074 int drive; 2075 int command; 2076 { 2077 2078 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2079 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 2080 DEBUG_FUNCS); 2081 2082 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 2083 chp->wdc->select(chp,drive); 2084 2085 /* Select drive. */ 2086 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2087 WDSD_IBM | (drive << 4)); 2088 2089 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2090 } 2091 2092 /* Add a command to the queue and start controller. Must be called at splbio */ 2093 2094 void 2095 wdc_exec_xfer(chp, xfer) 2096 struct channel_softc *chp; 2097 struct wdc_xfer *xfer; 2098 { 2099 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2100 chp->channel, xfer->drive), DEBUG_XFERS); 2101 2102 /* complete xfer setup */ 2103 xfer->chp = chp; 2104 2105 /* 2106 * If we are a polled command, and the list is not empty, 2107 * we are doing a dump. Drop the list to allow the polled command 2108 * to complete, we're going to reboot soon anyway. 2109 */ 2110 if ((xfer->c_flags & C_POLL) != 0 && 2111 chp->ch_queue->sc_xfer.tqh_first != NULL) { 2112 TAILQ_INIT(&chp->ch_queue->sc_xfer); 2113 } 2114 /* insert at the end of command list */ 2115 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 2116 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2117 chp->ch_flags), DEBUG_XFERS); 2118 wdcstart(chp); 2119 } 2120 2121 struct wdc_xfer * 2122 wdc_get_xfer(flags) 2123 int flags; 2124 { 2125 struct wdc_xfer *xfer; 2126 int s; 2127 2128 s = splbio(); 2129 xfer = pool_get(&wdc_xfer_pool, 2130 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2131 splx(s); 2132 if (xfer != NULL) { 2133 memset(xfer, 0, sizeof(struct wdc_xfer)); 2134 } 2135 return xfer; 2136 } 2137 2138 void 2139 wdc_free_xfer(chp, xfer) 2140 struct channel_softc *chp; 2141 struct wdc_xfer *xfer; 2142 { 2143 struct wdc_softc *wdc = chp->wdc; 2144 int s; 2145 2146 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2147 (*wdc->free_hw)(chp); 2148 s = splbio(); 2149 chp->ch_flags &= ~WDCF_ACTIVE; 2150 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 2151 pool_put(&wdc_xfer_pool, xfer); 2152 splx(s); 2153 } 2154 2155 /* 2156 * Kill off all pending xfers for a channel_softc. 2157 * 2158 * Must be called at splbio(). 2159 */ 2160 void 2161 wdc_kill_pending(chp) 2162 struct channel_softc *chp; 2163 { 2164 struct wdc_xfer *xfer; 2165 2166 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 2167 chp = xfer->chp; 2168 (*xfer->c_kill_xfer)(chp, xfer); 2169 } 2170 } 2171 2172 static void 2173 __wdcerror(chp, msg) 2174 struct channel_softc *chp; 2175 char *msg; 2176 { 2177 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 2178 2179 if (xfer == NULL) 2180 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2181 msg); 2182 else 2183 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 2184 chp->channel, xfer->drive, msg); 2185 } 2186 2187 /* 2188 * the bit bucket 2189 */ 2190 void 2191 wdcbit_bucket(chp, size) 2192 struct channel_softc *chp; 2193 int size; 2194 { 2195 2196 for (; size >= 2; size -= 2) 2197 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2198 if (size) 2199 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2200 } 2201 2202 int 2203 wdc_addref(chp) 2204 struct channel_softc *chp; 2205 { 2206 struct wdc_softc *wdc = chp->wdc; 2207 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2208 int s, error = 0; 2209 2210 s = splbio(); 2211 if (adapt->adapt_refcnt++ == 0 && 2212 adapt->adapt_enable != NULL) { 2213 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2214 if (error) 2215 adapt->adapt_refcnt--; 2216 } 2217 splx(s); 2218 return (error); 2219 } 2220 2221 void 2222 wdc_delref(chp) 2223 struct channel_softc *chp; 2224 { 2225 struct wdc_softc *wdc = chp->wdc; 2226 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2227 int s; 2228 2229 s = splbio(); 2230 if (adapt->adapt_refcnt-- == 1 && 2231 adapt->adapt_enable != NULL) 2232 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2233 splx(s); 2234 } 2235 2236 void 2237 wdc_print_modes(struct channel_softc *chp) 2238 { 2239 int drive; 2240 struct ata_drive_datas *drvp; 2241 2242 for (drive = 0; drive < 2; drive++) { 2243 drvp = &chp->ch_drive[drive]; 2244 if ((drvp->drive_flags & DRIVE) == 0) 2245 continue; 2246 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2247 drvp->drv_softc->dv_xname, 2248 chp->wdc->sc_dev.dv_xname, 2249 chp->channel, drive, drvp->PIO_mode); 2250 if (drvp->drive_flags & DRIVE_DMA) 2251 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2252 if (drvp->drive_flags & DRIVE_UDMA) { 2253 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2254 if (drvp->UDMA_mode == 2) 2255 aprint_normal(" (Ultra/33)"); 2256 else if (drvp->UDMA_mode == 4) 2257 aprint_normal(" (Ultra/66)"); 2258 else if (drvp->UDMA_mode == 5) 2259 aprint_normal(" (Ultra/100)"); 2260 else if (drvp->UDMA_mode == 6) 2261 aprint_normal(" (Ultra/133)"); 2262 } 2263 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2264 aprint_normal(" (using DMA data transfers)"); 2265 aprint_normal("\n"); 2266 } 2267 } 2268
Indexes created Fri Sep 26 20:09:58 GMT 2025