wdc.c revision 1.162
1 /* $NetBSD: wdc.c,v 1.162 2003/12/30 16:28:37 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.162 2003/12/30 16:28:37 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 int wdcprobe1 __P((struct channel_softc*, int)); 147 static void __wdcerror __P((struct channel_softc*, char *)); 148 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 149 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 150 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 151 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 152 int __wdcwait __P((struct channel_softc *, int, int, int)); 153 void wdc_finish_attach __P((struct device *)); 154 void wdc_channel_attach __P((struct channel_softc *)); 155 156 #define DEBUG_INTR 0x01 157 #define DEBUG_XFERS 0x02 158 #define DEBUG_STATUS 0x04 159 #define DEBUG_FUNCS 0x08 160 #define DEBUG_PROBE 0x10 161 #define DEBUG_DETACH 0x20 162 #define DEBUG_DELAY 0x40 163 #ifdef WDCDEBUG 164 int wdcdebug_mask = 0; 165 int wdc_nxfer = 0; 166 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 167 #else 168 #define WDCDEBUG_PRINT(args, level) 169 #endif 170 171 /* 172 * A queue of atabus instances, used to ensure the same bus probe order 173 * for a given hardware configuration at each boot. 174 */ 175 struct atabus_initq_head atabus_initq_head = 176 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 177 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 178 179 /* Test to see controller with at last one attached drive is there. 180 * Returns a bit for each possible drive found (0x01 for drive 0, 181 * 0x02 for drive 1). 182 * Logic: 183 * - If a status register is at 0xff, assume there is no drive here 184 * (ISA has pull-up resistors). Similarly if the status register has 185 * the value we last wrote to the bus (for IDE interfaces without pullups). 186 * If no drive at all -> return. 187 * - reset the controller, wait for it to complete (may take up to 31s !). 188 * If timeout -> return. 189 * - test ATA/ATAPI signatures. If at last one drive found -> return. 190 * - try an ATA command on the master. 191 */ 192 193 void 194 atabusconfig(atabus_sc) 195 struct atabus_softc *atabus_sc; 196 { 197 struct channel_softc *chp = atabus_sc->sc_chan; 198 int i, error, need_delref = 0; 199 struct ataparams params; 200 struct atabus_initq *atabus_initq = NULL; 201 u_int8_t st0 = 0, st1 = 0; 202 203 if ((error = wdc_addref(chp)) != 0) { 204 aprint_error("%s: unable to enable controller\n", 205 chp->wdc->sc_dev.dv_xname); 206 goto out; 207 } 208 need_delref = 1; 209 210 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_DRVPROBE) != 0) { 211 if ((*chp->wdc->drv_probe)(chp) == 0) { 212 /* If no drives, abort attach here. */ 213 goto out; 214 } 215 } else if (wdcprobe1(chp, 0) == 0) { 216 /* If no drives, abort attach here. */ 217 goto out; 218 } 219 220 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 221 for (i = 0; i < mstohz(3000); i++) { 222 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 223 chp->wdc->select(chp,0); 224 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 225 WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st0 = bus_space_read_1(chp->cmd_iot, 228 chp->cmd_iohs[wd_status], 0); 229 230 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 231 chp->wdc->select(chp,1); 232 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 233 WDSD_IBM | 0x10); 234 delay(10); /* 400ns delay */ 235 st1 = bus_space_read_1(chp->cmd_iot, 236 chp->cmd_iohs[wd_status], 0); 237 238 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 239 == 0 || 240 (st0 & WDCS_DRDY)) && 241 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 242 == 0 || 243 (st1 & WDCS_DRDY))) 244 break; 245 tsleep(&atabus_sc, PRIBIO, "atadrdy", 1); 246 } 247 if ((st0 & WDCS_DRDY) == 0) 248 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 249 if ((st1 & WDCS_DRDY) == 0) 250 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 251 252 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 253 chp->wdc->sc_dev.dv_xname, 254 chp->channel, st0, st1), DEBUG_PROBE); 255 256 /* Wait a bit, some devices are weird just after a reset. */ 257 delay(5000); 258 259 for (i = 0; i < 2; i++) { 260 chp->ch_drive[i].chnl_softc = chp; 261 chp->ch_drive[i].drive = i; 262 /* 263 * Init error counter so that an error withing the first xfers 264 * will trigger a downgrade 265 */ 266 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 267 268 /* If controller can't do 16bit flag the drives as 32bit */ 269 if ((chp->wdc->cap & 270 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 271 WDC_CAPABILITY_DATA32) 272 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 273 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 274 continue; 275 276 /* Shortcut in case we've been shutdown */ 277 if (chp->ch_flags & WDCF_SHUTDOWN) 278 goto out; 279 280 /* issue an identify, to try to detect ghosts */ 281 error = ata_get_params(&chp->ch_drive[i], 282 AT_WAIT | AT_POLL, ¶ms); 283 if (error != CMD_OK) { 284 tsleep(&atabus_sc, PRIBIO, "atacnf", mstohz(1000)); 285 286 /* Shortcut in case we've been shutdown */ 287 if (chp->ch_flags & WDCF_SHUTDOWN) 288 goto out; 289 290 error = ata_get_params(&chp->ch_drive[i], 291 AT_WAIT | AT_POLL, ¶ms); 292 } 293 if (error == CMD_OK) { 294 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 295 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 296 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 297 } else { 298 chp->ch_drive[i].drive_flags &= 299 ~(DRIVE_ATA | DRIVE_ATAPI); 300 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 301 chp->wdc->sc_dev.dv_xname, 302 chp->channel, i, error), DEBUG_PROBE); 303 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 304 continue; 305 /* 306 * Pre-ATA drive ? 307 * Test registers writability (Error register not 308 * writable, but cyllo is), then try an ATA command. 309 */ 310 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 311 chp->wdc->select(chp,i); 312 bus_space_write_1(chp->cmd_iot, 313 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 314 delay(10); /* 400ns delay */ 315 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 316 0, 0x58); 317 bus_space_write_1(chp->cmd_iot, 318 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 319 if (bus_space_read_1(chp->cmd_iot, 320 chp->cmd_iohs[wd_error], 0) == 0x58 || 321 bus_space_read_1(chp->cmd_iot, 322 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 323 WDCDEBUG_PRINT(("%s:%d:%d: register " 324 "writability failed\n", 325 chp->wdc->sc_dev.dv_xname, 326 chp->channel, i), DEBUG_PROBE); 327 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 328 continue; 329 } 330 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 331 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 332 chp->wdc->sc_dev.dv_xname, 333 chp->channel, i), DEBUG_PROBE); 334 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 335 continue; 336 } 337 bus_space_write_1(chp->cmd_iot, 338 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 339 delay(10); /* 400ns delay */ 340 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 341 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 342 chp->wdc->sc_dev.dv_xname, 343 chp->channel, i), DEBUG_PROBE); 344 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 345 } else { 346 chp->ch_drive[0].drive_flags &= 347 ~(DRIVE_ATA | DRIVE_ATAPI); 348 chp->ch_drive[1].drive_flags &= 349 ~(DRIVE_ATA | DRIVE_ATAPI); 350 } 351 } 352 } 353 354 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 355 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 356 DEBUG_PROBE); 357 358 /* If no drives, abort here */ 359 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 360 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 361 goto out; 362 363 /* Make sure the devices probe in atabus order to avoid jitter. */ 364 simple_lock(&atabus_interlock); 365 while(1) { 366 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 367 if (atabus_initq->atabus_sc == atabus_sc) 368 break; 369 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 370 &atabus_interlock); 371 } 372 simple_unlock(&atabus_interlock); 373 374 /* 375 * Attach an ATAPI bus, if needed. 376 */ 377 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 378 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 379 #if NATAPIBUS > 0 380 wdc_atapibus_attach(atabus_sc); 381 #else 382 /* 383 * Fake the autoconfig "not configured" message 384 */ 385 aprint_normal("atapibus at %s not configured\n", 386 chp->wdc->sc_dev.dv_xname); 387 chp->atapibus = NULL; 388 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 389 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 390 #endif 391 } 392 393 for (i = 0; i < 2; i++) { 394 struct ata_device adev; 395 if ((chp->ch_drive[i].drive_flags & 396 (DRIVE_ATA | DRIVE_OLD)) == 0) { 397 continue; 398 } 399 memset(&adev, 0, sizeof(struct ata_device)); 400 adev.adev_bustype = &wdc_ata_bustype; 401 adev.adev_channel = chp->channel; 402 adev.adev_openings = 1; 403 adev.adev_drv_data = &chp->ch_drive[i]; 404 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 405 &adev, ataprint); 406 if (chp->ata_drives[i] != NULL) 407 wdc_probe_caps(&chp->ch_drive[i]); 408 else 409 chp->ch_drive[i].drive_flags &= 410 ~(DRIVE_ATA | DRIVE_OLD); 411 } 412 413 /* now that we know the drives, the controller can set its modes */ 414 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 415 chp->wdc->set_modes(chp); 416 wdc_print_modes(chp); 417 } 418 #if NATARAID > 0 419 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 420 for (i = 0; i < 2; i++) 421 if (chp->ata_drives[i] != NULL) 422 ata_raid_check_component(chp->ata_drives[i]); 423 #endif /* NATARAID > 0 */ 424 425 /* 426 * reset drive_flags for unattached devices, reset state for attached 427 * ones 428 */ 429 for (i = 0; i < 2; i++) { 430 if (chp->ch_drive[i].drv_softc == NULL) 431 chp->ch_drive[i].drive_flags = 0; 432 else 433 chp->ch_drive[i].state = 0; 434 } 435 436 out: 437 if (atabus_initq == NULL) { 438 simple_lock(&atabus_interlock); 439 while(1) { 440 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 441 if (atabus_initq->atabus_sc == atabus_sc) 442 break; 443 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 444 &atabus_interlock); 445 } 446 simple_unlock(&atabus_interlock); 447 } 448 simple_lock(&atabus_interlock); 449 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 450 simple_unlock(&atabus_interlock); 451 452 free(atabus_initq, M_DEVBUF); 453 wakeup(&atabus_initq_head); 454 455 config_pending_decr(); 456 if (need_delref) 457 wdc_delref(chp); 458 } 459 460 int 461 wdcprobe(chp) 462 struct channel_softc *chp; 463 { 464 return wdcprobe1(chp, 1); 465 } 466 467 int 468 wdcprobe1(chp, poll) 469 struct channel_softc *chp; 470 int poll; 471 { 472 u_int8_t st0, st1, sc, sn, cl, ch; 473 u_int8_t ret_value = 0x03; 474 u_int8_t drive; 475 int s; 476 477 /* 478 * Sanity check to see if the wdc channel responds at all. 479 */ 480 481 if (chp->wdc == NULL || 482 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 483 484 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 485 chp->wdc->select(chp,0); 486 487 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 488 WDSD_IBM); 489 delay(10); /* 400ns delay */ 490 st0 = bus_space_read_1(chp->cmd_iot, 491 chp->cmd_iohs[wd_status], 0); 492 493 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 494 chp->wdc->select(chp,1); 495 496 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 497 WDSD_IBM | 0x10); 498 delay(10); /* 400ns delay */ 499 st1 = bus_space_read_1(chp->cmd_iot, 500 chp->cmd_iohs[wd_status], 0); 501 502 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 503 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 504 chp->channel, st0, st1), DEBUG_PROBE); 505 506 if (st0 == 0xff || st0 == WDSD_IBM) 507 ret_value &= ~0x01; 508 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 509 ret_value &= ~0x02; 510 /* Register writability test, drive 0. */ 511 if (ret_value & 0x01) { 512 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 513 chp->wdc->select(chp,0); 514 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 515 0, WDSD_IBM); 516 bus_space_write_1(chp->cmd_iot, 517 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 518 if (bus_space_read_1(chp->cmd_iot, 519 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 520 ret_value &= ~0x01; 521 bus_space_write_1(chp->cmd_iot, 522 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 523 if (bus_space_read_1(chp->cmd_iot, 524 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 525 ret_value &= ~0x01; 526 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 527 0, 0x01); 528 if (bus_space_read_1(chp->cmd_iot, 529 chp->cmd_iohs[wd_sector], 0) != 0x01) 530 ret_value &= ~0x01; 531 bus_space_write_1(chp->cmd_iot, 532 chp->cmd_iohs[wd_sector], 0, 0x02); 533 if (bus_space_read_1(chp->cmd_iot, 534 chp->cmd_iohs[wd_sector], 0) != 0x02) 535 ret_value &= ~0x01; 536 if (bus_space_read_1(chp->cmd_iot, 537 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 538 ret_value &= ~0x01; 539 } 540 /* Register writability test, drive 1. */ 541 if (ret_value & 0x02) { 542 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 543 chp->wdc->select(chp,1); 544 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 545 0, WDSD_IBM | 0x10); 546 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 547 0, 0x02); 548 if (bus_space_read_1(chp->cmd_iot, 549 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 550 ret_value &= ~0x02; 551 bus_space_write_1(chp->cmd_iot, 552 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 553 if (bus_space_read_1(chp->cmd_iot, 554 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 555 ret_value &= ~0x02; 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_sector], 0, 0x01); 558 if (bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_sector], 0) != 0x01) 560 ret_value &= ~0x02; 561 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 562 0, 0x02); 563 if (bus_space_read_1(chp->cmd_iot, 564 chp->cmd_iohs[wd_sector], 0) != 0x02) 565 ret_value &= ~0x02; 566 if (bus_space_read_1(chp->cmd_iot, 567 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 568 ret_value &= ~0x02; 569 } 570 571 if (ret_value == 0) 572 return 0; 573 } 574 575 s = splbio(); 576 577 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 578 chp->wdc->select(chp,0); 579 /* assert SRST, wait for reset to complete */ 580 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 581 delay(10); /* 400ns delay */ 582 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 583 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 584 DELAY(2000); 585 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 586 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 587 delay(10); /* 400ns delay */ 588 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 589 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_IRQACK)) 590 chp->wdc->irqack(chp); 591 splx(s); 592 593 ret_value = __wdcwait_reset(chp, ret_value, poll); 594 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 595 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 596 ret_value), DEBUG_PROBE); 597 598 /* if reset failed, there's nothing here */ 599 if (ret_value == 0) 600 return 0; 601 602 /* 603 * Test presence of drives. First test register signatures looking for 604 * ATAPI devices. If it's not an ATAPI and reset said there may be 605 * something here assume it's ATA or OLD. Ghost will be killed later in 606 * attach routine. 607 */ 608 for (drive = 0; drive < 2; drive++) { 609 if ((ret_value & (0x01 << drive)) == 0) 610 continue; 611 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 612 chp->wdc->select(chp,drive); 613 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 614 WDSD_IBM | (drive << 4)); 615 delay(10); /* 400ns delay */ 616 /* Save registers contents */ 617 sc = bus_space_read_1(chp->cmd_iot, 618 chp->cmd_iohs[wd_seccnt], 0); 619 sn = bus_space_read_1(chp->cmd_iot, 620 chp->cmd_iohs[wd_sector], 0); 621 cl = bus_space_read_1(chp->cmd_iot, 622 chp->cmd_iohs[wd_cyl_lo], 0); 623 ch = bus_space_read_1(chp->cmd_iot, 624 chp->cmd_iohs[wd_cyl_hi], 0); 625 626 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 627 "cl=0x%x ch=0x%x\n", 628 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 629 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 630 /* 631 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 632 * we get wrong values here, so ignore it. 633 */ 634 if (cl == 0x14 && ch == 0xeb) { 635 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 636 } else { 637 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 638 if (chp->wdc == NULL || 639 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 640 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 641 } 642 } 643 return (ret_value); 644 } 645 646 void 647 wdcattach(chp) 648 struct channel_softc *chp; 649 { 650 static int inited = 0; 651 652 if (chp->ch_flags & WDCF_DISABLED) 653 return; 654 655 /* initialise global data */ 656 callout_init(&chp->ch_callout); 657 if (inited == 0) { 658 /* Initialize the wdc_xfer pool. */ 659 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 660 0, 0, "wdcspl", NULL); 661 inited++; 662 } 663 TAILQ_INIT(&chp->ch_queue->sc_xfer); 664 chp->ch_queue->queue_freeze = 0; 665 666 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 667 } 668 669 int wdcactivate(self, act) 670 struct device *self; 671 enum devact act; 672 { 673 struct wdc_softc *wdc = (struct wdc_softc *)self; 674 int s, i, error = 0; 675 676 s = splbio(); 677 switch (act) { 678 case DVACT_ACTIVATE: 679 error = EOPNOTSUPP; 680 break; 681 682 case DVACT_DEACTIVATE: 683 for (i = 0; i < wdc->nchannels; i++) { 684 error = config_deactivate(wdc->channels[i]->atabus); 685 if (error) 686 break; 687 } 688 break; 689 } 690 splx(s); 691 return (error); 692 } 693 694 int 695 wdcdetach(self, flags) 696 struct device *self; 697 int flags; 698 { 699 struct wdc_softc *wdc = (struct wdc_softc *)self; 700 struct channel_softc *chp; 701 int i, error = 0; 702 703 for (i = 0; i < wdc->nchannels; i++) { 704 chp = wdc->channels[i]; 705 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 706 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 707 error = config_detach(chp->atabus, flags); 708 if (error) 709 break; 710 } 711 return (error); 712 } 713 714 /* 715 * Start I/O on a controller, for the given channel. 716 * The first xfer may be not for our channel if the channel queues 717 * are shared. 718 */ 719 void 720 wdcstart(chp) 721 struct channel_softc *chp; 722 { 723 struct wdc_xfer *xfer; 724 725 #ifdef WDC_DIAGNOSTIC 726 int spl1, spl2; 727 728 spl1 = splbio(); 729 spl2 = splbio(); 730 if (spl2 != spl1) { 731 printf("wdcstart: not at splbio()\n"); 732 panic("wdcstart"); 733 } 734 splx(spl2); 735 splx(spl1); 736 #endif /* WDC_DIAGNOSTIC */ 737 738 /* is there a xfer ? */ 739 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 740 return; 741 742 /* adjust chp, in case we have a shared queue */ 743 chp = xfer->chp; 744 745 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 746 return; /* channel aleady active */ 747 } 748 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 749 return; /* queue froozen */ 750 } 751 #ifdef DIAGNOSTIC 752 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 753 panic("wdcstart: channel waiting for irq"); 754 #endif 755 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 756 if (!(*chp->wdc->claim_hw)(chp, 0)) 757 return; 758 759 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 760 chp->channel, xfer->drive), DEBUG_XFERS); 761 chp->ch_flags |= WDCF_ACTIVE; 762 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 763 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 764 chp->ch_drive[xfer->drive].state = 0; 765 } 766 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 767 KASSERT(xfer->c_flags & C_POLL); 768 xfer->c_start(chp, xfer); 769 } 770 771 /* restart an interrupted I/O */ 772 void 773 wdcrestart(v) 774 void *v; 775 { 776 struct channel_softc *chp = v; 777 int s; 778 779 s = splbio(); 780 wdcstart(chp); 781 splx(s); 782 } 783 784 785 /* 786 * Interrupt routine for the controller. Acknowledge the interrupt, check for 787 * errors on the current operation, mark it done if necessary, and start the 788 * next request. Also check for a partially done transfer, and continue with 789 * the next chunk if so. 790 */ 791 int 792 wdcintr(arg) 793 void *arg; 794 { 795 struct channel_softc *chp = arg; 796 struct wdc_xfer *xfer; 797 int ret; 798 799 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 800 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 801 DEBUG_INTR); 802 return (0); 803 } 804 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 805 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 806 /* try to clear the pending interrupt anyway */ 807 (void)bus_space_read_1(chp->cmd_iot, 808 chp->cmd_iohs[wd_status], 0); 809 return (0); 810 } 811 812 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 813 xfer = chp->ch_queue->sc_xfer.tqh_first; 814 if (chp->ch_flags & WDCF_DMA_WAIT) { 815 chp->wdc->dma_status = 816 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 817 xfer->drive, 0); 818 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 819 /* IRQ not for us, not detected by DMA engine */ 820 return 0; 821 } 822 chp->ch_flags &= ~WDCF_DMA_WAIT; 823 } 824 chp->ch_flags &= ~WDCF_IRQ_WAIT; 825 ret = xfer->c_intr(chp, xfer, 1); 826 if (ret == 0) /* irq was not for us, still waiting for irq */ 827 chp->ch_flags |= WDCF_IRQ_WAIT; 828 return (ret); 829 } 830 831 /* Put all disk in RESET state */ 832 void 833 wdc_reset_channel(drvp, flags) 834 struct ata_drive_datas *drvp; 835 int flags; 836 { 837 struct channel_softc *chp = drvp->chnl_softc; 838 int drive; 839 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 840 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 841 DEBUG_FUNCS); 842 if ((flags & AT_POLL) == 0) { 843 if (chp->ch_flags & WDCF_TH_RESET) { 844 /* no need to schedule a reset more than one time */ 845 return; 846 } 847 chp->ch_flags |= WDCF_TH_RESET; 848 chp->ch_queue->queue_freeze++; 849 wakeup(&chp->thread); 850 return; 851 } 852 (void) wdcreset(chp, RESET_POLL); 853 for (drive = 0; drive < 2; drive++) { 854 chp->ch_drive[drive].state = 0; 855 } 856 } 857 858 int 859 wdcreset(chp, poll) 860 struct channel_softc *chp; 861 int poll; 862 { 863 int drv_mask1, drv_mask2; 864 int s = 0; 865 866 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 867 chp->wdc->select(chp,0); 868 if (poll != RESET_SLEEP) 869 s = splbio(); 870 /* master */ 871 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 872 delay(10); /* 400ns delay */ 873 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 874 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 875 delay(2000); 876 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 877 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 878 WDCTL_4BIT | WDCTL_IDS); 879 delay(10); /* 400ns delay */ 880 if (poll != RESET_SLEEP) { 881 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 882 chp->wdc->irqack(chp); 883 splx(s); 884 } 885 886 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 887 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 888 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 889 (poll == RESET_SLEEP) ? 0 : 1); 890 if (drv_mask2 != drv_mask1) { 891 printf("%s channel %d: reset failed for", 892 chp->wdc->sc_dev.dv_xname, chp->channel); 893 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 894 printf(" drive 0"); 895 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 896 printf(" drive 1"); 897 printf("\n"); 898 } 899 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 900 return (drv_mask1 != drv_mask2) ? 1 : 0; 901 } 902 903 static int 904 __wdcwait_reset(chp, drv_mask, poll) 905 struct channel_softc *chp; 906 int drv_mask; 907 { 908 int timeout, nloop; 909 u_int8_t st0 = 0, st1 = 0; 910 #ifdef WDCDEBUG 911 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 912 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 913 #endif 914 915 if (poll) 916 nloop = WDCNDELAY_RST; 917 else 918 nloop = WDC_RESET_WAIT * hz / 1000; 919 /* wait for BSY to deassert */ 920 for (timeout = 0; timeout < nloop; timeout++) { 921 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 922 chp->wdc->select(chp,0); 923 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 924 WDSD_IBM); /* master */ 925 delay(10); 926 st0 = bus_space_read_1(chp->cmd_iot, 927 chp->cmd_iohs[wd_status], 0); 928 #ifdef WDCDEBUG 929 sc0 = bus_space_read_1(chp->cmd_iot, 930 chp->cmd_iohs[wd_seccnt], 0); 931 sn0 = bus_space_read_1(chp->cmd_iot, 932 chp->cmd_iohs[wd_sector], 0); 933 cl0 = bus_space_read_1(chp->cmd_iot, 934 chp->cmd_iohs[wd_cyl_lo], 0); 935 ch0 = bus_space_read_1(chp->cmd_iot, 936 chp->cmd_iohs[wd_cyl_hi], 0); 937 #endif 938 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 939 chp->wdc->select(chp,1); 940 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 941 WDSD_IBM | 0x10); /* slave */ 942 delay(10); 943 st1 = bus_space_read_1(chp->cmd_iot, 944 chp->cmd_iohs[wd_status], 0); 945 #ifdef WDCDEBUG 946 sc1 = bus_space_read_1(chp->cmd_iot, 947 chp->cmd_iohs[wd_seccnt], 0); 948 sn1 = bus_space_read_1(chp->cmd_iot, 949 chp->cmd_iohs[wd_sector], 0); 950 cl1 = bus_space_read_1(chp->cmd_iot, 951 chp->cmd_iohs[wd_cyl_lo], 0); 952 ch1 = bus_space_read_1(chp->cmd_iot, 953 chp->cmd_iohs[wd_cyl_hi], 0); 954 #endif 955 956 if ((drv_mask & 0x01) == 0) { 957 /* no master */ 958 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 959 /* No master, slave is ready, it's done */ 960 goto end; 961 } 962 } else if ((drv_mask & 0x02) == 0) { 963 /* no slave */ 964 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 965 /* No slave, master is ready, it's done */ 966 goto end; 967 } 968 } else { 969 /* Wait for both master and slave to be ready */ 970 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 971 goto end; 972 } 973 } 974 if (poll) 975 delay(WDCDELAY); 976 else 977 tsleep(&nloop, PRIBIO, "atarst", 1); 978 } 979 /* Reset timed out. Maybe it's because drv_mask was not right */ 980 if (st0 & WDCS_BSY) 981 drv_mask &= ~0x01; 982 if (st1 & WDCS_BSY) 983 drv_mask &= ~0x02; 984 end: 985 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 986 "cl=0x%x ch=0x%x\n", 987 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 988 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 989 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 990 "cl=0x%x ch=0x%x\n", 991 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 992 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 993 994 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 995 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 996 st0, st1), DEBUG_PROBE); 997 998 return drv_mask; 999 } 1000 1001 /* 1002 * Wait for a drive to be !BSY, and have mask in its status register. 1003 * return -1 for a timeout after "timeout" ms. 1004 */ 1005 int 1006 __wdcwait(chp, mask, bits, timeout) 1007 struct channel_softc *chp; 1008 int mask, bits, timeout; 1009 { 1010 u_char status; 1011 int time = 0; 1012 1013 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1014 :"none", chp->channel), DEBUG_STATUS); 1015 chp->ch_error = 0; 1016 1017 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1018 1019 for (;;) { 1020 chp->ch_status = status = 1021 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1022 if ((status & (WDCS_BSY | mask)) == bits) 1023 break; 1024 if (++time > timeout) { 1025 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1026 "status %x error %x (mask 0x%x bits 0x%x)\n", 1027 time, status, 1028 bus_space_read_1(chp->cmd_iot, 1029 chp->cmd_iohs[wd_error], 0), mask, bits), 1030 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1031 return(WDCWAIT_TOUT); 1032 } 1033 delay(WDCDELAY); 1034 } 1035 #ifdef WDCDEBUG 1036 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1037 printf("__wdcwait: did busy-wait, time=%d\n", time); 1038 #endif 1039 if (status & WDCS_ERR) 1040 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1041 chp->cmd_iohs[wd_error], 0); 1042 #ifdef WDCNDELAY_DEBUG 1043 /* After autoconfig, there should be no long delays. */ 1044 if (!cold && time > WDCNDELAY_DEBUG) { 1045 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1046 if (xfer == NULL) 1047 printf("%s channel %d: warning: busy-wait took %dus\n", 1048 chp->wdc->sc_dev.dv_xname, chp->channel, 1049 WDCDELAY * time); 1050 else 1051 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1052 chp->wdc->sc_dev.dv_xname, chp->channel, 1053 xfer->drive, 1054 WDCDELAY * time); 1055 } 1056 #endif 1057 return(WDCWAIT_OK); 1058 } 1059 1060 /* 1061 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1062 * thread if possible 1063 */ 1064 int 1065 wdcwait(chp, mask, bits, timeout, flags) 1066 struct channel_softc *chp; 1067 int mask, bits, timeout, flags; 1068 { 1069 int error, i, timeout_hz = mstohz(timeout); 1070 1071 if (timeout_hz == 0 || 1072 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1073 error = __wdcwait(chp, mask, bits, timeout); 1074 else { 1075 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1076 if (error != 0) { 1077 if ((chp->ch_flags & WDCF_TH_RUN) || 1078 (flags & AT_WAIT)) { 1079 /* 1080 * we're running in the channel thread 1081 * or some userland thread context 1082 */ 1083 for (i = 0; i < timeout_hz; i++) { 1084 if (__wdcwait(chp, mask, bits, 1085 WDCDELAY_POLL) == 0) { 1086 error = 0; 1087 break; 1088 } 1089 tsleep(&chp, PRIBIO, "atapoll", 1); 1090 } 1091 } else { 1092 /* 1093 * we're probably in interrupt context, 1094 * ask the thread to come back here 1095 */ 1096 #ifdef DIAGNOSTIC 1097 if (chp->ch_queue->queue_freeze > 0) 1098 panic("wdcwait: queue_freeze"); 1099 #endif 1100 chp->ch_queue->queue_freeze++; 1101 wakeup(&chp->thread); 1102 return(WDCWAIT_THR); 1103 } 1104 } 1105 } 1106 return(error); 1107 } 1108 1109 1110 /* 1111 * Busy-wait for DMA to complete 1112 */ 1113 int 1114 wdc_dmawait(chp, xfer, timeout) 1115 struct channel_softc *chp; 1116 struct wdc_xfer *xfer; 1117 int timeout; 1118 { 1119 int time; 1120 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1121 chp->wdc->dma_status = 1122 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1123 chp->channel, xfer->drive, 0); 1124 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1125 return 0; 1126 delay(WDCDELAY); 1127 } 1128 /* timeout, force a DMA halt */ 1129 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1130 chp->channel, xfer->drive, 1); 1131 return 1; 1132 } 1133 1134 void 1135 wdctimeout(arg) 1136 void *arg; 1137 { 1138 struct channel_softc *chp = (struct channel_softc *)arg; 1139 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1140 int s; 1141 1142 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1143 1144 s = splbio(); 1145 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1146 __wdcerror(chp, "lost interrupt"); 1147 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1148 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1149 xfer->c_bcount, 1150 xfer->c_skip); 1151 if (chp->ch_flags & WDCF_DMA_WAIT) { 1152 chp->wdc->dma_status = 1153 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1154 chp->channel, xfer->drive, 1); 1155 chp->ch_flags &= ~WDCF_DMA_WAIT; 1156 } 1157 /* 1158 * Call the interrupt routine. If we just missed an interrupt, 1159 * it will do what's needed. Else, it will take the needed 1160 * action (reset the device). 1161 * Before that we need to reinstall the timeout callback, 1162 * in case it will miss another irq while in this transfer 1163 * We arbitray chose it to be 1s 1164 */ 1165 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1166 xfer->c_flags |= C_TIMEOU; 1167 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1168 xfer->c_intr(chp, xfer, 1); 1169 } else 1170 __wdcerror(chp, "missing untimeout"); 1171 splx(s); 1172 } 1173 1174 /* 1175 * Probe drive's capabilities, for use by the controller later 1176 * Assumes drvp points to an existing drive. 1177 * XXX this should be a controller-indep function 1178 */ 1179 void 1180 wdc_probe_caps(drvp) 1181 struct ata_drive_datas *drvp; 1182 { 1183 struct ataparams params, params2; 1184 struct channel_softc *chp = drvp->chnl_softc; 1185 struct device *drv_dev = drvp->drv_softc; 1186 struct wdc_softc *wdc = chp->wdc; 1187 int i, printed; 1188 char *sep = ""; 1189 int cf_flags; 1190 1191 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1192 /* IDENTIFY failed. Can't tell more about the device */ 1193 return; 1194 } 1195 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1196 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1197 /* 1198 * Controller claims 16 and 32 bit transfers. 1199 * Re-do an IDENTIFY with 32-bit transfers, 1200 * and compare results. 1201 */ 1202 drvp->drive_flags |= DRIVE_CAP32; 1203 ata_get_params(drvp, AT_WAIT, ¶ms2); 1204 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1205 /* Not good. fall back to 16bits */ 1206 drvp->drive_flags &= ~DRIVE_CAP32; 1207 } else { 1208 aprint_normal("%s: 32-bit data port\n", 1209 drv_dev->dv_xname); 1210 } 1211 } 1212 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1213 if (params.atap_ata_major > 0x01 && 1214 params.atap_ata_major != 0xffff) { 1215 for (i = 14; i > 0; i--) { 1216 if (params.atap_ata_major & (1 << i)) { 1217 aprint_normal("%s: ATA version %d\n", 1218 drv_dev->dv_xname, i); 1219 drvp->ata_vers = i; 1220 break; 1221 } 1222 } 1223 } 1224 #endif 1225 1226 /* An ATAPI device is at last PIO mode 3 */ 1227 if (drvp->drive_flags & DRIVE_ATAPI) 1228 drvp->PIO_mode = 3; 1229 1230 /* 1231 * It's not in the specs, but it seems that some drive 1232 * returns 0xffff in atap_extensions when this field is invalid 1233 */ 1234 if (params.atap_extensions != 0xffff && 1235 (params.atap_extensions & WDC_EXT_MODES)) { 1236 printed = 0; 1237 /* 1238 * XXX some drives report something wrong here (they claim to 1239 * support PIO mode 8 !). As mode is coded on 3 bits in 1240 * SET FEATURE, limit it to 7 (so limit i to 4). 1241 * If higher mode than 7 is found, abort. 1242 */ 1243 for (i = 7; i >= 0; i--) { 1244 if ((params.atap_piomode_supp & (1 << i)) == 0) 1245 continue; 1246 if (i > 4) 1247 return; 1248 /* 1249 * See if mode is accepted. 1250 * If the controller can't set its PIO mode, 1251 * assume the defaults are good, so don't try 1252 * to set it 1253 */ 1254 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1255 /* 1256 * It's OK to pool here, it's fast enouth 1257 * to not bother waiting for interrupt 1258 */ 1259 if (ata_set_mode(drvp, 0x08 | (i + 3), 1260 AT_WAIT) != CMD_OK) 1261 continue; 1262 if (!printed) { 1263 aprint_normal("%s: drive supports PIO mode %d", 1264 drv_dev->dv_xname, i + 3); 1265 sep = ","; 1266 printed = 1; 1267 } 1268 /* 1269 * If controller's driver can't set its PIO mode, 1270 * get the highter one for the drive. 1271 */ 1272 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1273 wdc->PIO_cap >= i + 3) { 1274 drvp->PIO_mode = i + 3; 1275 drvp->PIO_cap = i + 3; 1276 break; 1277 } 1278 } 1279 if (!printed) { 1280 /* 1281 * We didn't find a valid PIO mode. 1282 * Assume the values returned for DMA are buggy too 1283 */ 1284 return; 1285 } 1286 drvp->drive_flags |= DRIVE_MODE; 1287 printed = 0; 1288 for (i = 7; i >= 0; i--) { 1289 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1290 continue; 1291 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1292 (wdc->cap & WDC_CAPABILITY_MODE)) 1293 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1294 != CMD_OK) 1295 continue; 1296 if (!printed) { 1297 aprint_normal("%s DMA mode %d", sep, i); 1298 sep = ","; 1299 printed = 1; 1300 } 1301 if (wdc->cap & WDC_CAPABILITY_DMA) { 1302 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1303 wdc->DMA_cap < i) 1304 continue; 1305 drvp->DMA_mode = i; 1306 drvp->DMA_cap = i; 1307 drvp->drive_flags |= DRIVE_DMA; 1308 } 1309 break; 1310 } 1311 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1312 printed = 0; 1313 for (i = 7; i >= 0; i--) { 1314 if ((params.atap_udmamode_supp & (1 << i)) 1315 == 0) 1316 continue; 1317 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1318 (wdc->cap & WDC_CAPABILITY_UDMA)) 1319 if (ata_set_mode(drvp, 0x40 | i, 1320 AT_WAIT) != CMD_OK) 1321 continue; 1322 if (!printed) { 1323 aprint_normal("%s Ultra-DMA mode %d", 1324 sep, i); 1325 if (i == 2) 1326 aprint_normal(" (Ultra/33)"); 1327 else if (i == 4) 1328 aprint_normal(" (Ultra/66)"); 1329 else if (i == 5) 1330 aprint_normal(" (Ultra/100)"); 1331 else if (i == 6) 1332 aprint_normal(" (Ultra/133)"); 1333 sep = ","; 1334 printed = 1; 1335 } 1336 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1337 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1338 wdc->UDMA_cap < i) 1339 continue; 1340 drvp->UDMA_mode = i; 1341 drvp->UDMA_cap = i; 1342 drvp->drive_flags |= DRIVE_UDMA; 1343 } 1344 break; 1345 } 1346 } 1347 aprint_normal("\n"); 1348 } 1349 1350 /* Try to guess ATA version here, if it didn't get reported */ 1351 if (drvp->ata_vers == 0) { 1352 if (drvp->drive_flags & DRIVE_UDMA) 1353 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1354 else if (drvp->PIO_cap > 2) 1355 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1356 } 1357 cf_flags = drv_dev->dv_cfdata->cf_flags; 1358 if (cf_flags & ATA_CONFIG_PIO_SET) { 1359 drvp->PIO_mode = 1360 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1361 drvp->drive_flags |= DRIVE_MODE; 1362 } 1363 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1364 /* don't care about DMA modes */ 1365 return; 1366 } 1367 if (cf_flags & ATA_CONFIG_DMA_SET) { 1368 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1369 ATA_CONFIG_DMA_DISABLE) { 1370 drvp->drive_flags &= ~DRIVE_DMA; 1371 } else { 1372 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1373 ATA_CONFIG_DMA_OFF; 1374 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1375 } 1376 } 1377 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1378 /* don't care about UDMA modes */ 1379 return; 1380 } 1381 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1382 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1383 ATA_CONFIG_UDMA_DISABLE) { 1384 drvp->drive_flags &= ~DRIVE_UDMA; 1385 } else { 1386 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1387 ATA_CONFIG_UDMA_OFF; 1388 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1389 } 1390 } 1391 } 1392 1393 /* 1394 * downgrade the transfer mode of a drive after an error. return 1 if 1395 * downgrade was possible, 0 otherwise. 1396 */ 1397 int 1398 wdc_downgrade_mode(drvp, flags) 1399 struct ata_drive_datas *drvp; 1400 { 1401 struct channel_softc *chp = drvp->chnl_softc; 1402 struct device *drv_dev = drvp->drv_softc; 1403 struct wdc_softc *wdc = chp->wdc; 1404 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1405 1406 /* if drive or controller don't know its mode, we can't do much */ 1407 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1408 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1409 return 0; 1410 /* current drive mode was set by a config flag, let it this way */ 1411 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1412 (cf_flags & ATA_CONFIG_DMA_SET) || 1413 (cf_flags & ATA_CONFIG_UDMA_SET)) 1414 return 0; 1415 1416 /* 1417 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1418 * Maybe we didn't properly notice the cable type 1419 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1420 * It helps in some cases. 1421 */ 1422 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1423 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1424 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1425 drv_dev->dv_xname, drvp->UDMA_mode); 1426 } 1427 1428 /* 1429 * If we were using ultra-DMA, don't downgrade to multiword DMA 1430 * if we noticed a CRC error. It has been noticed that CRC errors 1431 * in ultra-DMA lead to silent data corruption in multiword DMA. 1432 * Data corruption is less likely to occur in PIO mode. 1433 */ 1434 else if ((drvp->drive_flags & DRIVE_UDMA) && 1435 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1436 drvp->drive_flags &= ~DRIVE_UDMA; 1437 drvp->drive_flags |= DRIVE_DMA; 1438 drvp->DMA_mode = drvp->DMA_cap; 1439 printf("%s: transfer error, downgrading to DMA mode %d\n", 1440 drv_dev->dv_xname, drvp->DMA_mode); 1441 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1442 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1443 drvp->PIO_mode = drvp->PIO_cap; 1444 printf("%s: transfer error, downgrading to PIO mode %d\n", 1445 drv_dev->dv_xname, drvp->PIO_mode); 1446 } else /* already using PIO, can't downgrade */ 1447 return 0; 1448 1449 wdc->set_modes(chp); 1450 wdc_print_modes(chp); 1451 /* reset the channel, which will shedule all drives for setup */ 1452 wdc_reset_channel(drvp, flags); 1453 return 1; 1454 } 1455 1456 int 1457 wdc_exec_command(drvp, wdc_c) 1458 struct ata_drive_datas *drvp; 1459 struct wdc_command *wdc_c; 1460 { 1461 struct channel_softc *chp = drvp->chnl_softc; 1462 struct wdc_xfer *xfer; 1463 int s, ret; 1464 1465 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1466 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1467 DEBUG_FUNCS); 1468 1469 /* set up an xfer and queue. Wait for completion */ 1470 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1471 WDC_NOSLEEP); 1472 if (xfer == NULL) { 1473 return WDC_TRY_AGAIN; 1474 } 1475 1476 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1477 wdc_c->flags |= AT_POLL; 1478 if (wdc_c->flags & AT_POLL) 1479 xfer->c_flags |= C_POLL; 1480 xfer->drive = drvp->drive; 1481 xfer->databuf = wdc_c->data; 1482 xfer->c_bcount = wdc_c->bcount; 1483 xfer->cmd = wdc_c; 1484 xfer->c_start = __wdccommand_start; 1485 xfer->c_intr = __wdccommand_intr; 1486 xfer->c_kill_xfer = __wdccommand_done; 1487 1488 s = splbio(); 1489 wdc_exec_xfer(chp, xfer); 1490 #ifdef DIAGNOSTIC 1491 if ((wdc_c->flags & AT_POLL) != 0 && 1492 (wdc_c->flags & AT_DONE) == 0) 1493 panic("wdc_exec_command: polled command not done"); 1494 #endif 1495 if (wdc_c->flags & AT_DONE) { 1496 ret = WDC_COMPLETE; 1497 } else { 1498 if (wdc_c->flags & AT_WAIT) { 1499 while ((wdc_c->flags & AT_DONE) == 0) { 1500 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1501 } 1502 ret = WDC_COMPLETE; 1503 } else { 1504 ret = WDC_QUEUED; 1505 } 1506 } 1507 splx(s); 1508 return ret; 1509 } 1510 1511 void 1512 __wdccommand_start(chp, xfer) 1513 struct channel_softc *chp; 1514 struct wdc_xfer *xfer; 1515 { 1516 int drive = xfer->drive; 1517 struct wdc_command *wdc_c = xfer->cmd; 1518 1519 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1520 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1521 DEBUG_FUNCS); 1522 1523 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1524 chp->wdc->select(chp,drive); 1525 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1526 WDSD_IBM | (drive << 4)); 1527 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1528 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1529 case WDCWAIT_OK: 1530 break; 1531 case WDCWAIT_TOUT: 1532 wdc_c->flags |= AT_TIMEOU; 1533 __wdccommand_done(chp, xfer); 1534 return; 1535 case WDCWAIT_THR: 1536 return; 1537 } 1538 if (wdc_c->flags & AT_POLL) { 1539 /* polled command, disable interrupts */ 1540 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1541 WDCTL_4BIT | WDCTL_IDS); 1542 } 1543 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1544 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1545 1546 if ((wdc_c->flags & AT_POLL) == 0) { 1547 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1548 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1549 wdctimeout, chp); 1550 return; 1551 } 1552 /* 1553 * Polled command. Wait for drive ready or drq. Done in intr(). 1554 * Wait for at last 400ns for status bit to be valid. 1555 */ 1556 delay(10); /* 400ns delay */ 1557 __wdccommand_intr(chp, xfer, 0); 1558 } 1559 1560 int 1561 __wdccommand_intr(chp, xfer, irq) 1562 struct channel_softc *chp; 1563 struct wdc_xfer *xfer; 1564 int irq; 1565 { 1566 struct wdc_command *wdc_c = xfer->cmd; 1567 int bcount = wdc_c->bcount; 1568 char *data = wdc_c->data; 1569 int wflags; 1570 1571 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1572 /* both wait and poll, we can tsleep here */ 1573 wflags = AT_WAIT | AT_POLL; 1574 } else { 1575 wflags = AT_POLL; 1576 } 1577 1578 again: 1579 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1580 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1581 /* 1582 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1583 * Reselect again, it doesn't hurt for others commands, and the time 1584 * penalty for the extra regiter write is acceptable, 1585 * wdc_exec_command() isn't called often (mosly for autoconfig) 1586 */ 1587 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1588 WDSD_IBM | (xfer->drive << 4)); 1589 if ((wdc_c->flags & AT_XFDONE) != 0) { 1590 /* 1591 * We have completed a data xfer. The drive should now be 1592 * in its initial state 1593 */ 1594 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1595 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1596 wflags) == WDCWAIT_TOUT) { 1597 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1598 return 0; /* IRQ was not for us */ 1599 wdc_c->flags |= AT_TIMEOU; 1600 } 1601 goto out; 1602 } 1603 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1604 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1605 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1606 return 0; /* IRQ was not for us */ 1607 wdc_c->flags |= AT_TIMEOU; 1608 goto out; 1609 } 1610 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1611 chp->wdc->irqack(chp); 1612 if (wdc_c->flags & AT_READ) { 1613 if ((chp->ch_status & WDCS_DRQ) == 0) { 1614 wdc_c->flags |= AT_TIMEOU; 1615 goto out; 1616 } 1617 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1618 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1619 0, (u_int32_t*)data, bcount >> 2); 1620 data += bcount & 0xfffffffc; 1621 bcount = bcount & 0x03; 1622 } 1623 if (bcount > 0) 1624 bus_space_read_multi_2(chp->cmd_iot, 1625 chp->cmd_iohs[wd_data], 0, 1626 (u_int16_t *)data, bcount >> 1); 1627 /* at this point the drive should be in its initial state */ 1628 wdc_c->flags |= AT_XFDONE; 1629 /* XXX should read status register here ? */ 1630 } else if (wdc_c->flags & AT_WRITE) { 1631 if ((chp->ch_status & WDCS_DRQ) == 0) { 1632 wdc_c->flags |= AT_TIMEOU; 1633 goto out; 1634 } 1635 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1636 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1637 0, (u_int32_t*)data, bcount >> 2); 1638 data += bcount & 0xfffffffc; 1639 bcount = bcount & 0x03; 1640 } 1641 if (bcount > 0) 1642 bus_space_write_multi_2(chp->cmd_iot, 1643 chp->cmd_iohs[wd_data], 0, 1644 (u_int16_t *)data, bcount >> 1); 1645 wdc_c->flags |= AT_XFDONE; 1646 if ((wdc_c->flags & AT_POLL) == 0) { 1647 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1648 callout_reset(&chp->ch_callout, 1649 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1650 return 1; 1651 } else { 1652 goto again; 1653 } 1654 } 1655 out: 1656 __wdccommand_done(chp, xfer); 1657 return 1; 1658 } 1659 1660 void 1661 __wdccommand_done(chp, xfer) 1662 struct channel_softc *chp; 1663 struct wdc_xfer *xfer; 1664 { 1665 struct wdc_command *wdc_c = xfer->cmd; 1666 1667 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1668 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1669 1670 callout_stop(&chp->ch_callout); 1671 1672 if (chp->ch_status & WDCS_DWF) 1673 wdc_c->flags |= AT_DF; 1674 if (chp->ch_status & WDCS_ERR) { 1675 wdc_c->flags |= AT_ERROR; 1676 wdc_c->r_error = chp->ch_error; 1677 } 1678 wdc_c->flags |= AT_DONE; 1679 if ((wdc_c->flags & AT_READREG) != 0 && 1680 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1681 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1682 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1683 chp->cmd_iohs[wd_sdh], 0); 1684 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1685 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1686 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1687 chp->cmd_iohs[wd_cyl_lo], 0); 1688 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1689 chp->cmd_iohs[wd_sector], 0); 1690 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1691 chp->cmd_iohs[wd_seccnt], 0); 1692 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1693 chp->cmd_iohs[wd_error], 0); 1694 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1695 chp->cmd_iohs[wd_precomp], 0); 1696 } 1697 1698 if (wdc_c->flags & AT_POLL) { 1699 /* enable interrupts */ 1700 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1701 WDCTL_4BIT); 1702 } 1703 wdc_free_xfer(chp, xfer); 1704 if (wdc_c->flags & AT_WAIT) 1705 wakeup(wdc_c); 1706 else if (wdc_c->callback) 1707 wdc_c->callback(wdc_c->callback_arg); 1708 wdcstart(chp); 1709 return; 1710 } 1711 1712 /* 1713 * Send a command. The drive should be ready. 1714 * Assumes interrupts are blocked. 1715 */ 1716 void 1717 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1718 struct channel_softc *chp; 1719 u_int8_t drive; 1720 u_int8_t command; 1721 u_int16_t cylin; 1722 u_int8_t head, sector, count, precomp; 1723 { 1724 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1725 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1726 chp->channel, drive, command, cylin, head, sector, count, precomp), 1727 DEBUG_FUNCS); 1728 1729 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1730 chp->wdc->select(chp,drive); 1731 1732 /* Select drive, head, and addressing mode. */ 1733 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1734 WDSD_IBM | (drive << 4) | head); 1735 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1736 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1737 precomp); 1738 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1739 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1740 0, cylin >> 8); 1741 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1742 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1743 1744 /* Send command. */ 1745 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1746 return; 1747 } 1748 1749 /* 1750 * Send a 48-bit addressing command. The drive should be ready. 1751 * Assumes interrupts are blocked. 1752 */ 1753 void 1754 wdccommandext(chp, drive, command, blkno, count) 1755 struct channel_softc *chp; 1756 u_int8_t drive; 1757 u_int8_t command; 1758 u_int64_t blkno; 1759 u_int16_t count; 1760 { 1761 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1762 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1763 chp->channel, drive, command, (u_int32_t) blkno, count), 1764 DEBUG_FUNCS); 1765 1766 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1767 chp->wdc->select(chp,drive); 1768 1769 /* Select drive, head, and addressing mode. */ 1770 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1771 (drive << 4) | WDSD_LBA); 1772 1773 /* previous */ 1774 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1775 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1776 0, count >> 8); 1777 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1778 0, blkno >> 40); 1779 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1780 0, blkno >> 32); 1781 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1782 0, blkno >> 24); 1783 1784 /* current */ 1785 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1786 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1787 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1788 0, blkno >> 16); 1789 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1790 0, blkno >> 8); 1791 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1792 1793 /* Send command. */ 1794 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1795 return; 1796 } 1797 1798 /* 1799 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1800 * tested by the caller. 1801 */ 1802 void 1803 wdccommandshort(chp, drive, command) 1804 struct channel_softc *chp; 1805 int drive; 1806 int command; 1807 { 1808 1809 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1810 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1811 DEBUG_FUNCS); 1812 1813 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1814 chp->wdc->select(chp,drive); 1815 1816 /* Select drive. */ 1817 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1818 WDSD_IBM | (drive << 4)); 1819 1820 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1821 } 1822 1823 /* Add a command to the queue and start controller. Must be called at splbio */ 1824 1825 void 1826 wdc_exec_xfer(chp, xfer) 1827 struct channel_softc *chp; 1828 struct wdc_xfer *xfer; 1829 { 1830 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1831 chp->channel, xfer->drive), DEBUG_XFERS); 1832 1833 /* complete xfer setup */ 1834 xfer->chp = chp; 1835 1836 /* 1837 * If we are a polled command, and the list is not empty, 1838 * we are doing a dump. Drop the list to allow the polled command 1839 * to complete, we're going to reboot soon anyway. 1840 */ 1841 if ((xfer->c_flags & C_POLL) != 0 && 1842 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1843 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1844 } 1845 /* insert at the end of command list */ 1846 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1847 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1848 chp->ch_flags), DEBUG_XFERS); 1849 wdcstart(chp); 1850 } 1851 1852 struct wdc_xfer * 1853 wdc_get_xfer(flags) 1854 int flags; 1855 { 1856 struct wdc_xfer *xfer; 1857 int s; 1858 1859 s = splbio(); 1860 xfer = pool_get(&wdc_xfer_pool, 1861 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1862 splx(s); 1863 if (xfer != NULL) { 1864 memset(xfer, 0, sizeof(struct wdc_xfer)); 1865 } 1866 return xfer; 1867 } 1868 1869 void 1870 wdc_free_xfer(chp, xfer) 1871 struct channel_softc *chp; 1872 struct wdc_xfer *xfer; 1873 { 1874 struct wdc_softc *wdc = chp->wdc; 1875 int s; 1876 1877 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1878 (*wdc->free_hw)(chp); 1879 s = splbio(); 1880 chp->ch_flags &= ~WDCF_ACTIVE; 1881 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1882 pool_put(&wdc_xfer_pool, xfer); 1883 splx(s); 1884 } 1885 1886 /* 1887 * Kill off all pending xfers for a channel_softc. 1888 * 1889 * Must be called at splbio(). 1890 */ 1891 void 1892 wdc_kill_pending(chp) 1893 struct channel_softc *chp; 1894 { 1895 struct wdc_xfer *xfer; 1896 1897 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1898 chp = xfer->chp; 1899 (*xfer->c_kill_xfer)(chp, xfer); 1900 } 1901 } 1902 1903 static void 1904 __wdcerror(chp, msg) 1905 struct channel_softc *chp; 1906 char *msg; 1907 { 1908 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1909 1910 if (xfer == NULL) 1911 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1912 msg); 1913 else 1914 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1915 chp->channel, xfer->drive, msg); 1916 } 1917 1918 /* 1919 * the bit bucket 1920 */ 1921 void 1922 wdcbit_bucket(chp, size) 1923 struct channel_softc *chp; 1924 int size; 1925 { 1926 1927 for (; size >= 2; size -= 2) 1928 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1929 if (size) 1930 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1931 } 1932 1933 int 1934 wdc_addref(chp) 1935 struct channel_softc *chp; 1936 { 1937 struct wdc_softc *wdc = chp->wdc; 1938 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1939 int s, error = 0; 1940 1941 s = splbio(); 1942 if (adapt->adapt_refcnt++ == 0 && 1943 adapt->adapt_enable != NULL) { 1944 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1945 if (error) 1946 adapt->adapt_refcnt--; 1947 } 1948 splx(s); 1949 return (error); 1950 } 1951 1952 void 1953 wdc_delref(chp) 1954 struct channel_softc *chp; 1955 { 1956 struct wdc_softc *wdc = chp->wdc; 1957 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1958 int s; 1959 1960 s = splbio(); 1961 if (adapt->adapt_refcnt-- == 1 && 1962 adapt->adapt_enable != NULL) 1963 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1964 splx(s); 1965 } 1966 1967 void 1968 wdc_print_modes(struct channel_softc *chp) 1969 { 1970 int drive; 1971 struct ata_drive_datas *drvp; 1972 1973 for (drive = 0; drive < 2; drive++) { 1974 drvp = &chp->ch_drive[drive]; 1975 if ((drvp->drive_flags & DRIVE) == 0) 1976 continue; 1977 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1978 drvp->drv_softc->dv_xname, 1979 chp->wdc->sc_dev.dv_xname, 1980 chp->channel, drive, drvp->PIO_mode); 1981 if (drvp->drive_flags & DRIVE_DMA) 1982 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1983 if (drvp->drive_flags & DRIVE_UDMA) { 1984 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1985 if (drvp->UDMA_mode == 2) 1986 aprint_normal(" (Ultra/33)"); 1987 else if (drvp->UDMA_mode == 4) 1988 aprint_normal(" (Ultra/66)"); 1989 else if (drvp->UDMA_mode == 5) 1990 aprint_normal(" (Ultra/100)"); 1991 else if (drvp->UDMA_mode == 6) 1992 aprint_normal(" (Ultra/133)"); 1993 } 1994 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1995 aprint_normal(" (using DMA data transfers)"); 1996 aprint_normal("\n"); 1997 } 1998 } 1999
Indexes created Tue Sep 23 21:09:50 GMT 2025