wdc.c revision 1.165
1 /* $NetBSD: wdc.c,v 1.165 2004/01/01 17:18:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.165 2004/01/01 17:18:53 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 int wdcprobe1 __P((struct channel_softc*, int)); 147 static void __wdcerror __P((struct channel_softc*, char *)); 148 static int __wdcwait_reset __P((struct channel_softc *, int, int)); 149 void __wdccommand_done __P((struct channel_softc *, struct ata_xfer *)); 150 void __wdccommand_start __P((struct channel_softc *, struct ata_xfer *)); 151 int __wdccommand_intr __P((struct channel_softc *, struct ata_xfer *, int)); 152 int __wdcwait __P((struct channel_softc *, int, int, int)); 153 void wdc_finish_attach __P((struct device *)); 154 void wdc_channel_attach __P((struct channel_softc *)); 155 156 #define DEBUG_INTR 0x01 157 #define DEBUG_XFERS 0x02 158 #define DEBUG_STATUS 0x04 159 #define DEBUG_FUNCS 0x08 160 #define DEBUG_PROBE 0x10 161 #define DEBUG_DETACH 0x20 162 #define DEBUG_DELAY 0x40 163 #ifdef WDCDEBUG 164 int wdcdebug_mask = 0; 165 int wdc_nxfer = 0; 166 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 167 #else 168 #define WDCDEBUG_PRINT(args, level) 169 #endif 170 171 /* 172 * A queue of atabus instances, used to ensure the same bus probe order 173 * for a given hardware configuration at each boot. 174 */ 175 struct atabus_initq_head atabus_initq_head = 176 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 177 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 178 179 /* Test to see controller with at last one attached drive is there. 180 * Returns a bit for each possible drive found (0x01 for drive 0, 181 * 0x02 for drive 1). 182 * Logic: 183 * - If a status register is at 0xff, assume there is no drive here 184 * (ISA has pull-up resistors). Similarly if the status register has 185 * the value we last wrote to the bus (for IDE interfaces without pullups). 186 * If no drive at all -> return. 187 * - reset the controller, wait for it to complete (may take up to 31s !). 188 * If timeout -> return. 189 * - test ATA/ATAPI signatures. If at last one drive found -> return. 190 * - try an ATA command on the master. 191 */ 192 193 static void 194 wdc_drvprobe(struct channel_softc *chp) 195 { 196 struct ataparams params; 197 u_int8_t st0 = 0, st1 = 0; 198 int i, error; 199 200 if (wdcprobe1(chp, 0) == 0) { 201 /* No drives, abort the attach here. */ 202 return; 203 } 204 205 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 206 for (i = 0; i < mstohz(3000); i++) { 207 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 208 chp->wdc->select(chp,0); 209 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 210 WDSD_IBM); 211 delay(10); /* 400ns delay */ 212 st0 = bus_space_read_1(chp->cmd_iot, 213 chp->cmd_iohs[wd_status], 0); 214 215 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 216 chp->wdc->select(chp,1); 217 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 218 WDSD_IBM | 0x10); 219 delay(10); /* 400ns delay */ 220 st1 = bus_space_read_1(chp->cmd_iot, 221 chp->cmd_iohs[wd_status], 0); 222 223 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 224 == 0 || 225 (st0 & WDCS_DRDY)) && 226 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 227 == 0 || 228 (st1 & WDCS_DRDY))) 229 break; 230 tsleep(¶ms, PRIBIO, "atadrdy", 1); 231 } 232 if ((st0 & WDCS_DRDY) == 0) 233 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 234 if ((st1 & WDCS_DRDY) == 0) 235 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 236 237 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 238 chp->wdc->sc_dev.dv_xname, 239 chp->channel, st0, st1), DEBUG_PROBE); 240 241 /* Wait a bit, some devices are weird just after a reset. */ 242 delay(5000); 243 244 for (i = 0; i < 2; i++) { 245 chp->ch_drive[i].chnl_softc = chp; 246 chp->ch_drive[i].drive = i; 247 /* 248 * Init error counter so that an error withing the first xfers 249 * will trigger a downgrade 250 */ 251 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 252 253 /* If controller can't do 16bit flag the drives as 32bit */ 254 if ((chp->wdc->cap & 255 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 256 WDC_CAPABILITY_DATA32) 257 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 258 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 259 continue; 260 261 /* Shortcut in case we've been shutdown */ 262 if (chp->ch_flags & WDCF_SHUTDOWN) 263 return; 264 265 /* issue an identify, to try to detect ghosts */ 266 error = ata_get_params(&chp->ch_drive[i], 267 AT_WAIT | AT_POLL, ¶ms); 268 if (error != CMD_OK) { 269 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 270 271 /* Shortcut in case we've been shutdown */ 272 if (chp->ch_flags & WDCF_SHUTDOWN) 273 return; 274 275 error = ata_get_params(&chp->ch_drive[i], 276 AT_WAIT | AT_POLL, ¶ms); 277 } 278 if (error == CMD_OK) { 279 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 280 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 281 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 282 } else { 283 chp->ch_drive[i].drive_flags &= 284 ~(DRIVE_ATA | DRIVE_ATAPI); 285 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 286 chp->wdc->sc_dev.dv_xname, 287 chp->channel, i, error), DEBUG_PROBE); 288 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 289 continue; 290 /* 291 * Pre-ATA drive ? 292 * Test registers writability (Error register not 293 * writable, but cyllo is), then try an ATA command. 294 */ 295 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 296 chp->wdc->select(chp,i); 297 bus_space_write_1(chp->cmd_iot, 298 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 299 delay(10); /* 400ns delay */ 300 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 301 0, 0x58); 302 bus_space_write_1(chp->cmd_iot, 303 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 304 if (bus_space_read_1(chp->cmd_iot, 305 chp->cmd_iohs[wd_error], 0) == 0x58 || 306 bus_space_read_1(chp->cmd_iot, 307 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 308 WDCDEBUG_PRINT(("%s:%d:%d: register " 309 "writability failed\n", 310 chp->wdc->sc_dev.dv_xname, 311 chp->channel, i), DEBUG_PROBE); 312 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 313 continue; 314 } 315 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 316 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 317 chp->wdc->sc_dev.dv_xname, 318 chp->channel, i), DEBUG_PROBE); 319 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 320 continue; 321 } 322 bus_space_write_1(chp->cmd_iot, 323 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 324 delay(10); /* 400ns delay */ 325 if (wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 326 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 327 chp->wdc->sc_dev.dv_xname, 328 chp->channel, i), DEBUG_PROBE); 329 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 330 } else { 331 chp->ch_drive[0].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 chp->ch_drive[1].drive_flags &= 334 ~(DRIVE_ATA | DRIVE_ATAPI); 335 } 336 } 337 } 338 } 339 340 void 341 atabusconfig(struct atabus_softc *atabus_sc) 342 { 343 struct channel_softc *chp = atabus_sc->sc_chan; 344 int i, error, need_delref = 0; 345 struct atabus_initq *atabus_initq = NULL; 346 347 if ((error = wdc_addref(chp)) != 0) { 348 aprint_error("%s: unable to enable controller\n", 349 chp->wdc->sc_dev.dv_xname); 350 goto out; 351 } 352 need_delref = 1; 353 354 /* Probe for the drives. */ 355 (*chp->wdc->drv_probe)(chp); 356 357 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 358 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 359 DEBUG_PROBE); 360 361 /* If no drives, abort here */ 362 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 363 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 364 goto out; 365 366 /* Shortcut in case we've been shutdown */ 367 if (chp->ch_flags & WDCF_SHUTDOWN) 368 goto out; 369 370 /* Make sure the devices probe in atabus order to avoid jitter. */ 371 simple_lock(&atabus_interlock); 372 while(1) { 373 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 374 if (atabus_initq->atabus_sc == atabus_sc) 375 break; 376 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 377 &atabus_interlock); 378 } 379 simple_unlock(&atabus_interlock); 380 381 /* 382 * Attach an ATAPI bus, if needed. 383 */ 384 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 385 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 386 #if NATAPIBUS > 0 387 wdc_atapibus_attach(atabus_sc); 388 #else 389 /* 390 * Fake the autoconfig "not configured" message 391 */ 392 aprint_normal("atapibus at %s not configured\n", 393 chp->wdc->sc_dev.dv_xname); 394 chp->atapibus = NULL; 395 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 396 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 397 #endif 398 } 399 400 for (i = 0; i < 2; i++) { 401 struct ata_device adev; 402 if ((chp->ch_drive[i].drive_flags & 403 (DRIVE_ATA | DRIVE_OLD)) == 0) { 404 continue; 405 } 406 memset(&adev, 0, sizeof(struct ata_device)); 407 adev.adev_bustype = &wdc_ata_bustype; 408 adev.adev_channel = chp->channel; 409 adev.adev_openings = 1; 410 adev.adev_drv_data = &chp->ch_drive[i]; 411 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 412 &adev, ataprint); 413 if (chp->ata_drives[i] != NULL) 414 wdc_probe_caps(&chp->ch_drive[i]); 415 else 416 chp->ch_drive[i].drive_flags &= 417 ~(DRIVE_ATA | DRIVE_OLD); 418 } 419 420 /* now that we know the drives, the controller can set its modes */ 421 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 422 chp->wdc->set_modes(chp); 423 wdc_print_modes(chp); 424 } 425 #if NATARAID > 0 426 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 427 for (i = 0; i < 2; i++) 428 if (chp->ata_drives[i] != NULL) 429 ata_raid_check_component(chp->ata_drives[i]); 430 #endif /* NATARAID > 0 */ 431 432 /* 433 * reset drive_flags for unattached devices, reset state for attached 434 * ones 435 */ 436 for (i = 0; i < 2; i++) { 437 if (chp->ch_drive[i].drv_softc == NULL) 438 chp->ch_drive[i].drive_flags = 0; 439 else 440 chp->ch_drive[i].state = 0; 441 } 442 443 out: 444 if (atabus_initq == NULL) { 445 simple_lock(&atabus_interlock); 446 while(1) { 447 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 448 if (atabus_initq->atabus_sc == atabus_sc) 449 break; 450 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 451 &atabus_interlock); 452 } 453 simple_unlock(&atabus_interlock); 454 } 455 simple_lock(&atabus_interlock); 456 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 457 simple_unlock(&atabus_interlock); 458 459 free(atabus_initq, M_DEVBUF); 460 wakeup(&atabus_initq_head); 461 462 config_pending_decr(); 463 if (need_delref) 464 wdc_delref(chp); 465 } 466 467 int 468 wdcprobe(struct channel_softc *chp) 469 { 470 471 return (wdcprobe1(chp, 1)); 472 } 473 474 int 475 wdcprobe1(struct channel_softc *chp, int poll) 476 { 477 u_int8_t st0, st1, sc, sn, cl, ch; 478 u_int8_t ret_value = 0x03; 479 u_int8_t drive; 480 int s; 481 482 /* 483 * Sanity check to see if the wdc channel responds at all. 484 */ 485 486 if (chp->wdc == NULL || 487 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 488 489 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 490 chp->wdc->select(chp,0); 491 492 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 493 WDSD_IBM); 494 delay(10); /* 400ns delay */ 495 st0 = bus_space_read_1(chp->cmd_iot, 496 chp->cmd_iohs[wd_status], 0); 497 498 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 499 chp->wdc->select(chp,1); 500 501 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 502 WDSD_IBM | 0x10); 503 delay(10); /* 400ns delay */ 504 st1 = bus_space_read_1(chp->cmd_iot, 505 chp->cmd_iohs[wd_status], 0); 506 507 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 508 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 509 chp->channel, st0, st1), DEBUG_PROBE); 510 511 if (st0 == 0xff || st0 == WDSD_IBM) 512 ret_value &= ~0x01; 513 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 514 ret_value &= ~0x02; 515 /* Register writability test, drive 0. */ 516 if (ret_value & 0x01) { 517 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 518 chp->wdc->select(chp,0); 519 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 520 0, WDSD_IBM); 521 bus_space_write_1(chp->cmd_iot, 522 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 523 if (bus_space_read_1(chp->cmd_iot, 524 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 525 ret_value &= ~0x01; 526 bus_space_write_1(chp->cmd_iot, 527 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 528 if (bus_space_read_1(chp->cmd_iot, 529 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 530 ret_value &= ~0x01; 531 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 532 0, 0x01); 533 if (bus_space_read_1(chp->cmd_iot, 534 chp->cmd_iohs[wd_sector], 0) != 0x01) 535 ret_value &= ~0x01; 536 bus_space_write_1(chp->cmd_iot, 537 chp->cmd_iohs[wd_sector], 0, 0x02); 538 if (bus_space_read_1(chp->cmd_iot, 539 chp->cmd_iohs[wd_sector], 0) != 0x02) 540 ret_value &= ~0x01; 541 if (bus_space_read_1(chp->cmd_iot, 542 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 543 ret_value &= ~0x01; 544 } 545 /* Register writability test, drive 1. */ 546 if (ret_value & 0x02) { 547 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 548 chp->wdc->select(chp,1); 549 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 550 0, WDSD_IBM | 0x10); 551 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 552 0, 0x02); 553 if (bus_space_read_1(chp->cmd_iot, 554 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 555 ret_value &= ~0x02; 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 558 if (bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 560 ret_value &= ~0x02; 561 bus_space_write_1(chp->cmd_iot, 562 chp->cmd_iohs[wd_sector], 0, 0x01); 563 if (bus_space_read_1(chp->cmd_iot, 564 chp->cmd_iohs[wd_sector], 0) != 0x01) 565 ret_value &= ~0x02; 566 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 567 0, 0x02); 568 if (bus_space_read_1(chp->cmd_iot, 569 chp->cmd_iohs[wd_sector], 0) != 0x02) 570 ret_value &= ~0x02; 571 if (bus_space_read_1(chp->cmd_iot, 572 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 573 ret_value &= ~0x02; 574 } 575 576 if (ret_value == 0) 577 return 0; 578 } 579 580 s = splbio(); 581 582 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 583 chp->wdc->select(chp,0); 584 /* assert SRST, wait for reset to complete */ 585 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 586 delay(10); /* 400ns delay */ 587 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 588 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 589 DELAY(2000); 590 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 591 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 592 delay(10); /* 400ns delay */ 593 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 594 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_IRQACK)) 595 chp->wdc->irqack(chp); 596 splx(s); 597 598 ret_value = __wdcwait_reset(chp, ret_value, poll); 599 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 600 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 601 ret_value), DEBUG_PROBE); 602 603 /* if reset failed, there's nothing here */ 604 if (ret_value == 0) 605 return 0; 606 607 /* 608 * Test presence of drives. First test register signatures looking for 609 * ATAPI devices. If it's not an ATAPI and reset said there may be 610 * something here assume it's ATA or OLD. Ghost will be killed later in 611 * attach routine. 612 */ 613 for (drive = 0; drive < 2; drive++) { 614 if ((ret_value & (0x01 << drive)) == 0) 615 continue; 616 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 617 chp->wdc->select(chp,drive); 618 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 619 WDSD_IBM | (drive << 4)); 620 delay(10); /* 400ns delay */ 621 /* Save registers contents */ 622 sc = bus_space_read_1(chp->cmd_iot, 623 chp->cmd_iohs[wd_seccnt], 0); 624 sn = bus_space_read_1(chp->cmd_iot, 625 chp->cmd_iohs[wd_sector], 0); 626 cl = bus_space_read_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_cyl_lo], 0); 628 ch = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_cyl_hi], 0); 630 631 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 632 "cl=0x%x ch=0x%x\n", 633 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 634 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 635 /* 636 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 637 * we get wrong values here, so ignore it. 638 */ 639 if (cl == 0x14 && ch == 0xeb) { 640 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 641 } else { 642 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 643 if (chp->wdc == NULL || 644 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 645 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 646 } 647 } 648 return (ret_value); 649 } 650 651 void 652 wdcattach(struct channel_softc *chp) 653 { 654 static int inited = 0; 655 656 if (chp->ch_flags & WDCF_DISABLED) 657 return; 658 659 /* initialise global data */ 660 callout_init(&chp->ch_callout); 661 if (chp->wdc->drv_probe == NULL) 662 chp->wdc->drv_probe = wdc_drvprobe; 663 if (inited == 0) { 664 /* Initialize the ata_xfer pool. */ 665 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 666 0, 0, "wdcspl", NULL); 667 inited++; 668 } 669 TAILQ_INIT(&chp->ch_queue->queue_xfer); 670 chp->ch_queue->queue_freeze = 0; 671 672 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 673 } 674 675 int 676 wdcactivate(struct device *self, enum devact act) 677 { 678 struct wdc_softc *wdc = (struct wdc_softc *)self; 679 int s, i, error = 0; 680 681 s = splbio(); 682 switch (act) { 683 case DVACT_ACTIVATE: 684 error = EOPNOTSUPP; 685 break; 686 687 case DVACT_DEACTIVATE: 688 for (i = 0; i < wdc->nchannels; i++) { 689 error = config_deactivate(wdc->channels[i]->atabus); 690 if (error) 691 break; 692 } 693 break; 694 } 695 splx(s); 696 return (error); 697 } 698 699 int 700 wdcdetach(struct device *self, int flags) 701 { 702 struct wdc_softc *wdc = (struct wdc_softc *)self; 703 struct channel_softc *chp; 704 int i, error = 0; 705 706 for (i = 0; i < wdc->nchannels; i++) { 707 chp = wdc->channels[i]; 708 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 709 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 710 error = config_detach(chp->atabus, flags); 711 if (error) 712 break; 713 } 714 return (error); 715 } 716 717 /* 718 * Start I/O on a controller, for the given channel. 719 * The first xfer may be not for our channel if the channel queues 720 * are shared. 721 */ 722 void 723 wdcstart(struct channel_softc *chp) 724 { 725 struct ata_xfer *xfer; 726 727 #ifdef WDC_DIAGNOSTIC 728 int spl1, spl2; 729 730 spl1 = splbio(); 731 spl2 = splbio(); 732 if (spl2 != spl1) { 733 printf("wdcstart: not at splbio()\n"); 734 panic("wdcstart"); 735 } 736 splx(spl2); 737 splx(spl1); 738 #endif /* WDC_DIAGNOSTIC */ 739 740 /* is there a xfer ? */ 741 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 742 return; 743 744 /* adjust chp, in case we have a shared queue */ 745 chp = xfer->c_chp; 746 747 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 748 return; /* channel aleady active */ 749 } 750 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 751 return; /* queue froozen */ 752 } 753 #ifdef DIAGNOSTIC 754 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 755 panic("wdcstart: channel waiting for irq"); 756 #endif 757 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 758 if (!(*chp->wdc->claim_hw)(chp, 0)) 759 return; 760 761 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 762 chp->channel, xfer->c_drive), DEBUG_XFERS); 763 chp->ch_flags |= WDCF_ACTIVE; 764 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 765 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 766 chp->ch_drive[xfer->c_drive].state = 0; 767 } 768 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 769 KASSERT(xfer->c_flags & C_POLL); 770 xfer->c_start(chp, xfer); 771 } 772 773 /* restart an interrupted I/O */ 774 void 775 wdcrestart(void *v) 776 { 777 struct channel_softc *chp = v; 778 int s; 779 780 s = splbio(); 781 wdcstart(chp); 782 splx(s); 783 } 784 785 786 /* 787 * Interrupt routine for the controller. Acknowledge the interrupt, check for 788 * errors on the current operation, mark it done if necessary, and start the 789 * next request. Also check for a partially done transfer, and continue with 790 * the next chunk if so. 791 */ 792 int 793 wdcintr(void *arg) 794 { 795 struct channel_softc *chp = arg; 796 struct ata_xfer *xfer; 797 int ret; 798 799 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 800 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 801 DEBUG_INTR); 802 return (0); 803 } 804 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 805 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 806 /* try to clear the pending interrupt anyway */ 807 (void)bus_space_read_1(chp->cmd_iot, 808 chp->cmd_iohs[wd_status], 0); 809 return (0); 810 } 811 812 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 813 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 814 if (chp->ch_flags & WDCF_DMA_WAIT) { 815 chp->wdc->dma_status = 816 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 817 xfer->c_drive, 0); 818 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 819 /* IRQ not for us, not detected by DMA engine */ 820 return 0; 821 } 822 chp->ch_flags &= ~WDCF_DMA_WAIT; 823 } 824 chp->ch_flags &= ~WDCF_IRQ_WAIT; 825 ret = xfer->c_intr(chp, xfer, 1); 826 if (ret == 0) /* irq was not for us, still waiting for irq */ 827 chp->ch_flags |= WDCF_IRQ_WAIT; 828 return (ret); 829 } 830 831 /* Put all disk in RESET state */ 832 void 833 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 834 { 835 struct channel_softc *chp = drvp->chnl_softc; 836 int drive; 837 838 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 839 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 840 DEBUG_FUNCS); 841 if ((flags & AT_POLL) == 0) { 842 if (chp->ch_flags & WDCF_TH_RESET) { 843 /* no need to schedule a reset more than one time */ 844 return; 845 } 846 chp->ch_flags |= WDCF_TH_RESET; 847 chp->ch_queue->queue_freeze++; 848 wakeup(&chp->thread); 849 return; 850 } 851 (void) wdcreset(chp, RESET_POLL); 852 for (drive = 0; drive < 2; drive++) { 853 chp->ch_drive[drive].state = 0; 854 } 855 } 856 857 int 858 wdcreset(struct channel_softc *chp, int poll) 859 { 860 int drv_mask1, drv_mask2; 861 int s = 0; 862 863 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 864 chp->wdc->select(chp,0); 865 if (poll != RESET_SLEEP) 866 s = splbio(); 867 /* master */ 868 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 869 delay(10); /* 400ns delay */ 870 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 871 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 872 delay(2000); 873 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 874 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 875 WDCTL_4BIT | WDCTL_IDS); 876 delay(10); /* 400ns delay */ 877 if (poll != RESET_SLEEP) { 878 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 879 chp->wdc->irqack(chp); 880 splx(s); 881 } 882 883 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 884 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 885 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 886 (poll == RESET_SLEEP) ? 0 : 1); 887 if (drv_mask2 != drv_mask1) { 888 printf("%s channel %d: reset failed for", 889 chp->wdc->sc_dev.dv_xname, chp->channel); 890 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 891 printf(" drive 0"); 892 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 893 printf(" drive 1"); 894 printf("\n"); 895 } 896 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 897 return (drv_mask1 != drv_mask2) ? 1 : 0; 898 } 899 900 static int 901 __wdcwait_reset(struct channel_softc *chp, int drv_mask, int poll) 902 { 903 int timeout, nloop; 904 u_int8_t st0 = 0, st1 = 0; 905 #ifdef WDCDEBUG 906 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 907 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 908 #endif 909 910 if (poll) 911 nloop = WDCNDELAY_RST; 912 else 913 nloop = WDC_RESET_WAIT * hz / 1000; 914 /* wait for BSY to deassert */ 915 for (timeout = 0; timeout < nloop; timeout++) { 916 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 917 chp->wdc->select(chp,0); 918 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 919 WDSD_IBM); /* master */ 920 delay(10); 921 st0 = bus_space_read_1(chp->cmd_iot, 922 chp->cmd_iohs[wd_status], 0); 923 #ifdef WDCDEBUG 924 sc0 = bus_space_read_1(chp->cmd_iot, 925 chp->cmd_iohs[wd_seccnt], 0); 926 sn0 = bus_space_read_1(chp->cmd_iot, 927 chp->cmd_iohs[wd_sector], 0); 928 cl0 = bus_space_read_1(chp->cmd_iot, 929 chp->cmd_iohs[wd_cyl_lo], 0); 930 ch0 = bus_space_read_1(chp->cmd_iot, 931 chp->cmd_iohs[wd_cyl_hi], 0); 932 #endif 933 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 934 chp->wdc->select(chp,1); 935 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 936 WDSD_IBM | 0x10); /* slave */ 937 delay(10); 938 st1 = bus_space_read_1(chp->cmd_iot, 939 chp->cmd_iohs[wd_status], 0); 940 #ifdef WDCDEBUG 941 sc1 = bus_space_read_1(chp->cmd_iot, 942 chp->cmd_iohs[wd_seccnt], 0); 943 sn1 = bus_space_read_1(chp->cmd_iot, 944 chp->cmd_iohs[wd_sector], 0); 945 cl1 = bus_space_read_1(chp->cmd_iot, 946 chp->cmd_iohs[wd_cyl_lo], 0); 947 ch1 = bus_space_read_1(chp->cmd_iot, 948 chp->cmd_iohs[wd_cyl_hi], 0); 949 #endif 950 951 if ((drv_mask & 0x01) == 0) { 952 /* no master */ 953 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 954 /* No master, slave is ready, it's done */ 955 goto end; 956 } 957 } else if ((drv_mask & 0x02) == 0) { 958 /* no slave */ 959 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 960 /* No slave, master is ready, it's done */ 961 goto end; 962 } 963 } else { 964 /* Wait for both master and slave to be ready */ 965 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 966 goto end; 967 } 968 } 969 if (poll) 970 delay(WDCDELAY); 971 else 972 tsleep(&nloop, PRIBIO, "atarst", 1); 973 } 974 /* Reset timed out. Maybe it's because drv_mask was not right */ 975 if (st0 & WDCS_BSY) 976 drv_mask &= ~0x01; 977 if (st1 & WDCS_BSY) 978 drv_mask &= ~0x02; 979 end: 980 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 981 "cl=0x%x ch=0x%x\n", 982 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 983 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 984 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 985 "cl=0x%x ch=0x%x\n", 986 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 987 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 988 989 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 990 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 991 st0, st1), DEBUG_PROBE); 992 993 return drv_mask; 994 } 995 996 /* 997 * Wait for a drive to be !BSY, and have mask in its status register. 998 * return -1 for a timeout after "timeout" ms. 999 */ 1000 int 1001 __wdcwait(struct channel_softc *chp, int mask, int bits, int timeout) 1002 { 1003 u_char status; 1004 int time = 0; 1005 1006 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1007 :"none", chp->channel), DEBUG_STATUS); 1008 chp->ch_error = 0; 1009 1010 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1011 1012 for (;;) { 1013 chp->ch_status = status = 1014 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1015 if ((status & (WDCS_BSY | mask)) == bits) 1016 break; 1017 if (++time > timeout) { 1018 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1019 "status %x error %x (mask 0x%x bits 0x%x)\n", 1020 time, status, 1021 bus_space_read_1(chp->cmd_iot, 1022 chp->cmd_iohs[wd_error], 0), mask, bits), 1023 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1024 return(WDCWAIT_TOUT); 1025 } 1026 delay(WDCDELAY); 1027 } 1028 #ifdef WDCDEBUG 1029 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1030 printf("__wdcwait: did busy-wait, time=%d\n", time); 1031 #endif 1032 if (status & WDCS_ERR) 1033 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1034 chp->cmd_iohs[wd_error], 0); 1035 #ifdef WDCNDELAY_DEBUG 1036 /* After autoconfig, there should be no long delays. */ 1037 if (!cold && time > WDCNDELAY_DEBUG) { 1038 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1039 if (xfer == NULL) 1040 printf("%s channel %d: warning: busy-wait took %dus\n", 1041 chp->wdc->sc_dev.dv_xname, chp->channel, 1042 WDCDELAY * time); 1043 else 1044 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1045 chp->wdc->sc_dev.dv_xname, chp->channel, 1046 xfer->drive, 1047 WDCDELAY * time); 1048 } 1049 #endif 1050 return(WDCWAIT_OK); 1051 } 1052 1053 /* 1054 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1055 * thread if possible 1056 */ 1057 int 1058 wdcwait(struct channel_softc *chp, int mask, int bits, int timeout, int flags) 1059 { 1060 int error, i, timeout_hz = mstohz(timeout); 1061 1062 if (timeout_hz == 0 || 1063 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1064 error = __wdcwait(chp, mask, bits, timeout); 1065 else { 1066 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1067 if (error != 0) { 1068 if ((chp->ch_flags & WDCF_TH_RUN) || 1069 (flags & AT_WAIT)) { 1070 /* 1071 * we're running in the channel thread 1072 * or some userland thread context 1073 */ 1074 for (i = 0; i < timeout_hz; i++) { 1075 if (__wdcwait(chp, mask, bits, 1076 WDCDELAY_POLL) == 0) { 1077 error = 0; 1078 break; 1079 } 1080 tsleep(&chp, PRIBIO, "atapoll", 1); 1081 } 1082 } else { 1083 /* 1084 * we're probably in interrupt context, 1085 * ask the thread to come back here 1086 */ 1087 #ifdef DIAGNOSTIC 1088 if (chp->ch_queue->queue_freeze > 0) 1089 panic("wdcwait: queue_freeze"); 1090 #endif 1091 chp->ch_queue->queue_freeze++; 1092 wakeup(&chp->thread); 1093 return(WDCWAIT_THR); 1094 } 1095 } 1096 } 1097 return (error); 1098 } 1099 1100 1101 /* 1102 * Busy-wait for DMA to complete 1103 */ 1104 int 1105 wdc_dmawait(struct channel_softc *chp, struct ata_xfer *xfer, int timeout) 1106 { 1107 int time; 1108 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1109 chp->wdc->dma_status = 1110 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1111 chp->channel, xfer->c_drive, 0); 1112 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1113 return 0; 1114 delay(WDCDELAY); 1115 } 1116 /* timeout, force a DMA halt */ 1117 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1118 chp->channel, xfer->c_drive, 1); 1119 return 1; 1120 } 1121 1122 void 1123 wdctimeout(void *arg) 1124 { 1125 struct channel_softc *chp = (struct channel_softc *)arg; 1126 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1127 int s; 1128 1129 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1130 1131 s = splbio(); 1132 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1133 __wdcerror(chp, "lost interrupt"); 1134 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1135 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1136 xfer->c_bcount, 1137 xfer->c_skip); 1138 if (chp->ch_flags & WDCF_DMA_WAIT) { 1139 chp->wdc->dma_status = 1140 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1141 chp->channel, xfer->c_drive, 1); 1142 chp->ch_flags &= ~WDCF_DMA_WAIT; 1143 } 1144 /* 1145 * Call the interrupt routine. If we just missed an interrupt, 1146 * it will do what's needed. Else, it will take the needed 1147 * action (reset the device). 1148 * Before that we need to reinstall the timeout callback, 1149 * in case it will miss another irq while in this transfer 1150 * We arbitray chose it to be 1s 1151 */ 1152 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1153 xfer->c_flags |= C_TIMEOU; 1154 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1155 xfer->c_intr(chp, xfer, 1); 1156 } else 1157 __wdcerror(chp, "missing untimeout"); 1158 splx(s); 1159 } 1160 1161 /* 1162 * Probe drive's capabilities, for use by the controller later 1163 * Assumes drvp points to an existing drive. 1164 * XXX this should be a controller-indep function 1165 */ 1166 void 1167 wdc_probe_caps(struct ata_drive_datas *drvp) 1168 { 1169 struct ataparams params, params2; 1170 struct channel_softc *chp = drvp->chnl_softc; 1171 struct device *drv_dev = drvp->drv_softc; 1172 struct wdc_softc *wdc = chp->wdc; 1173 int i, printed; 1174 char *sep = ""; 1175 int cf_flags; 1176 1177 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1178 /* IDENTIFY failed. Can't tell more about the device */ 1179 return; 1180 } 1181 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1182 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1183 /* 1184 * Controller claims 16 and 32 bit transfers. 1185 * Re-do an IDENTIFY with 32-bit transfers, 1186 * and compare results. 1187 */ 1188 drvp->drive_flags |= DRIVE_CAP32; 1189 ata_get_params(drvp, AT_WAIT, ¶ms2); 1190 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1191 /* Not good. fall back to 16bits */ 1192 drvp->drive_flags &= ~DRIVE_CAP32; 1193 } else { 1194 aprint_normal("%s: 32-bit data port\n", 1195 drv_dev->dv_xname); 1196 } 1197 } 1198 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1199 if (params.atap_ata_major > 0x01 && 1200 params.atap_ata_major != 0xffff) { 1201 for (i = 14; i > 0; i--) { 1202 if (params.atap_ata_major & (1 << i)) { 1203 aprint_normal("%s: ATA version %d\n", 1204 drv_dev->dv_xname, i); 1205 drvp->ata_vers = i; 1206 break; 1207 } 1208 } 1209 } 1210 #endif 1211 1212 /* An ATAPI device is at last PIO mode 3 */ 1213 if (drvp->drive_flags & DRIVE_ATAPI) 1214 drvp->PIO_mode = 3; 1215 1216 /* 1217 * It's not in the specs, but it seems that some drive 1218 * returns 0xffff in atap_extensions when this field is invalid 1219 */ 1220 if (params.atap_extensions != 0xffff && 1221 (params.atap_extensions & WDC_EXT_MODES)) { 1222 printed = 0; 1223 /* 1224 * XXX some drives report something wrong here (they claim to 1225 * support PIO mode 8 !). As mode is coded on 3 bits in 1226 * SET FEATURE, limit it to 7 (so limit i to 4). 1227 * If higher mode than 7 is found, abort. 1228 */ 1229 for (i = 7; i >= 0; i--) { 1230 if ((params.atap_piomode_supp & (1 << i)) == 0) 1231 continue; 1232 if (i > 4) 1233 return; 1234 /* 1235 * See if mode is accepted. 1236 * If the controller can't set its PIO mode, 1237 * assume the defaults are good, so don't try 1238 * to set it 1239 */ 1240 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1241 /* 1242 * It's OK to pool here, it's fast enouth 1243 * to not bother waiting for interrupt 1244 */ 1245 if (ata_set_mode(drvp, 0x08 | (i + 3), 1246 AT_WAIT) != CMD_OK) 1247 continue; 1248 if (!printed) { 1249 aprint_normal("%s: drive supports PIO mode %d", 1250 drv_dev->dv_xname, i + 3); 1251 sep = ","; 1252 printed = 1; 1253 } 1254 /* 1255 * If controller's driver can't set its PIO mode, 1256 * get the highter one for the drive. 1257 */ 1258 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1259 wdc->PIO_cap >= i + 3) { 1260 drvp->PIO_mode = i + 3; 1261 drvp->PIO_cap = i + 3; 1262 break; 1263 } 1264 } 1265 if (!printed) { 1266 /* 1267 * We didn't find a valid PIO mode. 1268 * Assume the values returned for DMA are buggy too 1269 */ 1270 return; 1271 } 1272 drvp->drive_flags |= DRIVE_MODE; 1273 printed = 0; 1274 for (i = 7; i >= 0; i--) { 1275 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1276 continue; 1277 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1278 (wdc->cap & WDC_CAPABILITY_MODE)) 1279 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1280 != CMD_OK) 1281 continue; 1282 if (!printed) { 1283 aprint_normal("%s DMA mode %d", sep, i); 1284 sep = ","; 1285 printed = 1; 1286 } 1287 if (wdc->cap & WDC_CAPABILITY_DMA) { 1288 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1289 wdc->DMA_cap < i) 1290 continue; 1291 drvp->DMA_mode = i; 1292 drvp->DMA_cap = i; 1293 drvp->drive_flags |= DRIVE_DMA; 1294 } 1295 break; 1296 } 1297 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1298 printed = 0; 1299 for (i = 7; i >= 0; i--) { 1300 if ((params.atap_udmamode_supp & (1 << i)) 1301 == 0) 1302 continue; 1303 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1304 (wdc->cap & WDC_CAPABILITY_UDMA)) 1305 if (ata_set_mode(drvp, 0x40 | i, 1306 AT_WAIT) != CMD_OK) 1307 continue; 1308 if (!printed) { 1309 aprint_normal("%s Ultra-DMA mode %d", 1310 sep, i); 1311 if (i == 2) 1312 aprint_normal(" (Ultra/33)"); 1313 else if (i == 4) 1314 aprint_normal(" (Ultra/66)"); 1315 else if (i == 5) 1316 aprint_normal(" (Ultra/100)"); 1317 else if (i == 6) 1318 aprint_normal(" (Ultra/133)"); 1319 sep = ","; 1320 printed = 1; 1321 } 1322 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1323 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1324 wdc->UDMA_cap < i) 1325 continue; 1326 drvp->UDMA_mode = i; 1327 drvp->UDMA_cap = i; 1328 drvp->drive_flags |= DRIVE_UDMA; 1329 } 1330 break; 1331 } 1332 } 1333 aprint_normal("\n"); 1334 } 1335 1336 /* Try to guess ATA version here, if it didn't get reported */ 1337 if (drvp->ata_vers == 0) { 1338 if (drvp->drive_flags & DRIVE_UDMA) 1339 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1340 else if (drvp->PIO_cap > 2) 1341 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1342 } 1343 cf_flags = drv_dev->dv_cfdata->cf_flags; 1344 if (cf_flags & ATA_CONFIG_PIO_SET) { 1345 drvp->PIO_mode = 1346 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1347 drvp->drive_flags |= DRIVE_MODE; 1348 } 1349 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1350 /* don't care about DMA modes */ 1351 return; 1352 } 1353 if (cf_flags & ATA_CONFIG_DMA_SET) { 1354 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1355 ATA_CONFIG_DMA_DISABLE) { 1356 drvp->drive_flags &= ~DRIVE_DMA; 1357 } else { 1358 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1359 ATA_CONFIG_DMA_OFF; 1360 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1361 } 1362 } 1363 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1364 /* don't care about UDMA modes */ 1365 return; 1366 } 1367 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1368 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1369 ATA_CONFIG_UDMA_DISABLE) { 1370 drvp->drive_flags &= ~DRIVE_UDMA; 1371 } else { 1372 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1373 ATA_CONFIG_UDMA_OFF; 1374 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1375 } 1376 } 1377 } 1378 1379 /* 1380 * downgrade the transfer mode of a drive after an error. return 1 if 1381 * downgrade was possible, 0 otherwise. 1382 */ 1383 int 1384 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1385 { 1386 struct channel_softc *chp = drvp->chnl_softc; 1387 struct device *drv_dev = drvp->drv_softc; 1388 struct wdc_softc *wdc = chp->wdc; 1389 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1390 1391 /* if drive or controller don't know its mode, we can't do much */ 1392 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1393 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1394 return 0; 1395 /* current drive mode was set by a config flag, let it this way */ 1396 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1397 (cf_flags & ATA_CONFIG_DMA_SET) || 1398 (cf_flags & ATA_CONFIG_UDMA_SET)) 1399 return 0; 1400 1401 /* 1402 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1403 * Maybe we didn't properly notice the cable type 1404 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1405 * It helps in some cases. 1406 */ 1407 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1408 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1409 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1410 drv_dev->dv_xname, drvp->UDMA_mode); 1411 } 1412 1413 /* 1414 * If we were using ultra-DMA, don't downgrade to multiword DMA 1415 * if we noticed a CRC error. It has been noticed that CRC errors 1416 * in ultra-DMA lead to silent data corruption in multiword DMA. 1417 * Data corruption is less likely to occur in PIO mode. 1418 */ 1419 else if ((drvp->drive_flags & DRIVE_UDMA) && 1420 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1421 drvp->drive_flags &= ~DRIVE_UDMA; 1422 drvp->drive_flags |= DRIVE_DMA; 1423 drvp->DMA_mode = drvp->DMA_cap; 1424 printf("%s: transfer error, downgrading to DMA mode %d\n", 1425 drv_dev->dv_xname, drvp->DMA_mode); 1426 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1427 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1428 drvp->PIO_mode = drvp->PIO_cap; 1429 printf("%s: transfer error, downgrading to PIO mode %d\n", 1430 drv_dev->dv_xname, drvp->PIO_mode); 1431 } else /* already using PIO, can't downgrade */ 1432 return 0; 1433 1434 wdc->set_modes(chp); 1435 wdc_print_modes(chp); 1436 /* reset the channel, which will shedule all drives for setup */ 1437 wdc_reset_channel(drvp, flags); 1438 return 1; 1439 } 1440 1441 int 1442 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1443 { 1444 struct channel_softc *chp = drvp->chnl_softc; 1445 struct ata_xfer *xfer; 1446 int s, ret; 1447 1448 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1449 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1450 DEBUG_FUNCS); 1451 1452 /* set up an xfer and queue. Wait for completion */ 1453 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1454 WDC_NOSLEEP); 1455 if (xfer == NULL) { 1456 return WDC_TRY_AGAIN; 1457 } 1458 1459 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1460 wdc_c->flags |= AT_POLL; 1461 if (wdc_c->flags & AT_POLL) 1462 xfer->c_flags |= C_POLL; 1463 xfer->c_drive = drvp->drive; 1464 xfer->c_databuf = wdc_c->data; 1465 xfer->c_bcount = wdc_c->bcount; 1466 xfer->c_cmd = wdc_c; 1467 xfer->c_start = __wdccommand_start; 1468 xfer->c_intr = __wdccommand_intr; 1469 xfer->c_kill_xfer = __wdccommand_done; 1470 1471 s = splbio(); 1472 wdc_exec_xfer(chp, xfer); 1473 #ifdef DIAGNOSTIC 1474 if ((wdc_c->flags & AT_POLL) != 0 && 1475 (wdc_c->flags & AT_DONE) == 0) 1476 panic("wdc_exec_command: polled command not done"); 1477 #endif 1478 if (wdc_c->flags & AT_DONE) { 1479 ret = WDC_COMPLETE; 1480 } else { 1481 if (wdc_c->flags & AT_WAIT) { 1482 while ((wdc_c->flags & AT_DONE) == 0) { 1483 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1484 } 1485 ret = WDC_COMPLETE; 1486 } else { 1487 ret = WDC_QUEUED; 1488 } 1489 } 1490 splx(s); 1491 return ret; 1492 } 1493 1494 void 1495 __wdccommand_start(struct channel_softc *chp, struct ata_xfer *xfer) 1496 { 1497 int drive = xfer->c_drive; 1498 struct wdc_command *wdc_c = xfer->c_cmd; 1499 1500 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1501 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1502 DEBUG_FUNCS); 1503 1504 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1505 chp->wdc->select(chp,drive); 1506 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1507 WDSD_IBM | (drive << 4)); 1508 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1509 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1510 case WDCWAIT_OK: 1511 break; 1512 case WDCWAIT_TOUT: 1513 wdc_c->flags |= AT_TIMEOU; 1514 __wdccommand_done(chp, xfer); 1515 return; 1516 case WDCWAIT_THR: 1517 return; 1518 } 1519 if (wdc_c->flags & AT_POLL) { 1520 /* polled command, disable interrupts */ 1521 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1522 WDCTL_4BIT | WDCTL_IDS); 1523 } 1524 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1525 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1526 1527 if ((wdc_c->flags & AT_POLL) == 0) { 1528 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1529 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1530 wdctimeout, chp); 1531 return; 1532 } 1533 /* 1534 * Polled command. Wait for drive ready or drq. Done in intr(). 1535 * Wait for at last 400ns for status bit to be valid. 1536 */ 1537 delay(10); /* 400ns delay */ 1538 __wdccommand_intr(chp, xfer, 0); 1539 } 1540 1541 int 1542 __wdccommand_intr(struct channel_softc *chp, struct ata_xfer *xfer, int irq) 1543 { 1544 struct wdc_command *wdc_c = xfer->c_cmd; 1545 int bcount = wdc_c->bcount; 1546 char *data = wdc_c->data; 1547 int wflags; 1548 1549 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1550 /* both wait and poll, we can tsleep here */ 1551 wflags = AT_WAIT | AT_POLL; 1552 } else { 1553 wflags = AT_POLL; 1554 } 1555 1556 again: 1557 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1558 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1559 DEBUG_INTR); 1560 /* 1561 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1562 * Reselect again, it doesn't hurt for others commands, and the time 1563 * penalty for the extra regiter write is acceptable, 1564 * wdc_exec_command() isn't called often (mosly for autoconfig) 1565 */ 1566 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1567 WDSD_IBM | (xfer->c_drive << 4)); 1568 if ((wdc_c->flags & AT_XFDONE) != 0) { 1569 /* 1570 * We have completed a data xfer. The drive should now be 1571 * in its initial state 1572 */ 1573 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1574 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1575 wflags) == WDCWAIT_TOUT) { 1576 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1577 return 0; /* IRQ was not for us */ 1578 wdc_c->flags |= AT_TIMEOU; 1579 } 1580 goto out; 1581 } 1582 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1583 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1584 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1585 return 0; /* IRQ was not for us */ 1586 wdc_c->flags |= AT_TIMEOU; 1587 goto out; 1588 } 1589 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1590 chp->wdc->irqack(chp); 1591 if (wdc_c->flags & AT_READ) { 1592 if ((chp->ch_status & WDCS_DRQ) == 0) { 1593 wdc_c->flags |= AT_TIMEOU; 1594 goto out; 1595 } 1596 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1597 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1598 0, (u_int32_t*)data, bcount >> 2); 1599 data += bcount & 0xfffffffc; 1600 bcount = bcount & 0x03; 1601 } 1602 if (bcount > 0) 1603 bus_space_read_multi_2(chp->cmd_iot, 1604 chp->cmd_iohs[wd_data], 0, 1605 (u_int16_t *)data, bcount >> 1); 1606 /* at this point the drive should be in its initial state */ 1607 wdc_c->flags |= AT_XFDONE; 1608 /* XXX should read status register here ? */ 1609 } else if (wdc_c->flags & AT_WRITE) { 1610 if ((chp->ch_status & WDCS_DRQ) == 0) { 1611 wdc_c->flags |= AT_TIMEOU; 1612 goto out; 1613 } 1614 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1615 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1616 0, (u_int32_t*)data, bcount >> 2); 1617 data += bcount & 0xfffffffc; 1618 bcount = bcount & 0x03; 1619 } 1620 if (bcount > 0) 1621 bus_space_write_multi_2(chp->cmd_iot, 1622 chp->cmd_iohs[wd_data], 0, 1623 (u_int16_t *)data, bcount >> 1); 1624 wdc_c->flags |= AT_XFDONE; 1625 if ((wdc_c->flags & AT_POLL) == 0) { 1626 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1627 callout_reset(&chp->ch_callout, 1628 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1629 return 1; 1630 } else { 1631 goto again; 1632 } 1633 } 1634 out: 1635 __wdccommand_done(chp, xfer); 1636 return 1; 1637 } 1638 1639 void 1640 __wdccommand_done(struct channel_softc *chp, struct ata_xfer *xfer) 1641 { 1642 struct wdc_command *wdc_c = xfer->c_cmd; 1643 1644 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1645 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1646 DEBUG_FUNCS); 1647 1648 callout_stop(&chp->ch_callout); 1649 1650 if (chp->ch_status & WDCS_DWF) 1651 wdc_c->flags |= AT_DF; 1652 if (chp->ch_status & WDCS_ERR) { 1653 wdc_c->flags |= AT_ERROR; 1654 wdc_c->r_error = chp->ch_error; 1655 } 1656 wdc_c->flags |= AT_DONE; 1657 if ((wdc_c->flags & AT_READREG) != 0 && 1658 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1659 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1660 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1661 chp->cmd_iohs[wd_sdh], 0); 1662 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1663 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1664 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1665 chp->cmd_iohs[wd_cyl_lo], 0); 1666 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1667 chp->cmd_iohs[wd_sector], 0); 1668 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1669 chp->cmd_iohs[wd_seccnt], 0); 1670 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1671 chp->cmd_iohs[wd_error], 0); 1672 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1673 chp->cmd_iohs[wd_precomp], 0); 1674 } 1675 1676 if (wdc_c->flags & AT_POLL) { 1677 /* enable interrupts */ 1678 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1679 WDCTL_4BIT); 1680 } 1681 wdc_free_xfer(chp, xfer); 1682 if (wdc_c->flags & AT_WAIT) 1683 wakeup(wdc_c); 1684 else if (wdc_c->callback) 1685 wdc_c->callback(wdc_c->callback_arg); 1686 wdcstart(chp); 1687 return; 1688 } 1689 1690 /* 1691 * Send a command. The drive should be ready. 1692 * Assumes interrupts are blocked. 1693 */ 1694 void 1695 wdccommand(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1696 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1697 u_int8_t precomp) 1698 { 1699 1700 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1701 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1702 chp->channel, drive, command, cylin, head, sector, count, precomp), 1703 DEBUG_FUNCS); 1704 1705 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1706 chp->wdc->select(chp,drive); 1707 1708 /* Select drive, head, and addressing mode. */ 1709 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1710 WDSD_IBM | (drive << 4) | head); 1711 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1712 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1713 precomp); 1714 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1715 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1716 0, cylin >> 8); 1717 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1718 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1719 1720 /* Send command. */ 1721 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1722 return; 1723 } 1724 1725 /* 1726 * Send a 48-bit addressing command. The drive should be ready. 1727 * Assumes interrupts are blocked. 1728 */ 1729 void 1730 wdccommandext(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1731 u_int64_t blkno, u_int16_t count) 1732 { 1733 1734 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1735 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1736 chp->channel, drive, command, (u_int32_t) blkno, count), 1737 DEBUG_FUNCS); 1738 1739 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1740 chp->wdc->select(chp,drive); 1741 1742 /* Select drive, head, and addressing mode. */ 1743 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1744 (drive << 4) | WDSD_LBA); 1745 1746 /* previous */ 1747 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1748 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1749 0, count >> 8); 1750 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1751 0, blkno >> 40); 1752 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1753 0, blkno >> 32); 1754 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1755 0, blkno >> 24); 1756 1757 /* current */ 1758 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1759 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1760 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1761 0, blkno >> 16); 1762 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1763 0, blkno >> 8); 1764 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1765 1766 /* Send command. */ 1767 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1768 return; 1769 } 1770 1771 /* 1772 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1773 * tested by the caller. 1774 */ 1775 void 1776 wdccommandshort(struct channel_softc *chp, int drive, int command) 1777 { 1778 1779 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1780 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1781 DEBUG_FUNCS); 1782 1783 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1784 chp->wdc->select(chp,drive); 1785 1786 /* Select drive. */ 1787 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1788 WDSD_IBM | (drive << 4)); 1789 1790 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1791 } 1792 1793 /* Add a command to the queue and start controller. Must be called at splbio */ 1794 void 1795 wdc_exec_xfer(struct channel_softc *chp, struct ata_xfer *xfer) 1796 { 1797 1798 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1799 chp->channel, xfer->c_drive), DEBUG_XFERS); 1800 1801 /* complete xfer setup */ 1802 xfer->c_chp = chp; 1803 1804 /* 1805 * If we are a polled command, and the list is not empty, 1806 * we are doing a dump. Drop the list to allow the polled command 1807 * to complete, we're going to reboot soon anyway. 1808 */ 1809 if ((xfer->c_flags & C_POLL) != 0 && 1810 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) { 1811 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1812 } 1813 /* insert at the end of command list */ 1814 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1815 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1816 chp->ch_flags), DEBUG_XFERS); 1817 wdcstart(chp); 1818 } 1819 1820 struct ata_xfer * 1821 wdc_get_xfer(int flags) 1822 { 1823 struct ata_xfer *xfer; 1824 int s; 1825 1826 s = splbio(); 1827 xfer = pool_get(&wdc_xfer_pool, 1828 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1829 splx(s); 1830 if (xfer != NULL) { 1831 memset(xfer, 0, sizeof(struct ata_xfer)); 1832 } 1833 return xfer; 1834 } 1835 1836 void 1837 wdc_free_xfer(struct channel_softc *chp, struct ata_xfer *xfer) 1838 { 1839 struct wdc_softc *wdc = chp->wdc; 1840 int s; 1841 1842 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1843 (*wdc->free_hw)(chp); 1844 s = splbio(); 1845 chp->ch_flags &= ~WDCF_ACTIVE; 1846 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1847 pool_put(&wdc_xfer_pool, xfer); 1848 splx(s); 1849 } 1850 1851 /* 1852 * Kill off all pending xfers for a channel_softc. 1853 * 1854 * Must be called at splbio(). 1855 */ 1856 void 1857 wdc_kill_pending(struct channel_softc *chp) 1858 { 1859 struct ata_xfer *xfer; 1860 1861 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 1862 chp = xfer->c_chp; 1863 (*xfer->c_kill_xfer)(chp, xfer); 1864 } 1865 } 1866 1867 static void 1868 __wdcerror(struct channel_softc *chp, char *msg) 1869 { 1870 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1871 1872 if (xfer == NULL) 1873 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1874 msg); 1875 else 1876 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1877 chp->channel, xfer->c_drive, msg); 1878 } 1879 1880 /* 1881 * the bit bucket 1882 */ 1883 void 1884 wdcbit_bucket(struct channel_softc *chp, int size) 1885 { 1886 1887 for (; size >= 2; size -= 2) 1888 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1889 if (size) 1890 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1891 } 1892 1893 int 1894 wdc_addref(struct channel_softc *chp) 1895 { 1896 struct wdc_softc *wdc = chp->wdc; 1897 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1898 int s, error = 0; 1899 1900 s = splbio(); 1901 if (adapt->adapt_refcnt++ == 0 && 1902 adapt->adapt_enable != NULL) { 1903 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1904 if (error) 1905 adapt->adapt_refcnt--; 1906 } 1907 splx(s); 1908 return (error); 1909 } 1910 1911 void 1912 wdc_delref(struct channel_softc *chp) 1913 { 1914 struct wdc_softc *wdc = chp->wdc; 1915 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1916 int s; 1917 1918 s = splbio(); 1919 if (adapt->adapt_refcnt-- == 1 && 1920 adapt->adapt_enable != NULL) 1921 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1922 splx(s); 1923 } 1924 1925 void 1926 wdc_print_modes(struct channel_softc *chp) 1927 { 1928 int drive; 1929 struct ata_drive_datas *drvp; 1930 1931 for (drive = 0; drive < 2; drive++) { 1932 drvp = &chp->ch_drive[drive]; 1933 if ((drvp->drive_flags & DRIVE) == 0) 1934 continue; 1935 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1936 drvp->drv_softc->dv_xname, 1937 chp->wdc->sc_dev.dv_xname, 1938 chp->channel, drive, drvp->PIO_mode); 1939 if (drvp->drive_flags & DRIVE_DMA) 1940 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1941 if (drvp->drive_flags & DRIVE_UDMA) { 1942 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1943 if (drvp->UDMA_mode == 2) 1944 aprint_normal(" (Ultra/33)"); 1945 else if (drvp->UDMA_mode == 4) 1946 aprint_normal(" (Ultra/66)"); 1947 else if (drvp->UDMA_mode == 5) 1948 aprint_normal(" (Ultra/100)"); 1949 else if (drvp->UDMA_mode == 6) 1950 aprint_normal(" (Ultra/133)"); 1951 } 1952 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1953 aprint_normal(" (using DMA data transfers)"); 1954 aprint_normal("\n"); 1955 } 1956 } 1957
Indexes created Wed Sep 24 05:09:52 GMT 2025