wdc.c revision 1.167
1 /* $NetBSD: wdc.c,v 1.167 2004/01/01 21:18:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.167 2004/01/01 21:18:28 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct channel_softc*, int); 147 static void __wdcerror(struct channel_softc*, char *); 148 static int __wdcwait_reset(struct channel_softc *, int, int); 149 static void __wdccommand_done(struct channel_softc *, struct ata_xfer *); 150 static void __wdccommand_start(struct channel_softc *, struct ata_xfer *); 151 static int __wdccommand_intr(struct channel_softc *, struct ata_xfer *, 152 int); 153 static int __wdcwait(struct channel_softc *, int, int, int); 154 155 #define DEBUG_INTR 0x01 156 #define DEBUG_XFERS 0x02 157 #define DEBUG_STATUS 0x04 158 #define DEBUG_FUNCS 0x08 159 #define DEBUG_PROBE 0x10 160 #define DEBUG_DETACH 0x20 161 #define DEBUG_DELAY 0x40 162 #ifdef WDCDEBUG 163 int wdcdebug_mask = 0; 164 int wdc_nxfer = 0; 165 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 166 #else 167 #define WDCDEBUG_PRINT(args, level) 168 #endif 169 170 /* 171 * A queue of atabus instances, used to ensure the same bus probe order 172 * for a given hardware configuration at each boot. 173 */ 174 struct atabus_initq_head atabus_initq_head = 175 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 176 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 177 178 /* Test to see controller with at last one attached drive is there. 179 * Returns a bit for each possible drive found (0x01 for drive 0, 180 * 0x02 for drive 1). 181 * Logic: 182 * - If a status register is at 0xff, assume there is no drive here 183 * (ISA has pull-up resistors). Similarly if the status register has 184 * the value we last wrote to the bus (for IDE interfaces without pullups). 185 * If no drive at all -> return. 186 * - reset the controller, wait for it to complete (may take up to 31s !). 187 * If timeout -> return. 188 * - test ATA/ATAPI signatures. If at last one drive found -> return. 189 * - try an ATA command on the master. 190 */ 191 192 static void 193 wdc_drvprobe(struct channel_softc *chp) 194 { 195 struct ataparams params; 196 u_int8_t st0 = 0, st1 = 0; 197 int i, error; 198 199 if (wdcprobe1(chp, 0) == 0) { 200 /* No drives, abort the attach here. */ 201 return; 202 } 203 204 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 205 for (i = 0; i < mstohz(3000); i++) { 206 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 207 chp->wdc->select(chp,0); 208 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 209 WDSD_IBM); 210 delay(10); /* 400ns delay */ 211 st0 = bus_space_read_1(chp->cmd_iot, 212 chp->cmd_iohs[wd_status], 0); 213 214 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 215 chp->wdc->select(chp,1); 216 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 217 WDSD_IBM | 0x10); 218 delay(10); /* 400ns delay */ 219 st1 = bus_space_read_1(chp->cmd_iot, 220 chp->cmd_iohs[wd_status], 0); 221 222 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 223 == 0 || 224 (st0 & WDCS_DRDY)) && 225 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 226 == 0 || 227 (st1 & WDCS_DRDY))) 228 break; 229 tsleep(¶ms, PRIBIO, "atadrdy", 1); 230 } 231 if ((st0 & WDCS_DRDY) == 0) 232 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 233 if ((st1 & WDCS_DRDY) == 0) 234 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 235 236 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 237 chp->wdc->sc_dev.dv_xname, 238 chp->channel, st0, st1), DEBUG_PROBE); 239 240 /* Wait a bit, some devices are weird just after a reset. */ 241 delay(5000); 242 243 for (i = 0; i < 2; i++) { 244 chp->ch_drive[i].chnl_softc = chp; 245 chp->ch_drive[i].drive = i; 246 /* 247 * Init error counter so that an error withing the first xfers 248 * will trigger a downgrade 249 */ 250 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 251 252 /* If controller can't do 16bit flag the drives as 32bit */ 253 if ((chp->wdc->cap & 254 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 255 WDC_CAPABILITY_DATA32) 256 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 257 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 258 continue; 259 260 /* Shortcut in case we've been shutdown */ 261 if (chp->ch_flags & WDCF_SHUTDOWN) 262 return; 263 264 /* issue an identify, to try to detect ghosts */ 265 error = ata_get_params(&chp->ch_drive[i], 266 AT_WAIT | AT_POLL, ¶ms); 267 if (error != CMD_OK) { 268 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 269 270 /* Shortcut in case we've been shutdown */ 271 if (chp->ch_flags & WDCF_SHUTDOWN) 272 return; 273 274 error = ata_get_params(&chp->ch_drive[i], 275 AT_WAIT | AT_POLL, ¶ms); 276 } 277 if (error == CMD_OK) { 278 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 279 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 280 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 281 } else { 282 chp->ch_drive[i].drive_flags &= 283 ~(DRIVE_ATA | DRIVE_ATAPI); 284 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 285 chp->wdc->sc_dev.dv_xname, 286 chp->channel, i, error), DEBUG_PROBE); 287 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 288 continue; 289 /* 290 * Pre-ATA drive ? 291 * Test registers writability (Error register not 292 * writable, but cyllo is), then try an ATA command. 293 */ 294 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 295 chp->wdc->select(chp,i); 296 bus_space_write_1(chp->cmd_iot, 297 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 298 delay(10); /* 400ns delay */ 299 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 300 0, 0x58); 301 bus_space_write_1(chp->cmd_iot, 302 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 303 if (bus_space_read_1(chp->cmd_iot, 304 chp->cmd_iohs[wd_error], 0) == 0x58 || 305 bus_space_read_1(chp->cmd_iot, 306 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 307 WDCDEBUG_PRINT(("%s:%d:%d: register " 308 "writability failed\n", 309 chp->wdc->sc_dev.dv_xname, 310 chp->channel, i), DEBUG_PROBE); 311 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 312 continue; 313 } 314 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 315 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 316 chp->wdc->sc_dev.dv_xname, 317 chp->channel, i), DEBUG_PROBE); 318 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 319 continue; 320 } 321 bus_space_write_1(chp->cmd_iot, 322 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 323 delay(10); /* 400ns delay */ 324 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 325 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 326 chp->wdc->sc_dev.dv_xname, 327 chp->channel, i), DEBUG_PROBE); 328 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 329 } else { 330 chp->ch_drive[0].drive_flags &= 331 ~(DRIVE_ATA | DRIVE_ATAPI); 332 chp->ch_drive[1].drive_flags &= 333 ~(DRIVE_ATA | DRIVE_ATAPI); 334 } 335 } 336 } 337 } 338 339 void 340 atabusconfig(struct atabus_softc *atabus_sc) 341 { 342 struct channel_softc *chp = atabus_sc->sc_chan; 343 int i, error, need_delref = 0; 344 struct atabus_initq *atabus_initq = NULL; 345 346 if ((error = wdc_addref(chp)) != 0) { 347 aprint_error("%s: unable to enable controller\n", 348 chp->wdc->sc_dev.dv_xname); 349 goto out; 350 } 351 need_delref = 1; 352 353 /* Probe for the drives. */ 354 (*chp->wdc->drv_probe)(chp); 355 356 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 357 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 358 DEBUG_PROBE); 359 360 /* If no drives, abort here */ 361 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 362 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 363 goto out; 364 365 /* Shortcut in case we've been shutdown */ 366 if (chp->ch_flags & WDCF_SHUTDOWN) 367 goto out; 368 369 /* Make sure the devices probe in atabus order to avoid jitter. */ 370 simple_lock(&atabus_interlock); 371 while(1) { 372 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 373 if (atabus_initq->atabus_sc == atabus_sc) 374 break; 375 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 376 &atabus_interlock); 377 } 378 simple_unlock(&atabus_interlock); 379 380 /* 381 * Attach an ATAPI bus, if needed. 382 */ 383 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 384 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 385 #if NATAPIBUS > 0 386 wdc_atapibus_attach(atabus_sc); 387 #else 388 /* 389 * Fake the autoconfig "not configured" message 390 */ 391 aprint_normal("atapibus at %s not configured\n", 392 chp->wdc->sc_dev.dv_xname); 393 chp->atapibus = NULL; 394 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 395 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 396 #endif 397 } 398 399 for (i = 0; i < 2; i++) { 400 struct ata_device adev; 401 if ((chp->ch_drive[i].drive_flags & 402 (DRIVE_ATA | DRIVE_OLD)) == 0) { 403 continue; 404 } 405 memset(&adev, 0, sizeof(struct ata_device)); 406 adev.adev_bustype = &wdc_ata_bustype; 407 adev.adev_channel = chp->channel; 408 adev.adev_openings = 1; 409 adev.adev_drv_data = &chp->ch_drive[i]; 410 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 411 &adev, ataprint); 412 if (chp->ata_drives[i] != NULL) 413 wdc_probe_caps(&chp->ch_drive[i]); 414 else 415 chp->ch_drive[i].drive_flags &= 416 ~(DRIVE_ATA | DRIVE_OLD); 417 } 418 419 /* now that we know the drives, the controller can set its modes */ 420 if (chp->wdc->cap & WDC_CAPABILITY_MODE) { 421 chp->wdc->set_modes(chp); 422 wdc_print_modes(chp); 423 } 424 #if NATARAID > 0 425 if (chp->wdc->cap & WDC_CAPABILITY_RAID) 426 for (i = 0; i < 2; i++) 427 if (chp->ata_drives[i] != NULL) 428 ata_raid_check_component(chp->ata_drives[i]); 429 #endif /* NATARAID > 0 */ 430 431 /* 432 * reset drive_flags for unattached devices, reset state for attached 433 * ones 434 */ 435 for (i = 0; i < 2; i++) { 436 if (chp->ch_drive[i].drv_softc == NULL) 437 chp->ch_drive[i].drive_flags = 0; 438 else 439 chp->ch_drive[i].state = 0; 440 } 441 442 out: 443 if (atabus_initq == NULL) { 444 simple_lock(&atabus_interlock); 445 while(1) { 446 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 447 if (atabus_initq->atabus_sc == atabus_sc) 448 break; 449 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 450 &atabus_interlock); 451 } 452 simple_unlock(&atabus_interlock); 453 } 454 simple_lock(&atabus_interlock); 455 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 456 simple_unlock(&atabus_interlock); 457 458 free(atabus_initq, M_DEVBUF); 459 wakeup(&atabus_initq_head); 460 461 config_pending_decr(); 462 if (need_delref) 463 wdc_delref(chp); 464 } 465 466 int 467 wdcprobe(struct channel_softc *chp) 468 { 469 470 return (wdcprobe1(chp, 1)); 471 } 472 473 static int 474 wdcprobe1(struct channel_softc *chp, int poll) 475 { 476 u_int8_t st0, st1, sc, sn, cl, ch; 477 u_int8_t ret_value = 0x03; 478 u_int8_t drive; 479 int s; 480 481 /* 482 * Sanity check to see if the wdc channel responds at all. 483 */ 484 485 if (chp->wdc == NULL || 486 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 487 488 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 489 chp->wdc->select(chp,0); 490 491 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 492 WDSD_IBM); 493 delay(10); /* 400ns delay */ 494 st0 = bus_space_read_1(chp->cmd_iot, 495 chp->cmd_iohs[wd_status], 0); 496 497 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 498 chp->wdc->select(chp,1); 499 500 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 501 WDSD_IBM | 0x10); 502 delay(10); /* 400ns delay */ 503 st1 = bus_space_read_1(chp->cmd_iot, 504 chp->cmd_iohs[wd_status], 0); 505 506 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 507 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 508 chp->channel, st0, st1), DEBUG_PROBE); 509 510 if (st0 == 0xff || st0 == WDSD_IBM) 511 ret_value &= ~0x01; 512 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 513 ret_value &= ~0x02; 514 /* Register writability test, drive 0. */ 515 if (ret_value & 0x01) { 516 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 517 chp->wdc->select(chp,0); 518 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 519 0, WDSD_IBM); 520 bus_space_write_1(chp->cmd_iot, 521 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 522 if (bus_space_read_1(chp->cmd_iot, 523 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 524 ret_value &= ~0x01; 525 bus_space_write_1(chp->cmd_iot, 526 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 527 if (bus_space_read_1(chp->cmd_iot, 528 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 529 ret_value &= ~0x01; 530 bus_space_write_1(chp->cmd_iot, 531 chp->cmd_iohs[wd_sector], 0, 0x01); 532 if (bus_space_read_1(chp->cmd_iot, 533 chp->cmd_iohs[wd_sector], 0) != 0x01) 534 ret_value &= ~0x01; 535 bus_space_write_1(chp->cmd_iot, 536 chp->cmd_iohs[wd_sector], 0, 0x02); 537 if (bus_space_read_1(chp->cmd_iot, 538 chp->cmd_iohs[wd_sector], 0) != 0x02) 539 ret_value &= ~0x01; 540 if (bus_space_read_1(chp->cmd_iot, 541 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 542 ret_value &= ~0x01; 543 } 544 /* Register writability test, drive 1. */ 545 if (ret_value & 0x02) { 546 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 547 chp->wdc->select(chp,1); 548 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 549 0, WDSD_IBM | 0x10); 550 bus_space_write_1(chp->cmd_iot, 551 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 552 if (bus_space_read_1(chp->cmd_iot, 553 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 554 ret_value &= ~0x02; 555 bus_space_write_1(chp->cmd_iot, 556 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 557 if (bus_space_read_1(chp->cmd_iot, 558 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 559 ret_value &= ~0x02; 560 bus_space_write_1(chp->cmd_iot, 561 chp->cmd_iohs[wd_sector], 0, 0x01); 562 if (bus_space_read_1(chp->cmd_iot, 563 chp->cmd_iohs[wd_sector], 0) != 0x01) 564 ret_value &= ~0x02; 565 bus_space_write_1(chp->cmd_iot, 566 chp->cmd_iohs[wd_sector], 0, 0x02); 567 if (bus_space_read_1(chp->cmd_iot, 568 chp->cmd_iohs[wd_sector], 0) != 0x02) 569 ret_value &= ~0x02; 570 if (bus_space_read_1(chp->cmd_iot, 571 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 572 ret_value &= ~0x02; 573 } 574 575 if (ret_value == 0) 576 return 0; 577 } 578 579 s = splbio(); 580 581 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT)) 582 chp->wdc->select(chp,0); 583 /* assert SRST, wait for reset to complete */ 584 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 585 delay(10); /* 400ns delay */ 586 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 587 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 588 DELAY(2000); 589 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 590 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 591 delay(10); /* 400ns delay */ 592 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 593 if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_IRQACK)) 594 chp->wdc->irqack(chp); 595 splx(s); 596 597 ret_value = __wdcwait_reset(chp, ret_value, poll); 598 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 599 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 600 ret_value), DEBUG_PROBE); 601 602 /* if reset failed, there's nothing here */ 603 if (ret_value == 0) 604 return 0; 605 606 /* 607 * Test presence of drives. First test register signatures looking 608 * for ATAPI devices. If it's not an ATAPI and reset said there may 609 * be something here assume it's ATA or OLD. Ghost will be killed 610 * later in attach routine. 611 */ 612 for (drive = 0; drive < 2; drive++) { 613 if ((ret_value & (0x01 << drive)) == 0) 614 continue; 615 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 616 chp->wdc->select(chp,drive); 617 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 618 WDSD_IBM | (drive << 4)); 619 delay(10); /* 400ns delay */ 620 /* Save registers contents */ 621 sc = bus_space_read_1(chp->cmd_iot, 622 chp->cmd_iohs[wd_seccnt], 0); 623 sn = bus_space_read_1(chp->cmd_iot, 624 chp->cmd_iohs[wd_sector], 0); 625 cl = bus_space_read_1(chp->cmd_iot, 626 chp->cmd_iohs[wd_cyl_lo], 0); 627 ch = bus_space_read_1(chp->cmd_iot, 628 chp->cmd_iohs[wd_cyl_hi], 0); 629 630 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 631 "cl=0x%x ch=0x%x\n", 632 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 633 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 634 /* 635 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 636 * we get wrong values here, so ignore it. 637 */ 638 if (cl == 0x14 && ch == 0xeb) { 639 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 640 } else { 641 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 642 if (chp->wdc == NULL || 643 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 644 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 645 } 646 } 647 return (ret_value); 648 } 649 650 void 651 wdcattach(struct channel_softc *chp) 652 { 653 static int inited = 0; 654 655 if (chp->ch_flags & WDCF_DISABLED) 656 return; 657 658 /* initialise global data */ 659 callout_init(&chp->ch_callout); 660 if (chp->wdc->drv_probe == NULL) 661 chp->wdc->drv_probe = wdc_drvprobe; 662 if (inited == 0) { 663 /* Initialize the ata_xfer pool. */ 664 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 665 0, 0, "wdcspl", NULL); 666 inited++; 667 } 668 TAILQ_INIT(&chp->ch_queue->queue_xfer); 669 chp->ch_queue->queue_freeze = 0; 670 671 chp->atabus = config_found(&chp->wdc->sc_dev, chp, atabusprint); 672 } 673 674 int 675 wdcactivate(struct device *self, enum devact act) 676 { 677 struct wdc_softc *wdc = (struct wdc_softc *)self; 678 int s, i, error = 0; 679 680 s = splbio(); 681 switch (act) { 682 case DVACT_ACTIVATE: 683 error = EOPNOTSUPP; 684 break; 685 686 case DVACT_DEACTIVATE: 687 for (i = 0; i < wdc->nchannels; i++) { 688 error = config_deactivate(wdc->channels[i]->atabus); 689 if (error) 690 break; 691 } 692 break; 693 } 694 splx(s); 695 return (error); 696 } 697 698 int 699 wdcdetach(struct device *self, int flags) 700 { 701 struct wdc_softc *wdc = (struct wdc_softc *)self; 702 struct channel_softc *chp; 703 int i, error = 0; 704 705 for (i = 0; i < wdc->nchannels; i++) { 706 chp = wdc->channels[i]; 707 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 708 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 709 error = config_detach(chp->atabus, flags); 710 if (error) 711 break; 712 } 713 return (error); 714 } 715 716 /* 717 * Start I/O on a controller, for the given channel. 718 * The first xfer may be not for our channel if the channel queues 719 * are shared. 720 */ 721 void 722 wdcstart(struct channel_softc *chp) 723 { 724 struct ata_xfer *xfer; 725 726 #ifdef WDC_DIAGNOSTIC 727 int spl1, spl2; 728 729 spl1 = splbio(); 730 spl2 = splbio(); 731 if (spl2 != spl1) { 732 printf("wdcstart: not at splbio()\n"); 733 panic("wdcstart"); 734 } 735 splx(spl2); 736 splx(spl1); 737 #endif /* WDC_DIAGNOSTIC */ 738 739 /* is there a xfer ? */ 740 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 741 return; 742 743 /* adjust chp, in case we have a shared queue */ 744 chp = xfer->c_chp; 745 746 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 747 return; /* channel aleady active */ 748 } 749 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 750 return; /* queue froozen */ 751 } 752 #ifdef DIAGNOSTIC 753 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 754 panic("wdcstart: channel waiting for irq"); 755 #endif 756 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 757 if (!(*chp->wdc->claim_hw)(chp, 0)) 758 return; 759 760 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 761 chp->channel, xfer->c_drive), DEBUG_XFERS); 762 chp->ch_flags |= WDCF_ACTIVE; 763 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 764 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 765 chp->ch_drive[xfer->c_drive].state = 0; 766 } 767 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 768 KASSERT(xfer->c_flags & C_POLL); 769 xfer->c_start(chp, xfer); 770 } 771 772 /* restart an interrupted I/O */ 773 void 774 wdcrestart(void *v) 775 { 776 struct channel_softc *chp = v; 777 int s; 778 779 s = splbio(); 780 wdcstart(chp); 781 splx(s); 782 } 783 784 785 /* 786 * Interrupt routine for the controller. Acknowledge the interrupt, check for 787 * errors on the current operation, mark it done if necessary, and start the 788 * next request. Also check for a partially done transfer, and continue with 789 * the next chunk if so. 790 */ 791 int 792 wdcintr(void *arg) 793 { 794 struct channel_softc *chp = arg; 795 struct ata_xfer *xfer; 796 int ret; 797 798 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 799 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 800 DEBUG_INTR); 801 return (0); 802 } 803 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 804 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 805 /* try to clear the pending interrupt anyway */ 806 (void)bus_space_read_1(chp->cmd_iot, 807 chp->cmd_iohs[wd_status], 0); 808 return (0); 809 } 810 811 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 812 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 813 if (chp->ch_flags & WDCF_DMA_WAIT) { 814 chp->wdc->dma_status = 815 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 816 xfer->c_drive, 0); 817 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 818 /* IRQ not for us, not detected by DMA engine */ 819 return 0; 820 } 821 chp->ch_flags &= ~WDCF_DMA_WAIT; 822 } 823 chp->ch_flags &= ~WDCF_IRQ_WAIT; 824 ret = xfer->c_intr(chp, xfer, 1); 825 if (ret == 0) /* irq was not for us, still waiting for irq */ 826 chp->ch_flags |= WDCF_IRQ_WAIT; 827 return (ret); 828 } 829 830 /* Put all disk in RESET state */ 831 void 832 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 833 { 834 struct channel_softc *chp = drvp->chnl_softc; 835 int drive; 836 837 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 838 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 839 DEBUG_FUNCS); 840 if ((flags & AT_POLL) == 0) { 841 if (chp->ch_flags & WDCF_TH_RESET) { 842 /* no need to schedule a reset more than one time */ 843 return; 844 } 845 chp->ch_flags |= WDCF_TH_RESET; 846 chp->ch_queue->queue_freeze++; 847 wakeup(&chp->thread); 848 return; 849 } 850 (void) wdcreset(chp, RESET_POLL); 851 for (drive = 0; drive < 2; drive++) { 852 chp->ch_drive[drive].state = 0; 853 } 854 } 855 856 int 857 wdcreset(struct channel_softc *chp, int poll) 858 { 859 int drv_mask1, drv_mask2; 860 int s = 0; 861 862 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 863 chp->wdc->select(chp,0); 864 if (poll != RESET_SLEEP) 865 s = splbio(); 866 /* master */ 867 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 868 delay(10); /* 400ns delay */ 869 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 870 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 871 delay(2000); 872 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 873 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 874 WDCTL_4BIT | WDCTL_IDS); 875 delay(10); /* 400ns delay */ 876 if (poll != RESET_SLEEP) { 877 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 878 chp->wdc->irqack(chp); 879 splx(s); 880 } 881 882 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 883 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 884 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 885 (poll == RESET_SLEEP) ? 0 : 1); 886 if (drv_mask2 != drv_mask1) { 887 printf("%s channel %d: reset failed for", 888 chp->wdc->sc_dev.dv_xname, chp->channel); 889 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 890 printf(" drive 0"); 891 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 892 printf(" drive 1"); 893 printf("\n"); 894 } 895 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 896 return (drv_mask1 != drv_mask2) ? 1 : 0; 897 } 898 899 static int 900 __wdcwait_reset(struct channel_softc *chp, int drv_mask, int poll) 901 { 902 int timeout, nloop; 903 u_int8_t st0 = 0, st1 = 0; 904 #ifdef WDCDEBUG 905 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 906 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 907 #endif 908 909 if (poll) 910 nloop = WDCNDELAY_RST; 911 else 912 nloop = WDC_RESET_WAIT * hz / 1000; 913 /* wait for BSY to deassert */ 914 for (timeout = 0; timeout < nloop; timeout++) { 915 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 916 chp->wdc->select(chp,0); 917 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 918 WDSD_IBM); /* master */ 919 delay(10); 920 st0 = bus_space_read_1(chp->cmd_iot, 921 chp->cmd_iohs[wd_status], 0); 922 #ifdef WDCDEBUG 923 sc0 = bus_space_read_1(chp->cmd_iot, 924 chp->cmd_iohs[wd_seccnt], 0); 925 sn0 = bus_space_read_1(chp->cmd_iot, 926 chp->cmd_iohs[wd_sector], 0); 927 cl0 = bus_space_read_1(chp->cmd_iot, 928 chp->cmd_iohs[wd_cyl_lo], 0); 929 ch0 = bus_space_read_1(chp->cmd_iot, 930 chp->cmd_iohs[wd_cyl_hi], 0); 931 #endif 932 if (chp->wdc && chp->wdc->cap & WDC_CAPABILITY_SELECT) 933 chp->wdc->select(chp,1); 934 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 935 WDSD_IBM | 0x10); /* slave */ 936 delay(10); 937 st1 = bus_space_read_1(chp->cmd_iot, 938 chp->cmd_iohs[wd_status], 0); 939 #ifdef WDCDEBUG 940 sc1 = bus_space_read_1(chp->cmd_iot, 941 chp->cmd_iohs[wd_seccnt], 0); 942 sn1 = bus_space_read_1(chp->cmd_iot, 943 chp->cmd_iohs[wd_sector], 0); 944 cl1 = bus_space_read_1(chp->cmd_iot, 945 chp->cmd_iohs[wd_cyl_lo], 0); 946 ch1 = bus_space_read_1(chp->cmd_iot, 947 chp->cmd_iohs[wd_cyl_hi], 0); 948 #endif 949 950 if ((drv_mask & 0x01) == 0) { 951 /* no master */ 952 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 953 /* No master, slave is ready, it's done */ 954 goto end; 955 } 956 } else if ((drv_mask & 0x02) == 0) { 957 /* no slave */ 958 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 959 /* No slave, master is ready, it's done */ 960 goto end; 961 } 962 } else { 963 /* Wait for both master and slave to be ready */ 964 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 965 goto end; 966 } 967 } 968 if (poll) 969 delay(WDCDELAY); 970 else 971 tsleep(&nloop, PRIBIO, "atarst", 1); 972 } 973 /* Reset timed out. Maybe it's because drv_mask was not right */ 974 if (st0 & WDCS_BSY) 975 drv_mask &= ~0x01; 976 if (st1 & WDCS_BSY) 977 drv_mask &= ~0x02; 978 end: 979 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 980 "cl=0x%x ch=0x%x\n", 981 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 982 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 983 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 984 "cl=0x%x ch=0x%x\n", 985 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 986 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 987 988 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 989 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 990 st0, st1), DEBUG_PROBE); 991 992 return drv_mask; 993 } 994 995 /* 996 * Wait for a drive to be !BSY, and have mask in its status register. 997 * return -1 for a timeout after "timeout" ms. 998 */ 999 static int 1000 __wdcwait(struct channel_softc *chp, int mask, int bits, int timeout) 1001 { 1002 u_char status; 1003 int time = 0; 1004 1005 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1006 :"none", chp->channel), DEBUG_STATUS); 1007 chp->ch_error = 0; 1008 1009 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1010 1011 for (;;) { 1012 chp->ch_status = status = 1013 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1014 if ((status & (WDCS_BSY | mask)) == bits) 1015 break; 1016 if (++time > timeout) { 1017 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1018 "status %x error %x (mask 0x%x bits 0x%x)\n", 1019 time, status, 1020 bus_space_read_1(chp->cmd_iot, 1021 chp->cmd_iohs[wd_error], 0), mask, bits), 1022 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1023 return(WDCWAIT_TOUT); 1024 } 1025 delay(WDCDELAY); 1026 } 1027 #ifdef WDCDEBUG 1028 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1029 printf("__wdcwait: did busy-wait, time=%d\n", time); 1030 #endif 1031 if (status & WDCS_ERR) 1032 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1033 chp->cmd_iohs[wd_error], 0); 1034 #ifdef WDCNDELAY_DEBUG 1035 /* After autoconfig, there should be no long delays. */ 1036 if (!cold && time > WDCNDELAY_DEBUG) { 1037 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1038 if (xfer == NULL) 1039 printf("%s channel %d: warning: busy-wait took %dus\n", 1040 chp->wdc->sc_dev.dv_xname, chp->channel, 1041 WDCDELAY * time); 1042 else 1043 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1044 chp->wdc->sc_dev.dv_xname, chp->channel, 1045 xfer->drive, 1046 WDCDELAY * time); 1047 } 1048 #endif 1049 return(WDCWAIT_OK); 1050 } 1051 1052 /* 1053 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1054 * thread if possible 1055 */ 1056 int 1057 wdcwait(struct channel_softc *chp, int mask, int bits, int timeout, int flags) 1058 { 1059 int error, i, timeout_hz = mstohz(timeout); 1060 1061 if (timeout_hz == 0 || 1062 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1063 error = __wdcwait(chp, mask, bits, timeout); 1064 else { 1065 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1066 if (error != 0) { 1067 if ((chp->ch_flags & WDCF_TH_RUN) || 1068 (flags & AT_WAIT)) { 1069 /* 1070 * we're running in the channel thread 1071 * or some userland thread context 1072 */ 1073 for (i = 0; i < timeout_hz; i++) { 1074 if (__wdcwait(chp, mask, bits, 1075 WDCDELAY_POLL) == 0) { 1076 error = 0; 1077 break; 1078 } 1079 tsleep(&chp, PRIBIO, "atapoll", 1); 1080 } 1081 } else { 1082 /* 1083 * we're probably in interrupt context, 1084 * ask the thread to come back here 1085 */ 1086 #ifdef DIAGNOSTIC 1087 if (chp->ch_queue->queue_freeze > 0) 1088 panic("wdcwait: queue_freeze"); 1089 #endif 1090 chp->ch_queue->queue_freeze++; 1091 wakeup(&chp->thread); 1092 return(WDCWAIT_THR); 1093 } 1094 } 1095 } 1096 return (error); 1097 } 1098 1099 1100 /* 1101 * Busy-wait for DMA to complete 1102 */ 1103 int 1104 wdc_dmawait(struct channel_softc *chp, struct ata_xfer *xfer, int timeout) 1105 { 1106 int time; 1107 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1108 chp->wdc->dma_status = 1109 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1110 chp->channel, xfer->c_drive, 0); 1111 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1112 return 0; 1113 delay(WDCDELAY); 1114 } 1115 /* timeout, force a DMA halt */ 1116 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1117 chp->channel, xfer->c_drive, 1); 1118 return 1; 1119 } 1120 1121 void 1122 wdctimeout(void *arg) 1123 { 1124 struct channel_softc *chp = (struct channel_softc *)arg; 1125 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1126 int s; 1127 1128 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1129 1130 s = splbio(); 1131 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1132 __wdcerror(chp, "lost interrupt"); 1133 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1134 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1135 xfer->c_bcount, 1136 xfer->c_skip); 1137 if (chp->ch_flags & WDCF_DMA_WAIT) { 1138 chp->wdc->dma_status = 1139 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1140 chp->channel, xfer->c_drive, 1); 1141 chp->ch_flags &= ~WDCF_DMA_WAIT; 1142 } 1143 /* 1144 * Call the interrupt routine. If we just missed an interrupt, 1145 * it will do what's needed. Else, it will take the needed 1146 * action (reset the device). 1147 * Before that we need to reinstall the timeout callback, 1148 * in case it will miss another irq while in this transfer 1149 * We arbitray chose it to be 1s 1150 */ 1151 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1152 xfer->c_flags |= C_TIMEOU; 1153 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1154 xfer->c_intr(chp, xfer, 1); 1155 } else 1156 __wdcerror(chp, "missing untimeout"); 1157 splx(s); 1158 } 1159 1160 /* 1161 * Probe drive's capabilities, for use by the controller later 1162 * Assumes drvp points to an existing drive. 1163 * XXX this should be a controller-indep function 1164 */ 1165 void 1166 wdc_probe_caps(struct ata_drive_datas *drvp) 1167 { 1168 struct ataparams params, params2; 1169 struct channel_softc *chp = drvp->chnl_softc; 1170 struct device *drv_dev = drvp->drv_softc; 1171 struct wdc_softc *wdc = chp->wdc; 1172 int i, printed; 1173 char *sep = ""; 1174 int cf_flags; 1175 1176 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1177 /* IDENTIFY failed. Can't tell more about the device */ 1178 return; 1179 } 1180 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1181 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1182 /* 1183 * Controller claims 16 and 32 bit transfers. 1184 * Re-do an IDENTIFY with 32-bit transfers, 1185 * and compare results. 1186 */ 1187 drvp->drive_flags |= DRIVE_CAP32; 1188 ata_get_params(drvp, AT_WAIT, ¶ms2); 1189 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1190 /* Not good. fall back to 16bits */ 1191 drvp->drive_flags &= ~DRIVE_CAP32; 1192 } else { 1193 aprint_normal("%s: 32-bit data port\n", 1194 drv_dev->dv_xname); 1195 } 1196 } 1197 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1198 if (params.atap_ata_major > 0x01 && 1199 params.atap_ata_major != 0xffff) { 1200 for (i = 14; i > 0; i--) { 1201 if (params.atap_ata_major & (1 << i)) { 1202 aprint_normal("%s: ATA version %d\n", 1203 drv_dev->dv_xname, i); 1204 drvp->ata_vers = i; 1205 break; 1206 } 1207 } 1208 } 1209 #endif 1210 1211 /* An ATAPI device is at last PIO mode 3 */ 1212 if (drvp->drive_flags & DRIVE_ATAPI) 1213 drvp->PIO_mode = 3; 1214 1215 /* 1216 * It's not in the specs, but it seems that some drive 1217 * returns 0xffff in atap_extensions when this field is invalid 1218 */ 1219 if (params.atap_extensions != 0xffff && 1220 (params.atap_extensions & WDC_EXT_MODES)) { 1221 printed = 0; 1222 /* 1223 * XXX some drives report something wrong here (they claim to 1224 * support PIO mode 8 !). As mode is coded on 3 bits in 1225 * SET FEATURE, limit it to 7 (so limit i to 4). 1226 * If higher mode than 7 is found, abort. 1227 */ 1228 for (i = 7; i >= 0; i--) { 1229 if ((params.atap_piomode_supp & (1 << i)) == 0) 1230 continue; 1231 if (i > 4) 1232 return; 1233 /* 1234 * See if mode is accepted. 1235 * If the controller can't set its PIO mode, 1236 * assume the defaults are good, so don't try 1237 * to set it 1238 */ 1239 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1240 /* 1241 * It's OK to pool here, it's fast enouth 1242 * to not bother waiting for interrupt 1243 */ 1244 if (ata_set_mode(drvp, 0x08 | (i + 3), 1245 AT_WAIT) != CMD_OK) 1246 continue; 1247 if (!printed) { 1248 aprint_normal("%s: drive supports PIO mode %d", 1249 drv_dev->dv_xname, i + 3); 1250 sep = ","; 1251 printed = 1; 1252 } 1253 /* 1254 * If controller's driver can't set its PIO mode, 1255 * get the highter one for the drive. 1256 */ 1257 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1258 wdc->PIO_cap >= i + 3) { 1259 drvp->PIO_mode = i + 3; 1260 drvp->PIO_cap = i + 3; 1261 break; 1262 } 1263 } 1264 if (!printed) { 1265 /* 1266 * We didn't find a valid PIO mode. 1267 * Assume the values returned for DMA are buggy too 1268 */ 1269 return; 1270 } 1271 drvp->drive_flags |= DRIVE_MODE; 1272 printed = 0; 1273 for (i = 7; i >= 0; i--) { 1274 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1275 continue; 1276 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1277 (wdc->cap & WDC_CAPABILITY_MODE)) 1278 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1279 != CMD_OK) 1280 continue; 1281 if (!printed) { 1282 aprint_normal("%s DMA mode %d", sep, i); 1283 sep = ","; 1284 printed = 1; 1285 } 1286 if (wdc->cap & WDC_CAPABILITY_DMA) { 1287 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1288 wdc->DMA_cap < i) 1289 continue; 1290 drvp->DMA_mode = i; 1291 drvp->DMA_cap = i; 1292 drvp->drive_flags |= DRIVE_DMA; 1293 } 1294 break; 1295 } 1296 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1297 printed = 0; 1298 for (i = 7; i >= 0; i--) { 1299 if ((params.atap_udmamode_supp & (1 << i)) 1300 == 0) 1301 continue; 1302 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1303 (wdc->cap & WDC_CAPABILITY_UDMA)) 1304 if (ata_set_mode(drvp, 0x40 | i, 1305 AT_WAIT) != CMD_OK) 1306 continue; 1307 if (!printed) { 1308 aprint_normal("%s Ultra-DMA mode %d", 1309 sep, i); 1310 if (i == 2) 1311 aprint_normal(" (Ultra/33)"); 1312 else if (i == 4) 1313 aprint_normal(" (Ultra/66)"); 1314 else if (i == 5) 1315 aprint_normal(" (Ultra/100)"); 1316 else if (i == 6) 1317 aprint_normal(" (Ultra/133)"); 1318 sep = ","; 1319 printed = 1; 1320 } 1321 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1322 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1323 wdc->UDMA_cap < i) 1324 continue; 1325 drvp->UDMA_mode = i; 1326 drvp->UDMA_cap = i; 1327 drvp->drive_flags |= DRIVE_UDMA; 1328 } 1329 break; 1330 } 1331 } 1332 aprint_normal("\n"); 1333 } 1334 1335 /* Try to guess ATA version here, if it didn't get reported */ 1336 if (drvp->ata_vers == 0) { 1337 if (drvp->drive_flags & DRIVE_UDMA) 1338 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1339 else if (drvp->PIO_cap > 2) 1340 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1341 } 1342 cf_flags = drv_dev->dv_cfdata->cf_flags; 1343 if (cf_flags & ATA_CONFIG_PIO_SET) { 1344 drvp->PIO_mode = 1345 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1346 drvp->drive_flags |= DRIVE_MODE; 1347 } 1348 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1349 /* don't care about DMA modes */ 1350 return; 1351 } 1352 if (cf_flags & ATA_CONFIG_DMA_SET) { 1353 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1354 ATA_CONFIG_DMA_DISABLE) { 1355 drvp->drive_flags &= ~DRIVE_DMA; 1356 } else { 1357 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1358 ATA_CONFIG_DMA_OFF; 1359 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1360 } 1361 } 1362 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1363 /* don't care about UDMA modes */ 1364 return; 1365 } 1366 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1367 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1368 ATA_CONFIG_UDMA_DISABLE) { 1369 drvp->drive_flags &= ~DRIVE_UDMA; 1370 } else { 1371 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1372 ATA_CONFIG_UDMA_OFF; 1373 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1374 } 1375 } 1376 } 1377 1378 /* 1379 * downgrade the transfer mode of a drive after an error. return 1 if 1380 * downgrade was possible, 0 otherwise. 1381 */ 1382 int 1383 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1384 { 1385 struct channel_softc *chp = drvp->chnl_softc; 1386 struct device *drv_dev = drvp->drv_softc; 1387 struct wdc_softc *wdc = chp->wdc; 1388 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1389 1390 /* if drive or controller don't know its mode, we can't do much */ 1391 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1392 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1393 return 0; 1394 /* current drive mode was set by a config flag, let it this way */ 1395 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1396 (cf_flags & ATA_CONFIG_DMA_SET) || 1397 (cf_flags & ATA_CONFIG_UDMA_SET)) 1398 return 0; 1399 1400 /* 1401 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1402 * Maybe we didn't properly notice the cable type 1403 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1404 * It helps in some cases. 1405 */ 1406 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1407 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1408 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1409 drv_dev->dv_xname, drvp->UDMA_mode); 1410 } 1411 1412 /* 1413 * If we were using ultra-DMA, don't downgrade to multiword DMA 1414 * if we noticed a CRC error. It has been noticed that CRC errors 1415 * in ultra-DMA lead to silent data corruption in multiword DMA. 1416 * Data corruption is less likely to occur in PIO mode. 1417 */ 1418 else if ((drvp->drive_flags & DRIVE_UDMA) && 1419 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1420 drvp->drive_flags &= ~DRIVE_UDMA; 1421 drvp->drive_flags |= DRIVE_DMA; 1422 drvp->DMA_mode = drvp->DMA_cap; 1423 printf("%s: transfer error, downgrading to DMA mode %d\n", 1424 drv_dev->dv_xname, drvp->DMA_mode); 1425 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1426 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1427 drvp->PIO_mode = drvp->PIO_cap; 1428 printf("%s: transfer error, downgrading to PIO mode %d\n", 1429 drv_dev->dv_xname, drvp->PIO_mode); 1430 } else /* already using PIO, can't downgrade */ 1431 return 0; 1432 1433 wdc->set_modes(chp); 1434 wdc_print_modes(chp); 1435 /* reset the channel, which will shedule all drives for setup */ 1436 wdc_reset_channel(drvp, flags); 1437 return 1; 1438 } 1439 1440 int 1441 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1442 { 1443 struct channel_softc *chp = drvp->chnl_softc; 1444 struct ata_xfer *xfer; 1445 int s, ret; 1446 1447 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1448 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1449 DEBUG_FUNCS); 1450 1451 /* set up an xfer and queue. Wait for completion */ 1452 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1453 WDC_NOSLEEP); 1454 if (xfer == NULL) { 1455 return WDC_TRY_AGAIN; 1456 } 1457 1458 if (chp->wdc->cap & WDC_CAPABILITY_NOIRQ) 1459 wdc_c->flags |= AT_POLL; 1460 if (wdc_c->flags & AT_POLL) 1461 xfer->c_flags |= C_POLL; 1462 xfer->c_drive = drvp->drive; 1463 xfer->c_databuf = wdc_c->data; 1464 xfer->c_bcount = wdc_c->bcount; 1465 xfer->c_cmd = wdc_c; 1466 xfer->c_start = __wdccommand_start; 1467 xfer->c_intr = __wdccommand_intr; 1468 xfer->c_kill_xfer = __wdccommand_done; 1469 1470 s = splbio(); 1471 wdc_exec_xfer(chp, xfer); 1472 #ifdef DIAGNOSTIC 1473 if ((wdc_c->flags & AT_POLL) != 0 && 1474 (wdc_c->flags & AT_DONE) == 0) 1475 panic("wdc_exec_command: polled command not done"); 1476 #endif 1477 if (wdc_c->flags & AT_DONE) { 1478 ret = WDC_COMPLETE; 1479 } else { 1480 if (wdc_c->flags & AT_WAIT) { 1481 while ((wdc_c->flags & AT_DONE) == 0) { 1482 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1483 } 1484 ret = WDC_COMPLETE; 1485 } else { 1486 ret = WDC_QUEUED; 1487 } 1488 } 1489 splx(s); 1490 return ret; 1491 } 1492 1493 static void 1494 __wdccommand_start(struct channel_softc *chp, struct ata_xfer *xfer) 1495 { 1496 int drive = xfer->c_drive; 1497 struct wdc_command *wdc_c = xfer->c_cmd; 1498 1499 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1500 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1501 DEBUG_FUNCS); 1502 1503 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1504 chp->wdc->select(chp,drive); 1505 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1506 WDSD_IBM | (drive << 4)); 1507 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1508 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1509 case WDCWAIT_OK: 1510 break; 1511 case WDCWAIT_TOUT: 1512 wdc_c->flags |= AT_TIMEOU; 1513 __wdccommand_done(chp, xfer); 1514 return; 1515 case WDCWAIT_THR: 1516 return; 1517 } 1518 if (wdc_c->flags & AT_POLL) { 1519 /* polled command, disable interrupts */ 1520 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1521 WDCTL_4BIT | WDCTL_IDS); 1522 } 1523 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1524 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1525 1526 if ((wdc_c->flags & AT_POLL) == 0) { 1527 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1528 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1529 wdctimeout, chp); 1530 return; 1531 } 1532 /* 1533 * Polled command. Wait for drive ready or drq. Done in intr(). 1534 * Wait for at last 400ns for status bit to be valid. 1535 */ 1536 delay(10); /* 400ns delay */ 1537 __wdccommand_intr(chp, xfer, 0); 1538 } 1539 1540 static int 1541 __wdccommand_intr(struct channel_softc *chp, struct ata_xfer *xfer, int irq) 1542 { 1543 struct wdc_command *wdc_c = xfer->c_cmd; 1544 int bcount = wdc_c->bcount; 1545 char *data = wdc_c->data; 1546 int wflags; 1547 1548 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1549 /* both wait and poll, we can tsleep here */ 1550 wflags = AT_WAIT | AT_POLL; 1551 } else { 1552 wflags = AT_POLL; 1553 } 1554 1555 again: 1556 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1557 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1558 DEBUG_INTR); 1559 /* 1560 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1561 * Reselect again, it doesn't hurt for others commands, and the time 1562 * penalty for the extra regiter write is acceptable, 1563 * wdc_exec_command() isn't called often (mosly for autoconfig) 1564 */ 1565 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1566 WDSD_IBM | (xfer->c_drive << 4)); 1567 if ((wdc_c->flags & AT_XFDONE) != 0) { 1568 /* 1569 * We have completed a data xfer. The drive should now be 1570 * in its initial state 1571 */ 1572 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1573 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1574 wflags) == WDCWAIT_TOUT) { 1575 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1576 return 0; /* IRQ was not for us */ 1577 wdc_c->flags |= AT_TIMEOU; 1578 } 1579 goto out; 1580 } 1581 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1582 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1583 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1584 return 0; /* IRQ was not for us */ 1585 wdc_c->flags |= AT_TIMEOU; 1586 goto out; 1587 } 1588 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1589 chp->wdc->irqack(chp); 1590 if (wdc_c->flags & AT_READ) { 1591 if ((chp->ch_status & WDCS_DRQ) == 0) { 1592 wdc_c->flags |= AT_TIMEOU; 1593 goto out; 1594 } 1595 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1596 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1597 0, (u_int32_t*)data, bcount >> 2); 1598 data += bcount & 0xfffffffc; 1599 bcount = bcount & 0x03; 1600 } 1601 if (bcount > 0) 1602 bus_space_read_multi_2(chp->cmd_iot, 1603 chp->cmd_iohs[wd_data], 0, 1604 (u_int16_t *)data, bcount >> 1); 1605 /* at this point the drive should be in its initial state */ 1606 wdc_c->flags |= AT_XFDONE; 1607 /* XXX should read status register here ? */ 1608 } else if (wdc_c->flags & AT_WRITE) { 1609 if ((chp->ch_status & WDCS_DRQ) == 0) { 1610 wdc_c->flags |= AT_TIMEOU; 1611 goto out; 1612 } 1613 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1614 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1615 0, (u_int32_t*)data, bcount >> 2); 1616 data += bcount & 0xfffffffc; 1617 bcount = bcount & 0x03; 1618 } 1619 if (bcount > 0) 1620 bus_space_write_multi_2(chp->cmd_iot, 1621 chp->cmd_iohs[wd_data], 0, 1622 (u_int16_t *)data, bcount >> 1); 1623 wdc_c->flags |= AT_XFDONE; 1624 if ((wdc_c->flags & AT_POLL) == 0) { 1625 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1626 callout_reset(&chp->ch_callout, 1627 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1628 return 1; 1629 } else { 1630 goto again; 1631 } 1632 } 1633 out: 1634 __wdccommand_done(chp, xfer); 1635 return 1; 1636 } 1637 1638 static void 1639 __wdccommand_done(struct channel_softc *chp, struct ata_xfer *xfer) 1640 { 1641 struct wdc_command *wdc_c = xfer->c_cmd; 1642 1643 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1644 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->c_drive), 1645 DEBUG_FUNCS); 1646 1647 callout_stop(&chp->ch_callout); 1648 1649 if (chp->ch_status & WDCS_DWF) 1650 wdc_c->flags |= AT_DF; 1651 if (chp->ch_status & WDCS_ERR) { 1652 wdc_c->flags |= AT_ERROR; 1653 wdc_c->r_error = chp->ch_error; 1654 } 1655 wdc_c->flags |= AT_DONE; 1656 if ((wdc_c->flags & AT_READREG) != 0 && 1657 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1658 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1659 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1660 chp->cmd_iohs[wd_sdh], 0); 1661 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1662 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1663 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1664 chp->cmd_iohs[wd_cyl_lo], 0); 1665 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1666 chp->cmd_iohs[wd_sector], 0); 1667 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1668 chp->cmd_iohs[wd_seccnt], 0); 1669 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1670 chp->cmd_iohs[wd_error], 0); 1671 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1672 chp->cmd_iohs[wd_precomp], 0); 1673 } 1674 1675 if (wdc_c->flags & AT_POLL) { 1676 /* enable interrupts */ 1677 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1678 WDCTL_4BIT); 1679 } 1680 wdc_free_xfer(chp, xfer); 1681 if (wdc_c->flags & AT_WAIT) 1682 wakeup(wdc_c); 1683 else if (wdc_c->callback) 1684 wdc_c->callback(wdc_c->callback_arg); 1685 wdcstart(chp); 1686 return; 1687 } 1688 1689 /* 1690 * Send a command. The drive should be ready. 1691 * Assumes interrupts are blocked. 1692 */ 1693 void 1694 wdccommand(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1695 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1696 u_int8_t precomp) 1697 { 1698 1699 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1700 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1701 chp->channel, drive, command, cylin, head, sector, count, precomp), 1702 DEBUG_FUNCS); 1703 1704 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1705 chp->wdc->select(chp,drive); 1706 1707 /* Select drive, head, and addressing mode. */ 1708 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1709 WDSD_IBM | (drive << 4) | head); 1710 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1711 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1712 precomp); 1713 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1714 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1715 0, cylin >> 8); 1716 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1717 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1718 1719 /* Send command. */ 1720 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1721 return; 1722 } 1723 1724 /* 1725 * Send a 48-bit addressing command. The drive should be ready. 1726 * Assumes interrupts are blocked. 1727 */ 1728 void 1729 wdccommandext(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1730 u_int64_t blkno, u_int16_t count) 1731 { 1732 1733 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1734 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1735 chp->channel, drive, command, (u_int32_t) blkno, count), 1736 DEBUG_FUNCS); 1737 1738 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1739 chp->wdc->select(chp,drive); 1740 1741 /* Select drive, head, and addressing mode. */ 1742 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1743 (drive << 4) | WDSD_LBA); 1744 1745 /* previous */ 1746 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1747 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1748 0, count >> 8); 1749 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1750 0, blkno >> 40); 1751 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1752 0, blkno >> 32); 1753 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1754 0, blkno >> 24); 1755 1756 /* current */ 1757 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1758 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1759 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1760 0, blkno >> 16); 1761 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1762 0, blkno >> 8); 1763 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1764 1765 /* Send command. */ 1766 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1767 return; 1768 } 1769 1770 /* 1771 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1772 * tested by the caller. 1773 */ 1774 void 1775 wdccommandshort(struct channel_softc *chp, int drive, int command) 1776 { 1777 1778 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1779 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1780 DEBUG_FUNCS); 1781 1782 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 1783 chp->wdc->select(chp,drive); 1784 1785 /* Select drive. */ 1786 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1787 WDSD_IBM | (drive << 4)); 1788 1789 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1790 } 1791 1792 /* Add a command to the queue and start controller. Must be called at splbio */ 1793 void 1794 wdc_exec_xfer(struct channel_softc *chp, struct ata_xfer *xfer) 1795 { 1796 1797 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1798 chp->channel, xfer->c_drive), DEBUG_XFERS); 1799 1800 /* complete xfer setup */ 1801 xfer->c_chp = chp; 1802 1803 /* 1804 * If we are a polled command, and the list is not empty, 1805 * we are doing a dump. Drop the list to allow the polled command 1806 * to complete, we're going to reboot soon anyway. 1807 */ 1808 if ((xfer->c_flags & C_POLL) != 0 && 1809 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) { 1810 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1811 } 1812 /* insert at the end of command list */ 1813 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1814 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1815 chp->ch_flags), DEBUG_XFERS); 1816 wdcstart(chp); 1817 } 1818 1819 struct ata_xfer * 1820 wdc_get_xfer(int flags) 1821 { 1822 struct ata_xfer *xfer; 1823 int s; 1824 1825 s = splbio(); 1826 xfer = pool_get(&wdc_xfer_pool, 1827 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1828 splx(s); 1829 if (xfer != NULL) { 1830 memset(xfer, 0, sizeof(struct ata_xfer)); 1831 } 1832 return xfer; 1833 } 1834 1835 void 1836 wdc_free_xfer(struct channel_softc *chp, struct ata_xfer *xfer) 1837 { 1838 struct wdc_softc *wdc = chp->wdc; 1839 int s; 1840 1841 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1842 (*wdc->free_hw)(chp); 1843 s = splbio(); 1844 chp->ch_flags &= ~WDCF_ACTIVE; 1845 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1846 pool_put(&wdc_xfer_pool, xfer); 1847 splx(s); 1848 } 1849 1850 /* 1851 * Kill off all pending xfers for a channel_softc. 1852 * 1853 * Must be called at splbio(). 1854 */ 1855 void 1856 wdc_kill_pending(struct channel_softc *chp) 1857 { 1858 struct ata_xfer *xfer; 1859 1860 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 1861 chp = xfer->c_chp; 1862 (*xfer->c_kill_xfer)(chp, xfer); 1863 } 1864 } 1865 1866 static void 1867 __wdcerror(struct channel_softc *chp, char *msg) 1868 { 1869 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1870 1871 if (xfer == NULL) 1872 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1873 msg); 1874 else 1875 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1876 chp->channel, xfer->c_drive, msg); 1877 } 1878 1879 /* 1880 * the bit bucket 1881 */ 1882 void 1883 wdcbit_bucket(struct channel_softc *chp, int size) 1884 { 1885 1886 for (; size >= 2; size -= 2) 1887 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1888 if (size) 1889 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1890 } 1891 1892 int 1893 wdc_addref(struct channel_softc *chp) 1894 { 1895 struct wdc_softc *wdc = chp->wdc; 1896 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1897 int s, error = 0; 1898 1899 s = splbio(); 1900 if (adapt->adapt_refcnt++ == 0 && 1901 adapt->adapt_enable != NULL) { 1902 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1903 if (error) 1904 adapt->adapt_refcnt--; 1905 } 1906 splx(s); 1907 return (error); 1908 } 1909 1910 void 1911 wdc_delref(struct channel_softc *chp) 1912 { 1913 struct wdc_softc *wdc = chp->wdc; 1914 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1915 int s; 1916 1917 s = splbio(); 1918 if (adapt->adapt_refcnt-- == 1 && 1919 adapt->adapt_enable != NULL) 1920 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1921 splx(s); 1922 } 1923 1924 void 1925 wdc_print_modes(struct channel_softc *chp) 1926 { 1927 int drive; 1928 struct ata_drive_datas *drvp; 1929 1930 for (drive = 0; drive < 2; drive++) { 1931 drvp = &chp->ch_drive[drive]; 1932 if ((drvp->drive_flags & DRIVE) == 0) 1933 continue; 1934 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1935 drvp->drv_softc->dv_xname, 1936 chp->wdc->sc_dev.dv_xname, 1937 chp->channel, drive, drvp->PIO_mode); 1938 if (drvp->drive_flags & DRIVE_DMA) 1939 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1940 if (drvp->drive_flags & DRIVE_UDMA) { 1941 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1942 if (drvp->UDMA_mode == 2) 1943 aprint_normal(" (Ultra/33)"); 1944 else if (drvp->UDMA_mode == 4) 1945 aprint_normal(" (Ultra/66)"); 1946 else if (drvp->UDMA_mode == 5) 1947 aprint_normal(" (Ultra/100)"); 1948 else if (drvp->UDMA_mode == 6) 1949 aprint_normal(" (Ultra/133)"); 1950 } 1951 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1952 aprint_normal(" (using DMA data transfers)"); 1953 aprint_normal("\n"); 1954 } 1955 } 1956
Indexes created Thu Sep 25 16:09:42 GMT 2025