wdc.c revision 1.170
1 /* $NetBSD: wdc.c,v 1.170 2004/01/03 23:59:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.170 2004/01/03 23:59:58 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, 152 int); 153 static int __wdcwait(struct wdc_channel *, int, int, int); 154 155 #define DEBUG_INTR 0x01 156 #define DEBUG_XFERS 0x02 157 #define DEBUG_STATUS 0x04 158 #define DEBUG_FUNCS 0x08 159 #define DEBUG_PROBE 0x10 160 #define DEBUG_DETACH 0x20 161 #define DEBUG_DELAY 0x40 162 #ifdef WDCDEBUG 163 int wdcdebug_mask = 0; 164 int wdc_nxfer = 0; 165 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 166 #else 167 #define WDCDEBUG_PRINT(args, level) 168 #endif 169 170 /* 171 * A queue of atabus instances, used to ensure the same bus probe order 172 * for a given hardware configuration at each boot. 173 */ 174 struct atabus_initq_head atabus_initq_head = 175 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 176 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 177 178 /* Test to see controller with at last one attached drive is there. 179 * Returns a bit for each possible drive found (0x01 for drive 0, 180 * 0x02 for drive 1). 181 * Logic: 182 * - If a status register is at 0xff, assume there is no drive here 183 * (ISA has pull-up resistors). Similarly if the status register has 184 * the value we last wrote to the bus (for IDE interfaces without pullups). 185 * If no drive at all -> return. 186 * - reset the controller, wait for it to complete (may take up to 31s !). 187 * If timeout -> return. 188 * - test ATA/ATAPI signatures. If at last one drive found -> return. 189 * - try an ATA command on the master. 190 */ 191 192 static void 193 wdc_drvprobe(struct wdc_channel *chp) 194 { 195 struct ataparams params; 196 struct wdc_softc *wdc = chp->ch_wdc; 197 u_int8_t st0 = 0, st1 = 0; 198 int i, error; 199 200 if (wdcprobe1(chp, 0) == 0) { 201 /* No drives, abort the attach here. */ 202 return; 203 } 204 205 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 206 for (i = 0; i < mstohz(3000); i++) { 207 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 208 wdc->select(chp,0); 209 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 210 WDSD_IBM); 211 delay(10); /* 400ns delay */ 212 st0 = bus_space_read_1(chp->cmd_iot, 213 chp->cmd_iohs[wd_status], 0); 214 215 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 216 wdc->select(chp,1); 217 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 218 WDSD_IBM | 0x10); 219 delay(10); /* 400ns delay */ 220 st1 = bus_space_read_1(chp->cmd_iot, 221 chp->cmd_iohs[wd_status], 0); 222 223 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 224 == 0 || 225 (st0 & WDCS_DRDY)) && 226 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 227 == 0 || 228 (st1 & WDCS_DRDY))) 229 break; 230 tsleep(¶ms, PRIBIO, "atadrdy", 1); 231 } 232 if ((st0 & WDCS_DRDY) == 0) 233 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 234 if ((st1 & WDCS_DRDY) == 0) 235 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 236 237 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 238 wdc->sc_dev.dv_xname, 239 chp->ch_channel, st0, st1), DEBUG_PROBE); 240 241 /* Wait a bit, some devices are weird just after a reset. */ 242 delay(5000); 243 244 for (i = 0; i < 2; i++) { 245 chp->ch_drive[i].chnl_softc = chp; 246 chp->ch_drive[i].drive = i; 247 /* 248 * Init error counter so that an error withing the first xfers 249 * will trigger a downgrade 250 */ 251 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 252 253 /* If controller can't do 16bit flag the drives as 32bit */ 254 if ((wdc->cap & 255 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 256 WDC_CAPABILITY_DATA32) 257 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 258 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 259 continue; 260 261 /* Shortcut in case we've been shutdown */ 262 if (chp->ch_flags & WDCF_SHUTDOWN) 263 return; 264 265 /* issue an identify, to try to detect ghosts */ 266 error = ata_get_params(&chp->ch_drive[i], 267 AT_WAIT | AT_POLL, ¶ms); 268 if (error != CMD_OK) { 269 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 270 271 /* Shortcut in case we've been shutdown */ 272 if (chp->ch_flags & WDCF_SHUTDOWN) 273 return; 274 275 error = ata_get_params(&chp->ch_drive[i], 276 AT_WAIT | AT_POLL, ¶ms); 277 } 278 if (error == CMD_OK) { 279 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 280 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 281 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 282 } else { 283 chp->ch_drive[i].drive_flags &= 284 ~(DRIVE_ATA | DRIVE_ATAPI); 285 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 286 wdc->sc_dev.dv_xname, 287 chp->ch_channel, i, error), DEBUG_PROBE); 288 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 289 continue; 290 /* 291 * Pre-ATA drive ? 292 * Test registers writability (Error register not 293 * writable, but cyllo is), then try an ATA command. 294 */ 295 if (wdc->cap & WDC_CAPABILITY_SELECT) 296 wdc->select(chp,i); 297 bus_space_write_1(chp->cmd_iot, 298 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 299 delay(10); /* 400ns delay */ 300 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 301 0, 0x58); 302 bus_space_write_1(chp->cmd_iot, 303 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 304 if (bus_space_read_1(chp->cmd_iot, 305 chp->cmd_iohs[wd_error], 0) == 0x58 || 306 bus_space_read_1(chp->cmd_iot, 307 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 308 WDCDEBUG_PRINT(("%s:%d:%d: register " 309 "writability failed\n", 310 wdc->sc_dev.dv_xname, 311 chp->ch_channel, i), DEBUG_PROBE); 312 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 313 continue; 314 } 315 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 316 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 317 wdc->sc_dev.dv_xname, 318 chp->ch_channel, i), DEBUG_PROBE); 319 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 320 continue; 321 } 322 bus_space_write_1(chp->cmd_iot, 323 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 324 delay(10); /* 400ns delay */ 325 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 326 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 327 wdc->sc_dev.dv_xname, 328 chp->ch_channel, i), DEBUG_PROBE); 329 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 330 } else { 331 chp->ch_drive[0].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 chp->ch_drive[1].drive_flags &= 334 ~(DRIVE_ATA | DRIVE_ATAPI); 335 } 336 } 337 } 338 } 339 340 void 341 atabusconfig(struct atabus_softc *atabus_sc) 342 { 343 struct wdc_channel *chp = atabus_sc->sc_chan; 344 struct wdc_softc *wdc = chp->ch_wdc; 345 int i, error, need_delref = 0; 346 struct atabus_initq *atabus_initq = NULL; 347 348 if ((error = wdc_addref(chp)) != 0) { 349 aprint_error("%s: unable to enable controller\n", 350 wdc->sc_dev.dv_xname); 351 goto out; 352 } 353 need_delref = 1; 354 355 /* Probe for the drives. */ 356 (*wdc->drv_probe)(chp); 357 358 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 359 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 360 DEBUG_PROBE); 361 362 /* If no drives, abort here */ 363 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 364 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 365 goto out; 366 367 /* Shortcut in case we've been shutdown */ 368 if (chp->ch_flags & WDCF_SHUTDOWN) 369 goto out; 370 371 /* Make sure the devices probe in atabus order to avoid jitter. */ 372 simple_lock(&atabus_interlock); 373 while(1) { 374 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 375 if (atabus_initq->atabus_sc == atabus_sc) 376 break; 377 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 378 &atabus_interlock); 379 } 380 simple_unlock(&atabus_interlock); 381 382 /* 383 * Attach an ATAPI bus, if needed. 384 */ 385 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 386 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 387 #if NATAPIBUS > 0 388 wdc_atapibus_attach(atabus_sc); 389 #else 390 /* 391 * Fake the autoconfig "not configured" message 392 */ 393 aprint_normal("atapibus at %s not configured\n", 394 wdc->sc_dev.dv_xname); 395 chp->atapibus = NULL; 396 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 397 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 398 #endif 399 } 400 401 for (i = 0; i < 2; i++) { 402 struct ata_device adev; 403 if ((chp->ch_drive[i].drive_flags & 404 (DRIVE_ATA | DRIVE_OLD)) == 0) { 405 continue; 406 } 407 memset(&adev, 0, sizeof(struct ata_device)); 408 adev.adev_bustype = &wdc_ata_bustype; 409 adev.adev_channel = chp->ch_channel; 410 adev.adev_openings = 1; 411 adev.adev_drv_data = &chp->ch_drive[i]; 412 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 413 &adev, ataprint); 414 if (chp->ata_drives[i] != NULL) 415 wdc_probe_caps(&chp->ch_drive[i]); 416 else 417 chp->ch_drive[i].drive_flags &= 418 ~(DRIVE_ATA | DRIVE_OLD); 419 } 420 421 /* now that we know the drives, the controller can set its modes */ 422 if (wdc->cap & WDC_CAPABILITY_MODE) { 423 wdc->set_modes(chp); 424 wdc_print_modes(chp); 425 } 426 #if NATARAID > 0 427 if (wdc->cap & WDC_CAPABILITY_RAID) 428 for (i = 0; i < 2; i++) 429 if (chp->ata_drives[i] != NULL) 430 ata_raid_check_component(chp->ata_drives[i]); 431 #endif /* NATARAID > 0 */ 432 433 /* 434 * reset drive_flags for unattached devices, reset state for attached 435 * ones 436 */ 437 for (i = 0; i < 2; i++) { 438 if (chp->ch_drive[i].drv_softc == NULL) 439 chp->ch_drive[i].drive_flags = 0; 440 else 441 chp->ch_drive[i].state = 0; 442 } 443 444 out: 445 if (atabus_initq == NULL) { 446 simple_lock(&atabus_interlock); 447 while(1) { 448 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 449 if (atabus_initq->atabus_sc == atabus_sc) 450 break; 451 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 452 &atabus_interlock); 453 } 454 simple_unlock(&atabus_interlock); 455 } 456 simple_lock(&atabus_interlock); 457 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 458 simple_unlock(&atabus_interlock); 459 460 free(atabus_initq, M_DEVBUF); 461 wakeup(&atabus_initq_head); 462 463 config_pending_decr(); 464 if (need_delref) 465 wdc_delref(chp); 466 } 467 468 int 469 wdcprobe(struct wdc_channel *chp) 470 { 471 472 return (wdcprobe1(chp, 1)); 473 } 474 475 static int 476 wdcprobe1(struct wdc_channel *chp, int poll) 477 { 478 struct wdc_softc *wdc = chp->ch_wdc; 479 u_int8_t st0, st1, sc, sn, cl, ch; 480 u_int8_t ret_value = 0x03; 481 u_int8_t drive; 482 int s; 483 484 /* 485 * Sanity check to see if the wdc channel responds at all. 486 */ 487 488 if (wdc == NULL || 489 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 490 491 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 492 wdc->select(chp,0); 493 494 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 495 WDSD_IBM); 496 delay(10); /* 400ns delay */ 497 st0 = bus_space_read_1(chp->cmd_iot, 498 chp->cmd_iohs[wd_status], 0); 499 500 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 501 wdc->select(chp,1); 502 503 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 504 WDSD_IBM | 0x10); 505 delay(10); /* 400ns delay */ 506 st1 = bus_space_read_1(chp->cmd_iot, 507 chp->cmd_iohs[wd_status], 0); 508 509 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 510 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 511 chp->ch_channel, st0, st1), DEBUG_PROBE); 512 513 if (st0 == 0xff || st0 == WDSD_IBM) 514 ret_value &= ~0x01; 515 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 516 ret_value &= ~0x02; 517 /* Register writability test, drive 0. */ 518 if (ret_value & 0x01) { 519 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 520 wdc->select(chp,0); 521 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 522 0, WDSD_IBM); 523 bus_space_write_1(chp->cmd_iot, 524 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 525 if (bus_space_read_1(chp->cmd_iot, 526 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 527 ret_value &= ~0x01; 528 bus_space_write_1(chp->cmd_iot, 529 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 530 if (bus_space_read_1(chp->cmd_iot, 531 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 532 ret_value &= ~0x01; 533 bus_space_write_1(chp->cmd_iot, 534 chp->cmd_iohs[wd_sector], 0, 0x01); 535 if (bus_space_read_1(chp->cmd_iot, 536 chp->cmd_iohs[wd_sector], 0) != 0x01) 537 ret_value &= ~0x01; 538 bus_space_write_1(chp->cmd_iot, 539 chp->cmd_iohs[wd_sector], 0, 0x02); 540 if (bus_space_read_1(chp->cmd_iot, 541 chp->cmd_iohs[wd_sector], 0) != 0x02) 542 ret_value &= ~0x01; 543 if (bus_space_read_1(chp->cmd_iot, 544 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 545 ret_value &= ~0x01; 546 } 547 /* Register writability test, drive 1. */ 548 if (ret_value & 0x02) { 549 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 550 wdc->select(chp,1); 551 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 552 0, WDSD_IBM | 0x10); 553 bus_space_write_1(chp->cmd_iot, 554 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 555 if (bus_space_read_1(chp->cmd_iot, 556 chp->cmd_iohs[wd_cyl_lo], 0) != 0x02) 557 ret_value &= ~0x02; 558 bus_space_write_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 560 if (bus_space_read_1(chp->cmd_iot, 561 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 562 ret_value &= ~0x02; 563 bus_space_write_1(chp->cmd_iot, 564 chp->cmd_iohs[wd_sector], 0, 0x01); 565 if (bus_space_read_1(chp->cmd_iot, 566 chp->cmd_iohs[wd_sector], 0) != 0x01) 567 ret_value &= ~0x02; 568 bus_space_write_1(chp->cmd_iot, 569 chp->cmd_iohs[wd_sector], 0, 0x02); 570 if (bus_space_read_1(chp->cmd_iot, 571 chp->cmd_iohs[wd_sector], 0) != 0x02) 572 ret_value &= ~0x02; 573 if (bus_space_read_1(chp->cmd_iot, 574 chp->cmd_iohs[wd_cyl_lo], 0) != 0x01) 575 ret_value &= ~0x02; 576 } 577 578 if (ret_value == 0) 579 return 0; 580 } 581 582 s = splbio(); 583 584 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 585 wdc->select(chp,0); 586 /* assert SRST, wait for reset to complete */ 587 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 588 delay(10); /* 400ns delay */ 589 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 590 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 591 DELAY(2000); 592 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 593 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 594 delay(10); /* 400ns delay */ 595 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 596 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 597 wdc->irqack(chp); 598 splx(s); 599 600 ret_value = __wdcwait_reset(chp, ret_value, poll); 601 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 602 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 603 ret_value), DEBUG_PROBE); 604 605 /* if reset failed, there's nothing here */ 606 if (ret_value == 0) 607 return 0; 608 609 /* 610 * Test presence of drives. First test register signatures looking 611 * for ATAPI devices. If it's not an ATAPI and reset said there may 612 * be something here assume it's ATA or OLD. Ghost will be killed 613 * later in attach routine. 614 */ 615 for (drive = 0; drive < 2; drive++) { 616 if ((ret_value & (0x01 << drive)) == 0) 617 continue; 618 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 619 wdc->select(chp,drive); 620 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 621 WDSD_IBM | (drive << 4)); 622 delay(10); /* 400ns delay */ 623 /* Save registers contents */ 624 sc = bus_space_read_1(chp->cmd_iot, 625 chp->cmd_iohs[wd_seccnt], 0); 626 sn = bus_space_read_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_sector], 0); 628 cl = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_cyl_lo], 0); 630 ch = bus_space_read_1(chp->cmd_iot, 631 chp->cmd_iohs[wd_cyl_hi], 0); 632 633 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 634 "cl=0x%x ch=0x%x\n", 635 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 636 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 637 /* 638 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 639 * we get wrong values here, so ignore it. 640 */ 641 if (cl == 0x14 && ch == 0xeb) { 642 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 643 } else { 644 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 645 if (wdc == NULL || 646 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 647 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 648 } 649 } 650 return (ret_value); 651 } 652 653 void 654 wdcattach(struct wdc_channel *chp) 655 { 656 struct wdc_softc *wdc = chp->ch_wdc; 657 static int inited = 0; 658 659 if (chp->ch_flags & WDCF_DISABLED) 660 return; 661 662 /* initialise global data */ 663 callout_init(&chp->ch_callout); 664 if (wdc->drv_probe == NULL) 665 wdc->drv_probe = wdc_drvprobe; 666 if (inited == 0) { 667 /* Initialize the ata_xfer pool. */ 668 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 669 0, 0, "wdcspl", NULL); 670 inited++; 671 } 672 TAILQ_INIT(&chp->ch_queue->queue_xfer); 673 chp->ch_queue->queue_freeze = 0; 674 675 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 676 } 677 678 int 679 wdcactivate(struct device *self, enum devact act) 680 { 681 struct wdc_softc *wdc = (struct wdc_softc *)self; 682 int s, i, error = 0; 683 684 s = splbio(); 685 switch (act) { 686 case DVACT_ACTIVATE: 687 error = EOPNOTSUPP; 688 break; 689 690 case DVACT_DEACTIVATE: 691 for (i = 0; i < wdc->nchannels; i++) { 692 error = config_deactivate(wdc->channels[i]->atabus); 693 if (error) 694 break; 695 } 696 break; 697 } 698 splx(s); 699 return (error); 700 } 701 702 int 703 wdcdetach(struct device *self, int flags) 704 { 705 struct wdc_softc *wdc = (struct wdc_softc *)self; 706 struct wdc_channel *chp; 707 int i, error = 0; 708 709 for (i = 0; i < wdc->nchannels; i++) { 710 chp = wdc->channels[i]; 711 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 712 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 713 error = config_detach(chp->atabus, flags); 714 if (error) 715 break; 716 } 717 return (error); 718 } 719 720 /* 721 * Start I/O on a controller, for the given channel. 722 * The first xfer may be not for our channel if the channel queues 723 * are shared. 724 */ 725 void 726 wdcstart(struct wdc_channel *chp) 727 { 728 struct wdc_softc *wdc = chp->ch_wdc; 729 struct ata_xfer *xfer; 730 731 #ifdef WDC_DIAGNOSTIC 732 int spl1, spl2; 733 734 spl1 = splbio(); 735 spl2 = splbio(); 736 if (spl2 != spl1) { 737 printf("wdcstart: not at splbio()\n"); 738 panic("wdcstart"); 739 } 740 splx(spl2); 741 splx(spl1); 742 #endif /* WDC_DIAGNOSTIC */ 743 744 /* is there a xfer ? */ 745 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 746 return; 747 748 /* adjust chp, in case we have a shared queue */ 749 chp = xfer->c_chp; 750 751 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 752 return; /* channel aleady active */ 753 } 754 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 755 return; /* queue froozen */ 756 } 757 #ifdef DIAGNOSTIC 758 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 759 panic("wdcstart: channel waiting for irq"); 760 #endif 761 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 762 if (!(*wdc->claim_hw)(chp, 0)) 763 return; 764 765 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 766 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 767 chp->ch_flags |= WDCF_ACTIVE; 768 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 769 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 770 chp->ch_drive[xfer->c_drive].state = 0; 771 } 772 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 773 KASSERT(xfer->c_flags & C_POLL); 774 xfer->c_start(chp, xfer); 775 } 776 777 /* restart an interrupted I/O */ 778 void 779 wdcrestart(void *v) 780 { 781 struct wdc_channel *chp = v; 782 int s; 783 784 s = splbio(); 785 wdcstart(chp); 786 splx(s); 787 } 788 789 790 /* 791 * Interrupt routine for the controller. Acknowledge the interrupt, check for 792 * errors on the current operation, mark it done if necessary, and start the 793 * next request. Also check for a partially done transfer, and continue with 794 * the next chunk if so. 795 */ 796 int 797 wdcintr(void *arg) 798 { 799 struct wdc_channel *chp = arg; 800 struct wdc_softc *wdc = chp->ch_wdc; 801 struct ata_xfer *xfer; 802 int ret; 803 804 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 805 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 806 DEBUG_INTR); 807 return (0); 808 } 809 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 810 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 811 /* try to clear the pending interrupt anyway */ 812 (void)bus_space_read_1(chp->cmd_iot, 813 chp->cmd_iohs[wd_status], 0); 814 return (0); 815 } 816 817 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 818 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 819 if (chp->ch_flags & WDCF_DMA_WAIT) { 820 wdc->dma_status = 821 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 822 xfer->c_drive, 0); 823 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 824 /* IRQ not for us, not detected by DMA engine */ 825 return 0; 826 } 827 chp->ch_flags &= ~WDCF_DMA_WAIT; 828 } 829 chp->ch_flags &= ~WDCF_IRQ_WAIT; 830 ret = xfer->c_intr(chp, xfer, 1); 831 if (ret == 0) /* irq was not for us, still waiting for irq */ 832 chp->ch_flags |= WDCF_IRQ_WAIT; 833 return (ret); 834 } 835 836 /* Put all disk in RESET state */ 837 void 838 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 839 { 840 struct wdc_channel *chp = drvp->chnl_softc; 841 struct wdc_softc *wdc = chp->ch_wdc; 842 int drive; 843 844 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 845 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 846 DEBUG_FUNCS); 847 if ((flags & AT_POLL) == 0) { 848 if (chp->ch_flags & WDCF_TH_RESET) { 849 /* no need to schedule a reset more than one time */ 850 return; 851 } 852 chp->ch_flags |= WDCF_TH_RESET; 853 chp->ch_queue->queue_freeze++; 854 wakeup(&chp->ch_thread); 855 return; 856 } 857 (void) wdcreset(chp, RESET_POLL); 858 for (drive = 0; drive < 2; drive++) { 859 chp->ch_drive[drive].state = 0; 860 } 861 } 862 863 int 864 wdcreset(struct wdc_channel *chp, int poll) 865 { 866 struct wdc_softc *wdc = chp->ch_wdc; 867 int drv_mask1, drv_mask2; 868 int s = 0; 869 870 if (wdc->cap & WDC_CAPABILITY_SELECT) 871 wdc->select(chp,0); 872 if (poll != RESET_SLEEP) 873 s = splbio(); 874 /* master */ 875 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 876 delay(10); /* 400ns delay */ 877 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 878 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 879 delay(2000); 880 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 881 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 882 WDCTL_4BIT | WDCTL_IDS); 883 delay(10); /* 400ns delay */ 884 if (poll != RESET_SLEEP) { 885 if (wdc->cap & WDC_CAPABILITY_IRQACK) 886 wdc->irqack(chp); 887 splx(s); 888 } 889 890 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 891 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 892 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 893 (poll == RESET_SLEEP) ? 0 : 1); 894 if (drv_mask2 != drv_mask1) { 895 printf("%s channel %d: reset failed for", 896 wdc->sc_dev.dv_xname, chp->ch_channel); 897 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 898 printf(" drive 0"); 899 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 900 printf(" drive 1"); 901 printf("\n"); 902 } 903 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 904 return (drv_mask1 != drv_mask2) ? 1 : 0; 905 } 906 907 static int 908 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 909 { 910 struct wdc_softc *wdc = chp->ch_wdc; 911 int timeout, nloop; 912 u_int8_t st0 = 0, st1 = 0; 913 #ifdef WDCDEBUG 914 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 915 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 916 #endif 917 918 if (poll) 919 nloop = WDCNDELAY_RST; 920 else 921 nloop = WDC_RESET_WAIT * hz / 1000; 922 /* wait for BSY to deassert */ 923 for (timeout = 0; timeout < nloop; timeout++) { 924 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 925 wdc->select(chp,0); 926 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 927 WDSD_IBM); /* master */ 928 delay(10); 929 st0 = bus_space_read_1(chp->cmd_iot, 930 chp->cmd_iohs[wd_status], 0); 931 #ifdef WDCDEBUG 932 sc0 = bus_space_read_1(chp->cmd_iot, 933 chp->cmd_iohs[wd_seccnt], 0); 934 sn0 = bus_space_read_1(chp->cmd_iot, 935 chp->cmd_iohs[wd_sector], 0); 936 cl0 = bus_space_read_1(chp->cmd_iot, 937 chp->cmd_iohs[wd_cyl_lo], 0); 938 ch0 = bus_space_read_1(chp->cmd_iot, 939 chp->cmd_iohs[wd_cyl_hi], 0); 940 #endif 941 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 942 wdc->select(chp,1); 943 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 944 WDSD_IBM | 0x10); /* slave */ 945 delay(10); 946 st1 = bus_space_read_1(chp->cmd_iot, 947 chp->cmd_iohs[wd_status], 0); 948 #ifdef WDCDEBUG 949 sc1 = bus_space_read_1(chp->cmd_iot, 950 chp->cmd_iohs[wd_seccnt], 0); 951 sn1 = bus_space_read_1(chp->cmd_iot, 952 chp->cmd_iohs[wd_sector], 0); 953 cl1 = bus_space_read_1(chp->cmd_iot, 954 chp->cmd_iohs[wd_cyl_lo], 0); 955 ch1 = bus_space_read_1(chp->cmd_iot, 956 chp->cmd_iohs[wd_cyl_hi], 0); 957 #endif 958 959 if ((drv_mask & 0x01) == 0) { 960 /* no master */ 961 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 962 /* No master, slave is ready, it's done */ 963 goto end; 964 } 965 } else if ((drv_mask & 0x02) == 0) { 966 /* no slave */ 967 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 968 /* No slave, master is ready, it's done */ 969 goto end; 970 } 971 } else { 972 /* Wait for both master and slave to be ready */ 973 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 974 goto end; 975 } 976 } 977 if (poll) 978 delay(WDCDELAY); 979 else 980 tsleep(&nloop, PRIBIO, "atarst", 1); 981 } 982 /* Reset timed out. Maybe it's because drv_mask was not right */ 983 if (st0 & WDCS_BSY) 984 drv_mask &= ~0x01; 985 if (st1 & WDCS_BSY) 986 drv_mask &= ~0x02; 987 end: 988 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 989 "cl=0x%x ch=0x%x\n", 990 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 991 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 992 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 993 "cl=0x%x ch=0x%x\n", 994 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 995 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 996 997 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 998 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 999 st0, st1), DEBUG_PROBE); 1000 1001 return drv_mask; 1002 } 1003 1004 /* 1005 * Wait for a drive to be !BSY, and have mask in its status register. 1006 * return -1 for a timeout after "timeout" ms. 1007 */ 1008 static int 1009 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1010 { 1011 struct wdc_softc *wdc = chp->ch_wdc; 1012 u_char status; 1013 int time = 0; 1014 1015 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1016 wdc->sc_dev.dv_xname : "none", 1017 chp->ch_channel), DEBUG_STATUS); 1018 chp->ch_error = 0; 1019 1020 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1021 1022 for (;;) { 1023 chp->ch_status = status = 1024 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1025 if ((status & (WDCS_BSY | mask)) == bits) 1026 break; 1027 if (++time > timeout) { 1028 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1029 "status %x error %x (mask 0x%x bits 0x%x)\n", 1030 time, status, 1031 bus_space_read_1(chp->cmd_iot, 1032 chp->cmd_iohs[wd_error], 0), mask, bits), 1033 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1034 return(WDCWAIT_TOUT); 1035 } 1036 delay(WDCDELAY); 1037 } 1038 #ifdef WDCDEBUG 1039 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1040 printf("__wdcwait: did busy-wait, time=%d\n", time); 1041 #endif 1042 if (status & WDCS_ERR) 1043 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1044 chp->cmd_iohs[wd_error], 0); 1045 #ifdef WDCNDELAY_DEBUG 1046 /* After autoconfig, there should be no long delays. */ 1047 if (!cold && time > WDCNDELAY_DEBUG) { 1048 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1049 if (xfer == NULL) 1050 printf("%s channel %d: warning: busy-wait took %dus\n", 1051 wdc->sc_dev.dv_xname, chp->ch_channel, 1052 WDCDELAY * time); 1053 else 1054 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1055 wdc->sc_dev.dv_xname, chp->ch_channel, 1056 xfer->drive, 1057 WDCDELAY * time); 1058 } 1059 #endif 1060 return(WDCWAIT_OK); 1061 } 1062 1063 /* 1064 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1065 * thread if possible 1066 */ 1067 int 1068 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1069 { 1070 int error, i, timeout_hz = mstohz(timeout); 1071 1072 if (timeout_hz == 0 || 1073 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1074 error = __wdcwait(chp, mask, bits, timeout); 1075 else { 1076 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1077 if (error != 0) { 1078 if ((chp->ch_flags & WDCF_TH_RUN) || 1079 (flags & AT_WAIT)) { 1080 /* 1081 * we're running in the channel thread 1082 * or some userland thread context 1083 */ 1084 for (i = 0; i < timeout_hz; i++) { 1085 if (__wdcwait(chp, mask, bits, 1086 WDCDELAY_POLL) == 0) { 1087 error = 0; 1088 break; 1089 } 1090 tsleep(&chp, PRIBIO, "atapoll", 1); 1091 } 1092 } else { 1093 /* 1094 * we're probably in interrupt context, 1095 * ask the thread to come back here 1096 */ 1097 #ifdef DIAGNOSTIC 1098 if (chp->ch_queue->queue_freeze > 0) 1099 panic("wdcwait: queue_freeze"); 1100 #endif 1101 chp->ch_queue->queue_freeze++; 1102 wakeup(&chp->ch_thread); 1103 return(WDCWAIT_THR); 1104 } 1105 } 1106 } 1107 return (error); 1108 } 1109 1110 1111 /* 1112 * Busy-wait for DMA to complete 1113 */ 1114 int 1115 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1116 { 1117 struct wdc_softc *wdc = chp->ch_wdc; 1118 int time; 1119 1120 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1121 wdc->dma_status = 1122 (*wdc->dma_finish)(wdc->dma_arg, 1123 chp->ch_channel, xfer->c_drive, 0); 1124 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1125 return 0; 1126 delay(WDCDELAY); 1127 } 1128 /* timeout, force a DMA halt */ 1129 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1130 chp->ch_channel, xfer->c_drive, 1); 1131 return 1; 1132 } 1133 1134 void 1135 wdctimeout(void *arg) 1136 { 1137 struct wdc_channel *chp = (struct wdc_channel *)arg; 1138 struct wdc_softc *wdc = chp->ch_wdc; 1139 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1140 int s; 1141 1142 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1143 1144 s = splbio(); 1145 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1146 __wdcerror(chp, "lost interrupt"); 1147 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1148 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1149 xfer->c_bcount, 1150 xfer->c_skip); 1151 if (chp->ch_flags & WDCF_DMA_WAIT) { 1152 wdc->dma_status = 1153 (*wdc->dma_finish)(wdc->dma_arg, 1154 chp->ch_channel, xfer->c_drive, 1); 1155 chp->ch_flags &= ~WDCF_DMA_WAIT; 1156 } 1157 /* 1158 * Call the interrupt routine. If we just missed an interrupt, 1159 * it will do what's needed. Else, it will take the needed 1160 * action (reset the device). 1161 * Before that we need to reinstall the timeout callback, 1162 * in case it will miss another irq while in this transfer 1163 * We arbitray chose it to be 1s 1164 */ 1165 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1166 xfer->c_flags |= C_TIMEOU; 1167 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1168 xfer->c_intr(chp, xfer, 1); 1169 } else 1170 __wdcerror(chp, "missing untimeout"); 1171 splx(s); 1172 } 1173 1174 /* 1175 * Probe drive's capabilities, for use by the controller later 1176 * Assumes drvp points to an existing drive. 1177 * XXX this should be a controller-indep function 1178 */ 1179 void 1180 wdc_probe_caps(struct ata_drive_datas *drvp) 1181 { 1182 struct ataparams params, params2; 1183 struct wdc_channel *chp = drvp->chnl_softc; 1184 struct wdc_softc *wdc = chp->ch_wdc; 1185 struct device *drv_dev = drvp->drv_softc; 1186 int i, printed; 1187 char *sep = ""; 1188 int cf_flags; 1189 1190 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1191 /* IDENTIFY failed. Can't tell more about the device */ 1192 return; 1193 } 1194 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1195 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1196 /* 1197 * Controller claims 16 and 32 bit transfers. 1198 * Re-do an IDENTIFY with 32-bit transfers, 1199 * and compare results. 1200 */ 1201 drvp->drive_flags |= DRIVE_CAP32; 1202 ata_get_params(drvp, AT_WAIT, ¶ms2); 1203 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1204 /* Not good. fall back to 16bits */ 1205 drvp->drive_flags &= ~DRIVE_CAP32; 1206 } else { 1207 aprint_normal("%s: 32-bit data port\n", 1208 drv_dev->dv_xname); 1209 } 1210 } 1211 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1212 if (params.atap_ata_major > 0x01 && 1213 params.atap_ata_major != 0xffff) { 1214 for (i = 14; i > 0; i--) { 1215 if (params.atap_ata_major & (1 << i)) { 1216 aprint_normal("%s: ATA version %d\n", 1217 drv_dev->dv_xname, i); 1218 drvp->ata_vers = i; 1219 break; 1220 } 1221 } 1222 } 1223 #endif 1224 1225 /* An ATAPI device is at last PIO mode 3 */ 1226 if (drvp->drive_flags & DRIVE_ATAPI) 1227 drvp->PIO_mode = 3; 1228 1229 /* 1230 * It's not in the specs, but it seems that some drive 1231 * returns 0xffff in atap_extensions when this field is invalid 1232 */ 1233 if (params.atap_extensions != 0xffff && 1234 (params.atap_extensions & WDC_EXT_MODES)) { 1235 printed = 0; 1236 /* 1237 * XXX some drives report something wrong here (they claim to 1238 * support PIO mode 8 !). As mode is coded on 3 bits in 1239 * SET FEATURE, limit it to 7 (so limit i to 4). 1240 * If higher mode than 7 is found, abort. 1241 */ 1242 for (i = 7; i >= 0; i--) { 1243 if ((params.atap_piomode_supp & (1 << i)) == 0) 1244 continue; 1245 if (i > 4) 1246 return; 1247 /* 1248 * See if mode is accepted. 1249 * If the controller can't set its PIO mode, 1250 * assume the defaults are good, so don't try 1251 * to set it 1252 */ 1253 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1254 /* 1255 * It's OK to pool here, it's fast enouth 1256 * to not bother waiting for interrupt 1257 */ 1258 if (ata_set_mode(drvp, 0x08 | (i + 3), 1259 AT_WAIT) != CMD_OK) 1260 continue; 1261 if (!printed) { 1262 aprint_normal("%s: drive supports PIO mode %d", 1263 drv_dev->dv_xname, i + 3); 1264 sep = ","; 1265 printed = 1; 1266 } 1267 /* 1268 * If controller's driver can't set its PIO mode, 1269 * get the highter one for the drive. 1270 */ 1271 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1272 wdc->PIO_cap >= i + 3) { 1273 drvp->PIO_mode = i + 3; 1274 drvp->PIO_cap = i + 3; 1275 break; 1276 } 1277 } 1278 if (!printed) { 1279 /* 1280 * We didn't find a valid PIO mode. 1281 * Assume the values returned for DMA are buggy too 1282 */ 1283 return; 1284 } 1285 drvp->drive_flags |= DRIVE_MODE; 1286 printed = 0; 1287 for (i = 7; i >= 0; i--) { 1288 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1289 continue; 1290 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1291 (wdc->cap & WDC_CAPABILITY_MODE)) 1292 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1293 != CMD_OK) 1294 continue; 1295 if (!printed) { 1296 aprint_normal("%s DMA mode %d", sep, i); 1297 sep = ","; 1298 printed = 1; 1299 } 1300 if (wdc->cap & WDC_CAPABILITY_DMA) { 1301 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1302 wdc->DMA_cap < i) 1303 continue; 1304 drvp->DMA_mode = i; 1305 drvp->DMA_cap = i; 1306 drvp->drive_flags |= DRIVE_DMA; 1307 } 1308 break; 1309 } 1310 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1311 printed = 0; 1312 for (i = 7; i >= 0; i--) { 1313 if ((params.atap_udmamode_supp & (1 << i)) 1314 == 0) 1315 continue; 1316 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1317 (wdc->cap & WDC_CAPABILITY_UDMA)) 1318 if (ata_set_mode(drvp, 0x40 | i, 1319 AT_WAIT) != CMD_OK) 1320 continue; 1321 if (!printed) { 1322 aprint_normal("%s Ultra-DMA mode %d", 1323 sep, i); 1324 if (i == 2) 1325 aprint_normal(" (Ultra/33)"); 1326 else if (i == 4) 1327 aprint_normal(" (Ultra/66)"); 1328 else if (i == 5) 1329 aprint_normal(" (Ultra/100)"); 1330 else if (i == 6) 1331 aprint_normal(" (Ultra/133)"); 1332 sep = ","; 1333 printed = 1; 1334 } 1335 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1336 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1337 wdc->UDMA_cap < i) 1338 continue; 1339 drvp->UDMA_mode = i; 1340 drvp->UDMA_cap = i; 1341 drvp->drive_flags |= DRIVE_UDMA; 1342 } 1343 break; 1344 } 1345 } 1346 aprint_normal("\n"); 1347 } 1348 1349 /* Try to guess ATA version here, if it didn't get reported */ 1350 if (drvp->ata_vers == 0) { 1351 if (drvp->drive_flags & DRIVE_UDMA) 1352 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1353 else if (drvp->PIO_cap > 2) 1354 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1355 } 1356 cf_flags = drv_dev->dv_cfdata->cf_flags; 1357 if (cf_flags & ATA_CONFIG_PIO_SET) { 1358 drvp->PIO_mode = 1359 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1360 drvp->drive_flags |= DRIVE_MODE; 1361 } 1362 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1363 /* don't care about DMA modes */ 1364 return; 1365 } 1366 if (cf_flags & ATA_CONFIG_DMA_SET) { 1367 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1368 ATA_CONFIG_DMA_DISABLE) { 1369 drvp->drive_flags &= ~DRIVE_DMA; 1370 } else { 1371 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1372 ATA_CONFIG_DMA_OFF; 1373 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1374 } 1375 } 1376 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1377 /* don't care about UDMA modes */ 1378 return; 1379 } 1380 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1381 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1382 ATA_CONFIG_UDMA_DISABLE) { 1383 drvp->drive_flags &= ~DRIVE_UDMA; 1384 } else { 1385 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1386 ATA_CONFIG_UDMA_OFF; 1387 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1388 } 1389 } 1390 } 1391 1392 /* 1393 * downgrade the transfer mode of a drive after an error. return 1 if 1394 * downgrade was possible, 0 otherwise. 1395 */ 1396 int 1397 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1398 { 1399 struct wdc_channel *chp = drvp->chnl_softc; 1400 struct wdc_softc *wdc = chp->ch_wdc; 1401 struct device *drv_dev = drvp->drv_softc; 1402 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1403 1404 /* if drive or controller don't know its mode, we can't do much */ 1405 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1406 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1407 return 0; 1408 /* current drive mode was set by a config flag, let it this way */ 1409 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1410 (cf_flags & ATA_CONFIG_DMA_SET) || 1411 (cf_flags & ATA_CONFIG_UDMA_SET)) 1412 return 0; 1413 1414 /* 1415 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1416 * Maybe we didn't properly notice the cable type 1417 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1418 * It helps in some cases. 1419 */ 1420 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1421 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1422 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1423 drv_dev->dv_xname, drvp->UDMA_mode); 1424 } 1425 1426 /* 1427 * If we were using ultra-DMA, don't downgrade to multiword DMA 1428 * if we noticed a CRC error. It has been noticed that CRC errors 1429 * in ultra-DMA lead to silent data corruption in multiword DMA. 1430 * Data corruption is less likely to occur in PIO mode. 1431 */ 1432 else if ((drvp->drive_flags & DRIVE_UDMA) && 1433 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1434 drvp->drive_flags &= ~DRIVE_UDMA; 1435 drvp->drive_flags |= DRIVE_DMA; 1436 drvp->DMA_mode = drvp->DMA_cap; 1437 printf("%s: transfer error, downgrading to DMA mode %d\n", 1438 drv_dev->dv_xname, drvp->DMA_mode); 1439 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1440 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1441 drvp->PIO_mode = drvp->PIO_cap; 1442 printf("%s: transfer error, downgrading to PIO mode %d\n", 1443 drv_dev->dv_xname, drvp->PIO_mode); 1444 } else /* already using PIO, can't downgrade */ 1445 return 0; 1446 1447 wdc->set_modes(chp); 1448 wdc_print_modes(chp); 1449 /* reset the channel, which will shedule all drives for setup */ 1450 wdc_reset_channel(drvp, flags); 1451 return 1; 1452 } 1453 1454 int 1455 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1456 { 1457 struct wdc_channel *chp = drvp->chnl_softc; 1458 struct wdc_softc *wdc = chp->ch_wdc; 1459 struct ata_xfer *xfer; 1460 int s, ret; 1461 1462 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1463 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1464 DEBUG_FUNCS); 1465 1466 /* set up an xfer and queue. Wait for completion */ 1467 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1468 WDC_NOSLEEP); 1469 if (xfer == NULL) { 1470 return WDC_TRY_AGAIN; 1471 } 1472 1473 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1474 wdc_c->flags |= AT_POLL; 1475 if (wdc_c->flags & AT_POLL) 1476 xfer->c_flags |= C_POLL; 1477 xfer->c_drive = drvp->drive; 1478 xfer->c_databuf = wdc_c->data; 1479 xfer->c_bcount = wdc_c->bcount; 1480 xfer->c_cmd = wdc_c; 1481 xfer->c_start = __wdccommand_start; 1482 xfer->c_intr = __wdccommand_intr; 1483 xfer->c_kill_xfer = __wdccommand_done; 1484 1485 s = splbio(); 1486 wdc_exec_xfer(chp, xfer); 1487 #ifdef DIAGNOSTIC 1488 if ((wdc_c->flags & AT_POLL) != 0 && 1489 (wdc_c->flags & AT_DONE) == 0) 1490 panic("wdc_exec_command: polled command not done"); 1491 #endif 1492 if (wdc_c->flags & AT_DONE) { 1493 ret = WDC_COMPLETE; 1494 } else { 1495 if (wdc_c->flags & AT_WAIT) { 1496 while ((wdc_c->flags & AT_DONE) == 0) { 1497 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1498 } 1499 ret = WDC_COMPLETE; 1500 } else { 1501 ret = WDC_QUEUED; 1502 } 1503 } 1504 splx(s); 1505 return ret; 1506 } 1507 1508 static void 1509 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1510 { 1511 struct wdc_softc *wdc = chp->ch_wdc; 1512 int drive = xfer->c_drive; 1513 struct wdc_command *wdc_c = xfer->c_cmd; 1514 1515 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1516 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1517 DEBUG_FUNCS); 1518 1519 if (wdc->cap & WDC_CAPABILITY_SELECT) 1520 wdc->select(chp,drive); 1521 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1522 WDSD_IBM | (drive << 4)); 1523 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1524 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1525 case WDCWAIT_OK: 1526 break; 1527 case WDCWAIT_TOUT: 1528 wdc_c->flags |= AT_TIMEOU; 1529 __wdccommand_done(chp, xfer); 1530 return; 1531 case WDCWAIT_THR: 1532 return; 1533 } 1534 if (wdc_c->flags & AT_POLL) { 1535 /* polled command, disable interrupts */ 1536 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1537 WDCTL_4BIT | WDCTL_IDS); 1538 } 1539 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1540 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1541 1542 if ((wdc_c->flags & AT_POLL) == 0) { 1543 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1544 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1545 wdctimeout, chp); 1546 return; 1547 } 1548 /* 1549 * Polled command. Wait for drive ready or drq. Done in intr(). 1550 * Wait for at last 400ns for status bit to be valid. 1551 */ 1552 delay(10); /* 400ns delay */ 1553 __wdccommand_intr(chp, xfer, 0); 1554 } 1555 1556 static int 1557 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1558 { 1559 struct wdc_softc *wdc = chp->ch_wdc; 1560 struct wdc_command *wdc_c = xfer->c_cmd; 1561 int bcount = wdc_c->bcount; 1562 char *data = wdc_c->data; 1563 int wflags; 1564 1565 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1566 /* both wait and poll, we can tsleep here */ 1567 wflags = AT_WAIT | AT_POLL; 1568 } else { 1569 wflags = AT_POLL; 1570 } 1571 1572 again: 1573 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1574 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1575 DEBUG_INTR); 1576 /* 1577 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1578 * Reselect again, it doesn't hurt for others commands, and the time 1579 * penalty for the extra regiter write is acceptable, 1580 * wdc_exec_command() isn't called often (mosly for autoconfig) 1581 */ 1582 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1583 WDSD_IBM | (xfer->c_drive << 4)); 1584 if ((wdc_c->flags & AT_XFDONE) != 0) { 1585 /* 1586 * We have completed a data xfer. The drive should now be 1587 * in its initial state 1588 */ 1589 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1590 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1591 wflags) == WDCWAIT_TOUT) { 1592 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1593 return 0; /* IRQ was not for us */ 1594 wdc_c->flags |= AT_TIMEOU; 1595 } 1596 goto out; 1597 } 1598 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1599 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1600 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1601 return 0; /* IRQ was not for us */ 1602 wdc_c->flags |= AT_TIMEOU; 1603 goto out; 1604 } 1605 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1606 wdc->irqack(chp); 1607 if (wdc_c->flags & AT_READ) { 1608 if ((chp->ch_status & WDCS_DRQ) == 0) { 1609 wdc_c->flags |= AT_TIMEOU; 1610 goto out; 1611 } 1612 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1613 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1614 0, (u_int32_t*)data, bcount >> 2); 1615 data += bcount & 0xfffffffc; 1616 bcount = bcount & 0x03; 1617 } 1618 if (bcount > 0) 1619 bus_space_read_multi_2(chp->cmd_iot, 1620 chp->cmd_iohs[wd_data], 0, 1621 (u_int16_t *)data, bcount >> 1); 1622 /* at this point the drive should be in its initial state */ 1623 wdc_c->flags |= AT_XFDONE; 1624 /* XXX should read status register here ? */ 1625 } else if (wdc_c->flags & AT_WRITE) { 1626 if ((chp->ch_status & WDCS_DRQ) == 0) { 1627 wdc_c->flags |= AT_TIMEOU; 1628 goto out; 1629 } 1630 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1631 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1632 0, (u_int32_t*)data, bcount >> 2); 1633 data += bcount & 0xfffffffc; 1634 bcount = bcount & 0x03; 1635 } 1636 if (bcount > 0) 1637 bus_space_write_multi_2(chp->cmd_iot, 1638 chp->cmd_iohs[wd_data], 0, 1639 (u_int16_t *)data, bcount >> 1); 1640 wdc_c->flags |= AT_XFDONE; 1641 if ((wdc_c->flags & AT_POLL) == 0) { 1642 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1643 callout_reset(&chp->ch_callout, 1644 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1645 return 1; 1646 } else { 1647 goto again; 1648 } 1649 } 1650 out: 1651 __wdccommand_done(chp, xfer); 1652 return 1; 1653 } 1654 1655 static void 1656 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1657 { 1658 struct wdc_softc *wdc = chp->ch_wdc; 1659 struct wdc_command *wdc_c = xfer->c_cmd; 1660 1661 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1662 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1663 DEBUG_FUNCS); 1664 1665 callout_stop(&chp->ch_callout); 1666 1667 if (chp->ch_status & WDCS_DWF) 1668 wdc_c->flags |= AT_DF; 1669 if (chp->ch_status & WDCS_ERR) { 1670 wdc_c->flags |= AT_ERROR; 1671 wdc_c->r_error = chp->ch_error; 1672 } 1673 wdc_c->flags |= AT_DONE; 1674 if ((wdc_c->flags & AT_READREG) != 0 && 1675 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1676 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1677 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1678 chp->cmd_iohs[wd_sdh], 0); 1679 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1680 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1681 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1682 chp->cmd_iohs[wd_cyl_lo], 0); 1683 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1684 chp->cmd_iohs[wd_sector], 0); 1685 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1686 chp->cmd_iohs[wd_seccnt], 0); 1687 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1688 chp->cmd_iohs[wd_error], 0); 1689 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1690 chp->cmd_iohs[wd_precomp], 0); 1691 } 1692 1693 if (wdc_c->flags & AT_POLL) { 1694 /* enable interrupts */ 1695 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1696 WDCTL_4BIT); 1697 } 1698 wdc_free_xfer(chp, xfer); 1699 if (wdc_c->flags & AT_WAIT) 1700 wakeup(wdc_c); 1701 else if (wdc_c->callback) 1702 wdc_c->callback(wdc_c->callback_arg); 1703 wdcstart(chp); 1704 return; 1705 } 1706 1707 /* 1708 * Send a command. The drive should be ready. 1709 * Assumes interrupts are blocked. 1710 */ 1711 void 1712 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1713 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1714 u_int8_t precomp) 1715 { 1716 struct wdc_softc *wdc = chp->ch_wdc; 1717 1718 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1719 "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname, 1720 chp->ch_channel, drive, command, cylin, head, sector, count, 1721 precomp), DEBUG_FUNCS); 1722 1723 if (wdc->cap & WDC_CAPABILITY_SELECT) 1724 wdc->select(chp,drive); 1725 1726 /* Select drive, head, and addressing mode. */ 1727 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1728 WDSD_IBM | (drive << 4) | head); 1729 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1730 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1731 precomp); 1732 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1733 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1734 0, cylin >> 8); 1735 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1736 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1737 1738 /* Send command. */ 1739 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1740 return; 1741 } 1742 1743 /* 1744 * Send a 48-bit addressing command. The drive should be ready. 1745 * Assumes interrupts are blocked. 1746 */ 1747 void 1748 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1749 u_int64_t blkno, u_int16_t count) 1750 { 1751 struct wdc_softc *wdc = chp->ch_wdc; 1752 1753 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1754 "count=%d\n", wdc->sc_dev.dv_xname, 1755 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1756 DEBUG_FUNCS); 1757 1758 if (wdc->cap & WDC_CAPABILITY_SELECT) 1759 wdc->select(chp,drive); 1760 1761 /* Select drive, head, and addressing mode. */ 1762 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1763 (drive << 4) | WDSD_LBA); 1764 1765 /* previous */ 1766 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1767 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1768 0, count >> 8); 1769 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1770 0, blkno >> 40); 1771 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1772 0, blkno >> 32); 1773 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1774 0, blkno >> 24); 1775 1776 /* current */ 1777 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1778 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1779 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1780 0, blkno >> 16); 1781 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1782 0, blkno >> 8); 1783 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1784 1785 /* Send command. */ 1786 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1787 return; 1788 } 1789 1790 /* 1791 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1792 * tested by the caller. 1793 */ 1794 void 1795 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1796 { 1797 struct wdc_softc *wdc = chp->ch_wdc; 1798 1799 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1800 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1801 DEBUG_FUNCS); 1802 1803 if (wdc->cap & WDC_CAPABILITY_SELECT) 1804 wdc->select(chp,drive); 1805 1806 /* Select drive. */ 1807 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1808 WDSD_IBM | (drive << 4)); 1809 1810 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1811 } 1812 1813 /* Add a command to the queue and start controller. Must be called at splbio */ 1814 void 1815 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1816 { 1817 1818 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1819 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 1820 1821 /* complete xfer setup */ 1822 xfer->c_chp = chp; 1823 1824 /* 1825 * If we are a polled command, and the list is not empty, 1826 * we are doing a dump. Drop the list to allow the polled command 1827 * to complete, we're going to reboot soon anyway. 1828 */ 1829 if ((xfer->c_flags & C_POLL) != 0 && 1830 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) { 1831 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1832 } 1833 /* insert at the end of command list */ 1834 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1835 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1836 chp->ch_flags), DEBUG_XFERS); 1837 wdcstart(chp); 1838 } 1839 1840 struct ata_xfer * 1841 wdc_get_xfer(int flags) 1842 { 1843 struct ata_xfer *xfer; 1844 int s; 1845 1846 s = splbio(); 1847 xfer = pool_get(&wdc_xfer_pool, 1848 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1849 splx(s); 1850 if (xfer != NULL) { 1851 memset(xfer, 0, sizeof(struct ata_xfer)); 1852 } 1853 return xfer; 1854 } 1855 1856 void 1857 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1858 { 1859 struct wdc_softc *wdc = chp->ch_wdc; 1860 int s; 1861 1862 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1863 (*wdc->free_hw)(chp); 1864 s = splbio(); 1865 chp->ch_flags &= ~WDCF_ACTIVE; 1866 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1867 pool_put(&wdc_xfer_pool, xfer); 1868 splx(s); 1869 } 1870 1871 /* 1872 * Kill off all pending xfers for a wdc_channel. 1873 * 1874 * Must be called at splbio(). 1875 */ 1876 void 1877 wdc_kill_pending(struct wdc_channel *chp) 1878 { 1879 struct ata_xfer *xfer; 1880 1881 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 1882 chp = xfer->c_chp; 1883 (*xfer->c_kill_xfer)(chp, xfer); 1884 } 1885 } 1886 1887 static void 1888 __wdcerror(struct wdc_channel *chp, char *msg) 1889 { 1890 struct wdc_softc *wdc = chp->ch_wdc; 1891 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1892 1893 if (xfer == NULL) 1894 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 1895 msg); 1896 else 1897 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 1898 chp->ch_channel, xfer->c_drive, msg); 1899 } 1900 1901 /* 1902 * the bit bucket 1903 */ 1904 void 1905 wdcbit_bucket(struct wdc_channel *chp, int size) 1906 { 1907 1908 for (; size >= 2; size -= 2) 1909 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1910 if (size) 1911 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1912 } 1913 1914 int 1915 wdc_addref(struct wdc_channel *chp) 1916 { 1917 struct wdc_softc *wdc = chp->ch_wdc; 1918 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1919 int s, error = 0; 1920 1921 s = splbio(); 1922 if (adapt->adapt_refcnt++ == 0 && 1923 adapt->adapt_enable != NULL) { 1924 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 1925 if (error) 1926 adapt->adapt_refcnt--; 1927 } 1928 splx(s); 1929 return (error); 1930 } 1931 1932 void 1933 wdc_delref(struct wdc_channel *chp) 1934 { 1935 struct wdc_softc *wdc = chp->ch_wdc; 1936 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 1937 int s; 1938 1939 s = splbio(); 1940 if (adapt->adapt_refcnt-- == 1 && 1941 adapt->adapt_enable != NULL) 1942 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 1943 splx(s); 1944 } 1945 1946 void 1947 wdc_print_modes(struct wdc_channel *chp) 1948 { 1949 struct wdc_softc *wdc = chp->ch_wdc; 1950 int drive; 1951 struct ata_drive_datas *drvp; 1952 1953 for (drive = 0; drive < 2; drive++) { 1954 drvp = &chp->ch_drive[drive]; 1955 if ((drvp->drive_flags & DRIVE) == 0) 1956 continue; 1957 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 1958 drvp->drv_softc->dv_xname, 1959 wdc->sc_dev.dv_xname, 1960 chp->ch_channel, drive, drvp->PIO_mode); 1961 if (drvp->drive_flags & DRIVE_DMA) 1962 aprint_normal(", DMA mode %d", drvp->DMA_mode); 1963 if (drvp->drive_flags & DRIVE_UDMA) { 1964 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 1965 if (drvp->UDMA_mode == 2) 1966 aprint_normal(" (Ultra/33)"); 1967 else if (drvp->UDMA_mode == 4) 1968 aprint_normal(" (Ultra/66)"); 1969 else if (drvp->UDMA_mode == 5) 1970 aprint_normal(" (Ultra/100)"); 1971 else if (drvp->UDMA_mode == 6) 1972 aprint_normal(" (Ultra/133)"); 1973 } 1974 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1975 aprint_normal(" (using DMA data transfers)"); 1976 aprint_normal("\n"); 1977 } 1978 } 1979
Indexes created Wed Sep 24 05:09:52 GMT 2025