wdc.c revision 1.174
1 /* $NetBSD: wdc.c,v 1.174 2004/05/15 17:15:09 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.174 2004/05/15 17:15:09 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, 152 int); 153 static int __wdcwait(struct wdc_channel *, int, int, int); 154 155 #define DEBUG_INTR 0x01 156 #define DEBUG_XFERS 0x02 157 #define DEBUG_STATUS 0x04 158 #define DEBUG_FUNCS 0x08 159 #define DEBUG_PROBE 0x10 160 #define DEBUG_DETACH 0x20 161 #define DEBUG_DELAY 0x40 162 #ifdef WDCDEBUG 163 int wdcdebug_mask = 0; 164 int wdc_nxfer = 0; 165 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 166 #else 167 #define WDCDEBUG_PRINT(args, level) 168 #endif 169 170 /* 171 * A queue of atabus instances, used to ensure the same bus probe order 172 * for a given hardware configuration at each boot. 173 */ 174 struct atabus_initq_head atabus_initq_head = 175 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 176 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 177 178 /* Test to see controller with at last one attached drive is there. 179 * Returns a bit for each possible drive found (0x01 for drive 0, 180 * 0x02 for drive 1). 181 * Logic: 182 * - If a status register is at 0xff, assume there is no drive here 183 * (ISA has pull-up resistors). Similarly if the status register has 184 * the value we last wrote to the bus (for IDE interfaces without pullups). 185 * If no drive at all -> return. 186 * - reset the controller, wait for it to complete (may take up to 31s !). 187 * If timeout -> return. 188 * - test ATA/ATAPI signatures. If at last one drive found -> return. 189 * - try an ATA command on the master. 190 */ 191 192 static void 193 wdc_drvprobe(struct wdc_channel *chp) 194 { 195 struct ataparams params; 196 struct wdc_softc *wdc = chp->ch_wdc; 197 u_int8_t st0 = 0, st1 = 0; 198 int i, error; 199 200 if (wdcprobe1(chp, 0) == 0) { 201 /* No drives, abort the attach here. */ 202 return; 203 } 204 205 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 206 for (i = 0; i < mstohz(3000); i++) { 207 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 208 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 209 wdc->select(chp,0); 210 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 211 0, WDSD_IBM); 212 delay(10); /* 400ns delay */ 213 st0 = bus_space_read_1(chp->cmd_iot, 214 chp->cmd_iohs[wd_status], 0); 215 } 216 217 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 218 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 219 wdc->select(chp,1); 220 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 221 0, WDSD_IBM | 0x10); 222 delay(10); /* 400ns delay */ 223 st1 = bus_space_read_1(chp->cmd_iot, 224 chp->cmd_iohs[wd_status], 0); 225 } 226 227 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 228 == 0 || 229 (st0 & WDCS_DRDY)) && 230 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 231 == 0 || 232 (st1 & WDCS_DRDY))) 233 break; 234 tsleep(¶ms, PRIBIO, "atadrdy", 1); 235 } 236 if ((st0 & WDCS_DRDY) == 0) 237 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 238 if ((st1 & WDCS_DRDY) == 0) 239 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 240 241 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 242 wdc->sc_dev.dv_xname, 243 chp->ch_channel, st0, st1), DEBUG_PROBE); 244 245 /* Wait a bit, some devices are weird just after a reset. */ 246 delay(5000); 247 248 for (i = 0; i < 2; i++) { 249 /* XXX This should be done by other code. */ 250 chp->ch_drive[i].chnl_softc = chp; 251 chp->ch_drive[i].drive = i; 252 253 /* 254 * Init error counter so that an error withing the first xfers 255 * will trigger a downgrade 256 */ 257 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 258 259 /* If controller can't do 16bit flag the drives as 32bit */ 260 if ((wdc->cap & 261 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 262 WDC_CAPABILITY_DATA32) 263 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 264 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 265 continue; 266 267 /* Shortcut in case we've been shutdown */ 268 if (chp->ch_flags & WDCF_SHUTDOWN) 269 return; 270 271 /* issue an identify, to try to detect ghosts */ 272 error = ata_get_params(&chp->ch_drive[i], 273 AT_WAIT | AT_POLL, ¶ms); 274 if (error != CMD_OK) { 275 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 276 277 /* Shortcut in case we've been shutdown */ 278 if (chp->ch_flags & WDCF_SHUTDOWN) 279 return; 280 281 error = ata_get_params(&chp->ch_drive[i], 282 AT_WAIT | AT_POLL, ¶ms); 283 } 284 if (error == CMD_OK) { 285 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 286 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 287 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 288 } else { 289 chp->ch_drive[i].drive_flags &= 290 ~(DRIVE_ATA | DRIVE_ATAPI); 291 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 292 wdc->sc_dev.dv_xname, 293 chp->ch_channel, i, error), DEBUG_PROBE); 294 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 295 continue; 296 /* 297 * Pre-ATA drive ? 298 * Test registers writability (Error register not 299 * writable, but cyllo is), then try an ATA command. 300 */ 301 if (wdc->cap & WDC_CAPABILITY_SELECT) 302 wdc->select(chp,i); 303 bus_space_write_1(chp->cmd_iot, 304 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 305 delay(10); /* 400ns delay */ 306 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 307 0, 0x58); 308 bus_space_write_1(chp->cmd_iot, 309 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 310 if (bus_space_read_1(chp->cmd_iot, 311 chp->cmd_iohs[wd_error], 0) == 0x58 || 312 bus_space_read_1(chp->cmd_iot, 313 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 314 WDCDEBUG_PRINT(("%s:%d:%d: register " 315 "writability failed\n", 316 wdc->sc_dev.dv_xname, 317 chp->ch_channel, i), DEBUG_PROBE); 318 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 319 continue; 320 } 321 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 322 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 323 wdc->sc_dev.dv_xname, 324 chp->ch_channel, i), DEBUG_PROBE); 325 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 326 continue; 327 } 328 bus_space_write_1(chp->cmd_iot, 329 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 330 delay(10); /* 400ns delay */ 331 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 332 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 333 wdc->sc_dev.dv_xname, 334 chp->ch_channel, i), DEBUG_PROBE); 335 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 336 } else { 337 chp->ch_drive[0].drive_flags &= 338 ~(DRIVE_ATA | DRIVE_ATAPI); 339 chp->ch_drive[1].drive_flags &= 340 ~(DRIVE_ATA | DRIVE_ATAPI); 341 } 342 } 343 } 344 } 345 346 void 347 atabusconfig(struct atabus_softc *atabus_sc) 348 { 349 struct wdc_channel *chp = atabus_sc->sc_chan; 350 struct wdc_softc *wdc = chp->ch_wdc; 351 int i, error, need_delref = 0; 352 struct atabus_initq *atabus_initq = NULL; 353 354 if ((error = wdc_addref(chp)) != 0) { 355 aprint_error("%s: unable to enable controller\n", 356 wdc->sc_dev.dv_xname); 357 goto out; 358 } 359 need_delref = 1; 360 361 /* Probe for the drives. */ 362 (*wdc->drv_probe)(chp); 363 364 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 365 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 366 DEBUG_PROBE); 367 368 /* If no drives, abort here */ 369 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 370 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 371 goto out; 372 373 /* Shortcut in case we've been shutdown */ 374 if (chp->ch_flags & WDCF_SHUTDOWN) 375 goto out; 376 377 /* Make sure the devices probe in atabus order to avoid jitter. */ 378 simple_lock(&atabus_interlock); 379 while(1) { 380 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 381 if (atabus_initq->atabus_sc == atabus_sc) 382 break; 383 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 384 &atabus_interlock); 385 } 386 simple_unlock(&atabus_interlock); 387 388 /* 389 * Attach an ATAPI bus, if needed. 390 */ 391 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 392 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 393 #if NATAPIBUS > 0 394 wdc_atapibus_attach(atabus_sc); 395 #else 396 /* 397 * Fake the autoconfig "not configured" message 398 */ 399 aprint_normal("atapibus at %s not configured\n", 400 wdc->sc_dev.dv_xname); 401 chp->atapibus = NULL; 402 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 403 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 404 #endif 405 } 406 407 for (i = 0; i < 2; i++) { 408 struct ata_device adev; 409 if ((chp->ch_drive[i].drive_flags & 410 (DRIVE_ATA | DRIVE_OLD)) == 0) { 411 continue; 412 } 413 memset(&adev, 0, sizeof(struct ata_device)); 414 adev.adev_bustype = &wdc_ata_bustype; 415 adev.adev_channel = chp->ch_channel; 416 adev.adev_openings = 1; 417 adev.adev_drv_data = &chp->ch_drive[i]; 418 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 419 &adev, ataprint); 420 if (chp->ata_drives[i] != NULL) 421 wdc_probe_caps(&chp->ch_drive[i]); 422 else 423 chp->ch_drive[i].drive_flags &= 424 ~(DRIVE_ATA | DRIVE_OLD); 425 } 426 427 /* now that we know the drives, the controller can set its modes */ 428 if (wdc->cap & WDC_CAPABILITY_MODE) { 429 wdc->set_modes(chp); 430 wdc_print_modes(chp); 431 } 432 #if NATARAID > 0 433 if (wdc->cap & WDC_CAPABILITY_RAID) 434 for (i = 0; i < 2; i++) 435 if (chp->ata_drives[i] != NULL) 436 ata_raid_check_component(chp->ata_drives[i]); 437 #endif /* NATARAID > 0 */ 438 439 /* 440 * reset drive_flags for unattached devices, reset state for attached 441 * ones 442 */ 443 for (i = 0; i < 2; i++) { 444 if (chp->ch_drive[i].drv_softc == NULL) 445 chp->ch_drive[i].drive_flags = 0; 446 else 447 chp->ch_drive[i].state = 0; 448 } 449 450 out: 451 if (atabus_initq == NULL) { 452 simple_lock(&atabus_interlock); 453 while(1) { 454 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 455 if (atabus_initq->atabus_sc == atabus_sc) 456 break; 457 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 458 &atabus_interlock); 459 } 460 simple_unlock(&atabus_interlock); 461 } 462 simple_lock(&atabus_interlock); 463 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 464 simple_unlock(&atabus_interlock); 465 466 free(atabus_initq, M_DEVBUF); 467 wakeup(&atabus_initq_head); 468 469 config_pending_decr(); 470 if (need_delref) 471 wdc_delref(chp); 472 } 473 474 int 475 wdcprobe(struct wdc_channel *chp) 476 { 477 478 return (wdcprobe1(chp, 1)); 479 } 480 481 static int 482 wdcprobe1(struct wdc_channel *chp, int poll) 483 { 484 struct wdc_softc *wdc = chp->ch_wdc; 485 u_int8_t st0, st1, sc, sn, cl, ch; 486 u_int8_t ret_value = 0x03; 487 u_int8_t drive; 488 int s; 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if (wdc == NULL || 496 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 497 498 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 499 wdc->select(chp,0); 500 501 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 502 WDSD_IBM); 503 delay(10); /* 400ns delay */ 504 st0 = bus_space_read_1(chp->cmd_iot, 505 chp->cmd_iohs[wd_status], 0); 506 507 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 508 wdc->select(chp,1); 509 510 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 511 WDSD_IBM | 0x10); 512 delay(10); /* 400ns delay */ 513 st1 = bus_space_read_1(chp->cmd_iot, 514 chp->cmd_iohs[wd_status], 0); 515 516 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 517 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 518 chp->ch_channel, st0, st1), DEBUG_PROBE); 519 520 if (st0 == 0xff || st0 == WDSD_IBM) 521 ret_value &= ~0x01; 522 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 523 ret_value &= ~0x02; 524 /* Register writability test, drive 0. */ 525 if (ret_value & 0x01) { 526 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 527 wdc->select(chp,0); 528 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 529 0, WDSD_IBM); 530 bus_space_write_1(chp->cmd_iot, 531 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 532 cl = bus_space_read_1(chp->cmd_iot, 533 chp->cmd_iohs[wd_cyl_lo], 0); 534 if (cl != 0x02) { 535 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 536 "got 0x%x != 0x02\n", 537 wdc != NULL ? 538 wdc->sc_dev.dv_xname : "wdcprobe", 539 chp->ch_channel, cl), 540 DEBUG_PROBE); 541 ret_value &= ~0x01; 542 } 543 bus_space_write_1(chp->cmd_iot, 544 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 545 cl = bus_space_read_1(chp->cmd_iot, 546 chp->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x01) { 548 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x01\n", 550 wdc != NULL ? 551 wdc->sc_dev.dv_xname : "wdcprobe", 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 wdc != NULL ? 564 wdc->sc_dev.dv_xname : "wdcprobe", 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x01; 568 } 569 bus_space_write_1(chp->cmd_iot, 570 chp->cmd_iohs[wd_sector], 0, 0x02); 571 cl = bus_space_read_1(chp->cmd_iot, 572 chp->cmd_iohs[wd_sector], 0); 573 if (cl != 0x02) { 574 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 575 "got 0x%x != 0x02\n", 576 wdc != NULL ? 577 wdc->sc_dev.dv_xname : "wdcprobe", 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x01; 581 } 582 cl = bus_space_read_1(chp->cmd_iot, 583 chp->cmd_iohs[wd_cyl_lo], 0); 584 if (cl != 0x01) { 585 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 586 "got 0x%x != 0x01\n", 587 wdc != NULL ? 588 wdc->sc_dev.dv_xname : "wdcprobe", 589 chp->ch_channel, cl), 590 DEBUG_PROBE); 591 ret_value &= ~0x01; 592 } 593 } 594 /* Register writability test, drive 1. */ 595 if (ret_value & 0x02) { 596 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 597 wdc->select(chp,1); 598 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 599 0, WDSD_IBM | 0x10); 600 bus_space_write_1(chp->cmd_iot, 601 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 602 cl = bus_space_read_1(chp->cmd_iot, 603 chp->cmd_iohs[wd_cyl_lo], 0); 604 if (cl != 0x02) { 605 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 606 "got 0x%x != 0x02\n", 607 wdc != NULL ? 608 wdc->sc_dev.dv_xname : "wdcprobe", 609 chp->ch_channel, cl), 610 DEBUG_PROBE); 611 ret_value &= ~0x02; 612 } 613 bus_space_write_1(chp->cmd_iot, 614 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 615 cl = bus_space_read_1(chp->cmd_iot, 616 chp->cmd_iohs[wd_cyl_lo], 0); 617 if (cl != 0x01) { 618 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 619 "got 0x%x != 0x01\n", 620 wdc != NULL ? 621 wdc->sc_dev.dv_xname : "wdcprobe", 622 chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_sector], 0, 0x01); 628 cl = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_sector], 0); 630 if (cl != 0x01) { 631 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 632 "got 0x%x != 0x01\n", 633 wdc != NULL ? 634 wdc->sc_dev.dv_xname : "wdcprobe", 635 chp->ch_channel, cl), 636 DEBUG_PROBE); 637 ret_value &= ~0x02; 638 } 639 bus_space_write_1(chp->cmd_iot, 640 chp->cmd_iohs[wd_sector], 0, 0x02); 641 cl = bus_space_read_1(chp->cmd_iot, 642 chp->cmd_iohs[wd_sector], 0); 643 if (cl != 0x02) { 644 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 645 "got 0x%x != 0x02\n", 646 wdc != NULL ? 647 wdc->sc_dev.dv_xname : "wdcprobe", 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 cl = bus_space_read_1(chp->cmd_iot, 653 chp->cmd_iohs[wd_cyl_lo], 0); 654 if (cl != 0x01) { 655 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 656 "got 0x%x != 0x01\n", 657 wdc != NULL ? 658 wdc->sc_dev.dv_xname : "wdcprobe", 659 chp->ch_channel, cl), 660 DEBUG_PROBE); 661 ret_value &= ~0x02; 662 } 663 } 664 665 if (ret_value == 0) { 666 splx(s); 667 return 0; 668 } 669 } 670 671 672 /* 673 * reset bus. Also send an ATAPI_RESET to devices, in case there are 674 * ATAPI device out there which don't react to the bus reset 675 */ 676 if (ret_value & 0x01) { 677 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 678 wdc->select(chp,0); 679 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 680 0, WDSD_IBM); 681 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 682 ATAPI_SOFT_RESET); 683 } 684 if (ret_value & 0x02) { 685 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 686 wdc->select(chp,0); 687 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 688 0, WDSD_IBM | 0x10); 689 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 690 ATAPI_SOFT_RESET); 691 } 692 693 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 694 wdc->select(chp,0); 695 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 696 delay(10); /* 400ns delay */ 697 /* assert SRST, wait for reset to complete */ 698 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 699 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 700 DELAY(1000); 701 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 702 WDCTL_IDS | WDCTL_4BIT); 703 DELAY(2000); 704 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 705 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 706 delay(10); /* 400ns delay */ 707 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 708 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 709 wdc->irqack(chp); 710 splx(s); 711 712 ret_value = __wdcwait_reset(chp, ret_value, poll); 713 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 714 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 715 ret_value), DEBUG_PROBE); 716 717 /* if reset failed, there's nothing here */ 718 if (ret_value == 0) 719 return 0; 720 721 /* 722 * Test presence of drives. First test register signatures looking 723 * for ATAPI devices. If it's not an ATAPI and reset said there may 724 * be something here assume it's ATA or OLD. Ghost will be killed 725 * later in attach routine. 726 */ 727 for (drive = 0; drive < 2; drive++) { 728 if ((ret_value & (0x01 << drive)) == 0) 729 continue; 730 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 731 wdc->select(chp,drive); 732 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 733 WDSD_IBM | (drive << 4)); 734 delay(10); /* 400ns delay */ 735 /* Save registers contents */ 736 sc = bus_space_read_1(chp->cmd_iot, 737 chp->cmd_iohs[wd_seccnt], 0); 738 sn = bus_space_read_1(chp->cmd_iot, 739 chp->cmd_iohs[wd_sector], 0); 740 cl = bus_space_read_1(chp->cmd_iot, 741 chp->cmd_iohs[wd_cyl_lo], 0); 742 ch = bus_space_read_1(chp->cmd_iot, 743 chp->cmd_iohs[wd_cyl_hi], 0); 744 745 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 746 "cl=0x%x ch=0x%x\n", 747 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 748 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 749 /* 750 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 751 * we get wrong values here, so ignore it. 752 */ 753 if (cl == 0x14 && ch == 0xeb) { 754 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 755 } else { 756 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 757 if (wdc == NULL || 758 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 759 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 760 } 761 } 762 return (ret_value); 763 } 764 765 void 766 wdcattach(struct wdc_channel *chp) 767 { 768 struct wdc_softc *wdc = chp->ch_wdc; 769 static int inited = 0; 770 771 if (chp->ch_flags & WDCF_DISABLED) 772 return; 773 774 /* initialise global data */ 775 callout_init(&chp->ch_callout); 776 if (wdc->drv_probe == NULL) 777 wdc->drv_probe = wdc_drvprobe; 778 if (inited == 0) { 779 /* Initialize the ata_xfer pool. */ 780 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 781 0, 0, "wdcspl", NULL); 782 inited++; 783 } 784 TAILQ_INIT(&chp->ch_queue->queue_xfer); 785 chp->ch_queue->queue_freeze = 0; 786 787 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 788 } 789 790 int 791 wdcactivate(struct device *self, enum devact act) 792 { 793 struct wdc_softc *wdc = (struct wdc_softc *)self; 794 int s, i, error = 0; 795 796 s = splbio(); 797 switch (act) { 798 case DVACT_ACTIVATE: 799 error = EOPNOTSUPP; 800 break; 801 802 case DVACT_DEACTIVATE: 803 for (i = 0; i < wdc->nchannels; i++) { 804 error = config_deactivate(wdc->channels[i]->atabus); 805 if (error) 806 break; 807 } 808 break; 809 } 810 splx(s); 811 return (error); 812 } 813 814 int 815 wdcdetach(struct device *self, int flags) 816 { 817 struct wdc_softc *wdc = (struct wdc_softc *)self; 818 struct wdc_channel *chp; 819 int i, error = 0; 820 821 for (i = 0; i < wdc->nchannels; i++) { 822 chp = wdc->channels[i]; 823 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 824 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 825 error = config_detach(chp->atabus, flags); 826 if (error) 827 break; 828 } 829 return (error); 830 } 831 832 /* 833 * Start I/O on a controller, for the given channel. 834 * The first xfer may be not for our channel if the channel queues 835 * are shared. 836 */ 837 void 838 wdcstart(struct wdc_channel *chp) 839 { 840 struct wdc_softc *wdc = chp->ch_wdc; 841 struct ata_xfer *xfer; 842 843 #ifdef WDC_DIAGNOSTIC 844 int spl1, spl2; 845 846 spl1 = splbio(); 847 spl2 = splbio(); 848 if (spl2 != spl1) { 849 printf("wdcstart: not at splbio()\n"); 850 panic("wdcstart"); 851 } 852 splx(spl2); 853 splx(spl1); 854 #endif /* WDC_DIAGNOSTIC */ 855 856 /* is there a xfer ? */ 857 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 858 return; 859 860 /* adjust chp, in case we have a shared queue */ 861 chp = xfer->c_chp; 862 863 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 864 return; /* channel aleady active */ 865 } 866 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 867 return; /* queue froozen */ 868 } 869 #ifdef DIAGNOSTIC 870 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 871 panic("wdcstart: channel waiting for irq"); 872 #endif 873 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 874 if (!(*wdc->claim_hw)(chp, 0)) 875 return; 876 877 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 878 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 879 chp->ch_flags |= WDCF_ACTIVE; 880 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 881 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 882 chp->ch_drive[xfer->c_drive].state = 0; 883 } 884 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 885 KASSERT(xfer->c_flags & C_POLL); 886 xfer->c_start(chp, xfer); 887 } 888 889 /* restart an interrupted I/O */ 890 void 891 wdcrestart(void *v) 892 { 893 struct wdc_channel *chp = v; 894 int s; 895 896 s = splbio(); 897 wdcstart(chp); 898 splx(s); 899 } 900 901 902 /* 903 * Interrupt routine for the controller. Acknowledge the interrupt, check for 904 * errors on the current operation, mark it done if necessary, and start the 905 * next request. Also check for a partially done transfer, and continue with 906 * the next chunk if so. 907 */ 908 int 909 wdcintr(void *arg) 910 { 911 struct wdc_channel *chp = arg; 912 struct wdc_softc *wdc = chp->ch_wdc; 913 struct ata_xfer *xfer; 914 int ret; 915 916 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 917 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 918 DEBUG_INTR); 919 return (0); 920 } 921 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 922 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 923 /* try to clear the pending interrupt anyway */ 924 (void)bus_space_read_1(chp->cmd_iot, 925 chp->cmd_iohs[wd_status], 0); 926 return (0); 927 } 928 929 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 930 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 931 if (chp->ch_flags & WDCF_DMA_WAIT) { 932 wdc->dma_status = 933 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 934 xfer->c_drive, 0); 935 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 936 /* IRQ not for us, not detected by DMA engine */ 937 return 0; 938 } 939 chp->ch_flags &= ~WDCF_DMA_WAIT; 940 } 941 chp->ch_flags &= ~WDCF_IRQ_WAIT; 942 ret = xfer->c_intr(chp, xfer, 1); 943 if (ret == 0) /* irq was not for us, still waiting for irq */ 944 chp->ch_flags |= WDCF_IRQ_WAIT; 945 return (ret); 946 } 947 948 /* Put all disk in RESET state */ 949 void 950 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 951 { 952 struct wdc_channel *chp = drvp->chnl_softc; 953 struct wdc_softc *wdc = chp->ch_wdc; 954 int drive; 955 956 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 957 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 958 DEBUG_FUNCS); 959 if ((flags & AT_POLL) == 0) { 960 if (chp->ch_flags & WDCF_TH_RESET) { 961 /* no need to schedule a reset more than one time */ 962 return; 963 } 964 chp->ch_flags |= WDCF_TH_RESET; 965 chp->ch_queue->queue_freeze++; 966 wakeup(&chp->ch_thread); 967 return; 968 } 969 (void) wdcreset(chp, RESET_POLL); 970 for (drive = 0; drive < 2; drive++) { 971 chp->ch_drive[drive].state = 0; 972 } 973 } 974 975 int 976 wdcreset(struct wdc_channel *chp, int poll) 977 { 978 struct wdc_softc *wdc = chp->ch_wdc; 979 int drv_mask1, drv_mask2; 980 int s = 0; 981 982 if (wdc->cap & WDC_CAPABILITY_SELECT) 983 wdc->select(chp,0); 984 if (poll != RESET_SLEEP) 985 s = splbio(); 986 /* master */ 987 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 988 delay(10); /* 400ns delay */ 989 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 990 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 991 delay(2000); 992 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 993 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 994 WDCTL_4BIT | WDCTL_IDS); 995 delay(10); /* 400ns delay */ 996 if (poll != RESET_SLEEP) { 997 if (wdc->cap & WDC_CAPABILITY_IRQACK) 998 wdc->irqack(chp); 999 splx(s); 1000 } 1001 1002 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1003 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1004 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1005 (poll == RESET_SLEEP) ? 0 : 1); 1006 if (drv_mask2 != drv_mask1) { 1007 printf("%s channel %d: reset failed for", 1008 wdc->sc_dev.dv_xname, chp->ch_channel); 1009 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1010 printf(" drive 0"); 1011 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1012 printf(" drive 1"); 1013 printf("\n"); 1014 } 1015 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1016 return (drv_mask1 != drv_mask2) ? 1 : 0; 1017 } 1018 1019 static int 1020 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1021 { 1022 struct wdc_softc *wdc = chp->ch_wdc; 1023 int timeout, nloop; 1024 u_int8_t st0 = 0, st1 = 0; 1025 #ifdef WDCDEBUG 1026 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1027 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1028 #endif 1029 1030 if (poll) 1031 nloop = WDCNDELAY_RST; 1032 else 1033 nloop = WDC_RESET_WAIT * hz / 1000; 1034 /* wait for BSY to deassert */ 1035 for (timeout = 0; timeout < nloop; timeout++) { 1036 if ((drv_mask & 0x01) != 0) { 1037 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1038 wdc->select(chp,0); 1039 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1040 0, WDSD_IBM); /* master */ 1041 delay(10); 1042 st0 = bus_space_read_1(chp->cmd_iot, 1043 chp->cmd_iohs[wd_status], 0); 1044 #ifdef WDCDEBUG 1045 sc0 = bus_space_read_1(chp->cmd_iot, 1046 chp->cmd_iohs[wd_seccnt], 0); 1047 sn0 = bus_space_read_1(chp->cmd_iot, 1048 chp->cmd_iohs[wd_sector], 0); 1049 cl0 = bus_space_read_1(chp->cmd_iot, 1050 chp->cmd_iohs[wd_cyl_lo], 0); 1051 ch0 = bus_space_read_1(chp->cmd_iot, 1052 chp->cmd_iohs[wd_cyl_hi], 0); 1053 #endif 1054 } 1055 if ((drv_mask & 0x02) != 0) { 1056 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1057 wdc->select(chp,1); 1058 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1059 0, WDSD_IBM | 0x10); /* slave */ 1060 delay(10); 1061 st1 = bus_space_read_1(chp->cmd_iot, 1062 chp->cmd_iohs[wd_status], 0); 1063 #ifdef WDCDEBUG 1064 sc1 = bus_space_read_1(chp->cmd_iot, 1065 chp->cmd_iohs[wd_seccnt], 0); 1066 sn1 = bus_space_read_1(chp->cmd_iot, 1067 chp->cmd_iohs[wd_sector], 0); 1068 cl1 = bus_space_read_1(chp->cmd_iot, 1069 chp->cmd_iohs[wd_cyl_lo], 0); 1070 ch1 = bus_space_read_1(chp->cmd_iot, 1071 chp->cmd_iohs[wd_cyl_hi], 0); 1072 #endif 1073 } 1074 1075 if ((drv_mask & 0x01) == 0) { 1076 /* no master */ 1077 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1078 /* No master, slave is ready, it's done */ 1079 goto end; 1080 } 1081 } else if ((drv_mask & 0x02) == 0) { 1082 /* no slave */ 1083 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1084 /* No slave, master is ready, it's done */ 1085 goto end; 1086 } 1087 } else { 1088 /* Wait for both master and slave to be ready */ 1089 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1090 goto end; 1091 } 1092 } 1093 if (poll) 1094 delay(WDCDELAY); 1095 else 1096 tsleep(&nloop, PRIBIO, "atarst", 1); 1097 } 1098 /* Reset timed out. Maybe it's because drv_mask was not right */ 1099 if (st0 & WDCS_BSY) 1100 drv_mask &= ~0x01; 1101 if (st1 & WDCS_BSY) 1102 drv_mask &= ~0x02; 1103 end: 1104 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1105 "cl=0x%x ch=0x%x\n", 1106 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1107 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1108 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1109 "cl=0x%x ch=0x%x\n", 1110 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1111 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1112 1113 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1114 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1115 st0, st1), DEBUG_PROBE); 1116 1117 return drv_mask; 1118 } 1119 1120 /* 1121 * Wait for a drive to be !BSY, and have mask in its status register. 1122 * return -1 for a timeout after "timeout" ms. 1123 */ 1124 static int 1125 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1126 { 1127 struct wdc_softc *wdc = chp->ch_wdc; 1128 u_char status; 1129 int time = 0; 1130 1131 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1132 wdc->sc_dev.dv_xname : "none", 1133 chp->ch_channel), DEBUG_STATUS); 1134 chp->ch_error = 0; 1135 1136 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1137 1138 for (;;) { 1139 chp->ch_status = status = 1140 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1141 if ((status & (WDCS_BSY | mask)) == bits) 1142 break; 1143 if (++time > timeout) { 1144 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1145 "status %x error %x (mask 0x%x bits 0x%x)\n", 1146 time, status, 1147 bus_space_read_1(chp->cmd_iot, 1148 chp->cmd_iohs[wd_error], 0), mask, bits), 1149 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1150 return(WDCWAIT_TOUT); 1151 } 1152 delay(WDCDELAY); 1153 } 1154 #ifdef WDCDEBUG 1155 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1156 printf("__wdcwait: did busy-wait, time=%d\n", time); 1157 #endif 1158 if (status & WDCS_ERR) 1159 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1160 chp->cmd_iohs[wd_error], 0); 1161 #ifdef WDCNDELAY_DEBUG 1162 /* After autoconfig, there should be no long delays. */ 1163 if (!cold && time > WDCNDELAY_DEBUG) { 1164 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1165 if (xfer == NULL) 1166 printf("%s channel %d: warning: busy-wait took %dus\n", 1167 wdc->sc_dev.dv_xname, chp->ch_channel, 1168 WDCDELAY * time); 1169 else 1170 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1171 wdc->sc_dev.dv_xname, chp->ch_channel, 1172 xfer->drive, 1173 WDCDELAY * time); 1174 } 1175 #endif 1176 return(WDCWAIT_OK); 1177 } 1178 1179 /* 1180 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1181 * thread if possible 1182 */ 1183 int 1184 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1185 { 1186 int error, i, timeout_hz = mstohz(timeout); 1187 1188 if (timeout_hz == 0 || 1189 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1190 error = __wdcwait(chp, mask, bits, timeout); 1191 else { 1192 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1193 if (error != 0) { 1194 if ((chp->ch_flags & WDCF_TH_RUN) || 1195 (flags & AT_WAIT)) { 1196 /* 1197 * we're running in the channel thread 1198 * or some userland thread context 1199 */ 1200 for (i = 0; i < timeout_hz; i++) { 1201 if (__wdcwait(chp, mask, bits, 1202 WDCDELAY_POLL) == 0) { 1203 error = 0; 1204 break; 1205 } 1206 tsleep(&chp, PRIBIO, "atapoll", 1); 1207 } 1208 } else { 1209 /* 1210 * we're probably in interrupt context, 1211 * ask the thread to come back here 1212 */ 1213 #ifdef DIAGNOSTIC 1214 if (chp->ch_queue->queue_freeze > 0) 1215 panic("wdcwait: queue_freeze"); 1216 #endif 1217 chp->ch_queue->queue_freeze++; 1218 wakeup(&chp->ch_thread); 1219 return(WDCWAIT_THR); 1220 } 1221 } 1222 } 1223 return (error); 1224 } 1225 1226 1227 /* 1228 * Busy-wait for DMA to complete 1229 */ 1230 int 1231 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1232 { 1233 struct wdc_softc *wdc = chp->ch_wdc; 1234 int time; 1235 1236 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1237 wdc->dma_status = 1238 (*wdc->dma_finish)(wdc->dma_arg, 1239 chp->ch_channel, xfer->c_drive, 0); 1240 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1241 return 0; 1242 delay(WDCDELAY); 1243 } 1244 /* timeout, force a DMA halt */ 1245 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1246 chp->ch_channel, xfer->c_drive, 1); 1247 return 1; 1248 } 1249 1250 void 1251 wdctimeout(void *arg) 1252 { 1253 struct wdc_channel *chp = (struct wdc_channel *)arg; 1254 struct wdc_softc *wdc = chp->ch_wdc; 1255 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1256 int s; 1257 1258 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1259 1260 s = splbio(); 1261 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1262 __wdcerror(chp, "lost interrupt"); 1263 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1264 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1265 xfer->c_bcount, 1266 xfer->c_skip); 1267 if (chp->ch_flags & WDCF_DMA_WAIT) { 1268 wdc->dma_status = 1269 (*wdc->dma_finish)(wdc->dma_arg, 1270 chp->ch_channel, xfer->c_drive, 1); 1271 chp->ch_flags &= ~WDCF_DMA_WAIT; 1272 } 1273 /* 1274 * Call the interrupt routine. If we just missed an interrupt, 1275 * it will do what's needed. Else, it will take the needed 1276 * action (reset the device). 1277 * Before that we need to reinstall the timeout callback, 1278 * in case it will miss another irq while in this transfer 1279 * We arbitray chose it to be 1s 1280 */ 1281 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1282 xfer->c_flags |= C_TIMEOU; 1283 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1284 xfer->c_intr(chp, xfer, 1); 1285 } else 1286 __wdcerror(chp, "missing untimeout"); 1287 splx(s); 1288 } 1289 1290 /* 1291 * Probe drive's capabilities, for use by the controller later 1292 * Assumes drvp points to an existing drive. 1293 * XXX this should be a controller-indep function 1294 */ 1295 void 1296 wdc_probe_caps(struct ata_drive_datas *drvp) 1297 { 1298 struct ataparams params, params2; 1299 struct wdc_channel *chp = drvp->chnl_softc; 1300 struct wdc_softc *wdc = chp->ch_wdc; 1301 struct device *drv_dev = drvp->drv_softc; 1302 int i, printed; 1303 char *sep = ""; 1304 int cf_flags; 1305 1306 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1307 /* IDENTIFY failed. Can't tell more about the device */ 1308 return; 1309 } 1310 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1311 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1312 /* 1313 * Controller claims 16 and 32 bit transfers. 1314 * Re-do an IDENTIFY with 32-bit transfers, 1315 * and compare results. 1316 */ 1317 drvp->drive_flags |= DRIVE_CAP32; 1318 ata_get_params(drvp, AT_WAIT, ¶ms2); 1319 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1320 /* Not good. fall back to 16bits */ 1321 drvp->drive_flags &= ~DRIVE_CAP32; 1322 } else { 1323 aprint_normal("%s: 32-bit data port\n", 1324 drv_dev->dv_xname); 1325 } 1326 } 1327 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1328 if (params.atap_ata_major > 0x01 && 1329 params.atap_ata_major != 0xffff) { 1330 for (i = 14; i > 0; i--) { 1331 if (params.atap_ata_major & (1 << i)) { 1332 aprint_normal("%s: ATA version %d\n", 1333 drv_dev->dv_xname, i); 1334 drvp->ata_vers = i; 1335 break; 1336 } 1337 } 1338 } 1339 #endif 1340 1341 /* An ATAPI device is at last PIO mode 3 */ 1342 if (drvp->drive_flags & DRIVE_ATAPI) 1343 drvp->PIO_mode = 3; 1344 1345 /* 1346 * It's not in the specs, but it seems that some drive 1347 * returns 0xffff in atap_extensions when this field is invalid 1348 */ 1349 if (params.atap_extensions != 0xffff && 1350 (params.atap_extensions & WDC_EXT_MODES)) { 1351 printed = 0; 1352 /* 1353 * XXX some drives report something wrong here (they claim to 1354 * support PIO mode 8 !). As mode is coded on 3 bits in 1355 * SET FEATURE, limit it to 7 (so limit i to 4). 1356 * If higher mode than 7 is found, abort. 1357 */ 1358 for (i = 7; i >= 0; i--) { 1359 if ((params.atap_piomode_supp & (1 << i)) == 0) 1360 continue; 1361 if (i > 4) 1362 return; 1363 /* 1364 * See if mode is accepted. 1365 * If the controller can't set its PIO mode, 1366 * assume the defaults are good, so don't try 1367 * to set it 1368 */ 1369 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1370 /* 1371 * It's OK to pool here, it's fast enouth 1372 * to not bother waiting for interrupt 1373 */ 1374 if (ata_set_mode(drvp, 0x08 | (i + 3), 1375 AT_WAIT) != CMD_OK) 1376 continue; 1377 if (!printed) { 1378 aprint_normal("%s: drive supports PIO mode %d", 1379 drv_dev->dv_xname, i + 3); 1380 sep = ","; 1381 printed = 1; 1382 } 1383 /* 1384 * If controller's driver can't set its PIO mode, 1385 * get the highter one for the drive. 1386 */ 1387 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1388 wdc->PIO_cap >= i + 3) { 1389 drvp->PIO_mode = i + 3; 1390 drvp->PIO_cap = i + 3; 1391 break; 1392 } 1393 } 1394 if (!printed) { 1395 /* 1396 * We didn't find a valid PIO mode. 1397 * Assume the values returned for DMA are buggy too 1398 */ 1399 return; 1400 } 1401 drvp->drive_flags |= DRIVE_MODE; 1402 printed = 0; 1403 for (i = 7; i >= 0; i--) { 1404 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1405 continue; 1406 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1407 (wdc->cap & WDC_CAPABILITY_MODE)) 1408 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1409 != CMD_OK) 1410 continue; 1411 if (!printed) { 1412 aprint_normal("%s DMA mode %d", sep, i); 1413 sep = ","; 1414 printed = 1; 1415 } 1416 if (wdc->cap & WDC_CAPABILITY_DMA) { 1417 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1418 wdc->DMA_cap < i) 1419 continue; 1420 drvp->DMA_mode = i; 1421 drvp->DMA_cap = i; 1422 drvp->drive_flags |= DRIVE_DMA; 1423 } 1424 break; 1425 } 1426 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1427 printed = 0; 1428 for (i = 7; i >= 0; i--) { 1429 if ((params.atap_udmamode_supp & (1 << i)) 1430 == 0) 1431 continue; 1432 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1433 (wdc->cap & WDC_CAPABILITY_UDMA)) 1434 if (ata_set_mode(drvp, 0x40 | i, 1435 AT_WAIT) != CMD_OK) 1436 continue; 1437 if (!printed) { 1438 aprint_normal("%s Ultra-DMA mode %d", 1439 sep, i); 1440 if (i == 2) 1441 aprint_normal(" (Ultra/33)"); 1442 else if (i == 4) 1443 aprint_normal(" (Ultra/66)"); 1444 else if (i == 5) 1445 aprint_normal(" (Ultra/100)"); 1446 else if (i == 6) 1447 aprint_normal(" (Ultra/133)"); 1448 sep = ","; 1449 printed = 1; 1450 } 1451 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1452 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1453 wdc->UDMA_cap < i) 1454 continue; 1455 drvp->UDMA_mode = i; 1456 drvp->UDMA_cap = i; 1457 drvp->drive_flags |= DRIVE_UDMA; 1458 } 1459 break; 1460 } 1461 } 1462 aprint_normal("\n"); 1463 } 1464 1465 /* Try to guess ATA version here, if it didn't get reported */ 1466 if (drvp->ata_vers == 0) { 1467 if (drvp->drive_flags & DRIVE_UDMA) 1468 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1469 else if (drvp->PIO_cap > 2) 1470 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1471 } 1472 cf_flags = drv_dev->dv_cfdata->cf_flags; 1473 if (cf_flags & ATA_CONFIG_PIO_SET) { 1474 drvp->PIO_mode = 1475 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1476 drvp->drive_flags |= DRIVE_MODE; 1477 } 1478 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1479 /* don't care about DMA modes */ 1480 return; 1481 } 1482 if (cf_flags & ATA_CONFIG_DMA_SET) { 1483 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1484 ATA_CONFIG_DMA_DISABLE) { 1485 drvp->drive_flags &= ~DRIVE_DMA; 1486 } else { 1487 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1488 ATA_CONFIG_DMA_OFF; 1489 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1490 } 1491 } 1492 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1493 /* don't care about UDMA modes */ 1494 return; 1495 } 1496 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1497 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1498 ATA_CONFIG_UDMA_DISABLE) { 1499 drvp->drive_flags &= ~DRIVE_UDMA; 1500 } else { 1501 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1502 ATA_CONFIG_UDMA_OFF; 1503 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1504 } 1505 } 1506 } 1507 1508 /* 1509 * downgrade the transfer mode of a drive after an error. return 1 if 1510 * downgrade was possible, 0 otherwise. 1511 */ 1512 int 1513 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1514 { 1515 struct wdc_channel *chp = drvp->chnl_softc; 1516 struct wdc_softc *wdc = chp->ch_wdc; 1517 struct device *drv_dev = drvp->drv_softc; 1518 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1519 1520 /* if drive or controller don't know its mode, we can't do much */ 1521 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1522 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1523 return 0; 1524 /* current drive mode was set by a config flag, let it this way */ 1525 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1526 (cf_flags & ATA_CONFIG_DMA_SET) || 1527 (cf_flags & ATA_CONFIG_UDMA_SET)) 1528 return 0; 1529 1530 /* 1531 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1532 * Maybe we didn't properly notice the cable type 1533 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1534 * It helps in some cases. 1535 */ 1536 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1537 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1538 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1539 drv_dev->dv_xname, drvp->UDMA_mode); 1540 } 1541 1542 /* 1543 * If we were using ultra-DMA, don't downgrade to multiword DMA 1544 * if we noticed a CRC error. It has been noticed that CRC errors 1545 * in ultra-DMA lead to silent data corruption in multiword DMA. 1546 * Data corruption is less likely to occur in PIO mode. 1547 */ 1548 else if ((drvp->drive_flags & DRIVE_UDMA) && 1549 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1550 drvp->drive_flags &= ~DRIVE_UDMA; 1551 drvp->drive_flags |= DRIVE_DMA; 1552 drvp->DMA_mode = drvp->DMA_cap; 1553 printf("%s: transfer error, downgrading to DMA mode %d\n", 1554 drv_dev->dv_xname, drvp->DMA_mode); 1555 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1556 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1557 drvp->PIO_mode = drvp->PIO_cap; 1558 printf("%s: transfer error, downgrading to PIO mode %d\n", 1559 drv_dev->dv_xname, drvp->PIO_mode); 1560 } else /* already using PIO, can't downgrade */ 1561 return 0; 1562 1563 wdc->set_modes(chp); 1564 wdc_print_modes(chp); 1565 /* reset the channel, which will shedule all drives for setup */ 1566 wdc_reset_channel(drvp, flags); 1567 return 1; 1568 } 1569 1570 int 1571 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1572 { 1573 struct wdc_channel *chp = drvp->chnl_softc; 1574 struct wdc_softc *wdc = chp->ch_wdc; 1575 struct ata_xfer *xfer; 1576 int s, ret; 1577 1578 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1579 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1580 DEBUG_FUNCS); 1581 1582 /* set up an xfer and queue. Wait for completion */ 1583 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1584 WDC_NOSLEEP); 1585 if (xfer == NULL) { 1586 return WDC_TRY_AGAIN; 1587 } 1588 1589 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1590 wdc_c->flags |= AT_POLL; 1591 if (wdc_c->flags & AT_POLL) 1592 xfer->c_flags |= C_POLL; 1593 xfer->c_drive = drvp->drive; 1594 xfer->c_databuf = wdc_c->data; 1595 xfer->c_bcount = wdc_c->bcount; 1596 xfer->c_cmd = wdc_c; 1597 xfer->c_start = __wdccommand_start; 1598 xfer->c_intr = __wdccommand_intr; 1599 xfer->c_kill_xfer = __wdccommand_done; 1600 1601 s = splbio(); 1602 wdc_exec_xfer(chp, xfer); 1603 #ifdef DIAGNOSTIC 1604 if ((wdc_c->flags & AT_POLL) != 0 && 1605 (wdc_c->flags & AT_DONE) == 0) 1606 panic("wdc_exec_command: polled command not done"); 1607 #endif 1608 if (wdc_c->flags & AT_DONE) { 1609 ret = WDC_COMPLETE; 1610 } else { 1611 if (wdc_c->flags & AT_WAIT) { 1612 while ((wdc_c->flags & AT_DONE) == 0) { 1613 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1614 } 1615 ret = WDC_COMPLETE; 1616 } else { 1617 ret = WDC_QUEUED; 1618 } 1619 } 1620 splx(s); 1621 return ret; 1622 } 1623 1624 static void 1625 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1626 { 1627 struct wdc_softc *wdc = chp->ch_wdc; 1628 int drive = xfer->c_drive; 1629 struct wdc_command *wdc_c = xfer->c_cmd; 1630 1631 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1632 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1633 DEBUG_FUNCS); 1634 1635 if (wdc->cap & WDC_CAPABILITY_SELECT) 1636 wdc->select(chp,drive); 1637 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1638 WDSD_IBM | (drive << 4)); 1639 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1640 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1641 case WDCWAIT_OK: 1642 break; 1643 case WDCWAIT_TOUT: 1644 wdc_c->flags |= AT_TIMEOU; 1645 __wdccommand_done(chp, xfer); 1646 return; 1647 case WDCWAIT_THR: 1648 return; 1649 } 1650 if (wdc_c->flags & AT_POLL) { 1651 /* polled command, disable interrupts */ 1652 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1653 WDCTL_4BIT | WDCTL_IDS); 1654 } 1655 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1656 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1657 1658 if ((wdc_c->flags & AT_POLL) == 0) { 1659 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1660 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1661 wdctimeout, chp); 1662 return; 1663 } 1664 /* 1665 * Polled command. Wait for drive ready or drq. Done in intr(). 1666 * Wait for at last 400ns for status bit to be valid. 1667 */ 1668 delay(10); /* 400ns delay */ 1669 __wdccommand_intr(chp, xfer, 0); 1670 } 1671 1672 static int 1673 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1674 { 1675 struct wdc_softc *wdc = chp->ch_wdc; 1676 struct wdc_command *wdc_c = xfer->c_cmd; 1677 int bcount = wdc_c->bcount; 1678 char *data = wdc_c->data; 1679 int wflags; 1680 1681 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1682 /* both wait and poll, we can tsleep here */ 1683 wflags = AT_WAIT | AT_POLL; 1684 } else { 1685 wflags = AT_POLL; 1686 } 1687 1688 again: 1689 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1690 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1691 DEBUG_INTR); 1692 /* 1693 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1694 * Reselect again, it doesn't hurt for others commands, and the time 1695 * penalty for the extra regiter write is acceptable, 1696 * wdc_exec_command() isn't called often (mosly for autoconfig) 1697 */ 1698 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1699 WDSD_IBM | (xfer->c_drive << 4)); 1700 if ((wdc_c->flags & AT_XFDONE) != 0) { 1701 /* 1702 * We have completed a data xfer. The drive should now be 1703 * in its initial state 1704 */ 1705 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1706 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1707 wflags) == WDCWAIT_TOUT) { 1708 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1709 return 0; /* IRQ was not for us */ 1710 wdc_c->flags |= AT_TIMEOU; 1711 } 1712 goto out; 1713 } 1714 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1715 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1716 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1717 return 0; /* IRQ was not for us */ 1718 wdc_c->flags |= AT_TIMEOU; 1719 goto out; 1720 } 1721 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1722 wdc->irqack(chp); 1723 if (wdc_c->flags & AT_READ) { 1724 if ((chp->ch_status & WDCS_DRQ) == 0) { 1725 wdc_c->flags |= AT_TIMEOU; 1726 goto out; 1727 } 1728 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1729 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1730 0, (u_int32_t*)data, bcount >> 2); 1731 data += bcount & 0xfffffffc; 1732 bcount = bcount & 0x03; 1733 } 1734 if (bcount > 0) 1735 bus_space_read_multi_2(chp->cmd_iot, 1736 chp->cmd_iohs[wd_data], 0, 1737 (u_int16_t *)data, bcount >> 1); 1738 /* at this point the drive should be in its initial state */ 1739 wdc_c->flags |= AT_XFDONE; 1740 /* XXX should read status register here ? */ 1741 } else if (wdc_c->flags & AT_WRITE) { 1742 if ((chp->ch_status & WDCS_DRQ) == 0) { 1743 wdc_c->flags |= AT_TIMEOU; 1744 goto out; 1745 } 1746 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1747 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1748 0, (u_int32_t*)data, bcount >> 2); 1749 data += bcount & 0xfffffffc; 1750 bcount = bcount & 0x03; 1751 } 1752 if (bcount > 0) 1753 bus_space_write_multi_2(chp->cmd_iot, 1754 chp->cmd_iohs[wd_data], 0, 1755 (u_int16_t *)data, bcount >> 1); 1756 wdc_c->flags |= AT_XFDONE; 1757 if ((wdc_c->flags & AT_POLL) == 0) { 1758 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1759 callout_reset(&chp->ch_callout, 1760 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1761 return 1; 1762 } else { 1763 goto again; 1764 } 1765 } 1766 out: 1767 __wdccommand_done(chp, xfer); 1768 return 1; 1769 } 1770 1771 static void 1772 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1773 { 1774 struct wdc_softc *wdc = chp->ch_wdc; 1775 struct wdc_command *wdc_c = xfer->c_cmd; 1776 1777 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1778 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1779 DEBUG_FUNCS); 1780 1781 callout_stop(&chp->ch_callout); 1782 1783 if (chp->ch_status & WDCS_DWF) 1784 wdc_c->flags |= AT_DF; 1785 if (chp->ch_status & WDCS_ERR) { 1786 wdc_c->flags |= AT_ERROR; 1787 wdc_c->r_error = chp->ch_error; 1788 } 1789 wdc_c->flags |= AT_DONE; 1790 if ((wdc_c->flags & AT_READREG) != 0 && 1791 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1792 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1793 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1794 chp->cmd_iohs[wd_sdh], 0); 1795 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1796 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1797 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1798 chp->cmd_iohs[wd_cyl_lo], 0); 1799 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1800 chp->cmd_iohs[wd_sector], 0); 1801 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1802 chp->cmd_iohs[wd_seccnt], 0); 1803 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1804 chp->cmd_iohs[wd_error], 0); 1805 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1806 chp->cmd_iohs[wd_precomp], 0); 1807 } 1808 1809 if (wdc_c->flags & AT_POLL) { 1810 /* enable interrupts */ 1811 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1812 WDCTL_4BIT); 1813 delay(10); /* some drives need a little delay here */ 1814 } 1815 wdc_free_xfer(chp, xfer); 1816 if (wdc_c->flags & AT_WAIT) 1817 wakeup(wdc_c); 1818 else if (wdc_c->callback) 1819 wdc_c->callback(wdc_c->callback_arg); 1820 wdcstart(chp); 1821 return; 1822 } 1823 1824 /* 1825 * Send a command. The drive should be ready. 1826 * Assumes interrupts are blocked. 1827 */ 1828 void 1829 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1830 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1831 u_int8_t precomp) 1832 { 1833 struct wdc_softc *wdc = chp->ch_wdc; 1834 1835 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1836 "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname, 1837 chp->ch_channel, drive, command, cylin, head, sector, count, 1838 precomp), DEBUG_FUNCS); 1839 1840 if (wdc->cap & WDC_CAPABILITY_SELECT) 1841 wdc->select(chp,drive); 1842 1843 /* Select drive, head, and addressing mode. */ 1844 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1845 WDSD_IBM | (drive << 4) | head); 1846 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1847 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1848 precomp); 1849 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1850 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1851 0, cylin >> 8); 1852 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1853 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1854 1855 /* Send command. */ 1856 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1857 return; 1858 } 1859 1860 /* 1861 * Send a 48-bit addressing command. The drive should be ready. 1862 * Assumes interrupts are blocked. 1863 */ 1864 void 1865 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1866 u_int64_t blkno, u_int16_t count) 1867 { 1868 struct wdc_softc *wdc = chp->ch_wdc; 1869 1870 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1871 "count=%d\n", wdc->sc_dev.dv_xname, 1872 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1873 DEBUG_FUNCS); 1874 1875 if (wdc->cap & WDC_CAPABILITY_SELECT) 1876 wdc->select(chp,drive); 1877 1878 /* Select drive, head, and addressing mode. */ 1879 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1880 (drive << 4) | WDSD_LBA); 1881 1882 /* previous */ 1883 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1884 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1885 0, count >> 8); 1886 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1887 0, blkno >> 40); 1888 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1889 0, blkno >> 32); 1890 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1891 0, blkno >> 24); 1892 1893 /* current */ 1894 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1895 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1896 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1897 0, blkno >> 16); 1898 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1899 0, blkno >> 8); 1900 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1901 1902 /* Send command. */ 1903 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1904 return; 1905 } 1906 1907 /* 1908 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1909 * tested by the caller. 1910 */ 1911 void 1912 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1913 { 1914 struct wdc_softc *wdc = chp->ch_wdc; 1915 1916 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1917 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1918 DEBUG_FUNCS); 1919 1920 if (wdc->cap & WDC_CAPABILITY_SELECT) 1921 wdc->select(chp,drive); 1922 1923 /* Select drive. */ 1924 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1925 WDSD_IBM | (drive << 4)); 1926 1927 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1928 } 1929 1930 /* Add a command to the queue and start controller. Must be called at splbio */ 1931 void 1932 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1933 { 1934 1935 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1936 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 1937 1938 /* complete xfer setup */ 1939 xfer->c_chp = chp; 1940 1941 /* 1942 * If we are a polled command, and the list is not empty, 1943 * we are doing a dump. Drop the list to allow the polled command 1944 * to complete, we're going to reboot soon anyway. 1945 */ 1946 if ((xfer->c_flags & C_POLL) != 0 && 1947 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) { 1948 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1949 } 1950 /* insert at the end of command list */ 1951 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1952 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1953 chp->ch_flags), DEBUG_XFERS); 1954 wdcstart(chp); 1955 } 1956 1957 struct ata_xfer * 1958 wdc_get_xfer(int flags) 1959 { 1960 struct ata_xfer *xfer; 1961 int s; 1962 1963 s = splbio(); 1964 xfer = pool_get(&wdc_xfer_pool, 1965 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1966 splx(s); 1967 if (xfer != NULL) { 1968 memset(xfer, 0, sizeof(struct ata_xfer)); 1969 } 1970 return xfer; 1971 } 1972 1973 void 1974 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1975 { 1976 struct wdc_softc *wdc = chp->ch_wdc; 1977 int s; 1978 1979 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1980 (*wdc->free_hw)(chp); 1981 s = splbio(); 1982 chp->ch_flags &= ~WDCF_ACTIVE; 1983 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1984 pool_put(&wdc_xfer_pool, xfer); 1985 splx(s); 1986 } 1987 1988 /* 1989 * Kill off all pending xfers for a wdc_channel. 1990 * 1991 * Must be called at splbio(). 1992 */ 1993 void 1994 wdc_kill_pending(struct wdc_channel *chp) 1995 { 1996 struct ata_xfer *xfer; 1997 1998 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 1999 chp = xfer->c_chp; 2000 (*xfer->c_kill_xfer)(chp, xfer); 2001 } 2002 } 2003 2004 static void 2005 __wdcerror(struct wdc_channel *chp, char *msg) 2006 { 2007 struct wdc_softc *wdc = chp->ch_wdc; 2008 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2009 2010 if (xfer == NULL) 2011 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2012 msg); 2013 else 2014 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2015 chp->ch_channel, xfer->c_drive, msg); 2016 } 2017 2018 /* 2019 * the bit bucket 2020 */ 2021 void 2022 wdcbit_bucket(struct wdc_channel *chp, int size) 2023 { 2024 2025 for (; size >= 2; size -= 2) 2026 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2027 if (size) 2028 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2029 } 2030 2031 int 2032 wdc_addref(struct wdc_channel *chp) 2033 { 2034 struct wdc_softc *wdc = chp->ch_wdc; 2035 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2036 int s, error = 0; 2037 2038 s = splbio(); 2039 if (adapt->adapt_refcnt++ == 0 && 2040 adapt->adapt_enable != NULL) { 2041 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2042 if (error) 2043 adapt->adapt_refcnt--; 2044 } 2045 splx(s); 2046 return (error); 2047 } 2048 2049 void 2050 wdc_delref(struct wdc_channel *chp) 2051 { 2052 struct wdc_softc *wdc = chp->ch_wdc; 2053 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2054 int s; 2055 2056 s = splbio(); 2057 if (adapt->adapt_refcnt-- == 1 && 2058 adapt->adapt_enable != NULL) 2059 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2060 splx(s); 2061 } 2062 2063 void 2064 wdc_print_modes(struct wdc_channel *chp) 2065 { 2066 struct wdc_softc *wdc = chp->ch_wdc; 2067 int drive; 2068 struct ata_drive_datas *drvp; 2069 2070 for (drive = 0; drive < 2; drive++) { 2071 drvp = &chp->ch_drive[drive]; 2072 if ((drvp->drive_flags & DRIVE) == 0) 2073 continue; 2074 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2075 drvp->drv_softc->dv_xname, 2076 wdc->sc_dev.dv_xname, 2077 chp->ch_channel, drive, drvp->PIO_mode); 2078 if (drvp->drive_flags & DRIVE_DMA) 2079 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2080 if (drvp->drive_flags & DRIVE_UDMA) { 2081 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2082 if (drvp->UDMA_mode == 2) 2083 aprint_normal(" (Ultra/33)"); 2084 else if (drvp->UDMA_mode == 4) 2085 aprint_normal(" (Ultra/66)"); 2086 else if (drvp->UDMA_mode == 5) 2087 aprint_normal(" (Ultra/100)"); 2088 else if (drvp->UDMA_mode == 6) 2089 aprint_normal(" (Ultra/133)"); 2090 } 2091 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2092 aprint_normal(" (using DMA data transfers)"); 2093 aprint_normal("\n"); 2094 } 2095 } 2096
Indexes created Tue Sep 23 21:09:50 GMT 2025