wdc.c revision 1.175
1 /* $NetBSD: wdc.c,v 1.175 2004/05/24 20:45:30 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.175 2004/05/24 20:45:30 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, 152 int); 153 static int __wdcwait(struct wdc_channel *, int, int, int); 154 155 #define DEBUG_INTR 0x01 156 #define DEBUG_XFERS 0x02 157 #define DEBUG_STATUS 0x04 158 #define DEBUG_FUNCS 0x08 159 #define DEBUG_PROBE 0x10 160 #define DEBUG_DETACH 0x20 161 #define DEBUG_DELAY 0x40 162 #ifdef WDCDEBUG 163 int wdcdebug_mask = 0; 164 int wdc_nxfer = 0; 165 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 166 #else 167 #define WDCDEBUG_PRINT(args, level) 168 #endif 169 170 /* 171 * A queue of atabus instances, used to ensure the same bus probe order 172 * for a given hardware configuration at each boot. 173 */ 174 struct atabus_initq_head atabus_initq_head = 175 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 176 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 177 178 /* Test to see controller with at last one attached drive is there. 179 * Returns a bit for each possible drive found (0x01 for drive 0, 180 * 0x02 for drive 1). 181 * Logic: 182 * - If a status register is at 0xff, assume there is no drive here 183 * (ISA has pull-up resistors). Similarly if the status register has 184 * the value we last wrote to the bus (for IDE interfaces without pullups). 185 * If no drive at all -> return. 186 * - reset the controller, wait for it to complete (may take up to 31s !). 187 * If timeout -> return. 188 * - test ATA/ATAPI signatures. If at last one drive found -> return. 189 * - try an ATA command on the master. 190 */ 191 192 static void 193 wdc_drvprobe(struct wdc_channel *chp) 194 { 195 struct ataparams params; 196 struct wdc_softc *wdc = chp->ch_wdc; 197 u_int8_t st0 = 0, st1 = 0; 198 int i, error; 199 200 if (wdcprobe1(chp, 0) == 0) { 201 /* No drives, abort the attach here. */ 202 return; 203 } 204 205 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 206 for (i = 0; i < mstohz(3000); i++) { 207 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 208 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 209 wdc->select(chp,0); 210 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 211 0, WDSD_IBM); 212 delay(10); /* 400ns delay */ 213 st0 = bus_space_read_1(chp->cmd_iot, 214 chp->cmd_iohs[wd_status], 0); 215 } 216 217 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 218 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 219 wdc->select(chp,1); 220 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 221 0, WDSD_IBM | 0x10); 222 delay(10); /* 400ns delay */ 223 st1 = bus_space_read_1(chp->cmd_iot, 224 chp->cmd_iohs[wd_status], 0); 225 } 226 227 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 228 == 0 || 229 (st0 & WDCS_DRDY)) && 230 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 231 == 0 || 232 (st1 & WDCS_DRDY))) 233 break; 234 tsleep(¶ms, PRIBIO, "atadrdy", 1); 235 } 236 if ((st0 & WDCS_DRDY) == 0) 237 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 238 if ((st1 & WDCS_DRDY) == 0) 239 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 240 241 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 242 wdc->sc_dev.dv_xname, 243 chp->ch_channel, st0, st1), DEBUG_PROBE); 244 245 /* Wait a bit, some devices are weird just after a reset. */ 246 delay(5000); 247 248 for (i = 0; i < 2; i++) { 249 /* XXX This should be done by other code. */ 250 chp->ch_drive[i].chnl_softc = chp; 251 chp->ch_drive[i].drive = i; 252 253 /* 254 * Init error counter so that an error withing the first xfers 255 * will trigger a downgrade 256 */ 257 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 258 259 /* If controller can't do 16bit flag the drives as 32bit */ 260 if ((wdc->cap & 261 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 262 WDC_CAPABILITY_DATA32) 263 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 264 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 265 continue; 266 267 /* Shortcut in case we've been shutdown */ 268 if (chp->ch_flags & WDCF_SHUTDOWN) 269 return; 270 271 /* issue an identify, to try to detect ghosts */ 272 error = ata_get_params(&chp->ch_drive[i], 273 AT_WAIT | AT_POLL, ¶ms); 274 if (error != CMD_OK) { 275 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 276 277 /* Shortcut in case we've been shutdown */ 278 if (chp->ch_flags & WDCF_SHUTDOWN) 279 return; 280 281 error = ata_get_params(&chp->ch_drive[i], 282 AT_WAIT | AT_POLL, ¶ms); 283 } 284 if (error == CMD_OK) { 285 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 286 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 287 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 288 } else { 289 chp->ch_drive[i].drive_flags &= 290 ~(DRIVE_ATA | DRIVE_ATAPI); 291 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 292 wdc->sc_dev.dv_xname, 293 chp->ch_channel, i, error), DEBUG_PROBE); 294 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 295 continue; 296 /* 297 * Pre-ATA drive ? 298 * Test registers writability (Error register not 299 * writable, but cyllo is), then try an ATA command. 300 */ 301 if (wdc->cap & WDC_CAPABILITY_SELECT) 302 wdc->select(chp,i); 303 bus_space_write_1(chp->cmd_iot, 304 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 305 delay(10); /* 400ns delay */ 306 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 307 0, 0x58); 308 bus_space_write_1(chp->cmd_iot, 309 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 310 if (bus_space_read_1(chp->cmd_iot, 311 chp->cmd_iohs[wd_error], 0) == 0x58 || 312 bus_space_read_1(chp->cmd_iot, 313 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 314 WDCDEBUG_PRINT(("%s:%d:%d: register " 315 "writability failed\n", 316 wdc->sc_dev.dv_xname, 317 chp->ch_channel, i), DEBUG_PROBE); 318 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 319 continue; 320 } 321 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 322 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 323 wdc->sc_dev.dv_xname, 324 chp->ch_channel, i), DEBUG_PROBE); 325 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 326 continue; 327 } 328 bus_space_write_1(chp->cmd_iot, 329 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 330 delay(10); /* 400ns delay */ 331 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 332 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 333 wdc->sc_dev.dv_xname, 334 chp->ch_channel, i), DEBUG_PROBE); 335 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 336 } else { 337 chp->ch_drive[0].drive_flags &= 338 ~(DRIVE_ATA | DRIVE_ATAPI); 339 chp->ch_drive[1].drive_flags &= 340 ~(DRIVE_ATA | DRIVE_ATAPI); 341 } 342 } 343 } 344 } 345 346 void 347 atabusconfig(struct atabus_softc *atabus_sc) 348 { 349 struct wdc_channel *chp = atabus_sc->sc_chan; 350 struct wdc_softc *wdc = chp->ch_wdc; 351 int i, error, need_delref = 0; 352 struct atabus_initq *atabus_initq = NULL; 353 354 if ((error = wdc_addref(chp)) != 0) { 355 aprint_error("%s: unable to enable controller\n", 356 wdc->sc_dev.dv_xname); 357 goto out; 358 } 359 need_delref = 1; 360 361 /* Probe for the drives. */ 362 (*wdc->drv_probe)(chp); 363 364 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 365 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 366 DEBUG_PROBE); 367 368 /* If no drives, abort here */ 369 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 370 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 371 goto out; 372 373 /* Shortcut in case we've been shutdown */ 374 if (chp->ch_flags & WDCF_SHUTDOWN) 375 goto out; 376 377 /* Make sure the devices probe in atabus order to avoid jitter. */ 378 simple_lock(&atabus_interlock); 379 while(1) { 380 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 381 if (atabus_initq->atabus_sc == atabus_sc) 382 break; 383 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 384 &atabus_interlock); 385 } 386 simple_unlock(&atabus_interlock); 387 388 /* 389 * Attach an ATAPI bus, if needed. 390 */ 391 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 392 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 393 #if NATAPIBUS > 0 394 wdc_atapibus_attach(atabus_sc); 395 #else 396 /* 397 * Fake the autoconfig "not configured" message 398 */ 399 aprint_normal("atapibus at %s not configured\n", 400 wdc->sc_dev.dv_xname); 401 chp->atapibus = NULL; 402 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 403 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 404 #endif 405 } 406 407 for (i = 0; i < 2; i++) { 408 struct ata_device adev; 409 if ((chp->ch_drive[i].drive_flags & 410 (DRIVE_ATA | DRIVE_OLD)) == 0) { 411 continue; 412 } 413 memset(&adev, 0, sizeof(struct ata_device)); 414 adev.adev_bustype = &wdc_ata_bustype; 415 adev.adev_channel = chp->ch_channel; 416 adev.adev_openings = 1; 417 adev.adev_drv_data = &chp->ch_drive[i]; 418 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 419 &adev, ataprint); 420 if (chp->ata_drives[i] != NULL) 421 wdc_probe_caps(&chp->ch_drive[i]); 422 else 423 chp->ch_drive[i].drive_flags &= 424 ~(DRIVE_ATA | DRIVE_OLD); 425 } 426 427 /* now that we know the drives, the controller can set its modes */ 428 if (wdc->cap & WDC_CAPABILITY_MODE) { 429 wdc->set_modes(chp); 430 wdc_print_modes(chp); 431 } 432 #if NATARAID > 0 433 if (wdc->cap & WDC_CAPABILITY_RAID) 434 for (i = 0; i < 2; i++) 435 if (chp->ata_drives[i] != NULL) 436 ata_raid_check_component(chp->ata_drives[i]); 437 #endif /* NATARAID > 0 */ 438 439 /* 440 * reset drive_flags for unattached devices, reset state for attached 441 * ones 442 */ 443 for (i = 0; i < 2; i++) { 444 if (chp->ch_drive[i].drv_softc == NULL) 445 chp->ch_drive[i].drive_flags = 0; 446 else 447 chp->ch_drive[i].state = 0; 448 } 449 450 out: 451 if (atabus_initq == NULL) { 452 simple_lock(&atabus_interlock); 453 while(1) { 454 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 455 if (atabus_initq->atabus_sc == atabus_sc) 456 break; 457 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 458 &atabus_interlock); 459 } 460 simple_unlock(&atabus_interlock); 461 } 462 simple_lock(&atabus_interlock); 463 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 464 simple_unlock(&atabus_interlock); 465 466 free(atabus_initq, M_DEVBUF); 467 wakeup(&atabus_initq_head); 468 469 config_pending_decr(); 470 if (need_delref) 471 wdc_delref(chp); 472 } 473 474 int 475 wdcprobe(struct wdc_channel *chp) 476 { 477 478 return (wdcprobe1(chp, 1)); 479 } 480 481 static int 482 wdcprobe1(struct wdc_channel *chp, int poll) 483 { 484 struct wdc_softc *wdc = chp->ch_wdc; 485 u_int8_t st0, st1, sc, sn, cl, ch; 486 u_int8_t ret_value = 0x03; 487 u_int8_t drive; 488 int s; 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if (wdc == NULL || 496 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 497 498 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 499 wdc->select(chp,0); 500 501 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 502 WDSD_IBM); 503 delay(10); /* 400ns delay */ 504 st0 = bus_space_read_1(chp->cmd_iot, 505 chp->cmd_iohs[wd_status], 0); 506 507 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 508 wdc->select(chp,1); 509 510 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 511 WDSD_IBM | 0x10); 512 delay(10); /* 400ns delay */ 513 st1 = bus_space_read_1(chp->cmd_iot, 514 chp->cmd_iohs[wd_status], 0); 515 516 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 517 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 518 chp->ch_channel, st0, st1), DEBUG_PROBE); 519 520 if (st0 == 0xff || st0 == WDSD_IBM) 521 ret_value &= ~0x01; 522 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 523 ret_value &= ~0x02; 524 /* Register writability test, drive 0. */ 525 if (ret_value & 0x01) { 526 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 527 wdc->select(chp,0); 528 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 529 0, WDSD_IBM); 530 bus_space_write_1(chp->cmd_iot, 531 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 532 cl = bus_space_read_1(chp->cmd_iot, 533 chp->cmd_iohs[wd_cyl_lo], 0); 534 if (cl != 0x02) { 535 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 536 "got 0x%x != 0x02\n", 537 wdc != NULL ? 538 wdc->sc_dev.dv_xname : "wdcprobe", 539 chp->ch_channel, cl), 540 DEBUG_PROBE); 541 ret_value &= ~0x01; 542 } 543 bus_space_write_1(chp->cmd_iot, 544 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 545 cl = bus_space_read_1(chp->cmd_iot, 546 chp->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x01) { 548 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x01\n", 550 wdc != NULL ? 551 wdc->sc_dev.dv_xname : "wdcprobe", 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 wdc != NULL ? 564 wdc->sc_dev.dv_xname : "wdcprobe", 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x01; 568 } 569 bus_space_write_1(chp->cmd_iot, 570 chp->cmd_iohs[wd_sector], 0, 0x02); 571 cl = bus_space_read_1(chp->cmd_iot, 572 chp->cmd_iohs[wd_sector], 0); 573 if (cl != 0x02) { 574 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 575 "got 0x%x != 0x02\n", 576 wdc != NULL ? 577 wdc->sc_dev.dv_xname : "wdcprobe", 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x01; 581 } 582 cl = bus_space_read_1(chp->cmd_iot, 583 chp->cmd_iohs[wd_cyl_lo], 0); 584 if (cl != 0x01) { 585 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 586 "got 0x%x != 0x01\n", 587 wdc != NULL ? 588 wdc->sc_dev.dv_xname : "wdcprobe", 589 chp->ch_channel, cl), 590 DEBUG_PROBE); 591 ret_value &= ~0x01; 592 } 593 } 594 /* Register writability test, drive 1. */ 595 if (ret_value & 0x02) { 596 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 597 wdc->select(chp,1); 598 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 599 0, WDSD_IBM | 0x10); 600 bus_space_write_1(chp->cmd_iot, 601 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 602 cl = bus_space_read_1(chp->cmd_iot, 603 chp->cmd_iohs[wd_cyl_lo], 0); 604 if (cl != 0x02) { 605 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 606 "got 0x%x != 0x02\n", 607 wdc != NULL ? 608 wdc->sc_dev.dv_xname : "wdcprobe", 609 chp->ch_channel, cl), 610 DEBUG_PROBE); 611 ret_value &= ~0x02; 612 } 613 bus_space_write_1(chp->cmd_iot, 614 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 615 cl = bus_space_read_1(chp->cmd_iot, 616 chp->cmd_iohs[wd_cyl_lo], 0); 617 if (cl != 0x01) { 618 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 619 "got 0x%x != 0x01\n", 620 wdc != NULL ? 621 wdc->sc_dev.dv_xname : "wdcprobe", 622 chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_sector], 0, 0x01); 628 cl = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_sector], 0); 630 if (cl != 0x01) { 631 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 632 "got 0x%x != 0x01\n", 633 wdc != NULL ? 634 wdc->sc_dev.dv_xname : "wdcprobe", 635 chp->ch_channel, cl), 636 DEBUG_PROBE); 637 ret_value &= ~0x02; 638 } 639 bus_space_write_1(chp->cmd_iot, 640 chp->cmd_iohs[wd_sector], 0, 0x02); 641 cl = bus_space_read_1(chp->cmd_iot, 642 chp->cmd_iohs[wd_sector], 0); 643 if (cl != 0x02) { 644 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 645 "got 0x%x != 0x02\n", 646 wdc != NULL ? 647 wdc->sc_dev.dv_xname : "wdcprobe", 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 cl = bus_space_read_1(chp->cmd_iot, 653 chp->cmd_iohs[wd_cyl_lo], 0); 654 if (cl != 0x01) { 655 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 656 "got 0x%x != 0x01\n", 657 wdc != NULL ? 658 wdc->sc_dev.dv_xname : "wdcprobe", 659 chp->ch_channel, cl), 660 DEBUG_PROBE); 661 ret_value &= ~0x02; 662 } 663 } 664 665 if (ret_value == 0) { 666 splx(s); 667 return 0; 668 } 669 } 670 671 672 /* 673 * reset bus. Also send an ATAPI_RESET to devices, in case there are 674 * ATAPI device out there which don't react to the bus reset 675 */ 676 if (ret_value & 0x01) { 677 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 678 wdc->select(chp,0); 679 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 680 0, WDSD_IBM); 681 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 682 ATAPI_SOFT_RESET); 683 } 684 if (ret_value & 0x02) { 685 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 686 wdc->select(chp,0); 687 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 688 0, WDSD_IBM | 0x10); 689 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 690 ATAPI_SOFT_RESET); 691 } 692 693 delay(5000); 694 695 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 696 wdc->select(chp,0); 697 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 698 delay(10); /* 400ns delay */ 699 /* assert SRST, wait for reset to complete */ 700 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 701 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 702 DELAY(1000); 703 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 704 WDCTL_IDS | WDCTL_4BIT); 705 DELAY(2000); 706 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 707 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 708 delay(10); /* 400ns delay */ 709 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 710 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 711 wdc->irqack(chp); 712 splx(s); 713 714 ret_value = __wdcwait_reset(chp, ret_value, poll); 715 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 716 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 717 ret_value), DEBUG_PROBE); 718 719 /* if reset failed, there's nothing here */ 720 if (ret_value == 0) 721 return 0; 722 723 /* 724 * Test presence of drives. First test register signatures looking 725 * for ATAPI devices. If it's not an ATAPI and reset said there may 726 * be something here assume it's ATA or OLD. Ghost will be killed 727 * later in attach routine. 728 */ 729 for (drive = 0; drive < 2; drive++) { 730 if ((ret_value & (0x01 << drive)) == 0) 731 continue; 732 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 733 wdc->select(chp,drive); 734 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 735 WDSD_IBM | (drive << 4)); 736 delay(10); /* 400ns delay */ 737 /* Save registers contents */ 738 sc = bus_space_read_1(chp->cmd_iot, 739 chp->cmd_iohs[wd_seccnt], 0); 740 sn = bus_space_read_1(chp->cmd_iot, 741 chp->cmd_iohs[wd_sector], 0); 742 cl = bus_space_read_1(chp->cmd_iot, 743 chp->cmd_iohs[wd_cyl_lo], 0); 744 ch = bus_space_read_1(chp->cmd_iot, 745 chp->cmd_iohs[wd_cyl_hi], 0); 746 747 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 748 "cl=0x%x ch=0x%x\n", 749 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 750 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 751 /* 752 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 753 * we get wrong values here, so ignore it. 754 */ 755 if (cl == 0x14 && ch == 0xeb) { 756 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 757 } else { 758 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 759 if (wdc == NULL || 760 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 761 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 762 } 763 } 764 return (ret_value); 765 } 766 767 void 768 wdcattach(struct wdc_channel *chp) 769 { 770 struct wdc_softc *wdc = chp->ch_wdc; 771 static int inited = 0; 772 773 if (chp->ch_flags & WDCF_DISABLED) 774 return; 775 776 /* initialise global data */ 777 callout_init(&chp->ch_callout); 778 if (wdc->drv_probe == NULL) 779 wdc->drv_probe = wdc_drvprobe; 780 if (inited == 0) { 781 /* Initialize the ata_xfer pool. */ 782 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 783 0, 0, "wdcspl", NULL); 784 inited++; 785 } 786 TAILQ_INIT(&chp->ch_queue->queue_xfer); 787 chp->ch_queue->queue_freeze = 0; 788 789 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 790 } 791 792 int 793 wdcactivate(struct device *self, enum devact act) 794 { 795 struct wdc_softc *wdc = (struct wdc_softc *)self; 796 int s, i, error = 0; 797 798 s = splbio(); 799 switch (act) { 800 case DVACT_ACTIVATE: 801 error = EOPNOTSUPP; 802 break; 803 804 case DVACT_DEACTIVATE: 805 for (i = 0; i < wdc->nchannels; i++) { 806 error = config_deactivate(wdc->channels[i]->atabus); 807 if (error) 808 break; 809 } 810 break; 811 } 812 splx(s); 813 return (error); 814 } 815 816 int 817 wdcdetach(struct device *self, int flags) 818 { 819 struct wdc_softc *wdc = (struct wdc_softc *)self; 820 struct wdc_channel *chp; 821 int i, error = 0; 822 823 for (i = 0; i < wdc->nchannels; i++) { 824 chp = wdc->channels[i]; 825 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 826 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 827 error = config_detach(chp->atabus, flags); 828 if (error) 829 break; 830 } 831 return (error); 832 } 833 834 /* 835 * Start I/O on a controller, for the given channel. 836 * The first xfer may be not for our channel if the channel queues 837 * are shared. 838 */ 839 void 840 wdcstart(struct wdc_channel *chp) 841 { 842 struct wdc_softc *wdc = chp->ch_wdc; 843 struct ata_xfer *xfer; 844 845 #ifdef WDC_DIAGNOSTIC 846 int spl1, spl2; 847 848 spl1 = splbio(); 849 spl2 = splbio(); 850 if (spl2 != spl1) { 851 printf("wdcstart: not at splbio()\n"); 852 panic("wdcstart"); 853 } 854 splx(spl2); 855 splx(spl1); 856 #endif /* WDC_DIAGNOSTIC */ 857 858 /* is there a xfer ? */ 859 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 860 return; 861 862 /* adjust chp, in case we have a shared queue */ 863 chp = xfer->c_chp; 864 865 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 866 return; /* channel aleady active */ 867 } 868 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 869 return; /* queue froozen */ 870 } 871 #ifdef DIAGNOSTIC 872 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 873 panic("wdcstart: channel waiting for irq"); 874 #endif 875 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 876 if (!(*wdc->claim_hw)(chp, 0)) 877 return; 878 879 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 880 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 881 chp->ch_flags |= WDCF_ACTIVE; 882 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 883 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 884 chp->ch_drive[xfer->c_drive].state = 0; 885 } 886 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 887 KASSERT(xfer->c_flags & C_POLL); 888 xfer->c_start(chp, xfer); 889 } 890 891 /* restart an interrupted I/O */ 892 void 893 wdcrestart(void *v) 894 { 895 struct wdc_channel *chp = v; 896 int s; 897 898 s = splbio(); 899 wdcstart(chp); 900 splx(s); 901 } 902 903 904 /* 905 * Interrupt routine for the controller. Acknowledge the interrupt, check for 906 * errors on the current operation, mark it done if necessary, and start the 907 * next request. Also check for a partially done transfer, and continue with 908 * the next chunk if so. 909 */ 910 int 911 wdcintr(void *arg) 912 { 913 struct wdc_channel *chp = arg; 914 struct wdc_softc *wdc = chp->ch_wdc; 915 struct ata_xfer *xfer; 916 int ret; 917 918 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 919 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 920 DEBUG_INTR); 921 return (0); 922 } 923 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 924 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 925 /* try to clear the pending interrupt anyway */ 926 (void)bus_space_read_1(chp->cmd_iot, 927 chp->cmd_iohs[wd_status], 0); 928 return (0); 929 } 930 931 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 932 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 933 if (chp->ch_flags & WDCF_DMA_WAIT) { 934 wdc->dma_status = 935 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 936 xfer->c_drive, 0); 937 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 938 /* IRQ not for us, not detected by DMA engine */ 939 return 0; 940 } 941 chp->ch_flags &= ~WDCF_DMA_WAIT; 942 } 943 chp->ch_flags &= ~WDCF_IRQ_WAIT; 944 ret = xfer->c_intr(chp, xfer, 1); 945 if (ret == 0) /* irq was not for us, still waiting for irq */ 946 chp->ch_flags |= WDCF_IRQ_WAIT; 947 return (ret); 948 } 949 950 /* Put all disk in RESET state */ 951 void 952 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 953 { 954 struct wdc_channel *chp = drvp->chnl_softc; 955 struct wdc_softc *wdc = chp->ch_wdc; 956 int drive; 957 958 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 959 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 960 DEBUG_FUNCS); 961 if ((flags & AT_POLL) == 0) { 962 if (chp->ch_flags & WDCF_TH_RESET) { 963 /* no need to schedule a reset more than one time */ 964 return; 965 } 966 chp->ch_flags |= WDCF_TH_RESET; 967 chp->ch_queue->queue_freeze++; 968 wakeup(&chp->ch_thread); 969 return; 970 } 971 (void) wdcreset(chp, RESET_POLL); 972 for (drive = 0; drive < 2; drive++) { 973 chp->ch_drive[drive].state = 0; 974 } 975 } 976 977 int 978 wdcreset(struct wdc_channel *chp, int poll) 979 { 980 struct wdc_softc *wdc = chp->ch_wdc; 981 int drv_mask1, drv_mask2; 982 int s = 0; 983 984 if (wdc->cap & WDC_CAPABILITY_SELECT) 985 wdc->select(chp,0); 986 if (poll != RESET_SLEEP) 987 s = splbio(); 988 /* master */ 989 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 990 delay(10); /* 400ns delay */ 991 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 992 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 993 delay(2000); 994 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 995 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 996 WDCTL_4BIT | WDCTL_IDS); 997 delay(10); /* 400ns delay */ 998 if (poll != RESET_SLEEP) { 999 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1000 wdc->irqack(chp); 1001 splx(s); 1002 } 1003 1004 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1005 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1006 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1007 (poll == RESET_SLEEP) ? 0 : 1); 1008 if (drv_mask2 != drv_mask1) { 1009 printf("%s channel %d: reset failed for", 1010 wdc->sc_dev.dv_xname, chp->ch_channel); 1011 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1012 printf(" drive 0"); 1013 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1014 printf(" drive 1"); 1015 printf("\n"); 1016 } 1017 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1018 return (drv_mask1 != drv_mask2) ? 1 : 0; 1019 } 1020 1021 static int 1022 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1023 { 1024 struct wdc_softc *wdc = chp->ch_wdc; 1025 int timeout, nloop; 1026 u_int8_t st0 = 0, st1 = 0; 1027 #ifdef WDCDEBUG 1028 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1029 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1030 #endif 1031 1032 if (poll) 1033 nloop = WDCNDELAY_RST; 1034 else 1035 nloop = WDC_RESET_WAIT * hz / 1000; 1036 /* wait for BSY to deassert */ 1037 for (timeout = 0; timeout < nloop; timeout++) { 1038 if ((drv_mask & 0x01) != 0) { 1039 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1040 wdc->select(chp,0); 1041 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1042 0, WDSD_IBM); /* master */ 1043 delay(10); 1044 st0 = bus_space_read_1(chp->cmd_iot, 1045 chp->cmd_iohs[wd_status], 0); 1046 #ifdef WDCDEBUG 1047 sc0 = bus_space_read_1(chp->cmd_iot, 1048 chp->cmd_iohs[wd_seccnt], 0); 1049 sn0 = bus_space_read_1(chp->cmd_iot, 1050 chp->cmd_iohs[wd_sector], 0); 1051 cl0 = bus_space_read_1(chp->cmd_iot, 1052 chp->cmd_iohs[wd_cyl_lo], 0); 1053 ch0 = bus_space_read_1(chp->cmd_iot, 1054 chp->cmd_iohs[wd_cyl_hi], 0); 1055 #endif 1056 } 1057 if ((drv_mask & 0x02) != 0) { 1058 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1059 wdc->select(chp,1); 1060 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1061 0, WDSD_IBM | 0x10); /* slave */ 1062 delay(10); 1063 st1 = bus_space_read_1(chp->cmd_iot, 1064 chp->cmd_iohs[wd_status], 0); 1065 #ifdef WDCDEBUG 1066 sc1 = bus_space_read_1(chp->cmd_iot, 1067 chp->cmd_iohs[wd_seccnt], 0); 1068 sn1 = bus_space_read_1(chp->cmd_iot, 1069 chp->cmd_iohs[wd_sector], 0); 1070 cl1 = bus_space_read_1(chp->cmd_iot, 1071 chp->cmd_iohs[wd_cyl_lo], 0); 1072 ch1 = bus_space_read_1(chp->cmd_iot, 1073 chp->cmd_iohs[wd_cyl_hi], 0); 1074 #endif 1075 } 1076 1077 if ((drv_mask & 0x01) == 0) { 1078 /* no master */ 1079 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1080 /* No master, slave is ready, it's done */ 1081 goto end; 1082 } 1083 } else if ((drv_mask & 0x02) == 0) { 1084 /* no slave */ 1085 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1086 /* No slave, master is ready, it's done */ 1087 goto end; 1088 } 1089 } else { 1090 /* Wait for both master and slave to be ready */ 1091 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1092 goto end; 1093 } 1094 } 1095 if (poll) 1096 delay(WDCDELAY); 1097 else 1098 tsleep(&nloop, PRIBIO, "atarst", 1); 1099 } 1100 /* Reset timed out. Maybe it's because drv_mask was not right */ 1101 if (st0 & WDCS_BSY) 1102 drv_mask &= ~0x01; 1103 if (st1 & WDCS_BSY) 1104 drv_mask &= ~0x02; 1105 end: 1106 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1107 "cl=0x%x ch=0x%x\n", 1108 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1109 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1110 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1111 "cl=0x%x ch=0x%x\n", 1112 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1113 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1114 1115 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1116 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1117 st0, st1), DEBUG_PROBE); 1118 1119 return drv_mask; 1120 } 1121 1122 /* 1123 * Wait for a drive to be !BSY, and have mask in its status register. 1124 * return -1 for a timeout after "timeout" ms. 1125 */ 1126 static int 1127 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1128 { 1129 struct wdc_softc *wdc = chp->ch_wdc; 1130 u_char status; 1131 int time = 0; 1132 1133 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1134 wdc->sc_dev.dv_xname : "none", 1135 chp->ch_channel), DEBUG_STATUS); 1136 chp->ch_error = 0; 1137 1138 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1139 1140 for (;;) { 1141 chp->ch_status = status = 1142 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1143 if ((status & (WDCS_BSY | mask)) == bits) 1144 break; 1145 if (++time > timeout) { 1146 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1147 "status %x error %x (mask 0x%x bits 0x%x)\n", 1148 time, status, 1149 bus_space_read_1(chp->cmd_iot, 1150 chp->cmd_iohs[wd_error], 0), mask, bits), 1151 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1152 return(WDCWAIT_TOUT); 1153 } 1154 delay(WDCDELAY); 1155 } 1156 #ifdef WDCDEBUG 1157 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1158 printf("__wdcwait: did busy-wait, time=%d\n", time); 1159 #endif 1160 if (status & WDCS_ERR) 1161 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1162 chp->cmd_iohs[wd_error], 0); 1163 #ifdef WDCNDELAY_DEBUG 1164 /* After autoconfig, there should be no long delays. */ 1165 if (!cold && time > WDCNDELAY_DEBUG) { 1166 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1167 if (xfer == NULL) 1168 printf("%s channel %d: warning: busy-wait took %dus\n", 1169 wdc->sc_dev.dv_xname, chp->ch_channel, 1170 WDCDELAY * time); 1171 else 1172 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1173 wdc->sc_dev.dv_xname, chp->ch_channel, 1174 xfer->drive, 1175 WDCDELAY * time); 1176 } 1177 #endif 1178 return(WDCWAIT_OK); 1179 } 1180 1181 /* 1182 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1183 * thread if possible 1184 */ 1185 int 1186 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1187 { 1188 int error, i, timeout_hz = mstohz(timeout); 1189 1190 if (timeout_hz == 0 || 1191 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1192 error = __wdcwait(chp, mask, bits, timeout); 1193 else { 1194 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1195 if (error != 0) { 1196 if ((chp->ch_flags & WDCF_TH_RUN) || 1197 (flags & AT_WAIT)) { 1198 /* 1199 * we're running in the channel thread 1200 * or some userland thread context 1201 */ 1202 for (i = 0; i < timeout_hz; i++) { 1203 if (__wdcwait(chp, mask, bits, 1204 WDCDELAY_POLL) == 0) { 1205 error = 0; 1206 break; 1207 } 1208 tsleep(&chp, PRIBIO, "atapoll", 1); 1209 } 1210 } else { 1211 /* 1212 * we're probably in interrupt context, 1213 * ask the thread to come back here 1214 */ 1215 #ifdef DIAGNOSTIC 1216 if (chp->ch_queue->queue_freeze > 0) 1217 panic("wdcwait: queue_freeze"); 1218 #endif 1219 chp->ch_queue->queue_freeze++; 1220 wakeup(&chp->ch_thread); 1221 return(WDCWAIT_THR); 1222 } 1223 } 1224 } 1225 return (error); 1226 } 1227 1228 1229 /* 1230 * Busy-wait for DMA to complete 1231 */ 1232 int 1233 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1234 { 1235 struct wdc_softc *wdc = chp->ch_wdc; 1236 int time; 1237 1238 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1239 wdc->dma_status = 1240 (*wdc->dma_finish)(wdc->dma_arg, 1241 chp->ch_channel, xfer->c_drive, 0); 1242 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1243 return 0; 1244 delay(WDCDELAY); 1245 } 1246 /* timeout, force a DMA halt */ 1247 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1248 chp->ch_channel, xfer->c_drive, 1); 1249 return 1; 1250 } 1251 1252 void 1253 wdctimeout(void *arg) 1254 { 1255 struct wdc_channel *chp = (struct wdc_channel *)arg; 1256 struct wdc_softc *wdc = chp->ch_wdc; 1257 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1258 int s; 1259 1260 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1261 1262 s = splbio(); 1263 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1264 __wdcerror(chp, "lost interrupt"); 1265 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1266 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1267 xfer->c_bcount, 1268 xfer->c_skip); 1269 if (chp->ch_flags & WDCF_DMA_WAIT) { 1270 wdc->dma_status = 1271 (*wdc->dma_finish)(wdc->dma_arg, 1272 chp->ch_channel, xfer->c_drive, 1); 1273 chp->ch_flags &= ~WDCF_DMA_WAIT; 1274 } 1275 /* 1276 * Call the interrupt routine. If we just missed an interrupt, 1277 * it will do what's needed. Else, it will take the needed 1278 * action (reset the device). 1279 * Before that we need to reinstall the timeout callback, 1280 * in case it will miss another irq while in this transfer 1281 * We arbitray chose it to be 1s 1282 */ 1283 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1284 xfer->c_flags |= C_TIMEOU; 1285 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1286 xfer->c_intr(chp, xfer, 1); 1287 } else 1288 __wdcerror(chp, "missing untimeout"); 1289 splx(s); 1290 } 1291 1292 /* 1293 * Probe drive's capabilities, for use by the controller later 1294 * Assumes drvp points to an existing drive. 1295 * XXX this should be a controller-indep function 1296 */ 1297 void 1298 wdc_probe_caps(struct ata_drive_datas *drvp) 1299 { 1300 struct ataparams params, params2; 1301 struct wdc_channel *chp = drvp->chnl_softc; 1302 struct wdc_softc *wdc = chp->ch_wdc; 1303 struct device *drv_dev = drvp->drv_softc; 1304 int i, printed; 1305 char *sep = ""; 1306 int cf_flags; 1307 1308 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1309 /* IDENTIFY failed. Can't tell more about the device */ 1310 return; 1311 } 1312 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1314 /* 1315 * Controller claims 16 and 32 bit transfers. 1316 * Re-do an IDENTIFY with 32-bit transfers, 1317 * and compare results. 1318 */ 1319 drvp->drive_flags |= DRIVE_CAP32; 1320 ata_get_params(drvp, AT_WAIT, ¶ms2); 1321 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1322 /* Not good. fall back to 16bits */ 1323 drvp->drive_flags &= ~DRIVE_CAP32; 1324 } else { 1325 aprint_normal("%s: 32-bit data port\n", 1326 drv_dev->dv_xname); 1327 } 1328 } 1329 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1330 if (params.atap_ata_major > 0x01 && 1331 params.atap_ata_major != 0xffff) { 1332 for (i = 14; i > 0; i--) { 1333 if (params.atap_ata_major & (1 << i)) { 1334 aprint_normal("%s: ATA version %d\n", 1335 drv_dev->dv_xname, i); 1336 drvp->ata_vers = i; 1337 break; 1338 } 1339 } 1340 } 1341 #endif 1342 1343 /* An ATAPI device is at last PIO mode 3 */ 1344 if (drvp->drive_flags & DRIVE_ATAPI) 1345 drvp->PIO_mode = 3; 1346 1347 /* 1348 * It's not in the specs, but it seems that some drive 1349 * returns 0xffff in atap_extensions when this field is invalid 1350 */ 1351 if (params.atap_extensions != 0xffff && 1352 (params.atap_extensions & WDC_EXT_MODES)) { 1353 printed = 0; 1354 /* 1355 * XXX some drives report something wrong here (they claim to 1356 * support PIO mode 8 !). As mode is coded on 3 bits in 1357 * SET FEATURE, limit it to 7 (so limit i to 4). 1358 * If higher mode than 7 is found, abort. 1359 */ 1360 for (i = 7; i >= 0; i--) { 1361 if ((params.atap_piomode_supp & (1 << i)) == 0) 1362 continue; 1363 if (i > 4) 1364 return; 1365 /* 1366 * See if mode is accepted. 1367 * If the controller can't set its PIO mode, 1368 * assume the defaults are good, so don't try 1369 * to set it 1370 */ 1371 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1372 /* 1373 * It's OK to pool here, it's fast enouth 1374 * to not bother waiting for interrupt 1375 */ 1376 if (ata_set_mode(drvp, 0x08 | (i + 3), 1377 AT_WAIT) != CMD_OK) 1378 continue; 1379 if (!printed) { 1380 aprint_normal("%s: drive supports PIO mode %d", 1381 drv_dev->dv_xname, i + 3); 1382 sep = ","; 1383 printed = 1; 1384 } 1385 /* 1386 * If controller's driver can't set its PIO mode, 1387 * get the highter one for the drive. 1388 */ 1389 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1390 wdc->PIO_cap >= i + 3) { 1391 drvp->PIO_mode = i + 3; 1392 drvp->PIO_cap = i + 3; 1393 break; 1394 } 1395 } 1396 if (!printed) { 1397 /* 1398 * We didn't find a valid PIO mode. 1399 * Assume the values returned for DMA are buggy too 1400 */ 1401 return; 1402 } 1403 drvp->drive_flags |= DRIVE_MODE; 1404 printed = 0; 1405 for (i = 7; i >= 0; i--) { 1406 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1407 continue; 1408 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1409 (wdc->cap & WDC_CAPABILITY_MODE)) 1410 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1411 != CMD_OK) 1412 continue; 1413 if (!printed) { 1414 aprint_normal("%s DMA mode %d", sep, i); 1415 sep = ","; 1416 printed = 1; 1417 } 1418 if (wdc->cap & WDC_CAPABILITY_DMA) { 1419 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1420 wdc->DMA_cap < i) 1421 continue; 1422 drvp->DMA_mode = i; 1423 drvp->DMA_cap = i; 1424 drvp->drive_flags |= DRIVE_DMA; 1425 } 1426 break; 1427 } 1428 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1429 printed = 0; 1430 for (i = 7; i >= 0; i--) { 1431 if ((params.atap_udmamode_supp & (1 << i)) 1432 == 0) 1433 continue; 1434 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1435 (wdc->cap & WDC_CAPABILITY_UDMA)) 1436 if (ata_set_mode(drvp, 0x40 | i, 1437 AT_WAIT) != CMD_OK) 1438 continue; 1439 if (!printed) { 1440 aprint_normal("%s Ultra-DMA mode %d", 1441 sep, i); 1442 if (i == 2) 1443 aprint_normal(" (Ultra/33)"); 1444 else if (i == 4) 1445 aprint_normal(" (Ultra/66)"); 1446 else if (i == 5) 1447 aprint_normal(" (Ultra/100)"); 1448 else if (i == 6) 1449 aprint_normal(" (Ultra/133)"); 1450 sep = ","; 1451 printed = 1; 1452 } 1453 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1454 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1455 wdc->UDMA_cap < i) 1456 continue; 1457 drvp->UDMA_mode = i; 1458 drvp->UDMA_cap = i; 1459 drvp->drive_flags |= DRIVE_UDMA; 1460 } 1461 break; 1462 } 1463 } 1464 aprint_normal("\n"); 1465 } 1466 1467 /* Try to guess ATA version here, if it didn't get reported */ 1468 if (drvp->ata_vers == 0) { 1469 if (drvp->drive_flags & DRIVE_UDMA) 1470 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1471 else if (drvp->PIO_cap > 2) 1472 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1473 } 1474 cf_flags = drv_dev->dv_cfdata->cf_flags; 1475 if (cf_flags & ATA_CONFIG_PIO_SET) { 1476 drvp->PIO_mode = 1477 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1478 drvp->drive_flags |= DRIVE_MODE; 1479 } 1480 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1481 /* don't care about DMA modes */ 1482 return; 1483 } 1484 if (cf_flags & ATA_CONFIG_DMA_SET) { 1485 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1486 ATA_CONFIG_DMA_DISABLE) { 1487 drvp->drive_flags &= ~DRIVE_DMA; 1488 } else { 1489 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1490 ATA_CONFIG_DMA_OFF; 1491 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1492 } 1493 } 1494 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1495 /* don't care about UDMA modes */ 1496 return; 1497 } 1498 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1499 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1500 ATA_CONFIG_UDMA_DISABLE) { 1501 drvp->drive_flags &= ~DRIVE_UDMA; 1502 } else { 1503 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1504 ATA_CONFIG_UDMA_OFF; 1505 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1506 } 1507 } 1508 } 1509 1510 /* 1511 * downgrade the transfer mode of a drive after an error. return 1 if 1512 * downgrade was possible, 0 otherwise. 1513 */ 1514 int 1515 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1516 { 1517 struct wdc_channel *chp = drvp->chnl_softc; 1518 struct wdc_softc *wdc = chp->ch_wdc; 1519 struct device *drv_dev = drvp->drv_softc; 1520 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1521 1522 /* if drive or controller don't know its mode, we can't do much */ 1523 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1524 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1525 return 0; 1526 /* current drive mode was set by a config flag, let it this way */ 1527 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1528 (cf_flags & ATA_CONFIG_DMA_SET) || 1529 (cf_flags & ATA_CONFIG_UDMA_SET)) 1530 return 0; 1531 1532 /* 1533 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1534 * Maybe we didn't properly notice the cable type 1535 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1536 * It helps in some cases. 1537 */ 1538 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1539 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1540 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1541 drv_dev->dv_xname, drvp->UDMA_mode); 1542 } 1543 1544 /* 1545 * If we were using ultra-DMA, don't downgrade to multiword DMA 1546 * if we noticed a CRC error. It has been noticed that CRC errors 1547 * in ultra-DMA lead to silent data corruption in multiword DMA. 1548 * Data corruption is less likely to occur in PIO mode. 1549 */ 1550 else if ((drvp->drive_flags & DRIVE_UDMA) && 1551 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1552 drvp->drive_flags &= ~DRIVE_UDMA; 1553 drvp->drive_flags |= DRIVE_DMA; 1554 drvp->DMA_mode = drvp->DMA_cap; 1555 printf("%s: transfer error, downgrading to DMA mode %d\n", 1556 drv_dev->dv_xname, drvp->DMA_mode); 1557 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1558 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1559 drvp->PIO_mode = drvp->PIO_cap; 1560 printf("%s: transfer error, downgrading to PIO mode %d\n", 1561 drv_dev->dv_xname, drvp->PIO_mode); 1562 } else /* already using PIO, can't downgrade */ 1563 return 0; 1564 1565 wdc->set_modes(chp); 1566 wdc_print_modes(chp); 1567 /* reset the channel, which will shedule all drives for setup */ 1568 wdc_reset_channel(drvp, flags); 1569 return 1; 1570 } 1571 1572 int 1573 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1574 { 1575 struct wdc_channel *chp = drvp->chnl_softc; 1576 struct wdc_softc *wdc = chp->ch_wdc; 1577 struct ata_xfer *xfer; 1578 int s, ret; 1579 1580 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1581 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1582 DEBUG_FUNCS); 1583 1584 /* set up an xfer and queue. Wait for completion */ 1585 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1586 WDC_NOSLEEP); 1587 if (xfer == NULL) { 1588 return WDC_TRY_AGAIN; 1589 } 1590 1591 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1592 wdc_c->flags |= AT_POLL; 1593 if (wdc_c->flags & AT_POLL) 1594 xfer->c_flags |= C_POLL; 1595 xfer->c_drive = drvp->drive; 1596 xfer->c_databuf = wdc_c->data; 1597 xfer->c_bcount = wdc_c->bcount; 1598 xfer->c_cmd = wdc_c; 1599 xfer->c_start = __wdccommand_start; 1600 xfer->c_intr = __wdccommand_intr; 1601 xfer->c_kill_xfer = __wdccommand_done; 1602 1603 s = splbio(); 1604 wdc_exec_xfer(chp, xfer); 1605 #ifdef DIAGNOSTIC 1606 if ((wdc_c->flags & AT_POLL) != 0 && 1607 (wdc_c->flags & AT_DONE) == 0) 1608 panic("wdc_exec_command: polled command not done"); 1609 #endif 1610 if (wdc_c->flags & AT_DONE) { 1611 ret = WDC_COMPLETE; 1612 } else { 1613 if (wdc_c->flags & AT_WAIT) { 1614 while ((wdc_c->flags & AT_DONE) == 0) { 1615 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1616 } 1617 ret = WDC_COMPLETE; 1618 } else { 1619 ret = WDC_QUEUED; 1620 } 1621 } 1622 splx(s); 1623 return ret; 1624 } 1625 1626 static void 1627 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1628 { 1629 struct wdc_softc *wdc = chp->ch_wdc; 1630 int drive = xfer->c_drive; 1631 struct wdc_command *wdc_c = xfer->c_cmd; 1632 1633 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1634 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1635 DEBUG_FUNCS); 1636 1637 if (wdc->cap & WDC_CAPABILITY_SELECT) 1638 wdc->select(chp,drive); 1639 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1640 WDSD_IBM | (drive << 4)); 1641 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1642 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1643 case WDCWAIT_OK: 1644 break; 1645 case WDCWAIT_TOUT: 1646 wdc_c->flags |= AT_TIMEOU; 1647 __wdccommand_done(chp, xfer); 1648 return; 1649 case WDCWAIT_THR: 1650 return; 1651 } 1652 if (wdc_c->flags & AT_POLL) { 1653 /* polled command, disable interrupts */ 1654 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1655 WDCTL_4BIT | WDCTL_IDS); 1656 } 1657 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1658 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1659 1660 if ((wdc_c->flags & AT_POLL) == 0) { 1661 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1662 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1663 wdctimeout, chp); 1664 return; 1665 } 1666 /* 1667 * Polled command. Wait for drive ready or drq. Done in intr(). 1668 * Wait for at last 400ns for status bit to be valid. 1669 */ 1670 delay(10); /* 400ns delay */ 1671 __wdccommand_intr(chp, xfer, 0); 1672 } 1673 1674 static int 1675 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1676 { 1677 struct wdc_softc *wdc = chp->ch_wdc; 1678 struct wdc_command *wdc_c = xfer->c_cmd; 1679 int bcount = wdc_c->bcount; 1680 char *data = wdc_c->data; 1681 int wflags; 1682 1683 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1684 /* both wait and poll, we can tsleep here */ 1685 wflags = AT_WAIT | AT_POLL; 1686 } else { 1687 wflags = AT_POLL; 1688 } 1689 1690 again: 1691 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1692 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1693 DEBUG_INTR); 1694 /* 1695 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1696 * Reselect again, it doesn't hurt for others commands, and the time 1697 * penalty for the extra regiter write is acceptable, 1698 * wdc_exec_command() isn't called often (mosly for autoconfig) 1699 */ 1700 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1701 WDSD_IBM | (xfer->c_drive << 4)); 1702 if ((wdc_c->flags & AT_XFDONE) != 0) { 1703 /* 1704 * We have completed a data xfer. The drive should now be 1705 * in its initial state 1706 */ 1707 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1708 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1709 wflags) == WDCWAIT_TOUT) { 1710 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1711 return 0; /* IRQ was not for us */ 1712 wdc_c->flags |= AT_TIMEOU; 1713 } 1714 goto out; 1715 } 1716 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1717 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1718 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1719 return 0; /* IRQ was not for us */ 1720 wdc_c->flags |= AT_TIMEOU; 1721 goto out; 1722 } 1723 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1724 wdc->irqack(chp); 1725 if (wdc_c->flags & AT_READ) { 1726 if ((chp->ch_status & WDCS_DRQ) == 0) { 1727 wdc_c->flags |= AT_TIMEOU; 1728 goto out; 1729 } 1730 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1731 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1732 0, (u_int32_t*)data, bcount >> 2); 1733 data += bcount & 0xfffffffc; 1734 bcount = bcount & 0x03; 1735 } 1736 if (bcount > 0) 1737 bus_space_read_multi_2(chp->cmd_iot, 1738 chp->cmd_iohs[wd_data], 0, 1739 (u_int16_t *)data, bcount >> 1); 1740 /* at this point the drive should be in its initial state */ 1741 wdc_c->flags |= AT_XFDONE; 1742 /* XXX should read status register here ? */ 1743 } else if (wdc_c->flags & AT_WRITE) { 1744 if ((chp->ch_status & WDCS_DRQ) == 0) { 1745 wdc_c->flags |= AT_TIMEOU; 1746 goto out; 1747 } 1748 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1749 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1750 0, (u_int32_t*)data, bcount >> 2); 1751 data += bcount & 0xfffffffc; 1752 bcount = bcount & 0x03; 1753 } 1754 if (bcount > 0) 1755 bus_space_write_multi_2(chp->cmd_iot, 1756 chp->cmd_iohs[wd_data], 0, 1757 (u_int16_t *)data, bcount >> 1); 1758 wdc_c->flags |= AT_XFDONE; 1759 if ((wdc_c->flags & AT_POLL) == 0) { 1760 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1761 callout_reset(&chp->ch_callout, 1762 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1763 return 1; 1764 } else { 1765 goto again; 1766 } 1767 } 1768 out: 1769 __wdccommand_done(chp, xfer); 1770 return 1; 1771 } 1772 1773 static void 1774 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1775 { 1776 struct wdc_softc *wdc = chp->ch_wdc; 1777 struct wdc_command *wdc_c = xfer->c_cmd; 1778 1779 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1780 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1781 DEBUG_FUNCS); 1782 1783 callout_stop(&chp->ch_callout); 1784 1785 if (chp->ch_status & WDCS_DWF) 1786 wdc_c->flags |= AT_DF; 1787 if (chp->ch_status & WDCS_ERR) { 1788 wdc_c->flags |= AT_ERROR; 1789 wdc_c->r_error = chp->ch_error; 1790 } 1791 wdc_c->flags |= AT_DONE; 1792 if ((wdc_c->flags & AT_READREG) != 0 && 1793 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1794 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1795 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1796 chp->cmd_iohs[wd_sdh], 0); 1797 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1798 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1799 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1800 chp->cmd_iohs[wd_cyl_lo], 0); 1801 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1802 chp->cmd_iohs[wd_sector], 0); 1803 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1804 chp->cmd_iohs[wd_seccnt], 0); 1805 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1806 chp->cmd_iohs[wd_error], 0); 1807 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1808 chp->cmd_iohs[wd_precomp], 0); 1809 } 1810 1811 if (wdc_c->flags & AT_POLL) { 1812 /* enable interrupts */ 1813 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1814 WDCTL_4BIT); 1815 delay(10); /* some drives need a little delay here */ 1816 } 1817 wdc_free_xfer(chp, xfer); 1818 if (wdc_c->flags & AT_WAIT) 1819 wakeup(wdc_c); 1820 else if (wdc_c->callback) 1821 wdc_c->callback(wdc_c->callback_arg); 1822 wdcstart(chp); 1823 return; 1824 } 1825 1826 /* 1827 * Send a command. The drive should be ready. 1828 * Assumes interrupts are blocked. 1829 */ 1830 void 1831 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1832 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1833 u_int8_t precomp) 1834 { 1835 struct wdc_softc *wdc = chp->ch_wdc; 1836 1837 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1838 "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname, 1839 chp->ch_channel, drive, command, cylin, head, sector, count, 1840 precomp), DEBUG_FUNCS); 1841 1842 if (wdc->cap & WDC_CAPABILITY_SELECT) 1843 wdc->select(chp,drive); 1844 1845 /* Select drive, head, and addressing mode. */ 1846 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1847 WDSD_IBM | (drive << 4) | head); 1848 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1849 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1850 precomp); 1851 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1852 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1853 0, cylin >> 8); 1854 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1855 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1856 1857 /* Send command. */ 1858 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1859 return; 1860 } 1861 1862 /* 1863 * Send a 48-bit addressing command. The drive should be ready. 1864 * Assumes interrupts are blocked. 1865 */ 1866 void 1867 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1868 u_int64_t blkno, u_int16_t count) 1869 { 1870 struct wdc_softc *wdc = chp->ch_wdc; 1871 1872 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1873 "count=%d\n", wdc->sc_dev.dv_xname, 1874 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1875 DEBUG_FUNCS); 1876 1877 if (wdc->cap & WDC_CAPABILITY_SELECT) 1878 wdc->select(chp,drive); 1879 1880 /* Select drive, head, and addressing mode. */ 1881 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1882 (drive << 4) | WDSD_LBA); 1883 1884 /* previous */ 1885 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1886 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1887 0, count >> 8); 1888 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1889 0, blkno >> 40); 1890 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1891 0, blkno >> 32); 1892 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1893 0, blkno >> 24); 1894 1895 /* current */ 1896 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1897 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1898 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1899 0, blkno >> 16); 1900 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1901 0, blkno >> 8); 1902 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1903 1904 /* Send command. */ 1905 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1906 return; 1907 } 1908 1909 /* 1910 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1911 * tested by the caller. 1912 */ 1913 void 1914 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1915 { 1916 struct wdc_softc *wdc = chp->ch_wdc; 1917 1918 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1919 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1920 DEBUG_FUNCS); 1921 1922 if (wdc->cap & WDC_CAPABILITY_SELECT) 1923 wdc->select(chp,drive); 1924 1925 /* Select drive. */ 1926 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1927 WDSD_IBM | (drive << 4)); 1928 1929 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1930 } 1931 1932 /* Add a command to the queue and start controller. Must be called at splbio */ 1933 void 1934 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1935 { 1936 1937 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1938 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 1939 1940 /* complete xfer setup */ 1941 xfer->c_chp = chp; 1942 1943 /* 1944 * If we are a polled command, and the list is not empty, 1945 * we are doing a dump. Drop the list to allow the polled command 1946 * to complete, we're going to reboot soon anyway. 1947 */ 1948 if ((xfer->c_flags & C_POLL) != 0 && 1949 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != NULL) { 1950 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1951 } 1952 /* insert at the end of command list */ 1953 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1954 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1955 chp->ch_flags), DEBUG_XFERS); 1956 wdcstart(chp); 1957 } 1958 1959 struct ata_xfer * 1960 wdc_get_xfer(int flags) 1961 { 1962 struct ata_xfer *xfer; 1963 int s; 1964 1965 s = splbio(); 1966 xfer = pool_get(&wdc_xfer_pool, 1967 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1968 splx(s); 1969 if (xfer != NULL) { 1970 memset(xfer, 0, sizeof(struct ata_xfer)); 1971 } 1972 return xfer; 1973 } 1974 1975 void 1976 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 1977 { 1978 struct wdc_softc *wdc = chp->ch_wdc; 1979 int s; 1980 1981 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1982 (*wdc->free_hw)(chp); 1983 s = splbio(); 1984 chp->ch_flags &= ~WDCF_ACTIVE; 1985 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 1986 pool_put(&wdc_xfer_pool, xfer); 1987 splx(s); 1988 } 1989 1990 /* 1991 * Kill off all pending xfers for a wdc_channel. 1992 * 1993 * Must be called at splbio(). 1994 */ 1995 void 1996 wdc_kill_pending(struct wdc_channel *chp) 1997 { 1998 struct ata_xfer *xfer; 1999 2000 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 2001 chp = xfer->c_chp; 2002 (*xfer->c_kill_xfer)(chp, xfer); 2003 } 2004 } 2005 2006 static void 2007 __wdcerror(struct wdc_channel *chp, char *msg) 2008 { 2009 struct wdc_softc *wdc = chp->ch_wdc; 2010 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2011 2012 if (xfer == NULL) 2013 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2014 msg); 2015 else 2016 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2017 chp->ch_channel, xfer->c_drive, msg); 2018 } 2019 2020 /* 2021 * the bit bucket 2022 */ 2023 void 2024 wdcbit_bucket(struct wdc_channel *chp, int size) 2025 { 2026 2027 for (; size >= 2; size -= 2) 2028 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2029 if (size) 2030 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2031 } 2032 2033 int 2034 wdc_addref(struct wdc_channel *chp) 2035 { 2036 struct wdc_softc *wdc = chp->ch_wdc; 2037 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2038 int s, error = 0; 2039 2040 s = splbio(); 2041 if (adapt->adapt_refcnt++ == 0 && 2042 adapt->adapt_enable != NULL) { 2043 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2044 if (error) 2045 adapt->adapt_refcnt--; 2046 } 2047 splx(s); 2048 return (error); 2049 } 2050 2051 void 2052 wdc_delref(struct wdc_channel *chp) 2053 { 2054 struct wdc_softc *wdc = chp->ch_wdc; 2055 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2056 int s; 2057 2058 s = splbio(); 2059 if (adapt->adapt_refcnt-- == 1 && 2060 adapt->adapt_enable != NULL) 2061 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2062 splx(s); 2063 } 2064 2065 void 2066 wdc_print_modes(struct wdc_channel *chp) 2067 { 2068 struct wdc_softc *wdc = chp->ch_wdc; 2069 int drive; 2070 struct ata_drive_datas *drvp; 2071 2072 for (drive = 0; drive < 2; drive++) { 2073 drvp = &chp->ch_drive[drive]; 2074 if ((drvp->drive_flags & DRIVE) == 0) 2075 continue; 2076 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2077 drvp->drv_softc->dv_xname, 2078 wdc->sc_dev.dv_xname, 2079 chp->ch_channel, drive, drvp->PIO_mode); 2080 if (drvp->drive_flags & DRIVE_DMA) 2081 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2082 if (drvp->drive_flags & DRIVE_UDMA) { 2083 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2084 if (drvp->UDMA_mode == 2) 2085 aprint_normal(" (Ultra/33)"); 2086 else if (drvp->UDMA_mode == 4) 2087 aprint_normal(" (Ultra/66)"); 2088 else if (drvp->UDMA_mode == 5) 2089 aprint_normal(" (Ultra/100)"); 2090 else if (drvp->UDMA_mode == 6) 2091 aprint_normal(" (Ultra/133)"); 2092 } 2093 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2094 aprint_normal(" (using DMA data transfers)"); 2095 aprint_normal("\n"); 2096 } 2097 } 2098
Indexes created Thu Sep 25 02:09:54 GMT 2025