wdc.c revision 1.182
1 /* $NetBSD: wdc.c,v 1.182 2004/07/31 21:26:42 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.182 2004/07/31 21:26:42 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdc_reset_channel(struct wdc_channel *, int); 150 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 151 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 152 static void __wdccommand_kill_xfer(struct wdc_channel *, 153 struct ata_xfer *, int); 154 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 155 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 156 static int __wdcwait(struct wdc_channel *, int, int, int); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef WDCDEBUG 166 int wdcdebug_mask = 0; 167 int wdc_nxfer = 0; 168 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 169 #else 170 #define WDCDEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * A queue of atabus instances, used to ensure the same bus probe order 175 * for a given hardware configuration at each boot. 176 */ 177 struct atabus_initq_head atabus_initq_head = 178 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 179 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct wdc_channel *chp) 186 { 187 188 chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command]; 189 chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error]; 190 } 191 192 /* Test to see controller with at last one attached drive is there. 193 * Returns a bit for each possible drive found (0x01 for drive 0, 194 * 0x02 for drive 1). 195 * Logic: 196 * - If a status register is at 0xff, assume there is no drive here 197 * (ISA has pull-up resistors). Similarly if the status register has 198 * the value we last wrote to the bus (for IDE interfaces without pullups). 199 * If no drive at all -> return. 200 * - reset the controller, wait for it to complete (may take up to 31s !). 201 * If timeout -> return. 202 * - test ATA/ATAPI signatures. If at last one drive found -> return. 203 * - try an ATA command on the master. 204 */ 205 206 static void 207 wdc_drvprobe(struct wdc_channel *chp) 208 { 209 struct ataparams params; 210 struct wdc_softc *wdc = chp->ch_wdc; 211 u_int8_t st0 = 0, st1 = 0; 212 int i, error; 213 214 if (wdcprobe1(chp, 0) == 0) { 215 /* No drives, abort the attach here. */ 216 return; 217 } 218 219 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 220 for (i = 0; i < mstohz(3000); i++) { 221 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 222 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 223 wdc->select(chp,0); 224 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 225 0, WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st0 = bus_space_read_1(chp->cmd_iot, 228 chp->cmd_iohs[wd_status], 0); 229 } 230 231 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 232 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 233 wdc->select(chp,1); 234 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 235 0, WDSD_IBM | 0x10); 236 delay(10); /* 400ns delay */ 237 st1 = bus_space_read_1(chp->cmd_iot, 238 chp->cmd_iohs[wd_status], 0); 239 } 240 241 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 242 == 0 || 243 (st0 & WDCS_DRDY)) && 244 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 245 == 0 || 246 (st1 & WDCS_DRDY))) 247 break; 248 tsleep(¶ms, PRIBIO, "atadrdy", 1); 249 } 250 if ((st0 & WDCS_DRDY) == 0) 251 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 252 if ((st1 & WDCS_DRDY) == 0) 253 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 254 255 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 256 wdc->sc_dev.dv_xname, 257 chp->ch_channel, st0, st1), DEBUG_PROBE); 258 259 /* Wait a bit, some devices are weird just after a reset. */ 260 delay(5000); 261 262 for (i = 0; i < 2; i++) { 263 /* XXX This should be done by other code. */ 264 chp->ch_drive[i].chnl_softc = chp; 265 chp->ch_drive[i].drive = i; 266 267 /* 268 * Init error counter so that an error withing the first xfers 269 * will trigger a downgrade 270 */ 271 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 272 273 /* If controller can't do 16bit flag the drives as 32bit */ 274 if ((wdc->cap & 275 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 276 WDC_CAPABILITY_DATA32) 277 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 278 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 279 continue; 280 281 /* Shortcut in case we've been shutdown */ 282 if (chp->ch_flags & WDCF_SHUTDOWN) 283 return; 284 285 /* issue an identify, to try to detect ghosts */ 286 error = ata_get_params(&chp->ch_drive[i], 287 AT_WAIT | AT_POLL, ¶ms); 288 if (error != CMD_OK) { 289 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 290 291 /* Shortcut in case we've been shutdown */ 292 if (chp->ch_flags & WDCF_SHUTDOWN) 293 return; 294 295 error = ata_get_params(&chp->ch_drive[i], 296 AT_WAIT | AT_POLL, ¶ms); 297 } 298 if (error == CMD_OK) { 299 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 300 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 301 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 302 } else { 303 chp->ch_drive[i].drive_flags &= 304 ~(DRIVE_ATA | DRIVE_ATAPI); 305 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 306 wdc->sc_dev.dv_xname, 307 chp->ch_channel, i, error), DEBUG_PROBE); 308 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 309 continue; 310 /* 311 * Pre-ATA drive ? 312 * Test registers writability (Error register not 313 * writable, but cyllo is), then try an ATA command. 314 */ 315 if (wdc->cap & WDC_CAPABILITY_SELECT) 316 wdc->select(chp,i); 317 bus_space_write_1(chp->cmd_iot, 318 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 319 delay(10); /* 400ns delay */ 320 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 321 0, 0x58); 322 bus_space_write_1(chp->cmd_iot, 323 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 324 if (bus_space_read_1(chp->cmd_iot, 325 chp->cmd_iohs[wd_error], 0) == 0x58 || 326 bus_space_read_1(chp->cmd_iot, 327 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 328 WDCDEBUG_PRINT(("%s:%d:%d: register " 329 "writability failed\n", 330 wdc->sc_dev.dv_xname, 331 chp->ch_channel, i), DEBUG_PROBE); 332 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 333 continue; 334 } 335 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 336 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 337 wdc->sc_dev.dv_xname, 338 chp->ch_channel, i), DEBUG_PROBE); 339 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 340 continue; 341 } 342 bus_space_write_1(chp->cmd_iot, 343 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 344 delay(10); /* 400ns delay */ 345 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 346 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 347 wdc->sc_dev.dv_xname, 348 chp->ch_channel, i), DEBUG_PROBE); 349 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 350 } else { 351 chp->ch_drive[0].drive_flags &= 352 ~(DRIVE_ATA | DRIVE_ATAPI); 353 chp->ch_drive[1].drive_flags &= 354 ~(DRIVE_ATA | DRIVE_ATAPI); 355 } 356 } 357 } 358 } 359 360 void 361 atabusconfig(struct atabus_softc *atabus_sc) 362 { 363 struct wdc_channel *chp = atabus_sc->sc_chan; 364 struct wdc_softc *wdc = chp->ch_wdc; 365 int i, error, need_delref = 0; 366 struct atabus_initq *atabus_initq = NULL; 367 368 if ((error = wdc_addref(chp)) != 0) { 369 aprint_error("%s: unable to enable controller\n", 370 wdc->sc_dev.dv_xname); 371 goto out; 372 } 373 need_delref = 1; 374 375 /* Probe for the drives. */ 376 (*wdc->drv_probe)(chp); 377 378 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 379 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 380 DEBUG_PROBE); 381 382 /* If no drives, abort here */ 383 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 384 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 385 goto out; 386 387 /* Shortcut in case we've been shutdown */ 388 if (chp->ch_flags & WDCF_SHUTDOWN) 389 goto out; 390 391 /* Make sure the devices probe in atabus order to avoid jitter. */ 392 simple_lock(&atabus_interlock); 393 while(1) { 394 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 395 if (atabus_initq->atabus_sc == atabus_sc) 396 break; 397 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 398 &atabus_interlock); 399 } 400 simple_unlock(&atabus_interlock); 401 402 /* 403 * Attach an ATAPI bus, if needed. 404 */ 405 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 406 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 407 #if NATAPIBUS > 0 408 wdc_atapibus_attach(atabus_sc); 409 #else 410 /* 411 * Fake the autoconfig "not configured" message 412 */ 413 aprint_normal("atapibus at %s not configured\n", 414 wdc->sc_dev.dv_xname); 415 chp->atapibus = NULL; 416 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 417 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 418 #endif 419 } 420 421 for (i = 0; i < 2; i++) { 422 struct ata_device adev; 423 if ((chp->ch_drive[i].drive_flags & 424 (DRIVE_ATA | DRIVE_OLD)) == 0) { 425 continue; 426 } 427 memset(&adev, 0, sizeof(struct ata_device)); 428 adev.adev_bustype = &wdc_ata_bustype; 429 adev.adev_channel = chp->ch_channel; 430 adev.adev_openings = 1; 431 adev.adev_drv_data = &chp->ch_drive[i]; 432 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 433 &adev, ataprint); 434 if (chp->ata_drives[i] != NULL) 435 wdc_probe_caps(&chp->ch_drive[i]); 436 else 437 chp->ch_drive[i].drive_flags &= 438 ~(DRIVE_ATA | DRIVE_OLD); 439 } 440 441 /* now that we know the drives, the controller can set its modes */ 442 if (wdc->cap & WDC_CAPABILITY_MODE) { 443 wdc->set_modes(chp); 444 wdc_print_modes(chp); 445 } 446 #if NATARAID > 0 447 if (wdc->cap & WDC_CAPABILITY_RAID) 448 for (i = 0; i < 2; i++) 449 if (chp->ata_drives[i] != NULL) 450 ata_raid_check_component(chp->ata_drives[i]); 451 #endif /* NATARAID > 0 */ 452 453 /* 454 * reset drive_flags for unattached devices, reset state for attached 455 * ones 456 */ 457 for (i = 0; i < 2; i++) { 458 if (chp->ch_drive[i].drv_softc == NULL) 459 chp->ch_drive[i].drive_flags = 0; 460 else 461 chp->ch_drive[i].state = 0; 462 } 463 464 out: 465 if (atabus_initq == NULL) { 466 simple_lock(&atabus_interlock); 467 while(1) { 468 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 469 if (atabus_initq->atabus_sc == atabus_sc) 470 break; 471 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 472 &atabus_interlock); 473 } 474 simple_unlock(&atabus_interlock); 475 } 476 simple_lock(&atabus_interlock); 477 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 478 simple_unlock(&atabus_interlock); 479 480 free(atabus_initq, M_DEVBUF); 481 wakeup(&atabus_initq_head); 482 483 config_pending_decr(); 484 if (need_delref) 485 wdc_delref(chp); 486 } 487 488 int 489 wdcprobe(struct wdc_channel *chp) 490 { 491 492 return (wdcprobe1(chp, 1)); 493 } 494 495 static int 496 wdcprobe1(struct wdc_channel *chp, int poll) 497 { 498 struct wdc_softc *wdc = chp->ch_wdc; 499 u_int8_t st0, st1, sc, sn, cl, ch; 500 u_int8_t ret_value = 0x03; 501 u_int8_t drive; 502 int s; 503 504 /* 505 * Sanity check to see if the wdc channel responds at all. 506 */ 507 508 s = splbio(); 509 if (wdc == NULL || 510 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 511 512 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 513 wdc->select(chp,0); 514 515 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 516 WDSD_IBM); 517 delay(10); /* 400ns delay */ 518 st0 = bus_space_read_1(chp->cmd_iot, 519 chp->cmd_iohs[wd_status], 0); 520 521 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 522 wdc->select(chp,1); 523 524 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 525 WDSD_IBM | 0x10); 526 delay(10); /* 400ns delay */ 527 st1 = bus_space_read_1(chp->cmd_iot, 528 chp->cmd_iohs[wd_status], 0); 529 530 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 531 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 532 chp->ch_channel, st0, st1), DEBUG_PROBE); 533 534 if (st0 == 0xff || st0 == WDSD_IBM) 535 ret_value &= ~0x01; 536 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 537 ret_value &= ~0x02; 538 /* Register writability test, drive 0. */ 539 if (ret_value & 0x01) { 540 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 541 wdc->select(chp,0); 542 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 543 0, WDSD_IBM); 544 bus_space_write_1(chp->cmd_iot, 545 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 546 cl = bus_space_read_1(chp->cmd_iot, 547 chp->cmd_iohs[wd_cyl_lo], 0); 548 if (cl != 0x02) { 549 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 550 "got 0x%x != 0x02\n", 551 wdc != NULL ? 552 wdc->sc_dev.dv_xname : "wdcprobe", 553 chp->ch_channel, cl), 554 DEBUG_PROBE); 555 ret_value &= ~0x01; 556 } 557 bus_space_write_1(chp->cmd_iot, 558 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 559 cl = bus_space_read_1(chp->cmd_iot, 560 chp->cmd_iohs[wd_cyl_lo], 0); 561 if (cl != 0x01) { 562 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 563 "got 0x%x != 0x01\n", 564 wdc != NULL ? 565 wdc->sc_dev.dv_xname : "wdcprobe", 566 chp->ch_channel, cl), 567 DEBUG_PROBE); 568 ret_value &= ~0x01; 569 } 570 bus_space_write_1(chp->cmd_iot, 571 chp->cmd_iohs[wd_sector], 0, 0x01); 572 cl = bus_space_read_1(chp->cmd_iot, 573 chp->cmd_iohs[wd_sector], 0); 574 if (cl != 0x01) { 575 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 576 "got 0x%x != 0x01\n", 577 wdc != NULL ? 578 wdc->sc_dev.dv_xname : "wdcprobe", 579 chp->ch_channel, cl), 580 DEBUG_PROBE); 581 ret_value &= ~0x01; 582 } 583 bus_space_write_1(chp->cmd_iot, 584 chp->cmd_iohs[wd_sector], 0, 0x02); 585 cl = bus_space_read_1(chp->cmd_iot, 586 chp->cmd_iohs[wd_sector], 0); 587 if (cl != 0x02) { 588 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 589 "got 0x%x != 0x02\n", 590 wdc != NULL ? 591 wdc->sc_dev.dv_xname : "wdcprobe", 592 chp->ch_channel, cl), 593 DEBUG_PROBE); 594 ret_value &= ~0x01; 595 } 596 cl = bus_space_read_1(chp->cmd_iot, 597 chp->cmd_iohs[wd_cyl_lo], 0); 598 if (cl != 0x01) { 599 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 600 "got 0x%x != 0x01\n", 601 wdc != NULL ? 602 wdc->sc_dev.dv_xname : "wdcprobe", 603 chp->ch_channel, cl), 604 DEBUG_PROBE); 605 ret_value &= ~0x01; 606 } 607 } 608 /* Register writability test, drive 1. */ 609 if (ret_value & 0x02) { 610 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 611 wdc->select(chp,1); 612 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 613 0, WDSD_IBM | 0x10); 614 bus_space_write_1(chp->cmd_iot, 615 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 616 cl = bus_space_read_1(chp->cmd_iot, 617 chp->cmd_iohs[wd_cyl_lo], 0); 618 if (cl != 0x02) { 619 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 620 "got 0x%x != 0x02\n", 621 wdc != NULL ? 622 wdc->sc_dev.dv_xname : "wdcprobe", 623 chp->ch_channel, cl), 624 DEBUG_PROBE); 625 ret_value &= ~0x02; 626 } 627 bus_space_write_1(chp->cmd_iot, 628 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 629 cl = bus_space_read_1(chp->cmd_iot, 630 chp->cmd_iohs[wd_cyl_lo], 0); 631 if (cl != 0x01) { 632 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 633 "got 0x%x != 0x01\n", 634 wdc != NULL ? 635 wdc->sc_dev.dv_xname : "wdcprobe", 636 chp->ch_channel, cl), 637 DEBUG_PROBE); 638 ret_value &= ~0x02; 639 } 640 bus_space_write_1(chp->cmd_iot, 641 chp->cmd_iohs[wd_sector], 0, 0x01); 642 cl = bus_space_read_1(chp->cmd_iot, 643 chp->cmd_iohs[wd_sector], 0); 644 if (cl != 0x01) { 645 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 646 "got 0x%x != 0x01\n", 647 wdc != NULL ? 648 wdc->sc_dev.dv_xname : "wdcprobe", 649 chp->ch_channel, cl), 650 DEBUG_PROBE); 651 ret_value &= ~0x02; 652 } 653 bus_space_write_1(chp->cmd_iot, 654 chp->cmd_iohs[wd_sector], 0, 0x02); 655 cl = bus_space_read_1(chp->cmd_iot, 656 chp->cmd_iohs[wd_sector], 0); 657 if (cl != 0x02) { 658 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 659 "got 0x%x != 0x02\n", 660 wdc != NULL ? 661 wdc->sc_dev.dv_xname : "wdcprobe", 662 chp->ch_channel, cl), 663 DEBUG_PROBE); 664 ret_value &= ~0x02; 665 } 666 cl = bus_space_read_1(chp->cmd_iot, 667 chp->cmd_iohs[wd_cyl_lo], 0); 668 if (cl != 0x01) { 669 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 670 "got 0x%x != 0x01\n", 671 wdc != NULL ? 672 wdc->sc_dev.dv_xname : "wdcprobe", 673 chp->ch_channel, cl), 674 DEBUG_PROBE); 675 ret_value &= ~0x02; 676 } 677 } 678 679 if (ret_value == 0) { 680 splx(s); 681 return 0; 682 } 683 } 684 685 686 #if 0 /* XXX this break some ATA or ATAPI devices */ 687 /* 688 * reset bus. Also send an ATAPI_RESET to devices, in case there are 689 * ATAPI device out there which don't react to the bus reset 690 */ 691 if (ret_value & 0x01) { 692 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 693 wdc->select(chp,0); 694 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 695 0, WDSD_IBM); 696 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 697 ATAPI_SOFT_RESET); 698 } 699 if (ret_value & 0x02) { 700 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 701 wdc->select(chp,0); 702 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 703 0, WDSD_IBM | 0x10); 704 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 705 ATAPI_SOFT_RESET); 706 } 707 708 delay(5000); 709 #endif 710 711 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 712 wdc->select(chp,0); 713 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 714 delay(10); /* 400ns delay */ 715 /* assert SRST, wait for reset to complete */ 716 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 717 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 718 DELAY(1000); 719 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 720 WDCTL_IDS | WDCTL_4BIT); 721 DELAY(2000); 722 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 723 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 724 delay(10); /* 400ns delay */ 725 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 726 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 727 wdc->irqack(chp); 728 splx(s); 729 730 ret_value = __wdcwait_reset(chp, ret_value, poll); 731 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 732 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 733 ret_value), DEBUG_PROBE); 734 735 /* if reset failed, there's nothing here */ 736 if (ret_value == 0) 737 return 0; 738 739 /* 740 * Test presence of drives. First test register signatures looking 741 * for ATAPI devices. If it's not an ATAPI and reset said there may 742 * be something here assume it's ATA or OLD. Ghost will be killed 743 * later in attach routine. 744 */ 745 for (drive = 0; drive < 2; drive++) { 746 if ((ret_value & (0x01 << drive)) == 0) 747 continue; 748 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 749 wdc->select(chp,drive); 750 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 751 WDSD_IBM | (drive << 4)); 752 delay(10); /* 400ns delay */ 753 /* Save registers contents */ 754 sc = bus_space_read_1(chp->cmd_iot, 755 chp->cmd_iohs[wd_seccnt], 0); 756 sn = bus_space_read_1(chp->cmd_iot, 757 chp->cmd_iohs[wd_sector], 0); 758 cl = bus_space_read_1(chp->cmd_iot, 759 chp->cmd_iohs[wd_cyl_lo], 0); 760 ch = bus_space_read_1(chp->cmd_iot, 761 chp->cmd_iohs[wd_cyl_hi], 0); 762 763 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 764 "cl=0x%x ch=0x%x\n", 765 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 766 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 767 /* 768 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 769 * we get wrong values here, so ignore it. 770 */ 771 if (cl == 0x14 && ch == 0xeb) { 772 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 773 } else { 774 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 775 if (wdc == NULL || 776 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 777 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 778 } 779 } 780 return (ret_value); 781 } 782 783 void 784 wdcattach(struct wdc_channel *chp) 785 { 786 struct wdc_softc *wdc = chp->ch_wdc; 787 static int inited = 0; 788 789 if (chp->ch_flags & WDCF_DISABLED) 790 return; 791 792 /* initialise global data */ 793 callout_init(&chp->ch_callout); 794 if (wdc->drv_probe == NULL) 795 wdc->drv_probe = wdc_drvprobe; 796 if (inited == 0) { 797 /* Initialize the ata_xfer pool. */ 798 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 799 0, 0, "wdcspl", NULL); 800 inited++; 801 } 802 TAILQ_INIT(&chp->ch_queue->queue_xfer); 803 chp->ch_queue->queue_freeze = 0; 804 805 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 806 } 807 808 int 809 wdcactivate(struct device *self, enum devact act) 810 { 811 struct wdc_softc *wdc = (struct wdc_softc *)self; 812 int s, i, error = 0; 813 814 s = splbio(); 815 switch (act) { 816 case DVACT_ACTIVATE: 817 error = EOPNOTSUPP; 818 break; 819 820 case DVACT_DEACTIVATE: 821 for (i = 0; i < wdc->nchannels; i++) { 822 error = config_deactivate(wdc->channels[i]->atabus); 823 if (error) 824 break; 825 } 826 break; 827 } 828 splx(s); 829 return (error); 830 } 831 832 int 833 wdcdetach(struct device *self, int flags) 834 { 835 struct wdc_softc *wdc = (struct wdc_softc *)self; 836 struct wdc_channel *chp; 837 int i, error = 0; 838 839 for (i = 0; i < wdc->nchannels; i++) { 840 chp = wdc->channels[i]; 841 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 842 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 843 error = config_detach(chp->atabus, flags); 844 if (error) 845 break; 846 } 847 return (error); 848 } 849 850 /* 851 * Start I/O on a controller, for the given channel. 852 * The first xfer may be not for our channel if the channel queues 853 * are shared. 854 */ 855 void 856 wdcstart(struct wdc_channel *chp) 857 { 858 struct wdc_softc *wdc = chp->ch_wdc; 859 struct ata_xfer *xfer; 860 861 #ifdef WDC_DIAGNOSTIC 862 int spl1, spl2; 863 864 spl1 = splbio(); 865 spl2 = splbio(); 866 if (spl2 != spl1) { 867 printf("wdcstart: not at splbio()\n"); 868 panic("wdcstart"); 869 } 870 splx(spl2); 871 splx(spl1); 872 #endif /* WDC_DIAGNOSTIC */ 873 874 /* is there a xfer ? */ 875 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 876 return; 877 878 /* adjust chp, in case we have a shared queue */ 879 chp = xfer->c_chp; 880 881 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 882 return; /* channel aleady active */ 883 } 884 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 885 return; /* queue froozen */ 886 } 887 #ifdef DIAGNOSTIC 888 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 889 panic("wdcstart: channel waiting for irq"); 890 #endif 891 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 892 if (!(*wdc->claim_hw)(chp, 0)) 893 return; 894 895 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 896 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 897 chp->ch_flags |= WDCF_ACTIVE; 898 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 899 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 900 chp->ch_drive[xfer->c_drive].state = 0; 901 } 902 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 903 KASSERT(xfer->c_flags & C_POLL); 904 xfer->c_start(chp, xfer); 905 } 906 907 /* restart an interrupted I/O */ 908 void 909 wdcrestart(void *v) 910 { 911 struct wdc_channel *chp = v; 912 int s; 913 914 s = splbio(); 915 wdcstart(chp); 916 splx(s); 917 } 918 919 920 /* 921 * Interrupt routine for the controller. Acknowledge the interrupt, check for 922 * errors on the current operation, mark it done if necessary, and start the 923 * next request. Also check for a partially done transfer, and continue with 924 * the next chunk if so. 925 */ 926 int 927 wdcintr(void *arg) 928 { 929 struct wdc_channel *chp = arg; 930 struct wdc_softc *wdc = chp->ch_wdc; 931 struct ata_xfer *xfer; 932 int ret; 933 934 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 935 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 936 DEBUG_INTR); 937 return (0); 938 } 939 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 940 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 941 /* try to clear the pending interrupt anyway */ 942 (void)bus_space_read_1(chp->cmd_iot, 943 chp->cmd_iohs[wd_status], 0); 944 return (0); 945 } 946 947 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 948 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 949 if (chp->ch_flags & WDCF_DMA_WAIT) { 950 wdc->dma_status = 951 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 952 xfer->c_drive, 0); 953 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 954 /* IRQ not for us, not detected by DMA engine */ 955 return 0; 956 } 957 chp->ch_flags &= ~WDCF_DMA_WAIT; 958 } 959 chp->ch_flags &= ~WDCF_IRQ_WAIT; 960 ret = xfer->c_intr(chp, xfer, 1); 961 if (ret == 0) /* irq was not for us, still waiting for irq */ 962 chp->ch_flags |= WDCF_IRQ_WAIT; 963 return (ret); 964 } 965 966 /* Put all disk in RESET state */ 967 void 968 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 969 { 970 struct wdc_channel *chp = drvp->chnl_softc; 971 struct wdc_softc *wdc = chp->ch_wdc; 972 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 973 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 974 DEBUG_FUNCS); 975 976 977 __wdc_reset_channel(chp, flags); 978 } 979 980 static void 981 __wdc_reset_channel(struct wdc_channel *chp, int flags) 982 { 983 struct ata_xfer *xfer; 984 int drive; 985 986 /* 987 * look for pending xfers. If we have a shared queue, we'll also reset 988 * the other channel if the current xfer is running on it. 989 * Then we'll freese the queue, and dequeue only the xfers for this 990 * channel. xfer->c_kill_xfer() will reset any ATAPI device when 991 * needed. 992 */ 993 chp->ch_queue->queue_freeze++; 994 if ((flags & AT_RST_NOCMD) == 0) { 995 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 996 if (xfer && xfer->c_chp != chp) 997 __wdc_reset_channel(xfer->c_chp, flags); 998 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 999 xfer != 0; ) { 1000 if (xfer->c_chp != chp) 1001 continue; 1002 if ((flags & AT_RST_EMERG) == 0) 1003 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1004 } 1005 } 1006 if ((flags & AT_POLL) == 0) { 1007 if (chp->ch_flags & WDCF_TH_RESET) { 1008 /* no need to schedule a reset more than one time */ 1009 return; 1010 } 1011 chp->ch_flags |= WDCF_TH_RESET; 1012 wakeup(&chp->ch_thread); 1013 return; 1014 } 1015 (void) wdcreset(chp, RESET_POLL); 1016 for (drive = 0; drive < 2; drive++) { 1017 chp->ch_drive[drive].state = 0; 1018 } 1019 if ((flags & AT_RST_EMERG) == 0) { 1020 chp->ch_queue->queue_freeze--; 1021 wdcstart(chp); 1022 } else { 1023 /* make sure that we can use polled commands */ 1024 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1025 chp->ch_queue->queue_freeze = 0; 1026 } 1027 } 1028 1029 int 1030 wdcreset(struct wdc_channel *chp, int poll) 1031 { 1032 struct wdc_softc *wdc = chp->ch_wdc; 1033 int drv_mask1, drv_mask2; 1034 int s = 0; 1035 1036 if (wdc->cap & WDC_CAPABILITY_SELECT) 1037 wdc->select(chp,0); 1038 if (poll != RESET_SLEEP) 1039 s = splbio(); 1040 /* master */ 1041 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1042 delay(10); /* 400ns delay */ 1043 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1044 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1045 delay(2000); 1046 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1047 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1048 WDCTL_4BIT | WDCTL_IDS); 1049 delay(10); /* 400ns delay */ 1050 if (poll != RESET_SLEEP) { 1051 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1052 wdc->irqack(chp); 1053 splx(s); 1054 } 1055 1056 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1057 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1058 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1059 (poll == RESET_SLEEP) ? 0 : 1); 1060 if (drv_mask2 != drv_mask1) { 1061 printf("%s channel %d: reset failed for", 1062 wdc->sc_dev.dv_xname, chp->ch_channel); 1063 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1064 printf(" drive 0"); 1065 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1066 printf(" drive 1"); 1067 printf("\n"); 1068 } 1069 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1070 return (drv_mask1 != drv_mask2) ? 1 : 0; 1071 } 1072 1073 static int 1074 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1075 { 1076 struct wdc_softc *wdc = chp->ch_wdc; 1077 int timeout, nloop; 1078 u_int8_t st0 = 0, st1 = 0; 1079 #ifdef WDCDEBUG 1080 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1081 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1082 #endif 1083 1084 if (poll) 1085 nloop = WDCNDELAY_RST; 1086 else 1087 nloop = WDC_RESET_WAIT * hz / 1000; 1088 /* wait for BSY to deassert */ 1089 for (timeout = 0; timeout < nloop; timeout++) { 1090 if ((drv_mask & 0x01) != 0) { 1091 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1092 wdc->select(chp,0); 1093 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1094 0, WDSD_IBM); /* master */ 1095 delay(10); 1096 st0 = bus_space_read_1(chp->cmd_iot, 1097 chp->cmd_iohs[wd_status], 0); 1098 #ifdef WDCDEBUG 1099 sc0 = bus_space_read_1(chp->cmd_iot, 1100 chp->cmd_iohs[wd_seccnt], 0); 1101 sn0 = bus_space_read_1(chp->cmd_iot, 1102 chp->cmd_iohs[wd_sector], 0); 1103 cl0 = bus_space_read_1(chp->cmd_iot, 1104 chp->cmd_iohs[wd_cyl_lo], 0); 1105 ch0 = bus_space_read_1(chp->cmd_iot, 1106 chp->cmd_iohs[wd_cyl_hi], 0); 1107 #endif 1108 } 1109 if ((drv_mask & 0x02) != 0) { 1110 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1111 wdc->select(chp,1); 1112 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1113 0, WDSD_IBM | 0x10); /* slave */ 1114 delay(10); 1115 st1 = bus_space_read_1(chp->cmd_iot, 1116 chp->cmd_iohs[wd_status], 0); 1117 #ifdef WDCDEBUG 1118 sc1 = bus_space_read_1(chp->cmd_iot, 1119 chp->cmd_iohs[wd_seccnt], 0); 1120 sn1 = bus_space_read_1(chp->cmd_iot, 1121 chp->cmd_iohs[wd_sector], 0); 1122 cl1 = bus_space_read_1(chp->cmd_iot, 1123 chp->cmd_iohs[wd_cyl_lo], 0); 1124 ch1 = bus_space_read_1(chp->cmd_iot, 1125 chp->cmd_iohs[wd_cyl_hi], 0); 1126 #endif 1127 } 1128 1129 if ((drv_mask & 0x01) == 0) { 1130 /* no master */ 1131 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1132 /* No master, slave is ready, it's done */ 1133 goto end; 1134 } 1135 } else if ((drv_mask & 0x02) == 0) { 1136 /* no slave */ 1137 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1138 /* No slave, master is ready, it's done */ 1139 goto end; 1140 } 1141 } else { 1142 /* Wait for both master and slave to be ready */ 1143 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1144 goto end; 1145 } 1146 } 1147 if (poll) 1148 delay(WDCDELAY); 1149 else 1150 tsleep(&nloop, PRIBIO, "atarst", 1); 1151 } 1152 /* Reset timed out. Maybe it's because drv_mask was not right */ 1153 if (st0 & WDCS_BSY) 1154 drv_mask &= ~0x01; 1155 if (st1 & WDCS_BSY) 1156 drv_mask &= ~0x02; 1157 end: 1158 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1159 "cl=0x%x ch=0x%x\n", 1160 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1161 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1162 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1163 "cl=0x%x ch=0x%x\n", 1164 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1165 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1166 1167 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1168 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1169 st0, st1), DEBUG_PROBE); 1170 1171 return drv_mask; 1172 } 1173 1174 /* 1175 * Wait for a drive to be !BSY, and have mask in its status register. 1176 * return -1 for a timeout after "timeout" ms. 1177 */ 1178 static int 1179 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1180 { 1181 struct wdc_softc *wdc = chp->ch_wdc; 1182 u_char status; 1183 int time = 0; 1184 1185 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1186 wdc->sc_dev.dv_xname : "none", 1187 chp->ch_channel), DEBUG_STATUS); 1188 chp->ch_error = 0; 1189 1190 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1191 1192 for (;;) { 1193 chp->ch_status = status = 1194 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1195 if ((status & (WDCS_BSY | mask)) == bits) 1196 break; 1197 if (++time > timeout) { 1198 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1199 "status %x error %x (mask 0x%x bits 0x%x)\n", 1200 time, status, 1201 bus_space_read_1(chp->cmd_iot, 1202 chp->cmd_iohs[wd_error], 0), mask, bits), 1203 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1204 return(WDCWAIT_TOUT); 1205 } 1206 delay(WDCDELAY); 1207 } 1208 #ifdef WDCDEBUG 1209 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1210 printf("__wdcwait: did busy-wait, time=%d\n", time); 1211 #endif 1212 if (status & WDCS_ERR) 1213 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1214 chp->cmd_iohs[wd_error], 0); 1215 #ifdef WDCNDELAY_DEBUG 1216 /* After autoconfig, there should be no long delays. */ 1217 if (!cold && time > WDCNDELAY_DEBUG) { 1218 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1219 if (xfer == NULL) 1220 printf("%s channel %d: warning: busy-wait took %dus\n", 1221 wdc->sc_dev.dv_xname, chp->ch_channel, 1222 WDCDELAY * time); 1223 else 1224 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1225 wdc->sc_dev.dv_xname, chp->ch_channel, 1226 xfer->drive, 1227 WDCDELAY * time); 1228 } 1229 #endif 1230 return(WDCWAIT_OK); 1231 } 1232 1233 /* 1234 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1235 * thread if possible 1236 */ 1237 int 1238 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1239 { 1240 int error, i, timeout_hz = mstohz(timeout); 1241 1242 if (timeout_hz == 0 || 1243 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1244 error = __wdcwait(chp, mask, bits, timeout); 1245 else { 1246 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1247 if (error != 0) { 1248 if ((chp->ch_flags & WDCF_TH_RUN) || 1249 (flags & AT_WAIT)) { 1250 /* 1251 * we're running in the channel thread 1252 * or some userland thread context 1253 */ 1254 for (i = 0; i < timeout_hz; i++) { 1255 if (__wdcwait(chp, mask, bits, 1256 WDCDELAY_POLL) == 0) { 1257 error = 0; 1258 break; 1259 } 1260 tsleep(&chp, PRIBIO, "atapoll", 1); 1261 } 1262 } else { 1263 /* 1264 * we're probably in interrupt context, 1265 * ask the thread to come back here 1266 */ 1267 #ifdef DIAGNOSTIC 1268 if (chp->ch_queue->queue_freeze > 0) 1269 panic("wdcwait: queue_freeze"); 1270 #endif 1271 chp->ch_queue->queue_freeze++; 1272 wakeup(&chp->ch_thread); 1273 return(WDCWAIT_THR); 1274 } 1275 } 1276 } 1277 return (error); 1278 } 1279 1280 1281 /* 1282 * Busy-wait for DMA to complete 1283 */ 1284 int 1285 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1286 { 1287 struct wdc_softc *wdc = chp->ch_wdc; 1288 int time; 1289 1290 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1291 wdc->dma_status = 1292 (*wdc->dma_finish)(wdc->dma_arg, 1293 chp->ch_channel, xfer->c_drive, 0); 1294 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1295 return 0; 1296 delay(WDCDELAY); 1297 } 1298 /* timeout, force a DMA halt */ 1299 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1300 chp->ch_channel, xfer->c_drive, 1); 1301 return 1; 1302 } 1303 1304 void 1305 wdctimeout(void *arg) 1306 { 1307 struct wdc_channel *chp = (struct wdc_channel *)arg; 1308 struct wdc_softc *wdc = chp->ch_wdc; 1309 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1310 int s; 1311 1312 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1313 1314 s = splbio(); 1315 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1316 __wdcerror(chp, "lost interrupt"); 1317 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1318 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1319 xfer->c_bcount, 1320 xfer->c_skip); 1321 if (chp->ch_flags & WDCF_DMA_WAIT) { 1322 wdc->dma_status = 1323 (*wdc->dma_finish)(wdc->dma_arg, 1324 chp->ch_channel, xfer->c_drive, 1); 1325 chp->ch_flags &= ~WDCF_DMA_WAIT; 1326 } 1327 /* 1328 * Call the interrupt routine. If we just missed an interrupt, 1329 * it will do what's needed. Else, it will take the needed 1330 * action (reset the device). 1331 * Before that we need to reinstall the timeout callback, 1332 * in case it will miss another irq while in this transfer 1333 * We arbitray chose it to be 1s 1334 */ 1335 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1336 xfer->c_flags |= C_TIMEOU; 1337 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1338 xfer->c_intr(chp, xfer, 1); 1339 } else 1340 __wdcerror(chp, "missing untimeout"); 1341 splx(s); 1342 } 1343 1344 /* 1345 * Probe drive's capabilities, for use by the controller later 1346 * Assumes drvp points to an existing drive. 1347 * XXX this should be a controller-indep function 1348 */ 1349 void 1350 wdc_probe_caps(struct ata_drive_datas *drvp) 1351 { 1352 struct ataparams params, params2; 1353 struct wdc_channel *chp = drvp->chnl_softc; 1354 struct wdc_softc *wdc = chp->ch_wdc; 1355 struct device *drv_dev = drvp->drv_softc; 1356 int i, printed; 1357 char *sep = ""; 1358 int cf_flags; 1359 1360 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1361 /* IDENTIFY failed. Can't tell more about the device */ 1362 return; 1363 } 1364 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1365 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1366 /* 1367 * Controller claims 16 and 32 bit transfers. 1368 * Re-do an IDENTIFY with 32-bit transfers, 1369 * and compare results. 1370 */ 1371 drvp->drive_flags |= DRIVE_CAP32; 1372 ata_get_params(drvp, AT_WAIT, ¶ms2); 1373 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1374 /* Not good. fall back to 16bits */ 1375 drvp->drive_flags &= ~DRIVE_CAP32; 1376 } else { 1377 aprint_normal("%s: 32-bit data port\n", 1378 drv_dev->dv_xname); 1379 } 1380 } 1381 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1382 if (params.atap_ata_major > 0x01 && 1383 params.atap_ata_major != 0xffff) { 1384 for (i = 14; i > 0; i--) { 1385 if (params.atap_ata_major & (1 << i)) { 1386 aprint_normal("%s: ATA version %d\n", 1387 drv_dev->dv_xname, i); 1388 drvp->ata_vers = i; 1389 break; 1390 } 1391 } 1392 } 1393 #endif 1394 1395 /* An ATAPI device is at last PIO mode 3 */ 1396 if (drvp->drive_flags & DRIVE_ATAPI) 1397 drvp->PIO_mode = 3; 1398 1399 /* 1400 * It's not in the specs, but it seems that some drive 1401 * returns 0xffff in atap_extensions when this field is invalid 1402 */ 1403 if (params.atap_extensions != 0xffff && 1404 (params.atap_extensions & WDC_EXT_MODES)) { 1405 printed = 0; 1406 /* 1407 * XXX some drives report something wrong here (they claim to 1408 * support PIO mode 8 !). As mode is coded on 3 bits in 1409 * SET FEATURE, limit it to 7 (so limit i to 4). 1410 * If higher mode than 7 is found, abort. 1411 */ 1412 for (i = 7; i >= 0; i--) { 1413 if ((params.atap_piomode_supp & (1 << i)) == 0) 1414 continue; 1415 if (i > 4) 1416 return; 1417 /* 1418 * See if mode is accepted. 1419 * If the controller can't set its PIO mode, 1420 * assume the defaults are good, so don't try 1421 * to set it 1422 */ 1423 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1424 /* 1425 * It's OK to pool here, it's fast enouth 1426 * to not bother waiting for interrupt 1427 */ 1428 if (ata_set_mode(drvp, 0x08 | (i + 3), 1429 AT_WAIT) != CMD_OK) 1430 continue; 1431 if (!printed) { 1432 aprint_normal("%s: drive supports PIO mode %d", 1433 drv_dev->dv_xname, i + 3); 1434 sep = ","; 1435 printed = 1; 1436 } 1437 /* 1438 * If controller's driver can't set its PIO mode, 1439 * get the highter one for the drive. 1440 */ 1441 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1442 wdc->PIO_cap >= i + 3) { 1443 drvp->PIO_mode = i + 3; 1444 drvp->PIO_cap = i + 3; 1445 break; 1446 } 1447 } 1448 if (!printed) { 1449 /* 1450 * We didn't find a valid PIO mode. 1451 * Assume the values returned for DMA are buggy too 1452 */ 1453 return; 1454 } 1455 drvp->drive_flags |= DRIVE_MODE; 1456 printed = 0; 1457 for (i = 7; i >= 0; i--) { 1458 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1459 continue; 1460 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1461 (wdc->cap & WDC_CAPABILITY_MODE)) 1462 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1463 != CMD_OK) 1464 continue; 1465 if (!printed) { 1466 aprint_normal("%s DMA mode %d", sep, i); 1467 sep = ","; 1468 printed = 1; 1469 } 1470 if (wdc->cap & WDC_CAPABILITY_DMA) { 1471 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1472 wdc->DMA_cap < i) 1473 continue; 1474 drvp->DMA_mode = i; 1475 drvp->DMA_cap = i; 1476 drvp->drive_flags |= DRIVE_DMA; 1477 } 1478 break; 1479 } 1480 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1481 printed = 0; 1482 for (i = 7; i >= 0; i--) { 1483 if ((params.atap_udmamode_supp & (1 << i)) 1484 == 0) 1485 continue; 1486 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1487 (wdc->cap & WDC_CAPABILITY_UDMA)) 1488 if (ata_set_mode(drvp, 0x40 | i, 1489 AT_WAIT) != CMD_OK) 1490 continue; 1491 if (!printed) { 1492 aprint_normal("%s Ultra-DMA mode %d", 1493 sep, i); 1494 if (i == 2) 1495 aprint_normal(" (Ultra/33)"); 1496 else if (i == 4) 1497 aprint_normal(" (Ultra/66)"); 1498 else if (i == 5) 1499 aprint_normal(" (Ultra/100)"); 1500 else if (i == 6) 1501 aprint_normal(" (Ultra/133)"); 1502 sep = ","; 1503 printed = 1; 1504 } 1505 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1506 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1507 wdc->UDMA_cap < i) 1508 continue; 1509 drvp->UDMA_mode = i; 1510 drvp->UDMA_cap = i; 1511 drvp->drive_flags |= DRIVE_UDMA; 1512 } 1513 break; 1514 } 1515 } 1516 aprint_normal("\n"); 1517 } 1518 1519 /* Try to guess ATA version here, if it didn't get reported */ 1520 if (drvp->ata_vers == 0) { 1521 if (drvp->drive_flags & DRIVE_UDMA) 1522 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1523 else if (drvp->PIO_cap > 2) 1524 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1525 } 1526 cf_flags = drv_dev->dv_cfdata->cf_flags; 1527 if (cf_flags & ATA_CONFIG_PIO_SET) { 1528 drvp->PIO_mode = 1529 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1530 drvp->drive_flags |= DRIVE_MODE; 1531 } 1532 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1533 /* don't care about DMA modes */ 1534 return; 1535 } 1536 if (cf_flags & ATA_CONFIG_DMA_SET) { 1537 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1538 ATA_CONFIG_DMA_DISABLE) { 1539 drvp->drive_flags &= ~DRIVE_DMA; 1540 } else { 1541 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1542 ATA_CONFIG_DMA_OFF; 1543 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1544 } 1545 } 1546 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1547 /* don't care about UDMA modes */ 1548 return; 1549 } 1550 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1551 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1552 ATA_CONFIG_UDMA_DISABLE) { 1553 drvp->drive_flags &= ~DRIVE_UDMA; 1554 } else { 1555 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1556 ATA_CONFIG_UDMA_OFF; 1557 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1558 } 1559 } 1560 } 1561 1562 /* 1563 * downgrade the transfer mode of a drive after an error. return 1 if 1564 * downgrade was possible, 0 otherwise. 1565 */ 1566 int 1567 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1568 { 1569 struct wdc_channel *chp = drvp->chnl_softc; 1570 struct wdc_softc *wdc = chp->ch_wdc; 1571 struct device *drv_dev = drvp->drv_softc; 1572 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1573 1574 /* if drive or controller don't know its mode, we can't do much */ 1575 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1576 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1577 return 0; 1578 /* current drive mode was set by a config flag, let it this way */ 1579 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1580 (cf_flags & ATA_CONFIG_DMA_SET) || 1581 (cf_flags & ATA_CONFIG_UDMA_SET)) 1582 return 0; 1583 1584 /* 1585 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1586 */ 1587 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1588 drvp->UDMA_mode--; 1589 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1590 drv_dev->dv_xname, drvp->UDMA_mode); 1591 } 1592 1593 /* 1594 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1595 */ 1596 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1597 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1598 drvp->PIO_mode = drvp->PIO_cap; 1599 printf("%s: transfer error, downgrading to PIO mode %d\n", 1600 drv_dev->dv_xname, drvp->PIO_mode); 1601 } else /* already using PIO, can't downgrade */ 1602 return 0; 1603 1604 wdc->set_modes(chp); 1605 wdc_print_modes(chp); 1606 /* reset the channel, which will shedule all drives for setup */ 1607 wdc_reset_channel(drvp, flags | AT_RST_NOCMD); 1608 return 1; 1609 } 1610 1611 int 1612 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1613 { 1614 struct wdc_channel *chp = drvp->chnl_softc; 1615 struct wdc_softc *wdc = chp->ch_wdc; 1616 struct ata_xfer *xfer; 1617 int s, ret; 1618 1619 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1620 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1621 DEBUG_FUNCS); 1622 1623 /* set up an xfer and queue. Wait for completion */ 1624 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1625 WDC_NOSLEEP); 1626 if (xfer == NULL) { 1627 return WDC_TRY_AGAIN; 1628 } 1629 1630 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1631 wdc_c->flags |= AT_POLL; 1632 if (wdc_c->flags & AT_POLL) 1633 xfer->c_flags |= C_POLL; 1634 xfer->c_drive = drvp->drive; 1635 xfer->c_databuf = wdc_c->data; 1636 xfer->c_bcount = wdc_c->bcount; 1637 xfer->c_cmd = wdc_c; 1638 xfer->c_start = __wdccommand_start; 1639 xfer->c_intr = __wdccommand_intr; 1640 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1641 1642 s = splbio(); 1643 wdc_exec_xfer(chp, xfer); 1644 #ifdef DIAGNOSTIC 1645 if ((wdc_c->flags & AT_POLL) != 0 && 1646 (wdc_c->flags & AT_DONE) == 0) 1647 panic("wdc_exec_command: polled command not done"); 1648 #endif 1649 if (wdc_c->flags & AT_DONE) { 1650 ret = WDC_COMPLETE; 1651 } else { 1652 if (wdc_c->flags & AT_WAIT) { 1653 while ((wdc_c->flags & AT_DONE) == 0) { 1654 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1655 } 1656 ret = WDC_COMPLETE; 1657 } else { 1658 ret = WDC_QUEUED; 1659 } 1660 } 1661 splx(s); 1662 return ret; 1663 } 1664 1665 static void 1666 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1667 { 1668 struct wdc_softc *wdc = chp->ch_wdc; 1669 int drive = xfer->c_drive; 1670 struct wdc_command *wdc_c = xfer->c_cmd; 1671 1672 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1673 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1674 DEBUG_FUNCS); 1675 1676 if (wdc->cap & WDC_CAPABILITY_SELECT) 1677 wdc->select(chp,drive); 1678 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1679 WDSD_IBM | (drive << 4)); 1680 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1681 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1682 case WDCWAIT_OK: 1683 break; 1684 case WDCWAIT_TOUT: 1685 wdc_c->flags |= AT_TIMEOU; 1686 __wdccommand_done(chp, xfer); 1687 return; 1688 case WDCWAIT_THR: 1689 return; 1690 } 1691 if (wdc_c->flags & AT_POLL) { 1692 /* polled command, disable interrupts */ 1693 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1694 WDCTL_4BIT | WDCTL_IDS); 1695 } 1696 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1697 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features); 1698 1699 if ((wdc_c->flags & AT_POLL) == 0) { 1700 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1701 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1702 wdctimeout, chp); 1703 return; 1704 } 1705 /* 1706 * Polled command. Wait for drive ready or drq. Done in intr(). 1707 * Wait for at last 400ns for status bit to be valid. 1708 */ 1709 delay(10); /* 400ns delay */ 1710 __wdccommand_intr(chp, xfer, 0); 1711 } 1712 1713 static int 1714 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1715 { 1716 struct wdc_softc *wdc = chp->ch_wdc; 1717 struct wdc_command *wdc_c = xfer->c_cmd; 1718 int bcount = wdc_c->bcount; 1719 char *data = wdc_c->data; 1720 int wflags; 1721 1722 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1723 /* both wait and poll, we can tsleep here */ 1724 wflags = AT_WAIT | AT_POLL; 1725 } else { 1726 wflags = AT_POLL; 1727 } 1728 1729 again: 1730 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1731 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1732 DEBUG_INTR); 1733 /* 1734 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1735 * Reselect again, it doesn't hurt for others commands, and the time 1736 * penalty for the extra regiter write is acceptable, 1737 * wdc_exec_command() isn't called often (mosly for autoconfig) 1738 */ 1739 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1740 WDSD_IBM | (xfer->c_drive << 4)); 1741 if ((wdc_c->flags & AT_XFDONE) != 0) { 1742 /* 1743 * We have completed a data xfer. The drive should now be 1744 * in its initial state 1745 */ 1746 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1747 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1748 wflags) == WDCWAIT_TOUT) { 1749 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1750 return 0; /* IRQ was not for us */ 1751 wdc_c->flags |= AT_TIMEOU; 1752 } 1753 goto out; 1754 } 1755 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1756 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1757 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1758 return 0; /* IRQ was not for us */ 1759 wdc_c->flags |= AT_TIMEOU; 1760 goto out; 1761 } 1762 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1763 wdc->irqack(chp); 1764 if (wdc_c->flags & AT_READ) { 1765 if ((chp->ch_status & WDCS_DRQ) == 0) { 1766 wdc_c->flags |= AT_TIMEOU; 1767 goto out; 1768 } 1769 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1770 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1771 0, (u_int32_t*)data, bcount >> 2); 1772 data += bcount & 0xfffffffc; 1773 bcount = bcount & 0x03; 1774 } 1775 if (bcount > 0) 1776 bus_space_read_multi_2(chp->cmd_iot, 1777 chp->cmd_iohs[wd_data], 0, 1778 (u_int16_t *)data, bcount >> 1); 1779 /* at this point the drive should be in its initial state */ 1780 wdc_c->flags |= AT_XFDONE; 1781 /* XXX should read status register here ? */ 1782 } else if (wdc_c->flags & AT_WRITE) { 1783 if ((chp->ch_status & WDCS_DRQ) == 0) { 1784 wdc_c->flags |= AT_TIMEOU; 1785 goto out; 1786 } 1787 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1788 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1789 0, (u_int32_t*)data, bcount >> 2); 1790 data += bcount & 0xfffffffc; 1791 bcount = bcount & 0x03; 1792 } 1793 if (bcount > 0) 1794 bus_space_write_multi_2(chp->cmd_iot, 1795 chp->cmd_iohs[wd_data], 0, 1796 (u_int16_t *)data, bcount >> 1); 1797 wdc_c->flags |= AT_XFDONE; 1798 if ((wdc_c->flags & AT_POLL) == 0) { 1799 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1800 callout_reset(&chp->ch_callout, 1801 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1802 return 1; 1803 } else { 1804 goto again; 1805 } 1806 } 1807 out: 1808 __wdccommand_done(chp, xfer); 1809 return 1; 1810 } 1811 1812 static void 1813 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1814 { 1815 struct wdc_softc *wdc = chp->ch_wdc; 1816 struct wdc_command *wdc_c = xfer->c_cmd; 1817 1818 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1819 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1820 DEBUG_FUNCS); 1821 1822 1823 if (chp->ch_status & WDCS_DWF) 1824 wdc_c->flags |= AT_DF; 1825 if (chp->ch_status & WDCS_ERR) { 1826 wdc_c->flags |= AT_ERROR; 1827 wdc_c->r_error = chp->ch_error; 1828 } 1829 if ((wdc_c->flags & AT_READREG) != 0 && 1830 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1831 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1832 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1833 chp->cmd_iohs[wd_sdh], 0); 1834 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1835 chp->cmd_iohs[wd_seccnt], 0); 1836 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1837 chp->cmd_iohs[wd_sector], 0); 1838 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1839 chp->cmd_iohs[wd_cyl_lo], 0); 1840 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1841 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1842 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1843 chp->cmd_iohs[wd_error], 0); 1844 wdc_c->r_features = bus_space_read_1(chp->cmd_iot, 1845 chp->cmd_iohs[wd_features], 0); 1846 } 1847 __wdccommand_done_end(chp, xfer); 1848 } 1849 1850 static void 1851 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1852 { 1853 struct wdc_command *wdc_c = xfer->c_cmd; 1854 1855 callout_stop(&chp->ch_callout); 1856 wdc_c->flags |= AT_DONE; 1857 if (wdc_c->flags & AT_POLL) { 1858 /* enable interrupts */ 1859 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1860 WDCTL_4BIT); 1861 delay(10); /* some drives need a little delay here */ 1862 } 1863 wdc_free_xfer(chp, xfer); 1864 if (wdc_c->flags & AT_WAIT) 1865 wakeup(wdc_c); 1866 else if (wdc_c->callback) 1867 wdc_c->callback(wdc_c->callback_arg); 1868 wdcstart(chp); 1869 return; 1870 } 1871 1872 static void 1873 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1874 int reason) 1875 { 1876 struct wdc_command *wdc_c = xfer->c_cmd; 1877 1878 switch (reason) { 1879 case KILL_GONE: 1880 wdc_c->flags |= AT_GONE; 1881 break; 1882 case KILL_RESET: 1883 wdc_c->flags |= AT_RESET; 1884 break; 1885 default: 1886 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1887 reason); 1888 panic("__wdccommand_kill_xfer"); 1889 } 1890 __wdccommand_done_end(chp, xfer); 1891 1892 } 1893 1894 /* 1895 * Send a command. The drive should be ready. 1896 * Assumes interrupts are blocked. 1897 */ 1898 void 1899 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1900 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1901 u_int8_t features) 1902 { 1903 struct wdc_softc *wdc = chp->ch_wdc; 1904 1905 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1906 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1907 chp->ch_channel, drive, command, cylin, head, sector, count, 1908 features), DEBUG_FUNCS); 1909 1910 if (wdc->cap & WDC_CAPABILITY_SELECT) 1911 wdc->select(chp,drive); 1912 1913 /* Select drive, head, and addressing mode. */ 1914 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1915 WDSD_IBM | (drive << 4) | head); 1916 /* Load parameters into the wd_features register. */ 1917 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 1918 features); 1919 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1920 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1921 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1922 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1923 0, cylin >> 8); 1924 1925 /* Send command. */ 1926 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1927 return; 1928 } 1929 1930 /* 1931 * Send a 48-bit addressing command. The drive should be ready. 1932 * Assumes interrupts are blocked. 1933 */ 1934 void 1935 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1936 u_int64_t blkno, u_int16_t count) 1937 { 1938 struct wdc_softc *wdc = chp->ch_wdc; 1939 1940 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1941 "count=%d\n", wdc->sc_dev.dv_xname, 1942 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1943 DEBUG_FUNCS); 1944 1945 if (wdc->cap & WDC_CAPABILITY_SELECT) 1946 wdc->select(chp,drive); 1947 1948 /* Select drive, head, and addressing mode. */ 1949 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1950 (drive << 4) | WDSD_LBA); 1951 1952 /* previous */ 1953 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1954 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1955 0, count >> 8); 1956 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1957 0, blkno >> 24); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1959 0, blkno >> 32); 1960 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1961 0, blkno >> 40); 1962 1963 /* current */ 1964 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1965 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1966 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1967 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1968 0, blkno >> 8); 1969 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1970 0, blkno >> 16); 1971 1972 /* Send command. */ 1973 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1974 return; 1975 } 1976 1977 /* 1978 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1979 * tested by the caller. 1980 */ 1981 void 1982 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1983 { 1984 struct wdc_softc *wdc = chp->ch_wdc; 1985 1986 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1987 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1988 DEBUG_FUNCS); 1989 1990 if (wdc->cap & WDC_CAPABILITY_SELECT) 1991 wdc->select(chp,drive); 1992 1993 /* Select drive. */ 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1995 WDSD_IBM | (drive << 4)); 1996 1997 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1998 } 1999 2000 /* Add a command to the queue and start controller. Must be called at splbio */ 2001 void 2002 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2003 { 2004 2005 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2006 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 2007 2008 /* complete xfer setup */ 2009 xfer->c_chp = chp; 2010 2011 /* insert at the end of command list */ 2012 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2013 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2014 chp->ch_flags), DEBUG_XFERS); 2015 wdcstart(chp); 2016 } 2017 2018 struct ata_xfer * 2019 wdc_get_xfer(int flags) 2020 { 2021 struct ata_xfer *xfer; 2022 int s; 2023 2024 s = splbio(); 2025 xfer = pool_get(&wdc_xfer_pool, 2026 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2027 splx(s); 2028 if (xfer != NULL) { 2029 memset(xfer, 0, sizeof(struct ata_xfer)); 2030 } 2031 return xfer; 2032 } 2033 2034 void 2035 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2036 { 2037 struct wdc_softc *wdc = chp->ch_wdc; 2038 int s; 2039 2040 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2041 (*wdc->free_hw)(chp); 2042 s = splbio(); 2043 chp->ch_flags &= ~WDCF_ACTIVE; 2044 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2045 pool_put(&wdc_xfer_pool, xfer); 2046 splx(s); 2047 } 2048 2049 /* 2050 * Kill off all pending xfers for a wdc_channel. 2051 * 2052 * Must be called at splbio(). 2053 */ 2054 void 2055 wdc_kill_pending(struct wdc_channel *chp) 2056 { 2057 struct ata_xfer *xfer; 2058 2059 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 2060 chp = xfer->c_chp; 2061 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 2062 } 2063 } 2064 2065 static void 2066 __wdcerror(struct wdc_channel *chp, char *msg) 2067 { 2068 struct wdc_softc *wdc = chp->ch_wdc; 2069 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2070 2071 if (xfer == NULL) 2072 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2073 msg); 2074 else 2075 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2076 chp->ch_channel, xfer->c_drive, msg); 2077 } 2078 2079 /* 2080 * the bit bucket 2081 */ 2082 void 2083 wdcbit_bucket(struct wdc_channel *chp, int size) 2084 { 2085 2086 for (; size >= 2; size -= 2) 2087 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2088 if (size) 2089 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2090 } 2091 2092 int 2093 wdc_addref(struct wdc_channel *chp) 2094 { 2095 struct wdc_softc *wdc = chp->ch_wdc; 2096 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2097 int s, error = 0; 2098 2099 s = splbio(); 2100 if (adapt->adapt_refcnt++ == 0 && 2101 adapt->adapt_enable != NULL) { 2102 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2103 if (error) 2104 adapt->adapt_refcnt--; 2105 } 2106 splx(s); 2107 return (error); 2108 } 2109 2110 void 2111 wdc_delref(struct wdc_channel *chp) 2112 { 2113 struct wdc_softc *wdc = chp->ch_wdc; 2114 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2115 int s; 2116 2117 s = splbio(); 2118 if (adapt->adapt_refcnt-- == 1 && 2119 adapt->adapt_enable != NULL) 2120 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2121 splx(s); 2122 } 2123 2124 void 2125 wdc_print_modes(struct wdc_channel *chp) 2126 { 2127 struct wdc_softc *wdc = chp->ch_wdc; 2128 int drive; 2129 struct ata_drive_datas *drvp; 2130 2131 for (drive = 0; drive < 2; drive++) { 2132 drvp = &chp->ch_drive[drive]; 2133 if ((drvp->drive_flags & DRIVE) == 0) 2134 continue; 2135 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2136 drvp->drv_softc->dv_xname, 2137 wdc->sc_dev.dv_xname, 2138 chp->ch_channel, drive, drvp->PIO_mode); 2139 if (drvp->drive_flags & DRIVE_DMA) 2140 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2141 if (drvp->drive_flags & DRIVE_UDMA) { 2142 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2143 if (drvp->UDMA_mode == 2) 2144 aprint_normal(" (Ultra/33)"); 2145 else if (drvp->UDMA_mode == 4) 2146 aprint_normal(" (Ultra/66)"); 2147 else if (drvp->UDMA_mode == 5) 2148 aprint_normal(" (Ultra/100)"); 2149 else if (drvp->UDMA_mode == 6) 2150 aprint_normal(" (Ultra/133)"); 2151 } 2152 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2153 aprint_normal(" (using DMA data transfers)"); 2154 aprint_normal("\n"); 2155 } 2156 } 2157
Indexes created Thu Sep 25 16:09:42 GMT 2025