wdc.c revision 1.185
1 /* $NetBSD: wdc.c,v 1.185 2004/08/02 22:20:54 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.185 2004/08/02 22:20:54 bouyer Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct wdc_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct wdc_channel *, int, int, int); 156 157 #define DEBUG_INTR 0x01 158 #define DEBUG_XFERS 0x02 159 #define DEBUG_STATUS 0x04 160 #define DEBUG_FUNCS 0x08 161 #define DEBUG_PROBE 0x10 162 #define DEBUG_DETACH 0x20 163 #define DEBUG_DELAY 0x40 164 #ifdef WDCDEBUG 165 int wdcdebug_mask = 0; 166 int wdc_nxfer = 0; 167 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 168 #else 169 #define WDCDEBUG_PRINT(args, level) 170 #endif 171 172 /* 173 * A queue of atabus instances, used to ensure the same bus probe order 174 * for a given hardware configuration at each boot. 175 */ 176 struct atabus_initq_head atabus_initq_head = 177 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 178 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 179 180 /* 181 * Initialize the "shadow register" handles for a standard wdc controller. 182 */ 183 void 184 wdc_init_shadow_regs(struct wdc_channel *chp) 185 { 186 187 chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command]; 188 chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error]; 189 } 190 191 /* Test to see controller with at last one attached drive is there. 192 * Returns a bit for each possible drive found (0x01 for drive 0, 193 * 0x02 for drive 1). 194 * Logic: 195 * - If a status register is at 0xff, assume there is no drive here 196 * (ISA has pull-up resistors). Similarly if the status register has 197 * the value we last wrote to the bus (for IDE interfaces without pullups). 198 * If no drive at all -> return. 199 * - reset the controller, wait for it to complete (may take up to 31s !). 200 * If timeout -> return. 201 * - test ATA/ATAPI signatures. If at last one drive found -> return. 202 * - try an ATA command on the master. 203 */ 204 205 static void 206 wdc_drvprobe(struct wdc_channel *chp) 207 { 208 struct ataparams params; 209 struct wdc_softc *wdc = chp->ch_wdc; 210 u_int8_t st0 = 0, st1 = 0; 211 int i, error; 212 213 if (wdcprobe1(chp, 0) == 0) { 214 /* No drives, abort the attach here. */ 215 return; 216 } 217 218 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 219 for (i = 0; i < mstohz(3000); i++) { 220 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 221 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 222 wdc->select(chp,0); 223 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 224 0, WDSD_IBM); 225 delay(10); /* 400ns delay */ 226 st0 = bus_space_read_1(chp->cmd_iot, 227 chp->cmd_iohs[wd_status], 0); 228 } 229 230 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 231 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 232 wdc->select(chp,1); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 234 0, WDSD_IBM | 0x10); 235 delay(10); /* 400ns delay */ 236 st1 = bus_space_read_1(chp->cmd_iot, 237 chp->cmd_iohs[wd_status], 0); 238 } 239 240 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 241 == 0 || 242 (st0 & WDCS_DRDY)) && 243 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 244 == 0 || 245 (st1 & WDCS_DRDY))) 246 break; 247 tsleep(¶ms, PRIBIO, "atadrdy", 1); 248 } 249 if ((st0 & WDCS_DRDY) == 0) 250 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 251 if ((st1 & WDCS_DRDY) == 0) 252 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 253 254 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 255 wdc->sc_dev.dv_xname, 256 chp->ch_channel, st0, st1), DEBUG_PROBE); 257 258 /* Wait a bit, some devices are weird just after a reset. */ 259 delay(5000); 260 261 for (i = 0; i < 2; i++) { 262 /* XXX This should be done by other code. */ 263 chp->ch_drive[i].chnl_softc = chp; 264 chp->ch_drive[i].drive = i; 265 266 /* 267 * Init error counter so that an error withing the first xfers 268 * will trigger a downgrade 269 */ 270 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 271 272 /* If controller can't do 16bit flag the drives as 32bit */ 273 if ((wdc->cap & 274 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 275 WDC_CAPABILITY_DATA32) 276 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 277 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 278 continue; 279 280 /* Shortcut in case we've been shutdown */ 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 return; 283 284 /* issue an identify, to try to detect ghosts */ 285 error = ata_get_params(&chp->ch_drive[i], 286 AT_WAIT | AT_POLL, ¶ms); 287 if (error != CMD_OK) { 288 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 289 290 /* Shortcut in case we've been shutdown */ 291 if (chp->ch_flags & WDCF_SHUTDOWN) 292 return; 293 294 error = ata_get_params(&chp->ch_drive[i], 295 AT_WAIT | AT_POLL, ¶ms); 296 } 297 if (error == CMD_OK) { 298 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 299 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 300 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 301 } else { 302 chp->ch_drive[i].drive_flags &= 303 ~(DRIVE_ATA | DRIVE_ATAPI); 304 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 305 wdc->sc_dev.dv_xname, 306 chp->ch_channel, i, error), DEBUG_PROBE); 307 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 308 continue; 309 /* 310 * Pre-ATA drive ? 311 * Test registers writability (Error register not 312 * writable, but cyllo is), then try an ATA command. 313 */ 314 if (wdc->cap & WDC_CAPABILITY_SELECT) 315 wdc->select(chp,i); 316 bus_space_write_1(chp->cmd_iot, 317 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 318 delay(10); /* 400ns delay */ 319 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 320 0, 0x58); 321 bus_space_write_1(chp->cmd_iot, 322 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 323 if (bus_space_read_1(chp->cmd_iot, 324 chp->cmd_iohs[wd_error], 0) == 0x58 || 325 bus_space_read_1(chp->cmd_iot, 326 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 327 WDCDEBUG_PRINT(("%s:%d:%d: register " 328 "writability failed\n", 329 wdc->sc_dev.dv_xname, 330 chp->ch_channel, i), DEBUG_PROBE); 331 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 332 continue; 333 } 334 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 335 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 336 wdc->sc_dev.dv_xname, 337 chp->ch_channel, i), DEBUG_PROBE); 338 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 339 continue; 340 } 341 bus_space_write_1(chp->cmd_iot, 342 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 343 delay(10); /* 400ns delay */ 344 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 345 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 346 wdc->sc_dev.dv_xname, 347 chp->ch_channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 } else { 350 chp->ch_drive[0].drive_flags &= 351 ~(DRIVE_ATA | DRIVE_ATAPI); 352 chp->ch_drive[1].drive_flags &= 353 ~(DRIVE_ATA | DRIVE_ATAPI); 354 } 355 } 356 } 357 } 358 359 void 360 atabusconfig(struct atabus_softc *atabus_sc) 361 { 362 struct wdc_channel *chp = atabus_sc->sc_chan; 363 struct wdc_softc *wdc = chp->ch_wdc; 364 int i, error, need_delref = 0; 365 struct atabus_initq *atabus_initq = NULL; 366 367 if ((error = wdc_addref(chp)) != 0) { 368 aprint_error("%s: unable to enable controller\n", 369 wdc->sc_dev.dv_xname); 370 goto out; 371 } 372 need_delref = 1; 373 374 /* Probe for the drives. */ 375 (*wdc->drv_probe)(chp); 376 377 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 378 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 379 DEBUG_PROBE); 380 381 /* If no drives, abort here */ 382 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 383 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 384 goto out; 385 386 /* Shortcut in case we've been shutdown */ 387 if (chp->ch_flags & WDCF_SHUTDOWN) 388 goto out; 389 390 /* Make sure the devices probe in atabus order to avoid jitter. */ 391 simple_lock(&atabus_interlock); 392 while(1) { 393 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 394 if (atabus_initq->atabus_sc == atabus_sc) 395 break; 396 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 397 &atabus_interlock); 398 } 399 simple_unlock(&atabus_interlock); 400 401 /* 402 * Attach an ATAPI bus, if needed. 403 */ 404 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 405 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 406 #if NATAPIBUS > 0 407 wdc_atapibus_attach(atabus_sc); 408 #else 409 /* 410 * Fake the autoconfig "not configured" message 411 */ 412 aprint_normal("atapibus at %s not configured\n", 413 wdc->sc_dev.dv_xname); 414 chp->atapibus = NULL; 415 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 416 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 417 #endif 418 } 419 420 for (i = 0; i < 2; i++) { 421 struct ata_device adev; 422 if ((chp->ch_drive[i].drive_flags & 423 (DRIVE_ATA | DRIVE_OLD)) == 0) { 424 continue; 425 } 426 memset(&adev, 0, sizeof(struct ata_device)); 427 adev.adev_bustype = &wdc_ata_bustype; 428 adev.adev_channel = chp->ch_channel; 429 adev.adev_openings = 1; 430 adev.adev_drv_data = &chp->ch_drive[i]; 431 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 432 &adev, ataprint); 433 if (chp->ata_drives[i] != NULL) 434 wdc_probe_caps(&chp->ch_drive[i]); 435 else 436 chp->ch_drive[i].drive_flags &= 437 ~(DRIVE_ATA | DRIVE_OLD); 438 } 439 440 /* now that we know the drives, the controller can set its modes */ 441 if (wdc->cap & WDC_CAPABILITY_MODE) { 442 wdc->set_modes(chp); 443 wdc_print_modes(chp); 444 } 445 #if NATARAID > 0 446 if (wdc->cap & WDC_CAPABILITY_RAID) 447 for (i = 0; i < 2; i++) 448 if (chp->ata_drives[i] != NULL) 449 ata_raid_check_component(chp->ata_drives[i]); 450 #endif /* NATARAID > 0 */ 451 452 /* 453 * reset drive_flags for unattached devices, reset state for attached 454 * ones 455 */ 456 for (i = 0; i < 2; i++) { 457 if (chp->ch_drive[i].drv_softc == NULL) 458 chp->ch_drive[i].drive_flags = 0; 459 else 460 chp->ch_drive[i].state = 0; 461 } 462 463 out: 464 if (atabus_initq == NULL) { 465 simple_lock(&atabus_interlock); 466 while(1) { 467 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 468 if (atabus_initq->atabus_sc == atabus_sc) 469 break; 470 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 471 &atabus_interlock); 472 } 473 simple_unlock(&atabus_interlock); 474 } 475 simple_lock(&atabus_interlock); 476 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 477 simple_unlock(&atabus_interlock); 478 479 free(atabus_initq, M_DEVBUF); 480 wakeup(&atabus_initq_head); 481 482 config_pending_decr(); 483 if (need_delref) 484 wdc_delref(chp); 485 } 486 487 int 488 wdcprobe(struct wdc_channel *chp) 489 { 490 491 return (wdcprobe1(chp, 1)); 492 } 493 494 static int 495 wdcprobe1(struct wdc_channel *chp, int poll) 496 { 497 struct wdc_softc *wdc = chp->ch_wdc; 498 u_int8_t st0, st1, sc, sn, cl, ch; 499 u_int8_t ret_value = 0x03; 500 u_int8_t drive; 501 int s; 502 503 /* 504 * Sanity check to see if the wdc channel responds at all. 505 */ 506 507 s = splbio(); 508 if (wdc == NULL || 509 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 510 511 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 512 wdc->select(chp,0); 513 514 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 515 WDSD_IBM); 516 delay(10); /* 400ns delay */ 517 st0 = bus_space_read_1(chp->cmd_iot, 518 chp->cmd_iohs[wd_status], 0); 519 520 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 521 wdc->select(chp,1); 522 523 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 524 WDSD_IBM | 0x10); 525 delay(10); /* 400ns delay */ 526 st1 = bus_space_read_1(chp->cmd_iot, 527 chp->cmd_iohs[wd_status], 0); 528 529 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 530 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 531 chp->ch_channel, st0, st1), DEBUG_PROBE); 532 533 if (st0 == 0xff || st0 == WDSD_IBM) 534 ret_value &= ~0x01; 535 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 536 ret_value &= ~0x02; 537 /* Register writability test, drive 0. */ 538 if (ret_value & 0x01) { 539 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 540 wdc->select(chp,0); 541 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 542 0, WDSD_IBM); 543 bus_space_write_1(chp->cmd_iot, 544 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 545 cl = bus_space_read_1(chp->cmd_iot, 546 chp->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x02) { 548 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x02\n", 550 wdc != NULL ? 551 wdc->sc_dev.dv_xname : "wdcprobe", 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 558 cl = bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_cyl_lo], 0); 560 if (cl != 0x01) { 561 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 562 "got 0x%x != 0x01\n", 563 wdc != NULL ? 564 wdc->sc_dev.dv_xname : "wdcprobe", 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x01; 568 } 569 bus_space_write_1(chp->cmd_iot, 570 chp->cmd_iohs[wd_sector], 0, 0x01); 571 cl = bus_space_read_1(chp->cmd_iot, 572 chp->cmd_iohs[wd_sector], 0); 573 if (cl != 0x01) { 574 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 575 "got 0x%x != 0x01\n", 576 wdc != NULL ? 577 wdc->sc_dev.dv_xname : "wdcprobe", 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x01; 581 } 582 bus_space_write_1(chp->cmd_iot, 583 chp->cmd_iohs[wd_sector], 0, 0x02); 584 cl = bus_space_read_1(chp->cmd_iot, 585 chp->cmd_iohs[wd_sector], 0); 586 if (cl != 0x02) { 587 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 588 "got 0x%x != 0x02\n", 589 wdc != NULL ? 590 wdc->sc_dev.dv_xname : "wdcprobe", 591 chp->ch_channel, cl), 592 DEBUG_PROBE); 593 ret_value &= ~0x01; 594 } 595 cl = bus_space_read_1(chp->cmd_iot, 596 chp->cmd_iohs[wd_cyl_lo], 0); 597 if (cl != 0x01) { 598 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 599 "got 0x%x != 0x01\n", 600 wdc != NULL ? 601 wdc->sc_dev.dv_xname : "wdcprobe", 602 chp->ch_channel, cl), 603 DEBUG_PROBE); 604 ret_value &= ~0x01; 605 } 606 } 607 /* Register writability test, drive 1. */ 608 if (ret_value & 0x02) { 609 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 610 wdc->select(chp,1); 611 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 612 0, WDSD_IBM | 0x10); 613 bus_space_write_1(chp->cmd_iot, 614 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 615 cl = bus_space_read_1(chp->cmd_iot, 616 chp->cmd_iohs[wd_cyl_lo], 0); 617 if (cl != 0x02) { 618 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 619 "got 0x%x != 0x02\n", 620 wdc != NULL ? 621 wdc->sc_dev.dv_xname : "wdcprobe", 622 chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 628 cl = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_cyl_lo], 0); 630 if (cl != 0x01) { 631 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 632 "got 0x%x != 0x01\n", 633 wdc != NULL ? 634 wdc->sc_dev.dv_xname : "wdcprobe", 635 chp->ch_channel, cl), 636 DEBUG_PROBE); 637 ret_value &= ~0x02; 638 } 639 bus_space_write_1(chp->cmd_iot, 640 chp->cmd_iohs[wd_sector], 0, 0x01); 641 cl = bus_space_read_1(chp->cmd_iot, 642 chp->cmd_iohs[wd_sector], 0); 643 if (cl != 0x01) { 644 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 645 "got 0x%x != 0x01\n", 646 wdc != NULL ? 647 wdc->sc_dev.dv_xname : "wdcprobe", 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 bus_space_write_1(chp->cmd_iot, 653 chp->cmd_iohs[wd_sector], 0, 0x02); 654 cl = bus_space_read_1(chp->cmd_iot, 655 chp->cmd_iohs[wd_sector], 0); 656 if (cl != 0x02) { 657 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 658 "got 0x%x != 0x02\n", 659 wdc != NULL ? 660 wdc->sc_dev.dv_xname : "wdcprobe", 661 chp->ch_channel, cl), 662 DEBUG_PROBE); 663 ret_value &= ~0x02; 664 } 665 cl = bus_space_read_1(chp->cmd_iot, 666 chp->cmd_iohs[wd_cyl_lo], 0); 667 if (cl != 0x01) { 668 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 669 "got 0x%x != 0x01\n", 670 wdc != NULL ? 671 wdc->sc_dev.dv_xname : "wdcprobe", 672 chp->ch_channel, cl), 673 DEBUG_PROBE); 674 ret_value &= ~0x02; 675 } 676 } 677 678 if (ret_value == 0) { 679 splx(s); 680 return 0; 681 } 682 } 683 684 685 #if 0 /* XXX this break some ATA or ATAPI devices */ 686 /* 687 * reset bus. Also send an ATAPI_RESET to devices, in case there are 688 * ATAPI device out there which don't react to the bus reset 689 */ 690 if (ret_value & 0x01) { 691 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 692 wdc->select(chp,0); 693 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 694 0, WDSD_IBM); 695 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 696 ATAPI_SOFT_RESET); 697 } 698 if (ret_value & 0x02) { 699 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 700 wdc->select(chp,0); 701 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 702 0, WDSD_IBM | 0x10); 703 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 704 ATAPI_SOFT_RESET); 705 } 706 707 delay(5000); 708 #endif 709 710 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 711 wdc->select(chp,0); 712 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 713 delay(10); /* 400ns delay */ 714 /* assert SRST, wait for reset to complete */ 715 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 716 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 717 DELAY(1000); 718 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 719 WDCTL_IDS | WDCTL_4BIT); 720 DELAY(2000); 721 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 722 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 723 delay(10); /* 400ns delay */ 724 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 725 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 726 wdc->irqack(chp); 727 splx(s); 728 729 ret_value = __wdcwait_reset(chp, ret_value, poll); 730 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 731 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 732 ret_value), DEBUG_PROBE); 733 734 /* if reset failed, there's nothing here */ 735 if (ret_value == 0) 736 return 0; 737 738 /* 739 * Test presence of drives. First test register signatures looking 740 * for ATAPI devices. If it's not an ATAPI and reset said there may 741 * be something here assume it's ATA or OLD. Ghost will be killed 742 * later in attach routine. 743 */ 744 for (drive = 0; drive < 2; drive++) { 745 if ((ret_value & (0x01 << drive)) == 0) 746 continue; 747 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 748 wdc->select(chp,drive); 749 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 750 WDSD_IBM | (drive << 4)); 751 delay(10); /* 400ns delay */ 752 /* Save registers contents */ 753 sc = bus_space_read_1(chp->cmd_iot, 754 chp->cmd_iohs[wd_seccnt], 0); 755 sn = bus_space_read_1(chp->cmd_iot, 756 chp->cmd_iohs[wd_sector], 0); 757 cl = bus_space_read_1(chp->cmd_iot, 758 chp->cmd_iohs[wd_cyl_lo], 0); 759 ch = bus_space_read_1(chp->cmd_iot, 760 chp->cmd_iohs[wd_cyl_hi], 0); 761 762 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 763 "cl=0x%x ch=0x%x\n", 764 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 765 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 766 /* 767 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 768 * we get wrong values here, so ignore it. 769 */ 770 if (cl == 0x14 && ch == 0xeb) { 771 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 772 } else { 773 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 774 if (wdc == NULL || 775 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 776 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 777 } 778 } 779 return (ret_value); 780 } 781 782 void 783 wdcattach(struct wdc_channel *chp) 784 { 785 struct wdc_softc *wdc = chp->ch_wdc; 786 static int inited = 0; 787 788 if (chp->ch_flags & WDCF_DISABLED) 789 return; 790 791 /* initialise global data */ 792 callout_init(&chp->ch_callout); 793 if (wdc->drv_probe == NULL) 794 wdc->drv_probe = wdc_drvprobe; 795 if (inited == 0) { 796 /* Initialize the ata_xfer pool. */ 797 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 798 0, 0, "wdcspl", NULL); 799 inited++; 800 } 801 TAILQ_INIT(&chp->ch_queue->queue_xfer); 802 chp->ch_queue->queue_freeze = 0; 803 804 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 805 } 806 807 int 808 wdcactivate(struct device *self, enum devact act) 809 { 810 struct wdc_softc *wdc = (struct wdc_softc *)self; 811 int s, i, error = 0; 812 813 s = splbio(); 814 switch (act) { 815 case DVACT_ACTIVATE: 816 error = EOPNOTSUPP; 817 break; 818 819 case DVACT_DEACTIVATE: 820 for (i = 0; i < wdc->nchannels; i++) { 821 error = config_deactivate(wdc->channels[i]->atabus); 822 if (error) 823 break; 824 } 825 break; 826 } 827 splx(s); 828 return (error); 829 } 830 831 int 832 wdcdetach(struct device *self, int flags) 833 { 834 struct wdc_softc *wdc = (struct wdc_softc *)self; 835 struct wdc_channel *chp; 836 int i, error = 0; 837 838 for (i = 0; i < wdc->nchannels; i++) { 839 chp = wdc->channels[i]; 840 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 841 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 842 error = config_detach(chp->atabus, flags); 843 if (error) 844 break; 845 } 846 return (error); 847 } 848 849 /* 850 * Start I/O on a controller, for the given channel. 851 * The first xfer may be not for our channel if the channel queues 852 * are shared. 853 */ 854 void 855 wdcstart(struct wdc_channel *chp) 856 { 857 struct wdc_softc *wdc = chp->ch_wdc; 858 struct ata_xfer *xfer; 859 860 #ifdef WDC_DIAGNOSTIC 861 int spl1, spl2; 862 863 spl1 = splbio(); 864 spl2 = splbio(); 865 if (spl2 != spl1) { 866 printf("wdcstart: not at splbio()\n"); 867 panic("wdcstart"); 868 } 869 splx(spl2); 870 splx(spl1); 871 #endif /* WDC_DIAGNOSTIC */ 872 873 /* is there a xfer ? */ 874 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 875 return; 876 877 /* adjust chp, in case we have a shared queue */ 878 chp = xfer->c_chp; 879 880 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 881 return; /* channel aleady active */ 882 } 883 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 884 return; /* queue froozen */ 885 } 886 #ifdef DIAGNOSTIC 887 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 888 panic("wdcstart: channel waiting for irq"); 889 #endif 890 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 891 if (!(*wdc->claim_hw)(chp, 0)) 892 return; 893 894 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 895 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 896 chp->ch_flags |= WDCF_ACTIVE; 897 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 898 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 899 chp->ch_drive[xfer->c_drive].state = 0; 900 } 901 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 902 KASSERT(xfer->c_flags & C_POLL); 903 xfer->c_start(chp, xfer); 904 } 905 906 /* restart an interrupted I/O */ 907 void 908 wdcrestart(void *v) 909 { 910 struct wdc_channel *chp = v; 911 int s; 912 913 s = splbio(); 914 wdcstart(chp); 915 splx(s); 916 } 917 918 919 /* 920 * Interrupt routine for the controller. Acknowledge the interrupt, check for 921 * errors on the current operation, mark it done if necessary, and start the 922 * next request. Also check for a partially done transfer, and continue with 923 * the next chunk if so. 924 */ 925 int 926 wdcintr(void *arg) 927 { 928 struct wdc_channel *chp = arg; 929 struct wdc_softc *wdc = chp->ch_wdc; 930 struct ata_xfer *xfer; 931 int ret; 932 933 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 934 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 935 DEBUG_INTR); 936 return (0); 937 } 938 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 939 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 940 /* try to clear the pending interrupt anyway */ 941 (void)bus_space_read_1(chp->cmd_iot, 942 chp->cmd_iohs[wd_status], 0); 943 return (0); 944 } 945 946 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 947 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 948 if (chp->ch_flags & WDCF_DMA_WAIT) { 949 wdc->dma_status = 950 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 951 xfer->c_drive, WDC_DMAEND_END); 952 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 953 /* IRQ not for us, not detected by DMA engine */ 954 return 0; 955 } 956 chp->ch_flags &= ~WDCF_DMA_WAIT; 957 } 958 chp->ch_flags &= ~WDCF_IRQ_WAIT; 959 ret = xfer->c_intr(chp, xfer, 1); 960 if (ret == 0) /* irq was not for us, still waiting for irq */ 961 chp->ch_flags |= WDCF_IRQ_WAIT; 962 return (ret); 963 } 964 965 /* Put all disk in RESET state */ 966 void 967 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 968 { 969 struct wdc_channel *chp = drvp->chnl_softc; 970 struct wdc_softc *wdc = chp->ch_wdc; 971 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 972 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 973 DEBUG_FUNCS); 974 975 976 wdc_reset_channel(chp, flags); 977 } 978 979 void 980 wdc_reset_channel(struct wdc_channel *chp, int flags) 981 { 982 struct ata_xfer *xfer, *next_xfer; 983 int drive; 984 985 chp->ch_queue->queue_freeze++; 986 987 /* if we can poll or wait it's OK, otherwise wake up the kernel 988 * thread 989 */ 990 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 991 if (chp->ch_flags & WDCF_TH_RESET) { 992 /* no need to schedule a reset more than one time */ 993 return; 994 } 995 chp->ch_flags |= WDCF_TH_RESET; 996 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 997 wakeup(&chp->ch_thread); 998 return; 999 } 1000 1001 /* reset the channel */ 1002 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1003 if ((flags & AT_WAIT) == 0) { 1004 (void) wdcreset(chp, RESET_POLL); 1005 } else { 1006 (void) wdcreset(chp, RESET_SLEEP); 1007 } 1008 1009 /* 1010 * wait a bit after reset; in case the the DMA engines needs some time 1011 * to recover. 1012 */ 1013 if (flags & AT_WAIT) 1014 tsleep(&flags, PRIBIO, "atardl", 1); 1015 else 1016 delay(1000); 1017 /* 1018 * look for pending xfers. If we have a shared queue, we'll also reset 1019 * the other channel if the current xfer is running on it. 1020 * Then we'll dequeue only the xfers for this channel. 1021 * xfer->c_kill_xfer() will reset any ATAPI device when needed. 1022 */ 1023 if ((flags & AT_RST_NOCMD) == 0) { 1024 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1025 if (xfer) { 1026 if (xfer->c_chp != chp) 1027 wdc_reset_channel(xfer->c_chp, flags); 1028 else { 1029 /* 1030 * If we're waiting for DMA, stop the 1031 * DMA engine 1032 */ 1033 if (chp->ch_flags & WDCF_DMA_WAIT) { 1034 (*chp->ch_wdc->dma_finish)( 1035 chp->ch_wdc->dma_arg, 1036 chp->ch_channel, 1037 xfer->c_drive, 1038 WDC_DMAEND_ABRT_QUIET); 1039 chp->ch_flags &= WDCF_DMA_WAIT; 1040 } 1041 } 1042 } 1043 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1044 xfer != NULL; xfer = next_xfer) { 1045 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1046 if (xfer->c_chp != chp) 1047 continue; 1048 if ((flags & AT_RST_EMERG) == 0) 1049 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1050 } 1051 } 1052 for (drive = 0; drive < 2; drive++) { 1053 chp->ch_drive[drive].state = 0; 1054 } 1055 chp->ch_flags &= ~WDCF_TH_RESET; 1056 if ((flags & AT_RST_EMERG) == 0) { 1057 chp->ch_queue->queue_freeze--; 1058 wdcstart(chp); 1059 } else { 1060 /* make sure that we can use polled commands */ 1061 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1062 chp->ch_queue->queue_freeze = 0; 1063 } 1064 } 1065 1066 int 1067 wdcreset(struct wdc_channel *chp, int poll) 1068 { 1069 struct wdc_softc *wdc = chp->ch_wdc; 1070 int drv_mask1, drv_mask2; 1071 int s = 0; 1072 1073 if (wdc->cap & WDC_CAPABILITY_SELECT) 1074 wdc->select(chp,0); 1075 if (poll != RESET_SLEEP) 1076 s = splbio(); 1077 /* master */ 1078 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1079 delay(10); /* 400ns delay */ 1080 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1081 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1082 delay(2000); 1083 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1084 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1085 WDCTL_4BIT | WDCTL_IDS); 1086 delay(10); /* 400ns delay */ 1087 if (poll != RESET_SLEEP) { 1088 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1089 wdc->irqack(chp); 1090 splx(s); 1091 } 1092 1093 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1094 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1095 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1096 (poll == RESET_SLEEP) ? 0 : 1); 1097 if (drv_mask2 != drv_mask1) { 1098 printf("%s channel %d: reset failed for", 1099 wdc->sc_dev.dv_xname, chp->ch_channel); 1100 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1101 printf(" drive 0"); 1102 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1103 printf(" drive 1"); 1104 printf("\n"); 1105 } 1106 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1107 return (drv_mask1 != drv_mask2) ? 1 : 0; 1108 } 1109 1110 static int 1111 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1112 { 1113 struct wdc_softc *wdc = chp->ch_wdc; 1114 int timeout, nloop; 1115 u_int8_t st0 = 0, st1 = 0; 1116 #ifdef WDCDEBUG 1117 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1118 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1119 #endif 1120 1121 if (poll) 1122 nloop = WDCNDELAY_RST; 1123 else 1124 nloop = WDC_RESET_WAIT * hz / 1000; 1125 /* wait for BSY to deassert */ 1126 for (timeout = 0; timeout < nloop; timeout++) { 1127 if ((drv_mask & 0x01) != 0) { 1128 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1129 wdc->select(chp,0); 1130 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1131 0, WDSD_IBM); /* master */ 1132 delay(10); 1133 st0 = bus_space_read_1(chp->cmd_iot, 1134 chp->cmd_iohs[wd_status], 0); 1135 #ifdef WDCDEBUG 1136 sc0 = bus_space_read_1(chp->cmd_iot, 1137 chp->cmd_iohs[wd_seccnt], 0); 1138 sn0 = bus_space_read_1(chp->cmd_iot, 1139 chp->cmd_iohs[wd_sector], 0); 1140 cl0 = bus_space_read_1(chp->cmd_iot, 1141 chp->cmd_iohs[wd_cyl_lo], 0); 1142 ch0 = bus_space_read_1(chp->cmd_iot, 1143 chp->cmd_iohs[wd_cyl_hi], 0); 1144 #endif 1145 } 1146 if ((drv_mask & 0x02) != 0) { 1147 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1148 wdc->select(chp,1); 1149 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1150 0, WDSD_IBM | 0x10); /* slave */ 1151 delay(10); 1152 st1 = bus_space_read_1(chp->cmd_iot, 1153 chp->cmd_iohs[wd_status], 0); 1154 #ifdef WDCDEBUG 1155 sc1 = bus_space_read_1(chp->cmd_iot, 1156 chp->cmd_iohs[wd_seccnt], 0); 1157 sn1 = bus_space_read_1(chp->cmd_iot, 1158 chp->cmd_iohs[wd_sector], 0); 1159 cl1 = bus_space_read_1(chp->cmd_iot, 1160 chp->cmd_iohs[wd_cyl_lo], 0); 1161 ch1 = bus_space_read_1(chp->cmd_iot, 1162 chp->cmd_iohs[wd_cyl_hi], 0); 1163 #endif 1164 } 1165 1166 if ((drv_mask & 0x01) == 0) { 1167 /* no master */ 1168 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1169 /* No master, slave is ready, it's done */ 1170 goto end; 1171 } 1172 } else if ((drv_mask & 0x02) == 0) { 1173 /* no slave */ 1174 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1175 /* No slave, master is ready, it's done */ 1176 goto end; 1177 } 1178 } else { 1179 /* Wait for both master and slave to be ready */ 1180 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1181 goto end; 1182 } 1183 } 1184 if (poll) 1185 delay(WDCDELAY); 1186 else 1187 tsleep(&nloop, PRIBIO, "atarst", 1); 1188 } 1189 /* Reset timed out. Maybe it's because drv_mask was not right */ 1190 if (st0 & WDCS_BSY) 1191 drv_mask &= ~0x01; 1192 if (st1 & WDCS_BSY) 1193 drv_mask &= ~0x02; 1194 end: 1195 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1196 "cl=0x%x ch=0x%x\n", 1197 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1198 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1199 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1200 "cl=0x%x ch=0x%x\n", 1201 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1202 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1203 1204 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1205 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1206 st0, st1), DEBUG_PROBE); 1207 1208 return drv_mask; 1209 } 1210 1211 /* 1212 * Wait for a drive to be !BSY, and have mask in its status register. 1213 * return -1 for a timeout after "timeout" ms. 1214 */ 1215 static int 1216 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1217 { 1218 struct wdc_softc *wdc = chp->ch_wdc; 1219 u_char status; 1220 int time = 0; 1221 1222 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1223 wdc->sc_dev.dv_xname : "none", 1224 chp->ch_channel), DEBUG_STATUS); 1225 chp->ch_error = 0; 1226 1227 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1228 1229 for (;;) { 1230 chp->ch_status = status = 1231 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1232 if ((status & (WDCS_BSY | mask)) == bits) 1233 break; 1234 if (++time > timeout) { 1235 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1236 "status %x error %x (mask 0x%x bits 0x%x)\n", 1237 time, status, 1238 bus_space_read_1(chp->cmd_iot, 1239 chp->cmd_iohs[wd_error], 0), mask, bits), 1240 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1241 return(WDCWAIT_TOUT); 1242 } 1243 delay(WDCDELAY); 1244 } 1245 #ifdef WDCDEBUG 1246 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1247 printf("__wdcwait: did busy-wait, time=%d\n", time); 1248 #endif 1249 if (status & WDCS_ERR) 1250 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1251 chp->cmd_iohs[wd_error], 0); 1252 #ifdef WDCNDELAY_DEBUG 1253 /* After autoconfig, there should be no long delays. */ 1254 if (!cold && time > WDCNDELAY_DEBUG) { 1255 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1256 if (xfer == NULL) 1257 printf("%s channel %d: warning: busy-wait took %dus\n", 1258 wdc->sc_dev.dv_xname, chp->ch_channel, 1259 WDCDELAY * time); 1260 else 1261 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1262 wdc->sc_dev.dv_xname, chp->ch_channel, 1263 xfer->drive, 1264 WDCDELAY * time); 1265 } 1266 #endif 1267 return(WDCWAIT_OK); 1268 } 1269 1270 /* 1271 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1272 * thread if possible 1273 */ 1274 int 1275 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1276 { 1277 int error, i, timeout_hz = mstohz(timeout); 1278 1279 if (timeout_hz == 0 || 1280 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1281 error = __wdcwait(chp, mask, bits, timeout); 1282 else { 1283 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1284 if (error != 0) { 1285 if ((chp->ch_flags & WDCF_TH_RUN) || 1286 (flags & AT_WAIT)) { 1287 /* 1288 * we're running in the channel thread 1289 * or some userland thread context 1290 */ 1291 for (i = 0; i < timeout_hz; i++) { 1292 if (__wdcwait(chp, mask, bits, 1293 WDCDELAY_POLL) == 0) { 1294 error = 0; 1295 break; 1296 } 1297 tsleep(&chp, PRIBIO, "atapoll", 1); 1298 } 1299 } else { 1300 /* 1301 * we're probably in interrupt context, 1302 * ask the thread to come back here 1303 */ 1304 #ifdef DIAGNOSTIC 1305 if (chp->ch_queue->queue_freeze > 0) 1306 panic("wdcwait: queue_freeze"); 1307 #endif 1308 chp->ch_queue->queue_freeze++; 1309 wakeup(&chp->ch_thread); 1310 return(WDCWAIT_THR); 1311 } 1312 } 1313 } 1314 return (error); 1315 } 1316 1317 1318 /* 1319 * Busy-wait for DMA to complete 1320 */ 1321 int 1322 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1323 { 1324 struct wdc_softc *wdc = chp->ch_wdc; 1325 int time; 1326 1327 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1328 wdc->dma_status = 1329 (*wdc->dma_finish)(wdc->dma_arg, 1330 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1331 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1332 return 0; 1333 delay(WDCDELAY); 1334 } 1335 /* timeout, force a DMA halt */ 1336 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1337 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1338 return 1; 1339 } 1340 1341 void 1342 wdctimeout(void *arg) 1343 { 1344 struct wdc_channel *chp = (struct wdc_channel *)arg; 1345 struct wdc_softc *wdc = chp->ch_wdc; 1346 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1347 int s; 1348 1349 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1350 1351 s = splbio(); 1352 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1353 __wdcerror(chp, "lost interrupt"); 1354 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1355 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1356 xfer->c_bcount, 1357 xfer->c_skip); 1358 if (chp->ch_flags & WDCF_DMA_WAIT) { 1359 wdc->dma_status = 1360 (*wdc->dma_finish)(wdc->dma_arg, 1361 chp->ch_channel, xfer->c_drive, 1362 WDC_DMAEND_ABRT); 1363 chp->ch_flags &= ~WDCF_DMA_WAIT; 1364 } 1365 /* 1366 * Call the interrupt routine. If we just missed an interrupt, 1367 * it will do what's needed. Else, it will take the needed 1368 * action (reset the device). 1369 * Before that we need to reinstall the timeout callback, 1370 * in case it will miss another irq while in this transfer 1371 * We arbitray chose it to be 1s 1372 */ 1373 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1374 xfer->c_flags |= C_TIMEOU; 1375 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1376 xfer->c_intr(chp, xfer, 1); 1377 } else 1378 __wdcerror(chp, "missing untimeout"); 1379 splx(s); 1380 } 1381 1382 /* 1383 * Probe drive's capabilities, for use by the controller later 1384 * Assumes drvp points to an existing drive. 1385 * XXX this should be a controller-indep function 1386 */ 1387 void 1388 wdc_probe_caps(struct ata_drive_datas *drvp) 1389 { 1390 struct ataparams params, params2; 1391 struct wdc_channel *chp = drvp->chnl_softc; 1392 struct wdc_softc *wdc = chp->ch_wdc; 1393 struct device *drv_dev = drvp->drv_softc; 1394 int i, printed; 1395 char *sep = ""; 1396 int cf_flags; 1397 1398 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1399 /* IDENTIFY failed. Can't tell more about the device */ 1400 return; 1401 } 1402 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1403 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1404 /* 1405 * Controller claims 16 and 32 bit transfers. 1406 * Re-do an IDENTIFY with 32-bit transfers, 1407 * and compare results. 1408 */ 1409 drvp->drive_flags |= DRIVE_CAP32; 1410 ata_get_params(drvp, AT_WAIT, ¶ms2); 1411 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1412 /* Not good. fall back to 16bits */ 1413 drvp->drive_flags &= ~DRIVE_CAP32; 1414 } else { 1415 aprint_normal("%s: 32-bit data port\n", 1416 drv_dev->dv_xname); 1417 } 1418 } 1419 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1420 if (params.atap_ata_major > 0x01 && 1421 params.atap_ata_major != 0xffff) { 1422 for (i = 14; i > 0; i--) { 1423 if (params.atap_ata_major & (1 << i)) { 1424 aprint_normal("%s: ATA version %d\n", 1425 drv_dev->dv_xname, i); 1426 drvp->ata_vers = i; 1427 break; 1428 } 1429 } 1430 } 1431 #endif 1432 1433 /* An ATAPI device is at last PIO mode 3 */ 1434 if (drvp->drive_flags & DRIVE_ATAPI) 1435 drvp->PIO_mode = 3; 1436 1437 /* 1438 * It's not in the specs, but it seems that some drive 1439 * returns 0xffff in atap_extensions when this field is invalid 1440 */ 1441 if (params.atap_extensions != 0xffff && 1442 (params.atap_extensions & WDC_EXT_MODES)) { 1443 printed = 0; 1444 /* 1445 * XXX some drives report something wrong here (they claim to 1446 * support PIO mode 8 !). As mode is coded on 3 bits in 1447 * SET FEATURE, limit it to 7 (so limit i to 4). 1448 * If higher mode than 7 is found, abort. 1449 */ 1450 for (i = 7; i >= 0; i--) { 1451 if ((params.atap_piomode_supp & (1 << i)) == 0) 1452 continue; 1453 if (i > 4) 1454 return; 1455 /* 1456 * See if mode is accepted. 1457 * If the controller can't set its PIO mode, 1458 * assume the defaults are good, so don't try 1459 * to set it 1460 */ 1461 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1462 /* 1463 * It's OK to pool here, it's fast enouth 1464 * to not bother waiting for interrupt 1465 */ 1466 if (ata_set_mode(drvp, 0x08 | (i + 3), 1467 AT_WAIT) != CMD_OK) 1468 continue; 1469 if (!printed) { 1470 aprint_normal("%s: drive supports PIO mode %d", 1471 drv_dev->dv_xname, i + 3); 1472 sep = ","; 1473 printed = 1; 1474 } 1475 /* 1476 * If controller's driver can't set its PIO mode, 1477 * get the highter one for the drive. 1478 */ 1479 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1480 wdc->PIO_cap >= i + 3) { 1481 drvp->PIO_mode = i + 3; 1482 drvp->PIO_cap = i + 3; 1483 break; 1484 } 1485 } 1486 if (!printed) { 1487 /* 1488 * We didn't find a valid PIO mode. 1489 * Assume the values returned for DMA are buggy too 1490 */ 1491 return; 1492 } 1493 drvp->drive_flags |= DRIVE_MODE; 1494 printed = 0; 1495 for (i = 7; i >= 0; i--) { 1496 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1497 continue; 1498 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1499 (wdc->cap & WDC_CAPABILITY_MODE)) 1500 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1501 != CMD_OK) 1502 continue; 1503 if (!printed) { 1504 aprint_normal("%s DMA mode %d", sep, i); 1505 sep = ","; 1506 printed = 1; 1507 } 1508 if (wdc->cap & WDC_CAPABILITY_DMA) { 1509 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1510 wdc->DMA_cap < i) 1511 continue; 1512 drvp->DMA_mode = i; 1513 drvp->DMA_cap = i; 1514 drvp->drive_flags |= DRIVE_DMA; 1515 } 1516 break; 1517 } 1518 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1519 printed = 0; 1520 for (i = 7; i >= 0; i--) { 1521 if ((params.atap_udmamode_supp & (1 << i)) 1522 == 0) 1523 continue; 1524 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1525 (wdc->cap & WDC_CAPABILITY_UDMA)) 1526 if (ata_set_mode(drvp, 0x40 | i, 1527 AT_WAIT) != CMD_OK) 1528 continue; 1529 if (!printed) { 1530 aprint_normal("%s Ultra-DMA mode %d", 1531 sep, i); 1532 if (i == 2) 1533 aprint_normal(" (Ultra/33)"); 1534 else if (i == 4) 1535 aprint_normal(" (Ultra/66)"); 1536 else if (i == 5) 1537 aprint_normal(" (Ultra/100)"); 1538 else if (i == 6) 1539 aprint_normal(" (Ultra/133)"); 1540 sep = ","; 1541 printed = 1; 1542 } 1543 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1544 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1545 wdc->UDMA_cap < i) 1546 continue; 1547 drvp->UDMA_mode = i; 1548 drvp->UDMA_cap = i; 1549 drvp->drive_flags |= DRIVE_UDMA; 1550 } 1551 break; 1552 } 1553 } 1554 aprint_normal("\n"); 1555 } 1556 1557 /* Try to guess ATA version here, if it didn't get reported */ 1558 if (drvp->ata_vers == 0) { 1559 if (drvp->drive_flags & DRIVE_UDMA) 1560 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1561 else if (drvp->PIO_cap > 2) 1562 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1563 } 1564 cf_flags = drv_dev->dv_cfdata->cf_flags; 1565 if (cf_flags & ATA_CONFIG_PIO_SET) { 1566 drvp->PIO_mode = 1567 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1568 drvp->drive_flags |= DRIVE_MODE; 1569 } 1570 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1571 /* don't care about DMA modes */ 1572 return; 1573 } 1574 if (cf_flags & ATA_CONFIG_DMA_SET) { 1575 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1576 ATA_CONFIG_DMA_DISABLE) { 1577 drvp->drive_flags &= ~DRIVE_DMA; 1578 } else { 1579 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1580 ATA_CONFIG_DMA_OFF; 1581 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1582 } 1583 } 1584 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1585 /* don't care about UDMA modes */ 1586 return; 1587 } 1588 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1589 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1590 ATA_CONFIG_UDMA_DISABLE) { 1591 drvp->drive_flags &= ~DRIVE_UDMA; 1592 } else { 1593 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1594 ATA_CONFIG_UDMA_OFF; 1595 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1596 } 1597 } 1598 } 1599 1600 /* 1601 * downgrade the transfer mode of a drive after an error. return 1 if 1602 * downgrade was possible, 0 otherwise. 1603 */ 1604 int 1605 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1606 { 1607 struct wdc_channel *chp = drvp->chnl_softc; 1608 struct wdc_softc *wdc = chp->ch_wdc; 1609 struct device *drv_dev = drvp->drv_softc; 1610 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1611 1612 /* if drive or controller don't know its mode, we can't do much */ 1613 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1614 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1615 return 0; 1616 /* current drive mode was set by a config flag, let it this way */ 1617 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1618 (cf_flags & ATA_CONFIG_DMA_SET) || 1619 (cf_flags & ATA_CONFIG_UDMA_SET)) 1620 return 0; 1621 1622 /* 1623 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1624 */ 1625 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1626 drvp->UDMA_mode--; 1627 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1628 drv_dev->dv_xname, drvp->UDMA_mode); 1629 } 1630 1631 /* 1632 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1633 */ 1634 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1635 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1636 drvp->PIO_mode = drvp->PIO_cap; 1637 printf("%s: transfer error, downgrading to PIO mode %d\n", 1638 drv_dev->dv_xname, drvp->PIO_mode); 1639 } else /* already using PIO, can't downgrade */ 1640 return 0; 1641 1642 wdc->set_modes(chp); 1643 wdc_print_modes(chp); 1644 /* reset the channel, which will shedule all drives for setup */ 1645 wdc_reset_channel(chp, flags | AT_RST_NOCMD); 1646 return 1; 1647 } 1648 1649 int 1650 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1651 { 1652 struct wdc_channel *chp = drvp->chnl_softc; 1653 struct wdc_softc *wdc = chp->ch_wdc; 1654 struct ata_xfer *xfer; 1655 int s, ret; 1656 1657 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1658 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1659 DEBUG_FUNCS); 1660 1661 /* set up an xfer and queue. Wait for completion */ 1662 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1663 WDC_NOSLEEP); 1664 if (xfer == NULL) { 1665 return WDC_TRY_AGAIN; 1666 } 1667 1668 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1669 wdc_c->flags |= AT_POLL; 1670 if (wdc_c->flags & AT_POLL) 1671 xfer->c_flags |= C_POLL; 1672 xfer->c_drive = drvp->drive; 1673 xfer->c_databuf = wdc_c->data; 1674 xfer->c_bcount = wdc_c->bcount; 1675 xfer->c_cmd = wdc_c; 1676 xfer->c_start = __wdccommand_start; 1677 xfer->c_intr = __wdccommand_intr; 1678 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1679 1680 s = splbio(); 1681 wdc_exec_xfer(chp, xfer); 1682 #ifdef DIAGNOSTIC 1683 if ((wdc_c->flags & AT_POLL) != 0 && 1684 (wdc_c->flags & AT_DONE) == 0) 1685 panic("wdc_exec_command: polled command not done"); 1686 #endif 1687 if (wdc_c->flags & AT_DONE) { 1688 ret = WDC_COMPLETE; 1689 } else { 1690 if (wdc_c->flags & AT_WAIT) { 1691 while ((wdc_c->flags & AT_DONE) == 0) { 1692 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1693 } 1694 ret = WDC_COMPLETE; 1695 } else { 1696 ret = WDC_QUEUED; 1697 } 1698 } 1699 splx(s); 1700 return ret; 1701 } 1702 1703 static void 1704 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1705 { 1706 struct wdc_softc *wdc = chp->ch_wdc; 1707 int drive = xfer->c_drive; 1708 struct wdc_command *wdc_c = xfer->c_cmd; 1709 1710 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1711 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1712 DEBUG_FUNCS); 1713 1714 if (wdc->cap & WDC_CAPABILITY_SELECT) 1715 wdc->select(chp,drive); 1716 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1717 WDSD_IBM | (drive << 4)); 1718 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1719 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1720 case WDCWAIT_OK: 1721 break; 1722 case WDCWAIT_TOUT: 1723 wdc_c->flags |= AT_TIMEOU; 1724 __wdccommand_done(chp, xfer); 1725 return; 1726 case WDCWAIT_THR: 1727 return; 1728 } 1729 if (wdc_c->flags & AT_POLL) { 1730 /* polled command, disable interrupts */ 1731 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1732 WDCTL_4BIT | WDCTL_IDS); 1733 } 1734 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1735 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features); 1736 1737 if ((wdc_c->flags & AT_POLL) == 0) { 1738 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1739 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1740 wdctimeout, chp); 1741 return; 1742 } 1743 /* 1744 * Polled command. Wait for drive ready or drq. Done in intr(). 1745 * Wait for at last 400ns for status bit to be valid. 1746 */ 1747 delay(10); /* 400ns delay */ 1748 __wdccommand_intr(chp, xfer, 0); 1749 } 1750 1751 static int 1752 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1753 { 1754 struct wdc_softc *wdc = chp->ch_wdc; 1755 struct wdc_command *wdc_c = xfer->c_cmd; 1756 int bcount = wdc_c->bcount; 1757 char *data = wdc_c->data; 1758 int wflags; 1759 1760 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1761 /* both wait and poll, we can tsleep here */ 1762 wflags = AT_WAIT | AT_POLL; 1763 } else { 1764 wflags = AT_POLL; 1765 } 1766 1767 again: 1768 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1769 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1770 DEBUG_INTR); 1771 /* 1772 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1773 * Reselect again, it doesn't hurt for others commands, and the time 1774 * penalty for the extra regiter write is acceptable, 1775 * wdc_exec_command() isn't called often (mosly for autoconfig) 1776 */ 1777 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1778 WDSD_IBM | (xfer->c_drive << 4)); 1779 if ((wdc_c->flags & AT_XFDONE) != 0) { 1780 /* 1781 * We have completed a data xfer. The drive should now be 1782 * in its initial state 1783 */ 1784 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1785 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1786 wflags) == WDCWAIT_TOUT) { 1787 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1788 return 0; /* IRQ was not for us */ 1789 wdc_c->flags |= AT_TIMEOU; 1790 } 1791 goto out; 1792 } 1793 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1794 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1795 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1796 return 0; /* IRQ was not for us */ 1797 wdc_c->flags |= AT_TIMEOU; 1798 goto out; 1799 } 1800 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1801 wdc->irqack(chp); 1802 if (wdc_c->flags & AT_READ) { 1803 if ((chp->ch_status & WDCS_DRQ) == 0) { 1804 wdc_c->flags |= AT_TIMEOU; 1805 goto out; 1806 } 1807 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1808 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1809 0, (u_int32_t*)data, bcount >> 2); 1810 data += bcount & 0xfffffffc; 1811 bcount = bcount & 0x03; 1812 } 1813 if (bcount > 0) 1814 bus_space_read_multi_2(chp->cmd_iot, 1815 chp->cmd_iohs[wd_data], 0, 1816 (u_int16_t *)data, bcount >> 1); 1817 /* at this point the drive should be in its initial state */ 1818 wdc_c->flags |= AT_XFDONE; 1819 /* XXX should read status register here ? */ 1820 } else if (wdc_c->flags & AT_WRITE) { 1821 if ((chp->ch_status & WDCS_DRQ) == 0) { 1822 wdc_c->flags |= AT_TIMEOU; 1823 goto out; 1824 } 1825 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1826 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1827 0, (u_int32_t*)data, bcount >> 2); 1828 data += bcount & 0xfffffffc; 1829 bcount = bcount & 0x03; 1830 } 1831 if (bcount > 0) 1832 bus_space_write_multi_2(chp->cmd_iot, 1833 chp->cmd_iohs[wd_data], 0, 1834 (u_int16_t *)data, bcount >> 1); 1835 wdc_c->flags |= AT_XFDONE; 1836 if ((wdc_c->flags & AT_POLL) == 0) { 1837 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1838 callout_reset(&chp->ch_callout, 1839 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1840 return 1; 1841 } else { 1842 goto again; 1843 } 1844 } 1845 out: 1846 __wdccommand_done(chp, xfer); 1847 return 1; 1848 } 1849 1850 static void 1851 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1852 { 1853 struct wdc_softc *wdc = chp->ch_wdc; 1854 struct wdc_command *wdc_c = xfer->c_cmd; 1855 1856 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1857 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1858 DEBUG_FUNCS); 1859 1860 1861 if (chp->ch_status & WDCS_DWF) 1862 wdc_c->flags |= AT_DF; 1863 if (chp->ch_status & WDCS_ERR) { 1864 wdc_c->flags |= AT_ERROR; 1865 wdc_c->r_error = chp->ch_error; 1866 } 1867 if ((wdc_c->flags & AT_READREG) != 0 && 1868 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1869 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1870 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1871 chp->cmd_iohs[wd_sdh], 0); 1872 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1873 chp->cmd_iohs[wd_seccnt], 0); 1874 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1875 chp->cmd_iohs[wd_sector], 0); 1876 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1877 chp->cmd_iohs[wd_cyl_lo], 0); 1878 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1879 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1880 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1881 chp->cmd_iohs[wd_error], 0); 1882 wdc_c->r_features = bus_space_read_1(chp->cmd_iot, 1883 chp->cmd_iohs[wd_features], 0); 1884 } 1885 __wdccommand_done_end(chp, xfer); 1886 } 1887 1888 static void 1889 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1890 { 1891 struct wdc_command *wdc_c = xfer->c_cmd; 1892 1893 callout_stop(&chp->ch_callout); 1894 wdc_c->flags |= AT_DONE; 1895 if (wdc_c->flags & AT_POLL) { 1896 /* enable interrupts */ 1897 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1898 WDCTL_4BIT); 1899 delay(10); /* some drives need a little delay here */ 1900 } 1901 wdc_free_xfer(chp, xfer); 1902 if (wdc_c->flags & AT_WAIT) 1903 wakeup(wdc_c); 1904 else if (wdc_c->callback) 1905 wdc_c->callback(wdc_c->callback_arg); 1906 wdcstart(chp); 1907 return; 1908 } 1909 1910 static void 1911 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1912 int reason) 1913 { 1914 struct wdc_command *wdc_c = xfer->c_cmd; 1915 1916 switch (reason) { 1917 case KILL_GONE: 1918 wdc_c->flags |= AT_GONE; 1919 break; 1920 case KILL_RESET: 1921 wdc_c->flags |= AT_RESET; 1922 break; 1923 default: 1924 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1925 reason); 1926 panic("__wdccommand_kill_xfer"); 1927 } 1928 __wdccommand_done_end(chp, xfer); 1929 1930 } 1931 1932 /* 1933 * Send a command. The drive should be ready. 1934 * Assumes interrupts are blocked. 1935 */ 1936 void 1937 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1938 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1939 u_int8_t features) 1940 { 1941 struct wdc_softc *wdc = chp->ch_wdc; 1942 1943 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1944 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1945 chp->ch_channel, drive, command, cylin, head, sector, count, 1946 features), DEBUG_FUNCS); 1947 1948 if (wdc->cap & WDC_CAPABILITY_SELECT) 1949 wdc->select(chp,drive); 1950 1951 /* Select drive, head, and addressing mode. */ 1952 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1953 WDSD_IBM | (drive << 4) | head); 1954 /* Load parameters into the wd_features register. */ 1955 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 1956 features); 1957 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1959 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1960 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1961 0, cylin >> 8); 1962 1963 /* Send command. */ 1964 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1965 return; 1966 } 1967 1968 /* 1969 * Send a 48-bit addressing command. The drive should be ready. 1970 * Assumes interrupts are blocked. 1971 */ 1972 void 1973 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1974 u_int64_t blkno, u_int16_t count) 1975 { 1976 struct wdc_softc *wdc = chp->ch_wdc; 1977 1978 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1979 "count=%d\n", wdc->sc_dev.dv_xname, 1980 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1981 DEBUG_FUNCS); 1982 1983 if (wdc->cap & WDC_CAPABILITY_SELECT) 1984 wdc->select(chp,drive); 1985 1986 /* Select drive, head, and addressing mode. */ 1987 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1988 (drive << 4) | WDSD_LBA); 1989 1990 /* previous */ 1991 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1992 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1993 0, count >> 8); 1994 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1995 0, blkno >> 24); 1996 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1997 0, blkno >> 32); 1998 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1999 0, blkno >> 40); 2000 2001 /* current */ 2002 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2003 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2004 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2006 0, blkno >> 8); 2007 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2008 0, blkno >> 16); 2009 2010 /* Send command. */ 2011 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2012 return; 2013 } 2014 2015 /* 2016 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2017 * tested by the caller. 2018 */ 2019 void 2020 wdccommandshort(struct wdc_channel *chp, int drive, int command) 2021 { 2022 struct wdc_softc *wdc = chp->ch_wdc; 2023 2024 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2025 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 2026 DEBUG_FUNCS); 2027 2028 if (wdc->cap & WDC_CAPABILITY_SELECT) 2029 wdc->select(chp,drive); 2030 2031 /* Select drive. */ 2032 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2033 WDSD_IBM | (drive << 4)); 2034 2035 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2036 } 2037 2038 /* Add a command to the queue and start controller. Must be called at splbio */ 2039 void 2040 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2041 { 2042 2043 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2044 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 2045 2046 /* complete xfer setup */ 2047 xfer->c_chp = chp; 2048 2049 /* insert at the end of command list */ 2050 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2051 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2052 chp->ch_flags), DEBUG_XFERS); 2053 wdcstart(chp); 2054 } 2055 2056 struct ata_xfer * 2057 wdc_get_xfer(int flags) 2058 { 2059 struct ata_xfer *xfer; 2060 int s; 2061 2062 s = splbio(); 2063 xfer = pool_get(&wdc_xfer_pool, 2064 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2065 splx(s); 2066 if (xfer != NULL) { 2067 memset(xfer, 0, sizeof(struct ata_xfer)); 2068 } 2069 return xfer; 2070 } 2071 2072 void 2073 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2074 { 2075 struct wdc_softc *wdc = chp->ch_wdc; 2076 int s; 2077 2078 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2079 (*wdc->free_hw)(chp); 2080 s = splbio(); 2081 chp->ch_flags &= ~WDCF_ACTIVE; 2082 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2083 pool_put(&wdc_xfer_pool, xfer); 2084 splx(s); 2085 } 2086 2087 /* 2088 * Kill off all pending xfers for a wdc_channel. 2089 * 2090 * Must be called at splbio(). 2091 */ 2092 void 2093 wdc_kill_pending(struct wdc_channel *chp) 2094 { 2095 struct ata_xfer *xfer; 2096 2097 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 2098 chp = xfer->c_chp; 2099 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 2100 } 2101 } 2102 2103 static void 2104 __wdcerror(struct wdc_channel *chp, char *msg) 2105 { 2106 struct wdc_softc *wdc = chp->ch_wdc; 2107 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2108 2109 if (xfer == NULL) 2110 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2111 msg); 2112 else 2113 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2114 chp->ch_channel, xfer->c_drive, msg); 2115 } 2116 2117 /* 2118 * the bit bucket 2119 */ 2120 void 2121 wdcbit_bucket(struct wdc_channel *chp, int size) 2122 { 2123 2124 for (; size >= 2; size -= 2) 2125 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2126 if (size) 2127 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2128 } 2129 2130 int 2131 wdc_addref(struct wdc_channel *chp) 2132 { 2133 struct wdc_softc *wdc = chp->ch_wdc; 2134 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2135 int s, error = 0; 2136 2137 s = splbio(); 2138 if (adapt->adapt_refcnt++ == 0 && 2139 adapt->adapt_enable != NULL) { 2140 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2141 if (error) 2142 adapt->adapt_refcnt--; 2143 } 2144 splx(s); 2145 return (error); 2146 } 2147 2148 void 2149 wdc_delref(struct wdc_channel *chp) 2150 { 2151 struct wdc_softc *wdc = chp->ch_wdc; 2152 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2153 int s; 2154 2155 s = splbio(); 2156 if (adapt->adapt_refcnt-- == 1 && 2157 adapt->adapt_enable != NULL) 2158 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2159 splx(s); 2160 } 2161 2162 void 2163 wdc_print_modes(struct wdc_channel *chp) 2164 { 2165 struct wdc_softc *wdc = chp->ch_wdc; 2166 int drive; 2167 struct ata_drive_datas *drvp; 2168 2169 for (drive = 0; drive < 2; drive++) { 2170 drvp = &chp->ch_drive[drive]; 2171 if ((drvp->drive_flags & DRIVE) == 0) 2172 continue; 2173 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2174 drvp->drv_softc->dv_xname, 2175 wdc->sc_dev.dv_xname, 2176 chp->ch_channel, drive, drvp->PIO_mode); 2177 if (drvp->drive_flags & DRIVE_DMA) 2178 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2179 if (drvp->drive_flags & DRIVE_UDMA) { 2180 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2181 if (drvp->UDMA_mode == 2) 2182 aprint_normal(" (Ultra/33)"); 2183 else if (drvp->UDMA_mode == 4) 2184 aprint_normal(" (Ultra/66)"); 2185 else if (drvp->UDMA_mode == 5) 2186 aprint_normal(" (Ultra/100)"); 2187 else if (drvp->UDMA_mode == 6) 2188 aprint_normal(" (Ultra/133)"); 2189 } 2190 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2191 aprint_normal(" (using DMA data transfers)"); 2192 aprint_normal("\n"); 2193 } 2194 } 2195
Indexes created Mon Sep 22 13:09:51 GMT 2025