wdc.c revision 1.188
1 /* $NetBSD: wdc.c,v 1.188 2004/08/10 02:40:51 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.188 2004/08/10 02:40:51 mycroft Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct wdc_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct wdc_channel *, int, int, int); 156 157 #define DEBUG_INTR 0x01 158 #define DEBUG_XFERS 0x02 159 #define DEBUG_STATUS 0x04 160 #define DEBUG_FUNCS 0x08 161 #define DEBUG_PROBE 0x10 162 #define DEBUG_DETACH 0x20 163 #define DEBUG_DELAY 0x40 164 #ifdef WDCDEBUG 165 int wdcdebug_mask = 0; 166 int wdc_nxfer = 0; 167 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 168 #else 169 #define WDCDEBUG_PRINT(args, level) 170 #endif 171 172 /* 173 * A queue of atabus instances, used to ensure the same bus probe order 174 * for a given hardware configuration at each boot. 175 */ 176 struct atabus_initq_head atabus_initq_head = 177 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 178 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 179 180 /* 181 * Initialize the "shadow register" handles for a standard wdc controller. 182 */ 183 void 184 wdc_init_shadow_regs(struct wdc_channel *chp) 185 { 186 187 chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command]; 188 chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error]; 189 } 190 191 /* Test to see controller with at last one attached drive is there. 192 * Returns a bit for each possible drive found (0x01 for drive 0, 193 * 0x02 for drive 1). 194 * Logic: 195 * - If a status register is at 0xff, assume there is no drive here 196 * (ISA has pull-up resistors). Similarly if the status register has 197 * the value we last wrote to the bus (for IDE interfaces without pullups). 198 * If no drive at all -> return. 199 * - reset the controller, wait for it to complete (may take up to 31s !). 200 * If timeout -> return. 201 * - test ATA/ATAPI signatures. If at last one drive found -> return. 202 * - try an ATA command on the master. 203 */ 204 205 static void 206 wdc_drvprobe(struct wdc_channel *chp) 207 { 208 struct ataparams params; 209 struct wdc_softc *wdc = chp->ch_wdc; 210 u_int8_t st0 = 0, st1 = 0; 211 int i, error; 212 213 if (wdcprobe1(chp, 0) == 0) { 214 /* No drives, abort the attach here. */ 215 return; 216 } 217 218 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 219 for (i = 0; i < mstohz(3000); i++) { 220 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 221 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 222 wdc->select(chp,0); 223 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 224 0, WDSD_IBM); 225 delay(10); /* 400ns delay */ 226 st0 = bus_space_read_1(chp->cmd_iot, 227 chp->cmd_iohs[wd_status], 0); 228 } 229 230 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 231 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 232 wdc->select(chp,1); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 234 0, WDSD_IBM | 0x10); 235 delay(10); /* 400ns delay */ 236 st1 = bus_space_read_1(chp->cmd_iot, 237 chp->cmd_iohs[wd_status], 0); 238 } 239 240 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 241 == 0 || 242 (st0 & WDCS_DRDY)) && 243 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 244 == 0 || 245 (st1 & WDCS_DRDY))) 246 break; 247 tsleep(¶ms, PRIBIO, "atadrdy", 1); 248 } 249 if ((st0 & WDCS_DRDY) == 0) 250 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 251 if ((st1 & WDCS_DRDY) == 0) 252 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 253 254 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 255 wdc->sc_dev.dv_xname, 256 chp->ch_channel, st0, st1), DEBUG_PROBE); 257 258 /* Wait a bit, some devices are weird just after a reset. */ 259 delay(5000); 260 261 for (i = 0; i < 2; i++) { 262 /* XXX This should be done by other code. */ 263 chp->ch_drive[i].chnl_softc = chp; 264 chp->ch_drive[i].drive = i; 265 266 /* 267 * Init error counter so that an error withing the first xfers 268 * will trigger a downgrade 269 */ 270 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 271 272 /* If controller can't do 16bit flag the drives as 32bit */ 273 if ((wdc->cap & 274 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 275 WDC_CAPABILITY_DATA32) 276 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 277 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 278 continue; 279 280 /* Shortcut in case we've been shutdown */ 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 return; 283 284 /* issue an identify, to try to detect ghosts */ 285 error = ata_get_params(&chp->ch_drive[i], 286 AT_WAIT | AT_POLL, ¶ms); 287 if (error != CMD_OK) { 288 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 289 290 /* Shortcut in case we've been shutdown */ 291 if (chp->ch_flags & WDCF_SHUTDOWN) 292 return; 293 294 error = ata_get_params(&chp->ch_drive[i], 295 AT_WAIT | AT_POLL, ¶ms); 296 } 297 if (error == CMD_OK) { 298 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 299 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 300 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 301 } else { 302 chp->ch_drive[i].drive_flags &= 303 ~(DRIVE_ATA | DRIVE_ATAPI); 304 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 305 wdc->sc_dev.dv_xname, 306 chp->ch_channel, i, error), DEBUG_PROBE); 307 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 308 continue; 309 /* 310 * Pre-ATA drive ? 311 * Test registers writability (Error register not 312 * writable, but cyllo is), then try an ATA command. 313 */ 314 if (wdc->cap & WDC_CAPABILITY_SELECT) 315 wdc->select(chp,i); 316 bus_space_write_1(chp->cmd_iot, 317 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 318 delay(10); /* 400ns delay */ 319 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 320 0, 0x58); 321 bus_space_write_1(chp->cmd_iot, 322 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 323 if (bus_space_read_1(chp->cmd_iot, 324 chp->cmd_iohs[wd_error], 0) == 0x58 || 325 bus_space_read_1(chp->cmd_iot, 326 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 327 WDCDEBUG_PRINT(("%s:%d:%d: register " 328 "writability failed\n", 329 wdc->sc_dev.dv_xname, 330 chp->ch_channel, i), DEBUG_PROBE); 331 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 332 continue; 333 } 334 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 335 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 336 wdc->sc_dev.dv_xname, 337 chp->ch_channel, i), DEBUG_PROBE); 338 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 339 continue; 340 } 341 bus_space_write_1(chp->cmd_iot, 342 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 343 delay(10); /* 400ns delay */ 344 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 345 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 346 wdc->sc_dev.dv_xname, 347 chp->ch_channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 } else { 350 chp->ch_drive[0].drive_flags &= 351 ~(DRIVE_ATA | DRIVE_ATAPI); 352 chp->ch_drive[1].drive_flags &= 353 ~(DRIVE_ATA | DRIVE_ATAPI); 354 } 355 } 356 } 357 } 358 359 void 360 atabusconfig(struct atabus_softc *atabus_sc) 361 { 362 struct wdc_channel *chp = atabus_sc->sc_chan; 363 struct wdc_softc *wdc = chp->ch_wdc; 364 int i, error, need_delref = 0; 365 struct atabus_initq *atabus_initq = NULL; 366 367 if ((error = wdc_addref(chp)) != 0) { 368 aprint_error("%s: unable to enable controller\n", 369 wdc->sc_dev.dv_xname); 370 goto out; 371 } 372 need_delref = 1; 373 374 /* Probe for the drives. */ 375 (*wdc->drv_probe)(chp); 376 377 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 378 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 379 DEBUG_PROBE); 380 381 /* If no drives, abort here */ 382 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 383 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 384 goto out; 385 386 /* Shortcut in case we've been shutdown */ 387 if (chp->ch_flags & WDCF_SHUTDOWN) 388 goto out; 389 390 /* Make sure the devices probe in atabus order to avoid jitter. */ 391 simple_lock(&atabus_interlock); 392 while(1) { 393 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 394 if (atabus_initq->atabus_sc == atabus_sc) 395 break; 396 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 397 &atabus_interlock); 398 } 399 simple_unlock(&atabus_interlock); 400 401 /* 402 * Attach an ATAPI bus, if needed. 403 */ 404 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 405 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 406 #if NATAPIBUS > 0 407 wdc_atapibus_attach(atabus_sc); 408 #else 409 /* 410 * Fake the autoconfig "not configured" message 411 */ 412 aprint_normal("atapibus at %s not configured\n", 413 wdc->sc_dev.dv_xname); 414 chp->atapibus = NULL; 415 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 416 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 417 #endif 418 } 419 420 for (i = 0; i < 2; i++) { 421 struct ata_device adev; 422 if ((chp->ch_drive[i].drive_flags & 423 (DRIVE_ATA | DRIVE_OLD)) == 0) { 424 continue; 425 } 426 memset(&adev, 0, sizeof(struct ata_device)); 427 adev.adev_bustype = &wdc_ata_bustype; 428 adev.adev_channel = chp->ch_channel; 429 adev.adev_openings = 1; 430 adev.adev_drv_data = &chp->ch_drive[i]; 431 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 432 &adev, ataprint); 433 if (chp->ata_drives[i] != NULL) 434 wdc_probe_caps(&chp->ch_drive[i]); 435 else 436 chp->ch_drive[i].drive_flags &= 437 ~(DRIVE_ATA | DRIVE_OLD); 438 } 439 440 /* now that we know the drives, the controller can set its modes */ 441 if (wdc->cap & WDC_CAPABILITY_MODE) { 442 wdc->set_modes(chp); 443 wdc_print_modes(chp); 444 } 445 #if NATARAID > 0 446 if (wdc->cap & WDC_CAPABILITY_RAID) 447 for (i = 0; i < 2; i++) 448 if (chp->ata_drives[i] != NULL) 449 ata_raid_check_component(chp->ata_drives[i]); 450 #endif /* NATARAID > 0 */ 451 452 /* 453 * reset drive_flags for unattached devices, reset state for attached 454 * ones 455 */ 456 for (i = 0; i < 2; i++) { 457 if (chp->ch_drive[i].drv_softc == NULL) 458 chp->ch_drive[i].drive_flags = 0; 459 else 460 chp->ch_drive[i].state = 0; 461 } 462 463 out: 464 if (atabus_initq == NULL) { 465 simple_lock(&atabus_interlock); 466 while(1) { 467 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 468 if (atabus_initq->atabus_sc == atabus_sc) 469 break; 470 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 471 &atabus_interlock); 472 } 473 simple_unlock(&atabus_interlock); 474 } 475 simple_lock(&atabus_interlock); 476 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 477 simple_unlock(&atabus_interlock); 478 479 free(atabus_initq, M_DEVBUF); 480 wakeup(&atabus_initq_head); 481 482 config_pending_decr(); 483 if (need_delref) 484 wdc_delref(chp); 485 } 486 487 int 488 wdcprobe(struct wdc_channel *chp) 489 { 490 491 return (wdcprobe1(chp, 1)); 492 } 493 494 static int 495 wdcprobe1(struct wdc_channel *chp, int poll) 496 { 497 struct wdc_softc *wdc = chp->ch_wdc; 498 u_int8_t st0, st1, sc, sn, cl, ch; 499 u_int8_t ret_value = 0x03; 500 u_int8_t drive; 501 int s; 502 503 /* 504 * Sanity check to see if the wdc channel responds at all. 505 */ 506 507 s = splbio(); 508 if (wdc == NULL || 509 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 510 511 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 512 wdc->select(chp,0); 513 514 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 515 WDSD_IBM); 516 delay(10); /* 400ns delay */ 517 st0 = bus_space_read_1(chp->cmd_iot, 518 chp->cmd_iohs[wd_status], 0); 519 520 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 521 wdc->select(chp,1); 522 523 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 524 WDSD_IBM | 0x10); 525 delay(10); /* 400ns delay */ 526 st1 = bus_space_read_1(chp->cmd_iot, 527 chp->cmd_iohs[wd_status], 0); 528 529 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 530 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 531 chp->ch_channel, st0, st1), DEBUG_PROBE); 532 533 if (st0 == 0xff || st0 == WDSD_IBM) 534 ret_value &= ~0x01; 535 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 536 ret_value &= ~0x02; 537 /* Register writability test, drive 0. */ 538 if (ret_value & 0x01) { 539 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 540 wdc->select(chp,0); 541 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 542 0, WDSD_IBM); 543 bus_space_write_1(chp->cmd_iot, 544 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 545 cl = bus_space_read_1(chp->cmd_iot, 546 chp->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x02) { 548 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x02\n", 550 wdc != NULL ? 551 wdc->sc_dev.dv_xname : "wdcprobe", 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(chp->cmd_iot, 557 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 558 cl = bus_space_read_1(chp->cmd_iot, 559 chp->cmd_iohs[wd_cyl_lo], 0); 560 if (cl != 0x01) { 561 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 562 "got 0x%x != 0x01\n", 563 wdc != NULL ? 564 wdc->sc_dev.dv_xname : "wdcprobe", 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x01; 568 } 569 bus_space_write_1(chp->cmd_iot, 570 chp->cmd_iohs[wd_sector], 0, 0x01); 571 cl = bus_space_read_1(chp->cmd_iot, 572 chp->cmd_iohs[wd_sector], 0); 573 if (cl != 0x01) { 574 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 575 "got 0x%x != 0x01\n", 576 wdc != NULL ? 577 wdc->sc_dev.dv_xname : "wdcprobe", 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x01; 581 } 582 bus_space_write_1(chp->cmd_iot, 583 chp->cmd_iohs[wd_sector], 0, 0x02); 584 cl = bus_space_read_1(chp->cmd_iot, 585 chp->cmd_iohs[wd_sector], 0); 586 if (cl != 0x02) { 587 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 588 "got 0x%x != 0x02\n", 589 wdc != NULL ? 590 wdc->sc_dev.dv_xname : "wdcprobe", 591 chp->ch_channel, cl), 592 DEBUG_PROBE); 593 ret_value &= ~0x01; 594 } 595 cl = bus_space_read_1(chp->cmd_iot, 596 chp->cmd_iohs[wd_cyl_lo], 0); 597 if (cl != 0x01) { 598 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 599 "got 0x%x != 0x01\n", 600 wdc != NULL ? 601 wdc->sc_dev.dv_xname : "wdcprobe", 602 chp->ch_channel, cl), 603 DEBUG_PROBE); 604 ret_value &= ~0x01; 605 } 606 } 607 /* Register writability test, drive 1. */ 608 if (ret_value & 0x02) { 609 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 610 wdc->select(chp,1); 611 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 612 0, WDSD_IBM | 0x10); 613 bus_space_write_1(chp->cmd_iot, 614 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 615 cl = bus_space_read_1(chp->cmd_iot, 616 chp->cmd_iohs[wd_cyl_lo], 0); 617 if (cl != 0x02) { 618 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 619 "got 0x%x != 0x02\n", 620 wdc != NULL ? 621 wdc->sc_dev.dv_xname : "wdcprobe", 622 chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(chp->cmd_iot, 627 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 628 cl = bus_space_read_1(chp->cmd_iot, 629 chp->cmd_iohs[wd_cyl_lo], 0); 630 if (cl != 0x01) { 631 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 632 "got 0x%x != 0x01\n", 633 wdc != NULL ? 634 wdc->sc_dev.dv_xname : "wdcprobe", 635 chp->ch_channel, cl), 636 DEBUG_PROBE); 637 ret_value &= ~0x02; 638 } 639 bus_space_write_1(chp->cmd_iot, 640 chp->cmd_iohs[wd_sector], 0, 0x01); 641 cl = bus_space_read_1(chp->cmd_iot, 642 chp->cmd_iohs[wd_sector], 0); 643 if (cl != 0x01) { 644 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 645 "got 0x%x != 0x01\n", 646 wdc != NULL ? 647 wdc->sc_dev.dv_xname : "wdcprobe", 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 bus_space_write_1(chp->cmd_iot, 653 chp->cmd_iohs[wd_sector], 0, 0x02); 654 cl = bus_space_read_1(chp->cmd_iot, 655 chp->cmd_iohs[wd_sector], 0); 656 if (cl != 0x02) { 657 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 658 "got 0x%x != 0x02\n", 659 wdc != NULL ? 660 wdc->sc_dev.dv_xname : "wdcprobe", 661 chp->ch_channel, cl), 662 DEBUG_PROBE); 663 ret_value &= ~0x02; 664 } 665 cl = bus_space_read_1(chp->cmd_iot, 666 chp->cmd_iohs[wd_cyl_lo], 0); 667 if (cl != 0x01) { 668 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 669 "got 0x%x != 0x01\n", 670 wdc != NULL ? 671 wdc->sc_dev.dv_xname : "wdcprobe", 672 chp->ch_channel, cl), 673 DEBUG_PROBE); 674 ret_value &= ~0x02; 675 } 676 } 677 678 if (ret_value == 0) { 679 splx(s); 680 return 0; 681 } 682 } 683 684 685 #if 0 /* XXX this break some ATA or ATAPI devices */ 686 /* 687 * reset bus. Also send an ATAPI_RESET to devices, in case there are 688 * ATAPI device out there which don't react to the bus reset 689 */ 690 if (ret_value & 0x01) { 691 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 692 wdc->select(chp,0); 693 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 694 0, WDSD_IBM); 695 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 696 ATAPI_SOFT_RESET); 697 } 698 if (ret_value & 0x02) { 699 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 700 wdc->select(chp,0); 701 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 702 0, WDSD_IBM | 0x10); 703 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 704 ATAPI_SOFT_RESET); 705 } 706 707 delay(5000); 708 #endif 709 710 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 711 wdc->select(chp,0); 712 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 713 delay(10); /* 400ns delay */ 714 /* assert SRST, wait for reset to complete */ 715 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 716 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 717 DELAY(1000); 718 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 719 WDCTL_IDS | WDCTL_4BIT); 720 DELAY(2000); 721 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 722 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 723 delay(10); /* 400ns delay */ 724 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 725 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 726 wdc->irqack(chp); 727 splx(s); 728 729 ret_value = __wdcwait_reset(chp, ret_value, poll); 730 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 731 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 732 ret_value), DEBUG_PROBE); 733 734 /* if reset failed, there's nothing here */ 735 if (ret_value == 0) 736 return 0; 737 738 /* 739 * Test presence of drives. First test register signatures looking 740 * for ATAPI devices. If it's not an ATAPI and reset said there may 741 * be something here assume it's ATA or OLD. Ghost will be killed 742 * later in attach routine. 743 */ 744 for (drive = 0; drive < 2; drive++) { 745 if ((ret_value & (0x01 << drive)) == 0) 746 continue; 747 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 748 wdc->select(chp,drive); 749 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 750 WDSD_IBM | (drive << 4)); 751 delay(10); /* 400ns delay */ 752 /* Save registers contents */ 753 sc = bus_space_read_1(chp->cmd_iot, 754 chp->cmd_iohs[wd_seccnt], 0); 755 sn = bus_space_read_1(chp->cmd_iot, 756 chp->cmd_iohs[wd_sector], 0); 757 cl = bus_space_read_1(chp->cmd_iot, 758 chp->cmd_iohs[wd_cyl_lo], 0); 759 ch = bus_space_read_1(chp->cmd_iot, 760 chp->cmd_iohs[wd_cyl_hi], 0); 761 762 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 763 "cl=0x%x ch=0x%x\n", 764 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 765 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 766 /* 767 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 768 * we get wrong values here, so ignore it. 769 */ 770 if (cl == 0x14 && ch == 0xeb) { 771 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 772 } else { 773 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 774 if (wdc == NULL || 775 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 776 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 777 } 778 } 779 return (ret_value); 780 } 781 782 void 783 wdcattach(struct wdc_channel *chp) 784 { 785 struct wdc_softc *wdc = chp->ch_wdc; 786 static int inited = 0; 787 788 if (chp->ch_flags & WDCF_DISABLED) 789 return; 790 791 /* initialise global data */ 792 callout_init(&chp->ch_callout); 793 if (wdc->drv_probe == NULL) 794 wdc->drv_probe = wdc_drvprobe; 795 if (inited == 0) { 796 /* Initialize the ata_xfer pool. */ 797 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 798 0, 0, "wdcspl", NULL); 799 inited++; 800 } 801 TAILQ_INIT(&chp->ch_queue->queue_xfer); 802 chp->ch_queue->queue_freeze = 0; 803 chp->ch_queue->active_xfer = NULL; 804 805 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 806 } 807 808 int 809 wdcactivate(struct device *self, enum devact act) 810 { 811 struct wdc_softc *wdc = (struct wdc_softc *)self; 812 int s, i, error = 0; 813 814 s = splbio(); 815 switch (act) { 816 case DVACT_ACTIVATE: 817 error = EOPNOTSUPP; 818 break; 819 820 case DVACT_DEACTIVATE: 821 for (i = 0; i < wdc->nchannels; i++) { 822 error = config_deactivate(wdc->channels[i]->atabus); 823 if (error) 824 break; 825 } 826 break; 827 } 828 splx(s); 829 return (error); 830 } 831 832 int 833 wdcdetach(struct device *self, int flags) 834 { 835 struct wdc_softc *wdc = (struct wdc_softc *)self; 836 struct wdc_channel *chp; 837 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 838 int i, error = 0; 839 840 for (i = 0; i < wdc->nchannels; i++) { 841 chp = wdc->channels[i]; 842 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 843 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 844 error = config_detach(chp->atabus, flags); 845 if (error) 846 break; 847 } 848 if (adapt->adapt_refcnt != 0) { 849 #ifdef DIAGNOSTIC 850 printf("wdcdetach: refcnt should be 0 here??\n"); 851 #endif 852 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 853 } 854 return (error); 855 } 856 857 /* 858 * Start I/O on a controller, for the given channel. 859 * The first xfer may be not for our channel if the channel queues 860 * are shared. 861 */ 862 void 863 wdcstart(struct wdc_channel *chp) 864 { 865 struct wdc_softc *wdc = chp->ch_wdc; 866 struct ata_xfer *xfer; 867 868 #ifdef WDC_DIAGNOSTIC 869 int spl1, spl2; 870 871 spl1 = splbio(); 872 spl2 = splbio(); 873 if (spl2 != spl1) { 874 printf("wdcstart: not at splbio()\n"); 875 panic("wdcstart"); 876 } 877 splx(spl2); 878 splx(spl1); 879 #endif /* WDC_DIAGNOSTIC */ 880 881 /* is there a xfer ? */ 882 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 883 return; 884 885 /* adjust chp, in case we have a shared queue */ 886 chp = xfer->c_chp; 887 888 if (chp->ch_queue->active_xfer != NULL) { 889 return; /* channel aleady active */ 890 } 891 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 892 return; /* queue froozen */ 893 } 894 #ifdef DIAGNOSTIC 895 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 896 panic("wdcstart: channel waiting for irq"); 897 #endif 898 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 899 if (!(*wdc->claim_hw)(chp, 0)) 900 return; 901 902 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 903 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 904 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 905 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 906 chp->ch_drive[xfer->c_drive].state = 0; 907 } 908 chp->ch_queue->active_xfer = xfer; 909 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 910 911 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 912 KASSERT(xfer->c_flags & C_POLL); 913 xfer->c_start(chp, xfer); 914 } 915 916 /* restart an interrupted I/O */ 917 void 918 wdcrestart(void *v) 919 { 920 struct wdc_channel *chp = v; 921 int s; 922 923 s = splbio(); 924 wdcstart(chp); 925 splx(s); 926 } 927 928 929 /* 930 * Interrupt routine for the controller. Acknowledge the interrupt, check for 931 * errors on the current operation, mark it done if necessary, and start the 932 * next request. Also check for a partially done transfer, and continue with 933 * the next chunk if so. 934 */ 935 int 936 wdcintr(void *arg) 937 { 938 struct wdc_channel *chp = arg; 939 struct wdc_softc *wdc = chp->ch_wdc; 940 struct ata_xfer *xfer; 941 int ret; 942 943 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 944 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 945 DEBUG_INTR); 946 return (0); 947 } 948 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 949 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 950 /* try to clear the pending interrupt anyway */ 951 (void)bus_space_read_1(chp->cmd_iot, 952 chp->cmd_iohs[wd_status], 0); 953 return (0); 954 } 955 956 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 957 xfer = chp->ch_queue->active_xfer; 958 #ifdef DIAGNOSTIC 959 if (xfer == NULL) 960 panic("wdcintr: no xfer"); 961 #endif 962 if (chp->ch_flags & WDCF_DMA_WAIT) { 963 wdc->dma_status = 964 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 965 xfer->c_drive, WDC_DMAEND_END); 966 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 967 /* IRQ not for us, not detected by DMA engine */ 968 return 0; 969 } 970 chp->ch_flags &= ~WDCF_DMA_WAIT; 971 } 972 chp->ch_flags &= ~WDCF_IRQ_WAIT; 973 ret = xfer->c_intr(chp, xfer, 1); 974 if (ret == 0) /* irq was not for us, still waiting for irq */ 975 chp->ch_flags |= WDCF_IRQ_WAIT; 976 return (ret); 977 } 978 979 /* Put all disk in RESET state */ 980 void 981 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 982 { 983 struct wdc_channel *chp = drvp->chnl_softc; 984 struct wdc_softc *wdc = chp->ch_wdc; 985 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 986 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 987 DEBUG_FUNCS); 988 989 990 wdc_reset_channel(chp, flags); 991 } 992 993 void 994 wdc_reset_channel(struct wdc_channel *chp, int flags) 995 { 996 TAILQ_HEAD(, ata_xfer) reset_xfer; 997 struct ata_xfer *xfer, *next_xfer; 998 int drive; 999 1000 chp->ch_queue->queue_freeze++; 1001 TAILQ_INIT(&reset_xfer); 1002 1003 /* if we can poll or wait it's OK, otherwise wake up the kernel 1004 * thread 1005 */ 1006 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 1007 if (chp->ch_flags & WDCF_TH_RESET) { 1008 /* no need to schedule a reset more than one time */ 1009 return; 1010 } 1011 chp->ch_flags |= WDCF_TH_RESET; 1012 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1013 wakeup(&chp->ch_thread); 1014 return; 1015 } 1016 1017 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1018 /* 1019 * if the current command if on an ATAPI device, issue a 1020 * ATAPI_SOFT_RESET 1021 */ 1022 xfer = chp->ch_queue->active_xfer; 1023 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1024 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1025 if (flags & AT_WAIT) 1026 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1027 else 1028 delay(1000); 1029 } 1030 1031 /* reset the channel */ 1032 if (flags & AT_WAIT) 1033 (void) wdcreset(chp, RESET_SLEEP); 1034 else 1035 (void) wdcreset(chp, RESET_POLL); 1036 1037 /* 1038 * wait a bit after reset; in case the DMA engines needs some time 1039 * to recover. 1040 */ 1041 if (flags & AT_WAIT) 1042 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1043 else 1044 delay(1000); 1045 /* 1046 * look for pending xfers. If we have a shared queue, we'll also reset 1047 * the other channel if the current xfer is running on it. 1048 * Then we'll dequeue only the xfers for this channel. 1049 */ 1050 if ((flags & AT_RST_NOCMD) == 0) { 1051 /* 1052 * move all xfers queued for this channel to the reset queue, 1053 * and then process the current xfer and then the reset queue. 1054 * We have to use a temporary queue because c_kill_xfer() 1055 * may requeue commands. 1056 */ 1057 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1058 xfer != NULL; xfer = next_xfer) { 1059 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1060 if (xfer->c_chp != chp) 1061 continue; 1062 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1063 xfer, c_xferchain); 1064 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1065 } 1066 xfer = chp->ch_queue->active_xfer; 1067 if (xfer) { 1068 if (xfer->c_chp != chp) 1069 wdc_reset_channel(xfer->c_chp, flags); 1070 else { 1071 callout_stop(&chp->ch_callout); 1072 /* 1073 * If we're waiting for DMA, stop the 1074 * DMA engine 1075 */ 1076 if (chp->ch_flags & WDCF_DMA_WAIT) { 1077 (*chp->ch_wdc->dma_finish)( 1078 chp->ch_wdc->dma_arg, 1079 chp->ch_channel, 1080 xfer->c_drive, 1081 WDC_DMAEND_ABRT_QUIET); 1082 chp->ch_flags &= ~WDCF_DMA_WAIT; 1083 } 1084 chp->ch_queue->active_xfer = NULL; 1085 if ((flags & AT_RST_EMERG) == 0) 1086 xfer->c_kill_xfer( 1087 chp, xfer, KILL_RESET); 1088 } 1089 } 1090 1091 for (xfer = TAILQ_FIRST(&reset_xfer); 1092 xfer != NULL; xfer = next_xfer) { 1093 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1094 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1095 if ((flags & AT_RST_EMERG) == 0) 1096 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1097 } 1098 } 1099 for (drive = 0; drive < 2; drive++) { 1100 chp->ch_drive[drive].state = 0; 1101 } 1102 chp->ch_flags &= ~WDCF_TH_RESET; 1103 if ((flags & AT_RST_EMERG) == 0) { 1104 chp->ch_queue->queue_freeze--; 1105 wdcstart(chp); 1106 } else { 1107 /* make sure that we can use polled commands */ 1108 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1109 chp->ch_queue->queue_freeze = 0; 1110 chp->ch_queue->active_xfer = NULL; 1111 } 1112 } 1113 1114 int 1115 wdcreset(struct wdc_channel *chp, int poll) 1116 { 1117 struct wdc_softc *wdc = chp->ch_wdc; 1118 int drv_mask1, drv_mask2; 1119 int s = 0; 1120 1121 if (wdc->cap & WDC_CAPABILITY_SELECT) 1122 wdc->select(chp,0); 1123 if (poll != RESET_SLEEP) 1124 s = splbio(); 1125 /* master */ 1126 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1127 delay(10); /* 400ns delay */ 1128 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1129 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1130 delay(2000); 1131 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1132 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1133 WDCTL_4BIT | WDCTL_IDS); 1134 delay(10); /* 400ns delay */ 1135 if (poll != RESET_SLEEP) { 1136 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1137 wdc->irqack(chp); 1138 splx(s); 1139 } 1140 1141 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1142 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1143 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1144 (poll == RESET_SLEEP) ? 0 : 1); 1145 if (drv_mask2 != drv_mask1) { 1146 printf("%s channel %d: reset failed for", 1147 wdc->sc_dev.dv_xname, chp->ch_channel); 1148 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1149 printf(" drive 0"); 1150 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1151 printf(" drive 1"); 1152 printf("\n"); 1153 } 1154 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1155 return (drv_mask1 != drv_mask2) ? 1 : 0; 1156 } 1157 1158 static int 1159 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1160 { 1161 struct wdc_softc *wdc = chp->ch_wdc; 1162 int timeout, nloop; 1163 u_int8_t st0 = 0, st1 = 0; 1164 #ifdef WDCDEBUG 1165 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1166 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1167 #endif 1168 1169 if (poll) 1170 nloop = WDCNDELAY_RST; 1171 else 1172 nloop = WDC_RESET_WAIT * hz / 1000; 1173 /* wait for BSY to deassert */ 1174 for (timeout = 0; timeout < nloop; timeout++) { 1175 if ((drv_mask & 0x01) != 0) { 1176 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1177 wdc->select(chp,0); 1178 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1179 0, WDSD_IBM); /* master */ 1180 delay(10); 1181 st0 = bus_space_read_1(chp->cmd_iot, 1182 chp->cmd_iohs[wd_status], 0); 1183 #ifdef WDCDEBUG 1184 sc0 = bus_space_read_1(chp->cmd_iot, 1185 chp->cmd_iohs[wd_seccnt], 0); 1186 sn0 = bus_space_read_1(chp->cmd_iot, 1187 chp->cmd_iohs[wd_sector], 0); 1188 cl0 = bus_space_read_1(chp->cmd_iot, 1189 chp->cmd_iohs[wd_cyl_lo], 0); 1190 ch0 = bus_space_read_1(chp->cmd_iot, 1191 chp->cmd_iohs[wd_cyl_hi], 0); 1192 #endif 1193 } 1194 if ((drv_mask & 0x02) != 0) { 1195 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1196 wdc->select(chp,1); 1197 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1198 0, WDSD_IBM | 0x10); /* slave */ 1199 delay(10); 1200 st1 = bus_space_read_1(chp->cmd_iot, 1201 chp->cmd_iohs[wd_status], 0); 1202 #ifdef WDCDEBUG 1203 sc1 = bus_space_read_1(chp->cmd_iot, 1204 chp->cmd_iohs[wd_seccnt], 0); 1205 sn1 = bus_space_read_1(chp->cmd_iot, 1206 chp->cmd_iohs[wd_sector], 0); 1207 cl1 = bus_space_read_1(chp->cmd_iot, 1208 chp->cmd_iohs[wd_cyl_lo], 0); 1209 ch1 = bus_space_read_1(chp->cmd_iot, 1210 chp->cmd_iohs[wd_cyl_hi], 0); 1211 #endif 1212 } 1213 1214 if ((drv_mask & 0x01) == 0) { 1215 /* no master */ 1216 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1217 /* No master, slave is ready, it's done */ 1218 goto end; 1219 } 1220 } else if ((drv_mask & 0x02) == 0) { 1221 /* no slave */ 1222 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1223 /* No slave, master is ready, it's done */ 1224 goto end; 1225 } 1226 } else { 1227 /* Wait for both master and slave to be ready */ 1228 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1229 goto end; 1230 } 1231 } 1232 if (poll) 1233 delay(WDCDELAY); 1234 else 1235 tsleep(&nloop, PRIBIO, "atarst", 1); 1236 } 1237 /* Reset timed out. Maybe it's because drv_mask was not right */ 1238 if (st0 & WDCS_BSY) 1239 drv_mask &= ~0x01; 1240 if (st1 & WDCS_BSY) 1241 drv_mask &= ~0x02; 1242 end: 1243 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1244 "cl=0x%x ch=0x%x\n", 1245 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1246 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1247 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1248 "cl=0x%x ch=0x%x\n", 1249 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1250 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1251 1252 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1253 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1254 st0, st1), DEBUG_PROBE); 1255 1256 return drv_mask; 1257 } 1258 1259 /* 1260 * Wait for a drive to be !BSY, and have mask in its status register. 1261 * return -1 for a timeout after "timeout" ms. 1262 */ 1263 static int 1264 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1265 { 1266 struct wdc_softc *wdc = chp->ch_wdc; 1267 u_char status; 1268 int time = 0; 1269 1270 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1271 wdc->sc_dev.dv_xname : "none", 1272 chp->ch_channel), DEBUG_STATUS); 1273 chp->ch_error = 0; 1274 1275 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1276 1277 for (;;) { 1278 chp->ch_status = status = 1279 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1280 if ((status & (WDCS_BSY | mask)) == bits) 1281 break; 1282 if (++time > timeout) { 1283 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1284 "status %x error %x (mask 0x%x bits 0x%x)\n", 1285 time, status, 1286 bus_space_read_1(chp->cmd_iot, 1287 chp->cmd_iohs[wd_error], 0), mask, bits), 1288 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1289 return(WDCWAIT_TOUT); 1290 } 1291 delay(WDCDELAY); 1292 } 1293 #ifdef WDCDEBUG 1294 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1295 printf("__wdcwait: did busy-wait, time=%d\n", time); 1296 #endif 1297 if (status & WDCS_ERR) 1298 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1299 chp->cmd_iohs[wd_error], 0); 1300 #ifdef WDCNDELAY_DEBUG 1301 /* After autoconfig, there should be no long delays. */ 1302 if (!cold && time > WDCNDELAY_DEBUG) { 1303 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1304 if (xfer == NULL) 1305 printf("%s channel %d: warning: busy-wait took %dus\n", 1306 wdc->sc_dev.dv_xname, chp->ch_channel, 1307 WDCDELAY * time); 1308 else 1309 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1310 wdc->sc_dev.dv_xname, chp->ch_channel, 1311 xfer->drive, 1312 WDCDELAY * time); 1313 } 1314 #endif 1315 return(WDCWAIT_OK); 1316 } 1317 1318 /* 1319 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1320 * thread if possible 1321 */ 1322 int 1323 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1324 { 1325 int error, i, timeout_hz = mstohz(timeout); 1326 1327 if (timeout_hz == 0 || 1328 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1329 error = __wdcwait(chp, mask, bits, timeout); 1330 else { 1331 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1332 if (error != 0) { 1333 if ((chp->ch_flags & WDCF_TH_RUN) || 1334 (flags & AT_WAIT)) { 1335 /* 1336 * we're running in the channel thread 1337 * or some userland thread context 1338 */ 1339 for (i = 0; i < timeout_hz; i++) { 1340 if (__wdcwait(chp, mask, bits, 1341 WDCDELAY_POLL) == 0) { 1342 error = 0; 1343 break; 1344 } 1345 tsleep(&chp, PRIBIO, "atapoll", 1); 1346 } 1347 } else { 1348 /* 1349 * we're probably in interrupt context, 1350 * ask the thread to come back here 1351 */ 1352 #ifdef DIAGNOSTIC 1353 if (chp->ch_queue->queue_freeze > 0) 1354 panic("wdcwait: queue_freeze"); 1355 #endif 1356 chp->ch_queue->queue_freeze++; 1357 wakeup(&chp->ch_thread); 1358 return(WDCWAIT_THR); 1359 } 1360 } 1361 } 1362 return (error); 1363 } 1364 1365 1366 /* 1367 * Busy-wait for DMA to complete 1368 */ 1369 int 1370 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1371 { 1372 struct wdc_softc *wdc = chp->ch_wdc; 1373 int time; 1374 1375 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1376 wdc->dma_status = 1377 (*wdc->dma_finish)(wdc->dma_arg, 1378 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1379 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1380 return 0; 1381 delay(WDCDELAY); 1382 } 1383 /* timeout, force a DMA halt */ 1384 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1385 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1386 return 1; 1387 } 1388 1389 void 1390 wdctimeout(void *arg) 1391 { 1392 struct wdc_channel *chp = (struct wdc_channel *)arg; 1393 struct wdc_softc *wdc = chp->ch_wdc; 1394 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1395 int s; 1396 1397 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1398 1399 s = splbio(); 1400 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1401 __wdcerror(chp, "lost interrupt"); 1402 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1403 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1404 xfer->c_bcount, 1405 xfer->c_skip); 1406 if (chp->ch_flags & WDCF_DMA_WAIT) { 1407 wdc->dma_status = 1408 (*wdc->dma_finish)(wdc->dma_arg, 1409 chp->ch_channel, xfer->c_drive, 1410 WDC_DMAEND_ABRT); 1411 chp->ch_flags &= ~WDCF_DMA_WAIT; 1412 } 1413 /* 1414 * Call the interrupt routine. If we just missed an interrupt, 1415 * it will do what's needed. Else, it will take the needed 1416 * action (reset the device). 1417 * Before that we need to reinstall the timeout callback, 1418 * in case it will miss another irq while in this transfer 1419 * We arbitray chose it to be 1s 1420 */ 1421 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1422 xfer->c_flags |= C_TIMEOU; 1423 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1424 xfer->c_intr(chp, xfer, 1); 1425 } else 1426 __wdcerror(chp, "missing untimeout"); 1427 splx(s); 1428 } 1429 1430 /* 1431 * Probe drive's capabilities, for use by the controller later 1432 * Assumes drvp points to an existing drive. 1433 * XXX this should be a controller-indep function 1434 */ 1435 void 1436 wdc_probe_caps(struct ata_drive_datas *drvp) 1437 { 1438 struct ataparams params, params2; 1439 struct wdc_channel *chp = drvp->chnl_softc; 1440 struct wdc_softc *wdc = chp->ch_wdc; 1441 struct device *drv_dev = drvp->drv_softc; 1442 int i, printed; 1443 char *sep = ""; 1444 int cf_flags; 1445 1446 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1447 /* IDENTIFY failed. Can't tell more about the device */ 1448 return; 1449 } 1450 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1451 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1452 /* 1453 * Controller claims 16 and 32 bit transfers. 1454 * Re-do an IDENTIFY with 32-bit transfers, 1455 * and compare results. 1456 */ 1457 drvp->drive_flags |= DRIVE_CAP32; 1458 ata_get_params(drvp, AT_WAIT, ¶ms2); 1459 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1460 /* Not good. fall back to 16bits */ 1461 drvp->drive_flags &= ~DRIVE_CAP32; 1462 } else { 1463 aprint_normal("%s: 32-bit data port\n", 1464 drv_dev->dv_xname); 1465 } 1466 } 1467 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1468 if (params.atap_ata_major > 0x01 && 1469 params.atap_ata_major != 0xffff) { 1470 for (i = 14; i > 0; i--) { 1471 if (params.atap_ata_major & (1 << i)) { 1472 aprint_normal("%s: ATA version %d\n", 1473 drv_dev->dv_xname, i); 1474 drvp->ata_vers = i; 1475 break; 1476 } 1477 } 1478 } 1479 #endif 1480 1481 /* An ATAPI device is at last PIO mode 3 */ 1482 if (drvp->drive_flags & DRIVE_ATAPI) 1483 drvp->PIO_mode = 3; 1484 1485 /* 1486 * It's not in the specs, but it seems that some drive 1487 * returns 0xffff in atap_extensions when this field is invalid 1488 */ 1489 if (params.atap_extensions != 0xffff && 1490 (params.atap_extensions & WDC_EXT_MODES)) { 1491 printed = 0; 1492 /* 1493 * XXX some drives report something wrong here (they claim to 1494 * support PIO mode 8 !). As mode is coded on 3 bits in 1495 * SET FEATURE, limit it to 7 (so limit i to 4). 1496 * If higher mode than 7 is found, abort. 1497 */ 1498 for (i = 7; i >= 0; i--) { 1499 if ((params.atap_piomode_supp & (1 << i)) == 0) 1500 continue; 1501 if (i > 4) 1502 return; 1503 /* 1504 * See if mode is accepted. 1505 * If the controller can't set its PIO mode, 1506 * assume the defaults are good, so don't try 1507 * to set it 1508 */ 1509 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1510 /* 1511 * It's OK to pool here, it's fast enouth 1512 * to not bother waiting for interrupt 1513 */ 1514 if (ata_set_mode(drvp, 0x08 | (i + 3), 1515 AT_WAIT) != CMD_OK) 1516 continue; 1517 if (!printed) { 1518 aprint_normal("%s: drive supports PIO mode %d", 1519 drv_dev->dv_xname, i + 3); 1520 sep = ","; 1521 printed = 1; 1522 } 1523 /* 1524 * If controller's driver can't set its PIO mode, 1525 * get the highter one for the drive. 1526 */ 1527 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1528 wdc->PIO_cap >= i + 3) { 1529 drvp->PIO_mode = i + 3; 1530 drvp->PIO_cap = i + 3; 1531 break; 1532 } 1533 } 1534 if (!printed) { 1535 /* 1536 * We didn't find a valid PIO mode. 1537 * Assume the values returned for DMA are buggy too 1538 */ 1539 return; 1540 } 1541 drvp->drive_flags |= DRIVE_MODE; 1542 printed = 0; 1543 for (i = 7; i >= 0; i--) { 1544 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1545 continue; 1546 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1547 (wdc->cap & WDC_CAPABILITY_MODE)) 1548 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1549 != CMD_OK) 1550 continue; 1551 if (!printed) { 1552 aprint_normal("%s DMA mode %d", sep, i); 1553 sep = ","; 1554 printed = 1; 1555 } 1556 if (wdc->cap & WDC_CAPABILITY_DMA) { 1557 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1558 wdc->DMA_cap < i) 1559 continue; 1560 drvp->DMA_mode = i; 1561 drvp->DMA_cap = i; 1562 drvp->drive_flags |= DRIVE_DMA; 1563 } 1564 break; 1565 } 1566 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1567 printed = 0; 1568 for (i = 7; i >= 0; i--) { 1569 if ((params.atap_udmamode_supp & (1 << i)) 1570 == 0) 1571 continue; 1572 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1573 (wdc->cap & WDC_CAPABILITY_UDMA)) 1574 if (ata_set_mode(drvp, 0x40 | i, 1575 AT_WAIT) != CMD_OK) 1576 continue; 1577 if (!printed) { 1578 aprint_normal("%s Ultra-DMA mode %d", 1579 sep, i); 1580 if (i == 2) 1581 aprint_normal(" (Ultra/33)"); 1582 else if (i == 4) 1583 aprint_normal(" (Ultra/66)"); 1584 else if (i == 5) 1585 aprint_normal(" (Ultra/100)"); 1586 else if (i == 6) 1587 aprint_normal(" (Ultra/133)"); 1588 sep = ","; 1589 printed = 1; 1590 } 1591 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1592 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1593 wdc->UDMA_cap < i) 1594 continue; 1595 drvp->UDMA_mode = i; 1596 drvp->UDMA_cap = i; 1597 drvp->drive_flags |= DRIVE_UDMA; 1598 } 1599 break; 1600 } 1601 } 1602 aprint_normal("\n"); 1603 } 1604 1605 /* Try to guess ATA version here, if it didn't get reported */ 1606 if (drvp->ata_vers == 0) { 1607 if (drvp->drive_flags & DRIVE_UDMA) 1608 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1609 else if (drvp->PIO_cap > 2) 1610 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1611 } 1612 cf_flags = drv_dev->dv_cfdata->cf_flags; 1613 if (cf_flags & ATA_CONFIG_PIO_SET) { 1614 drvp->PIO_mode = 1615 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1616 drvp->drive_flags |= DRIVE_MODE; 1617 } 1618 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1619 /* don't care about DMA modes */ 1620 return; 1621 } 1622 if (cf_flags & ATA_CONFIG_DMA_SET) { 1623 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1624 ATA_CONFIG_DMA_DISABLE) { 1625 drvp->drive_flags &= ~DRIVE_DMA; 1626 } else { 1627 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1628 ATA_CONFIG_DMA_OFF; 1629 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1630 } 1631 } 1632 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1633 /* don't care about UDMA modes */ 1634 return; 1635 } 1636 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1637 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1638 ATA_CONFIG_UDMA_DISABLE) { 1639 drvp->drive_flags &= ~DRIVE_UDMA; 1640 } else { 1641 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1642 ATA_CONFIG_UDMA_OFF; 1643 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1644 } 1645 } 1646 } 1647 1648 /* 1649 * downgrade the transfer mode of a drive after an error. return 1 if 1650 * downgrade was possible, 0 otherwise. 1651 */ 1652 int 1653 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1654 { 1655 struct wdc_channel *chp = drvp->chnl_softc; 1656 struct wdc_softc *wdc = chp->ch_wdc; 1657 struct device *drv_dev = drvp->drv_softc; 1658 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1659 1660 /* if drive or controller don't know its mode, we can't do much */ 1661 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1662 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1663 return 0; 1664 /* current drive mode was set by a config flag, let it this way */ 1665 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1666 (cf_flags & ATA_CONFIG_DMA_SET) || 1667 (cf_flags & ATA_CONFIG_UDMA_SET)) 1668 return 0; 1669 1670 /* 1671 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1672 */ 1673 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1674 drvp->UDMA_mode--; 1675 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1676 drv_dev->dv_xname, drvp->UDMA_mode); 1677 } 1678 1679 /* 1680 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1681 */ 1682 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1683 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1684 drvp->PIO_mode = drvp->PIO_cap; 1685 printf("%s: transfer error, downgrading to PIO mode %d\n", 1686 drv_dev->dv_xname, drvp->PIO_mode); 1687 } else /* already using PIO, can't downgrade */ 1688 return 0; 1689 1690 wdc->set_modes(chp); 1691 wdc_print_modes(chp); 1692 /* reset the channel, which will shedule all drives for setup */ 1693 wdc_reset_channel(chp, flags | AT_RST_NOCMD); 1694 return 1; 1695 } 1696 1697 int 1698 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1699 { 1700 struct wdc_channel *chp = drvp->chnl_softc; 1701 struct wdc_softc *wdc = chp->ch_wdc; 1702 struct ata_xfer *xfer; 1703 int s, ret; 1704 1705 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1706 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1707 DEBUG_FUNCS); 1708 1709 /* set up an xfer and queue. Wait for completion */ 1710 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1711 WDC_NOSLEEP); 1712 if (xfer == NULL) { 1713 return WDC_TRY_AGAIN; 1714 } 1715 1716 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1717 wdc_c->flags |= AT_POLL; 1718 if (wdc_c->flags & AT_POLL) 1719 xfer->c_flags |= C_POLL; 1720 xfer->c_drive = drvp->drive; 1721 xfer->c_databuf = wdc_c->data; 1722 xfer->c_bcount = wdc_c->bcount; 1723 xfer->c_cmd = wdc_c; 1724 xfer->c_start = __wdccommand_start; 1725 xfer->c_intr = __wdccommand_intr; 1726 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1727 1728 s = splbio(); 1729 wdc_exec_xfer(chp, xfer); 1730 #ifdef DIAGNOSTIC 1731 if ((wdc_c->flags & AT_POLL) != 0 && 1732 (wdc_c->flags & AT_DONE) == 0) 1733 panic("wdc_exec_command: polled command not done"); 1734 #endif 1735 if (wdc_c->flags & AT_DONE) { 1736 ret = WDC_COMPLETE; 1737 } else { 1738 if (wdc_c->flags & AT_WAIT) { 1739 while ((wdc_c->flags & AT_DONE) == 0) { 1740 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1741 } 1742 ret = WDC_COMPLETE; 1743 } else { 1744 ret = WDC_QUEUED; 1745 } 1746 } 1747 splx(s); 1748 return ret; 1749 } 1750 1751 static void 1752 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1753 { 1754 struct wdc_softc *wdc = chp->ch_wdc; 1755 int drive = xfer->c_drive; 1756 struct wdc_command *wdc_c = xfer->c_cmd; 1757 1758 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1759 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1760 DEBUG_FUNCS); 1761 1762 if (wdc->cap & WDC_CAPABILITY_SELECT) 1763 wdc->select(chp,drive); 1764 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1765 WDSD_IBM | (drive << 4)); 1766 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1767 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1768 case WDCWAIT_OK: 1769 break; 1770 case WDCWAIT_TOUT: 1771 wdc_c->flags |= AT_TIMEOU; 1772 __wdccommand_done(chp, xfer); 1773 return; 1774 case WDCWAIT_THR: 1775 return; 1776 } 1777 if (wdc_c->flags & AT_POLL) { 1778 /* polled command, disable interrupts */ 1779 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1780 WDCTL_4BIT | WDCTL_IDS); 1781 } 1782 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1783 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features); 1784 1785 if ((wdc_c->flags & AT_POLL) == 0) { 1786 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1787 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1788 wdctimeout, chp); 1789 return; 1790 } 1791 /* 1792 * Polled command. Wait for drive ready or drq. Done in intr(). 1793 * Wait for at last 400ns for status bit to be valid. 1794 */ 1795 delay(10); /* 400ns delay */ 1796 __wdccommand_intr(chp, xfer, 0); 1797 } 1798 1799 static int 1800 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1801 { 1802 struct wdc_softc *wdc = chp->ch_wdc; 1803 struct wdc_command *wdc_c = xfer->c_cmd; 1804 int bcount = wdc_c->bcount; 1805 char *data = wdc_c->data; 1806 int wflags; 1807 1808 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1809 /* both wait and poll, we can tsleep here */ 1810 wflags = AT_WAIT | AT_POLL; 1811 } else { 1812 wflags = AT_POLL; 1813 } 1814 1815 again: 1816 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1817 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1818 DEBUG_INTR); 1819 /* 1820 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1821 * Reselect again, it doesn't hurt for others commands, and the time 1822 * penalty for the extra regiter write is acceptable, 1823 * wdc_exec_command() isn't called often (mosly for autoconfig) 1824 */ 1825 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1826 WDSD_IBM | (xfer->c_drive << 4)); 1827 if ((wdc_c->flags & AT_XFDONE) != 0) { 1828 /* 1829 * We have completed a data xfer. The drive should now be 1830 * in its initial state 1831 */ 1832 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1833 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1834 wflags) == WDCWAIT_TOUT) { 1835 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1836 return 0; /* IRQ was not for us */ 1837 wdc_c->flags |= AT_TIMEOU; 1838 } 1839 goto out; 1840 } 1841 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1842 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1843 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1844 return 0; /* IRQ was not for us */ 1845 wdc_c->flags |= AT_TIMEOU; 1846 goto out; 1847 } 1848 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1849 wdc->irqack(chp); 1850 if (wdc_c->flags & AT_READ) { 1851 if ((chp->ch_status & WDCS_DRQ) == 0) { 1852 wdc_c->flags |= AT_TIMEOU; 1853 goto out; 1854 } 1855 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1856 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1857 0, (u_int32_t*)data, bcount >> 2); 1858 data += bcount & 0xfffffffc; 1859 bcount = bcount & 0x03; 1860 } 1861 if (bcount > 0) 1862 bus_space_read_multi_2(chp->cmd_iot, 1863 chp->cmd_iohs[wd_data], 0, 1864 (u_int16_t *)data, bcount >> 1); 1865 /* at this point the drive should be in its initial state */ 1866 wdc_c->flags |= AT_XFDONE; 1867 /* XXX should read status register here ? */ 1868 } else if (wdc_c->flags & AT_WRITE) { 1869 if ((chp->ch_status & WDCS_DRQ) == 0) { 1870 wdc_c->flags |= AT_TIMEOU; 1871 goto out; 1872 } 1873 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1874 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1875 0, (u_int32_t*)data, bcount >> 2); 1876 data += bcount & 0xfffffffc; 1877 bcount = bcount & 0x03; 1878 } 1879 if (bcount > 0) 1880 bus_space_write_multi_2(chp->cmd_iot, 1881 chp->cmd_iohs[wd_data], 0, 1882 (u_int16_t *)data, bcount >> 1); 1883 wdc_c->flags |= AT_XFDONE; 1884 if ((wdc_c->flags & AT_POLL) == 0) { 1885 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1886 callout_reset(&chp->ch_callout, 1887 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1888 return 1; 1889 } else { 1890 goto again; 1891 } 1892 } 1893 out: 1894 __wdccommand_done(chp, xfer); 1895 return 1; 1896 } 1897 1898 static void 1899 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1900 { 1901 struct wdc_softc *wdc = chp->ch_wdc; 1902 struct wdc_command *wdc_c = xfer->c_cmd; 1903 1904 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1905 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1906 DEBUG_FUNCS); 1907 1908 1909 if (chp->ch_status & WDCS_DWF) 1910 wdc_c->flags |= AT_DF; 1911 if (chp->ch_status & WDCS_ERR) { 1912 wdc_c->flags |= AT_ERROR; 1913 wdc_c->r_error = chp->ch_error; 1914 } 1915 if ((wdc_c->flags & AT_READREG) != 0 && 1916 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1917 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1918 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1919 chp->cmd_iohs[wd_sdh], 0); 1920 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1921 chp->cmd_iohs[wd_seccnt], 0); 1922 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1923 chp->cmd_iohs[wd_sector], 0); 1924 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1925 chp->cmd_iohs[wd_cyl_lo], 0); 1926 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1927 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1928 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1929 chp->cmd_iohs[wd_error], 0); 1930 wdc_c->r_features = bus_space_read_1(chp->cmd_iot, 1931 chp->cmd_iohs[wd_features], 0); 1932 } 1933 callout_stop(&chp->ch_callout); 1934 chp->ch_queue->active_xfer = NULL; 1935 if (wdc_c->flags & AT_POLL) { 1936 /* enable interrupts */ 1937 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1938 WDCTL_4BIT); 1939 delay(10); /* some drives need a little delay here */ 1940 } 1941 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1942 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1943 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1944 wakeup(&chp->ch_queue->active_xfer); 1945 } else 1946 __wdccommand_done_end(chp, xfer); 1947 } 1948 1949 static void 1950 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1951 { 1952 struct wdc_command *wdc_c = xfer->c_cmd; 1953 1954 wdc_c->flags |= AT_DONE; 1955 wdc_free_xfer(chp, xfer); 1956 if (wdc_c->flags & AT_WAIT) 1957 wakeup(wdc_c); 1958 else if (wdc_c->callback) 1959 wdc_c->callback(wdc_c->callback_arg); 1960 wdcstart(chp); 1961 return; 1962 } 1963 1964 static void 1965 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1966 int reason) 1967 { 1968 struct wdc_command *wdc_c = xfer->c_cmd; 1969 1970 switch (reason) { 1971 case KILL_GONE: 1972 wdc_c->flags |= AT_GONE; 1973 break; 1974 case KILL_RESET: 1975 wdc_c->flags |= AT_RESET; 1976 break; 1977 default: 1978 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1979 reason); 1980 panic("__wdccommand_kill_xfer"); 1981 } 1982 __wdccommand_done_end(chp, xfer); 1983 } 1984 1985 /* 1986 * Send a command. The drive should be ready. 1987 * Assumes interrupts are blocked. 1988 */ 1989 void 1990 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1991 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1992 u_int8_t features) 1993 { 1994 struct wdc_softc *wdc = chp->ch_wdc; 1995 1996 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1997 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1998 chp->ch_channel, drive, command, cylin, head, sector, count, 1999 features), DEBUG_FUNCS); 2000 2001 if (wdc->cap & WDC_CAPABILITY_SELECT) 2002 wdc->select(chp,drive); 2003 2004 /* Select drive, head, and addressing mode. */ 2005 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2006 WDSD_IBM | (drive << 4) | head); 2007 /* Load parameters into the wd_features register. */ 2008 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 2009 features); 2010 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2011 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 2012 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 2013 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 2014 0, cylin >> 8); 2015 2016 /* Send command. */ 2017 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2018 return; 2019 } 2020 2021 /* 2022 * Send a 48-bit addressing command. The drive should be ready. 2023 * Assumes interrupts are blocked. 2024 */ 2025 void 2026 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 2027 u_int64_t blkno, u_int16_t count) 2028 { 2029 struct wdc_softc *wdc = chp->ch_wdc; 2030 2031 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2032 "count=%d\n", wdc->sc_dev.dv_xname, 2033 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 2034 DEBUG_FUNCS); 2035 2036 if (wdc->cap & WDC_CAPABILITY_SELECT) 2037 wdc->select(chp,drive); 2038 2039 /* Select drive, head, and addressing mode. */ 2040 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2041 (drive << 4) | WDSD_LBA); 2042 2043 /* previous */ 2044 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2045 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 2046 0, count >> 8); 2047 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 2048 0, blkno >> 24); 2049 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2050 0, blkno >> 32); 2051 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2052 0, blkno >> 40); 2053 2054 /* current */ 2055 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2056 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2057 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2058 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2059 0, blkno >> 8); 2060 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2061 0, blkno >> 16); 2062 2063 /* Send command. */ 2064 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2065 return; 2066 } 2067 2068 /* 2069 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2070 * tested by the caller. 2071 */ 2072 void 2073 wdccommandshort(struct wdc_channel *chp, int drive, int command) 2074 { 2075 struct wdc_softc *wdc = chp->ch_wdc; 2076 2077 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2078 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 2079 DEBUG_FUNCS); 2080 2081 if (wdc->cap & WDC_CAPABILITY_SELECT) 2082 wdc->select(chp,drive); 2083 2084 /* Select drive. */ 2085 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2086 WDSD_IBM | (drive << 4)); 2087 2088 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2089 } 2090 2091 /* Add a command to the queue and start controller. Must be called at splbio */ 2092 void 2093 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2094 { 2095 2096 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2097 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 2098 2099 /* complete xfer setup */ 2100 xfer->c_chp = chp; 2101 2102 /* insert at the end of command list */ 2103 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2104 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2105 chp->ch_flags), DEBUG_XFERS); 2106 wdcstart(chp); 2107 } 2108 2109 struct ata_xfer * 2110 wdc_get_xfer(int flags) 2111 { 2112 struct ata_xfer *xfer; 2113 int s; 2114 2115 s = splbio(); 2116 xfer = pool_get(&wdc_xfer_pool, 2117 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2118 splx(s); 2119 if (xfer != NULL) { 2120 memset(xfer, 0, sizeof(struct ata_xfer)); 2121 } 2122 return xfer; 2123 } 2124 2125 void 2126 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2127 { 2128 struct wdc_softc *wdc = chp->ch_wdc; 2129 int s; 2130 2131 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2132 (*wdc->free_hw)(chp); 2133 s = splbio(); 2134 pool_put(&wdc_xfer_pool, xfer); 2135 splx(s); 2136 } 2137 2138 /* 2139 * Kill off all pending xfers for a wdc_channel. 2140 * 2141 * Must be called at splbio(). 2142 */ 2143 void 2144 wdc_kill_pending(struct ata_drive_datas *drvp) 2145 { 2146 struct wdc_channel *chp = drvp->chnl_softc; 2147 struct ata_xfer *xfer, *next_xfer; 2148 int s = splbio(); 2149 2150 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2151 xfer != NULL; xfer = next_xfer) { 2152 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 2153 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 2154 continue; 2155 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2156 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 2157 } 2158 2159 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 2160 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 2161 drvp->drive_flags |= DRIVE_WAITDRAIN; 2162 (void) tsleep(&chp->ch_queue->active_xfer, 2163 PRIBIO, "atdrn", 0); 2164 } else { 2165 /* no more xfer for us */ 2166 break; 2167 } 2168 } 2169 splx(s); 2170 } 2171 2172 static void 2173 __wdcerror(struct wdc_channel *chp, char *msg) 2174 { 2175 struct wdc_softc *wdc = chp->ch_wdc; 2176 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2177 2178 if (xfer == NULL) 2179 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2180 msg); 2181 else 2182 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2183 chp->ch_channel, xfer->c_drive, msg); 2184 } 2185 2186 /* 2187 * the bit bucket 2188 */ 2189 void 2190 wdcbit_bucket(struct wdc_channel *chp, int size) 2191 { 2192 2193 for (; size >= 2; size -= 2) 2194 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2195 if (size) 2196 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2197 } 2198 2199 int 2200 wdc_addref(struct wdc_channel *chp) 2201 { 2202 struct wdc_softc *wdc = chp->ch_wdc; 2203 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2204 int s, error = 0; 2205 2206 s = splbio(); 2207 if (adapt->adapt_refcnt++ == 0 && 2208 adapt->adapt_enable != NULL) { 2209 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2210 if (error) 2211 adapt->adapt_refcnt--; 2212 } 2213 splx(s); 2214 return (error); 2215 } 2216 2217 void 2218 wdc_delref(struct wdc_channel *chp) 2219 { 2220 struct wdc_softc *wdc = chp->ch_wdc; 2221 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2222 int s; 2223 2224 s = splbio(); 2225 if (adapt->adapt_refcnt-- == 1 && 2226 adapt->adapt_enable != NULL) 2227 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2228 splx(s); 2229 } 2230 2231 void 2232 wdc_print_modes(struct wdc_channel *chp) 2233 { 2234 struct wdc_softc *wdc = chp->ch_wdc; 2235 int drive; 2236 struct ata_drive_datas *drvp; 2237 2238 for (drive = 0; drive < 2; drive++) { 2239 drvp = &chp->ch_drive[drive]; 2240 if ((drvp->drive_flags & DRIVE) == 0) 2241 continue; 2242 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2243 drvp->drv_softc->dv_xname, 2244 wdc->sc_dev.dv_xname, 2245 chp->ch_channel, drive, drvp->PIO_mode); 2246 if (drvp->drive_flags & DRIVE_DMA) 2247 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2248 if (drvp->drive_flags & DRIVE_UDMA) { 2249 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2250 if (drvp->UDMA_mode == 2) 2251 aprint_normal(" (Ultra/33)"); 2252 else if (drvp->UDMA_mode == 4) 2253 aprint_normal(" (Ultra/66)"); 2254 else if (drvp->UDMA_mode == 5) 2255 aprint_normal(" (Ultra/100)"); 2256 else if (drvp->UDMA_mode == 6) 2257 aprint_normal(" (Ultra/133)"); 2258 } 2259 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2260 aprint_normal(" (using DMA data transfers)"); 2261 aprint_normal("\n"); 2262 } 2263 } 2264
Indexes created Thu Sep 25 02:09:54 GMT 2025