wdc.c revision 1.19
1 /* $NetBSD: wdc.c,v 1.19 1998/04/07 19:51:57 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved. 5 * 6 * DMA and multi-sector PIO handling are derived from code contributed by 7 * Onno van der Linden. 8 * 9 * Atapi support added by Manuel Bouyer. 10 * 11 * Bus_space-ified by Christopher G. Demetriou. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Charles M. Hannum. 24 * 4. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * CODE UNTESTED IN THE CURRENT REVISION: 41 * * DMA 42 * * 32-bit data port access. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/stat.h> 51 #include <sys/ioctl.h> 52 #include <sys/buf.h> 53 #include <sys/uio.h> 54 #include <sys/malloc.h> 55 #include <sys/device.h> 56 #include <sys/disklabel.h> 57 #include <sys/disk.h> 58 #include <sys/syslog.h> 59 #include <sys/proc.h> 60 61 #include <vm/vm.h> 62 63 #include <machine/intr.h> 64 #include <machine/bus.h> 65 66 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 67 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 68 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 69 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 70 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 71 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 72 73 #include <dev/ic/wdcreg.h> 74 #include <dev/ic/wdcvar.h> 75 #include <dev/ata/wdlink.h> 76 #include "atapibus.h" 77 #include "wdc.h" 78 79 #if NATAPIBUS > 0 80 #include <dev/scsipi/scsipi_all.h> 81 #include <dev/scsipi/atapi_all.h> 82 #include <dev/scsipi/atapiconf.h> 83 #endif 84 85 #define WAITTIME (10 * hz) /* time to wait for a completion */ 86 /* this is a lot for hard drives, but not for cdroms */ 87 #define RECOVERYTIME hz/2 88 #define WDCDELAY 100 89 #define WDCNDELAY 100000 /* delay = 100us; so 10s for a controller state change */ 90 #if 0 91 /* If you enable this, it will report any delays more than 100us * N long. */ 92 #define WDCNDELAY_DEBUG 50 93 #endif 94 95 #define WDIORETRIES 5 /* number of retries before giving up */ 96 97 #define WDPART(dev) DISKPART(dev) 98 99 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 100 101 int wdc_init_controller __P((struct wdc_softc *, 102 const struct wdc_attachment_data *)); 103 void wdcstart __P((struct wdc_softc *)); 104 int wdcreset __P((struct wdc_softc *, int)); 105 #define VERBOSE 1 106 #define SILENT 0 107 void wdcrestart __P((void *arg)); 108 void wdcunwedge __P((struct wdc_softc *)); 109 void wdctimeout __P((void *arg)); 110 int wdccontrol __P((struct wdc_softc*, struct wd_link *)); 111 void wdc_free_xfer __P((struct wdc_xfer *)); 112 void wdcerror __P((struct wdc_softc*, char *)); 113 void wdcbit_bucket __P(( struct wdc_softc *, int)); 114 #if NWD > 0 115 int wdprint __P((void *, const char *)); 116 int wdsetctlr __P((struct wd_link *)); 117 int wdc_ata_intr __P((struct wdc_softc *,struct wdc_xfer *)); 118 void wdc_ata_start __P((struct wdc_softc *,struct wdc_xfer *)); 119 void wdc_ata_done __P((struct wdc_softc *, struct wdc_xfer *)); 120 #endif /* NWD > 0 */ 121 #if NATAPIBUS > 0 122 void wdc_atapi_minphys __P((struct buf *bp)); 123 void wdc_atapi_start __P((struct wdc_softc *,struct wdc_xfer *)); 124 int wdc_atapi_intr __P((struct wdc_softc *, struct wdc_xfer *)); 125 void wdc_atapi_done __P((struct wdc_softc *, struct wdc_xfer *)); 126 int wdc_atapi_send_command_packet __P((struct scsipi_xfer *sc_xfer)); 127 #define MAX_SIZE MAXPHYS /* XXX */ 128 #endif 129 130 #ifdef ATAPI_DEBUG2 131 static int wdc_nxfer; 132 #endif 133 134 #ifdef WDDEBUG 135 #define WDDEBUG_PRINT(args) printf args 136 #else 137 #define WDDEBUG_PRINT(args) 138 #endif 139 140 #if NATAPIBUS > 0 141 static struct scsipi_adapter wdc_switch = { 142 wdc_atapi_send_command_packet, 143 wdc_atapi_minphys, 144 0, 145 0 146 }; 147 #endif 148 149 /* 150 * wdc_init_controller: Does a quick probe/init of the controller. 151 * 152 * Return values: 153 * 0 No controller present (as far as it can tell). 154 * >0 Controller present and seemingly functional. 155 * <0 Controller present, but not working correctly. 156 */ 157 int 158 wdc_init_controller(wdc, adp) 159 struct wdc_softc *wdc; 160 const struct wdc_attachment_data *adp; 161 { 162 bus_space_tag_t iot; 163 bus_space_handle_t ioh; 164 165 iot = wdc->sc_iot; 166 ioh = wdc->sc_ioh; 167 168 if (wdcreset(wdc, SILENT) != 0) { 169 /* 170 * If the reset failed, there is no master. test for 171 * ATAPI signature on the slave device. If no ATAPI 172 * slave, wait 5s and retry a reset. 173 */ 174 bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | 0x10); /*slave*/ 175 if (bus_space_read_1(iot, ioh, wd_cyl_lo) == 0x14 && 176 bus_space_read_1(iot, ioh, wd_cyl_hi) == 0xeb) { 177 wdc->sc_flags |= WDCF_ONESLAVE; 178 goto drivefound; 179 } else { 180 delay(500000); 181 if (wdcreset(wdc, SILENT) != 0) 182 return (0); 183 } 184 } 185 delay(1000); 186 187 /* 188 * Reset succeeded. Test for ATAPI signature on both master 189 * and slave. 190 */ 191 if (bus_space_read_1(iot, ioh, wd_cyl_lo) == 0x14 && 192 bus_space_read_1(iot, ioh, wd_cyl_hi) == 0xeb) 193 goto drivefound; 194 bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | 0x10); 195 if (bus_space_read_1(iot, ioh, wd_cyl_lo) == 0x14 && 196 bus_space_read_1(iot, ioh, wd_cyl_hi) == 0xeb) { 197 wdc->sc_flags |= WDCF_ONESLAVE; 198 goto drivefound; 199 } 200 201 /* 202 * Test non-ATAPI registers. Error register not writable, 203 * but all of cyllo is. 204 */ 205 bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM); 206 bus_space_write_1(iot, ioh, wd_error, 0x58); 207 bus_space_write_1(iot, ioh, wd_cyl_lo, 0xa5); 208 if (bus_space_read_1(iot, ioh, wd_error) != 0x58 && 209 bus_space_read_1(iot, ioh, wd_cyl_lo) == 0xa5) 210 goto drivefound; 211 212 /* 213 * If no drives found, but the resets succeeded, we claim to 214 * have the controller, at least. 215 */ 216 return (1); 217 218 drivefound: 219 /* Select drive 0 or ATAPI slave device */ 220 if (wdc->sc_flags & WDCF_ONESLAVE) 221 bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM | 0x10); 222 else 223 bus_space_write_1(iot, ioh, wd_sdh, WDSD_IBM); 224 225 /* Wait for controller to become ready. */ 226 if (wait_for_unbusy(wdc) < 0) 227 return (-1); 228 229 /* Start drive diagnostics. */ 230 bus_space_write_1(iot, ioh, wd_command, WDCC_DIAGNOSE); 231 232 /* Wait for command to complete. */ 233 if (wait_for_unbusy(wdc) < 0) 234 return (-1); 235 236 return 1; 237 } 238 239 int 240 wdcprobe(adp) 241 const struct wdc_attachment_data *adp; 242 { 243 struct wdc_softc _wdc, *wdc = &_wdc; /* XXX EWWWWW! */ 244 int rv; 245 246 bzero(wdc, sizeof *wdc); 247 strcpy(wdc->sc_dev.dv_xname, "wdcprobe"); 248 wdc->sc_adp = adp; 249 250 rv = wdc_init_controller(wdc, adp); 251 252 if (rv < 0) 253 rv = 1; 254 return (rv); 255 } 256 257 void 258 wdcattach(wdc, adp) 259 struct wdc_softc *wdc; 260 const struct wdc_attachment_data *adp; 261 { 262 #if NWD > 0 263 int drive; 264 #endif 265 266 wdc->sc_adp = adp; 267 if (wdc_init_controller(wdc, adp) <= 0) { 268 printf("%s: controller wouldn't initialize properly\n", 269 wdc->sc_dev.dv_xname); 270 return; 271 } 272 273 TAILQ_INIT(&wdc->sc_xfer); 274 275 if (wdc->sc_cap & WDC_CAPABILITY_DMA) 276 (*wdc->sc_dma_setup)(wdc->sc_dma_arg); 277 278 #ifdef ATAPI_DEBUG2 279 wdc_nxfer = 0; 280 #endif 281 282 #if NATAPIBUS > 0 283 /* 284 * Attach an ATAPI bus, if configured. 285 */ 286 wdc->ab_link = malloc(sizeof(struct scsipi_link), M_DEVBUF, M_NOWAIT); 287 if (wdc->ab_link == NULL) { 288 printf("%s: can't allocate ATAPI link\n", 289 wdc->sc_dev.dv_xname); 290 return; 291 } 292 bzero(wdc->ab_link,sizeof(struct scsipi_link)); 293 wdc->ab_link->type = BUS_ATAPI; 294 wdc->ab_link->openings = 1; 295 wdc->ab_link->scsipi_atapi.type = ATAPI; 296 wdc->ab_link->scsipi_atapi.channel = 0; 297 wdc->ab_link->adapter_softc = (caddr_t)wdc; 298 wdc->ab_link->adapter = &wdc_switch; 299 (void)config_found(&wdc->sc_dev, (void *)wdc->ab_link, NULL); 300 #endif /* NATAPIBUS > 0 */ 301 #if NWD > 0 302 /* 303 * Attach standard IDE/ESDI/etc. disks to the controller. 304 */ 305 for (drive = 0; drive < 2; drive++) { 306 /* if a disk is already present, skip */ 307 if ((wdc->sc_drives_mask & (1 << drive)) != 0) { 308 continue; 309 } 310 /* controller active while autoconf */ 311 wdc->sc_flags |= WDCF_ACTIVE; 312 313 if (wdccommandshort(wdc, drive, WDCC_RECAL) != 0 || 314 wait_for_ready(wdc) != 0) { 315 wdc->d_link[drive] = NULL; 316 wdc->sc_flags &= ~WDCF_ACTIVE; 317 } else { 318 wdc->sc_flags &= ~WDCF_ACTIVE; 319 wdc->d_link[drive] = malloc(sizeof(struct wd_link), 320 M_DEVBUF, M_NOWAIT); 321 if (wdc->d_link[drive] == NULL) { 322 printf("%s: can't allocate link for drive %d\n", 323 wdc->sc_dev.dv_xname, drive); 324 continue; 325 } 326 bzero(wdc->d_link[drive],sizeof(struct wd_link)); 327 wdc->d_link[drive]->type = ATA; 328 wdc->d_link[drive]->wdc_softc =(caddr_t) wdc; 329 wdc->d_link[drive]->drive = drive; 330 if (wdc->sc_cap & WDC_CAPABILITY_DMA) 331 wdc->d_link[drive]->sc_mode = WDM_DMA; 332 else 333 wdc->d_link[drive]->sc_mode = 0; 334 335 wdc->sc_drives_mask |= (1 << drive); 336 (void)config_found(&wdc->sc_dev, 337 (void *)wdc->d_link[drive], wdprint); 338 } 339 } 340 #endif /* NWD > 0 */ 341 /* explicitly select an existing drive, to avoid spurious interrupts */ 342 if (wdc->sc_flags & WDCF_ONESLAVE) 343 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM | 0x10); /* slave */ 344 else 345 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM); /* master */ 346 /* 347 * Reset controller. The probe, with some combinations of ATA/ATAPI 348 * devices keep it in a mostly working, but strange state (with busy 349 * led on) 350 */ 351 wdcreset(wdc, VERBOSE); 352 } 353 354 /* 355 * Start I/O on a controller. This does the calculation, and starts a read or 356 * write operation. Called to from wdstart() to start a transfer, from 357 * wdcintr() to continue a multi-sector transfer or start the next transfer, or 358 * wdcrestart() after recovering from an error. 359 */ 360 void 361 wdcstart(wdc) 362 struct wdc_softc *wdc; 363 { 364 struct wdc_xfer *xfer; 365 366 if ((wdc->sc_flags & WDCF_ACTIVE) != 0 ) { 367 WDDEBUG_PRINT(("wdcstart: already active\n")); 368 return; /* controller aleady active */ 369 } 370 #ifdef DIAGNOSTIC 371 if ((wdc->sc_flags & WDCF_IRQ_WAIT) != 0) 372 panic("wdcstart: controller waiting for irq\n"); 373 #endif 374 /* is there a xfer ? */ 375 xfer = wdc->sc_xfer.tqh_first; 376 if (xfer == NULL) { 377 #ifdef ATAPI_DEBUG2 378 printf("wdcstart: null xfer\n"); 379 #endif 380 /* 381 * XXX 382 * This is a kluge. See comments in wd_get_parms(). 383 */ 384 if ((wdc->sc_flags & WDCF_WANTED) != 0) { 385 #ifdef ATAPI_DEBUG2 386 printf("WDCF_WANTED\n"); 387 #endif 388 wdc->sc_flags &= ~WDCF_WANTED; 389 wakeup(wdc); 390 } 391 return; 392 } 393 394 if (wdc->sc_cap & WDC_CAPABILITY_HWLOCK) 395 if (!(*wdc->sc_claim_hw)(wdc, 0)) 396 return; 397 398 wdc->sc_flags |= WDCF_ACTIVE; 399 #ifdef ATAPI_DEBUG2 400 printf("wdcstart: drive %d\n", (int)xfer->d_link->drive); 401 #endif 402 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM | xfer->d_link->drive << 4); 403 #if NATAPIBUS > 0 && NWD > 0 404 if (xfer->c_flags & C_ATAPI) { 405 #ifdef ATAPI_DEBUG_WDC 406 printf("wdcstart: atapi\n"); 407 #endif 408 wdc_atapi_start(wdc,xfer); 409 } else 410 wdc_ata_start(wdc,xfer); 411 #else /* NATAPIBUS > 0 && NWD > 0 */ 412 #if NATAPIBUS > 0 413 #ifdef ATAPI_DEBUG_WDC 414 printf("wdcstart: atapi\n"); 415 #endif 416 wdc_atapi_start(wdc,xfer); 417 #endif /* NATAPIBUS > */ 418 #if NWD > 0 419 wdc_ata_start(wdc,xfer); 420 #endif /* NWD > 0 */ 421 #endif /* NATAPIBUS > 0 && NWD > 0 */ 422 } 423 424 #if NWD > 0 425 int 426 wdprint(aux, wdc) 427 void *aux; 428 const char *wdc; 429 { 430 struct wd_link *d_link = aux; 431 432 if (!wdc) 433 printf(" drive %d", d_link->drive); 434 return QUIET; 435 } 436 437 void 438 wdc_ata_start(wdc, xfer) 439 struct wdc_softc *wdc; 440 struct wdc_xfer *xfer; 441 { 442 struct wd_link *d_link; 443 struct buf *bp = xfer->c_bp; 444 int nblks; 445 446 d_link=xfer->d_link; 447 448 if (wdc->sc_errors >= WDIORETRIES) { 449 wderror(d_link, bp, "wdc_ata_start hard error"); 450 xfer->c_flags |= C_ERROR; 451 wdc_ata_done(wdc, xfer); 452 return; 453 } 454 455 /* Do control operations specially. */ 456 if (d_link->sc_state < READY) { 457 /* 458 * Actually, we want to be careful not to mess with the control 459 * state if the device is currently busy, but we can assume 460 * that we never get to this point if that's the case. 461 */ 462 if (wdccontrol(wdc, d_link) == 0) { 463 /* The drive is busy. Wait. */ 464 return; 465 } 466 } 467 468 /* 469 * WDCF_ERROR is set by wdcunwedge() and wdcintr() when an error is 470 * encountered. If we are in multi-sector mode, then we switch to 471 * single-sector mode and retry the operation from the start. 472 */ 473 if (wdc->sc_flags & WDCF_ERROR) { 474 wdc->sc_flags &= ~WDCF_ERROR; 475 if ((wdc->sc_flags & WDCF_SINGLE) == 0) { 476 wdc->sc_flags |= WDCF_SINGLE; 477 xfer->c_skip = 0; 478 } 479 } 480 481 482 /* When starting a transfer... */ 483 if (xfer->c_skip == 0) { 484 daddr_t blkno; 485 486 WDDEBUG_PRINT(("\n%s: wdc_ata_start %s %d@%d; map ", 487 wdc->sc_dev.dv_xname, 488 (xfer->c_flags & B_READ) ? "read" : "write", 489 xfer->c_bcount, xfer->c_blkno)); 490 491 blkno = xfer->c_blkno+xfer->c_p_offset; 492 xfer->c_blkno = blkno / (d_link->sc_lp->d_secsize / DEV_BSIZE); 493 } else { 494 WDDEBUG_PRINT((" %d)%x", xfer->c_skip, 495 bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_altsts))); 496 } 497 498 /* 499 * When starting a multi-sector transfer, or doing single-sector 500 * transfers... 501 */ 502 if (xfer->c_skip == 0 || (wdc->sc_flags & WDCF_SINGLE) != 0 || 503 d_link->sc_mode == WDM_DMA) { 504 daddr_t blkno = xfer->c_blkno; 505 long cylin, head, sector; 506 int command; 507 508 if ((wdc->sc_flags & WDCF_SINGLE) != 0) 509 nblks = 1; 510 else if (d_link->sc_mode != WDM_DMA) 511 nblks = xfer->c_bcount / d_link->sc_lp->d_secsize; 512 else 513 nblks = 514 min(xfer->c_bcount / d_link->sc_lp->d_secsize, 8); 515 516 /* Check for bad sectors and adjust transfer, if necessary. */ 517 if ((d_link->sc_lp->d_flags & D_BADSECT) != 0 518 #ifdef B_FORMAT 519 && (bp->b_flags & B_FORMAT) == 0 520 #endif 521 ) { 522 long blkdiff; 523 int i; 524 525 for (i = 0; 526 (blkdiff = d_link->sc_badsect[i]) != -1; i++) { 527 blkdiff -= blkno; 528 if (blkdiff < 0) 529 continue; 530 if (blkdiff == 0) { 531 /* Replace current block of transfer. */ 532 blkno = 533 d_link->sc_lp->d_secperunit - 534 d_link->sc_lp->d_nsectors - i - 1; 535 } 536 if (blkdiff < nblks) { 537 /* Bad block inside transfer. */ 538 wdc->sc_flags |= WDCF_SINGLE; 539 nblks = 1; 540 } 541 break; 542 } 543 /* Transfer is okay now. */ 544 } 545 546 if ((d_link->sc_params.wdp_capabilities & WD_CAP_LBA) != 0) { 547 sector = (blkno >> 0) & 0xff; 548 cylin = (blkno >> 8) & 0xffff; 549 head = (blkno >> 24) & 0xf; 550 head |= WDSD_LBA; 551 } else { 552 sector = blkno % d_link->sc_lp->d_nsectors; 553 sector++; /* Sectors begin with 1, not 0. */ 554 blkno /= d_link->sc_lp->d_nsectors; 555 head = blkno % d_link->sc_lp->d_ntracks; 556 blkno /= d_link->sc_lp->d_ntracks; 557 cylin = blkno; 558 head |= WDSD_CHS; 559 } 560 561 if (d_link->sc_mode == WDM_PIOSINGLE || 562 (wdc->sc_flags & WDCF_SINGLE) != 0) 563 xfer->c_nblks = 1; 564 else if (d_link->sc_mode == WDM_PIOMULTI) 565 xfer->c_nblks = min(nblks, d_link->sc_multiple); 566 else 567 xfer->c_nblks = nblks; 568 xfer->c_nbytes = xfer->c_nblks * d_link->sc_lp->d_secsize; 569 570 #ifdef B_FORMAT 571 if (bp->b_flags & B_FORMAT) { 572 sector = d_link->sc_lp->d_gap3; 573 nblks = d_link->sc_lp->d_nsectors; 574 command = WDCC_FORMAT; 575 } else 576 #endif 577 switch (d_link->sc_mode) { 578 case WDM_DMA: 579 command = (xfer->c_flags & B_READ) ? 580 WDCC_READDMA : WDCC_WRITEDMA; 581 /* Start the DMA channel. */ 582 (*wdc->sc_dma_start)(wdc->sc_dma_arg, 583 xfer->databuf + xfer->c_skip, xfer->c_nbytes, 584 xfer->c_flags & B_READ); 585 break; 586 587 case WDM_PIOMULTI: 588 command = (xfer->c_flags & B_READ) ? 589 WDCC_READMULTI : WDCC_WRITEMULTI; 590 break; 591 592 case WDM_PIOSINGLE: 593 command = (xfer->c_flags & B_READ) ? 594 WDCC_READ : WDCC_WRITE; 595 break; 596 597 default: 598 #ifdef DIAGNOSTIC 599 panic("bad wd mode"); 600 #endif 601 return; 602 } 603 604 /* Initiate command! */ 605 if (wdccommand(wdc, d_link, command, d_link->drive, 606 cylin, head, sector, nblks) != 0) { 607 wderror(d_link, NULL, 608 "wdc_ata_start: timeout waiting for unbusy"); 609 wdcunwedge(wdc); 610 return; 611 } 612 613 WDDEBUG_PRINT(("sector %lu cylin %lu head %lu addr %p sts %x\n", 614 sector, cylin, head, xfer->databuf, 615 bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_altsts))); 616 617 } else if (xfer->c_nblks > 1) { 618 /* The number of blocks in the last stretch may be smaller. */ 619 nblks = xfer->c_bcount / d_link->sc_lp->d_secsize; 620 if (xfer->c_nblks > nblks) { 621 xfer->c_nblks = nblks; 622 xfer->c_nbytes = xfer->c_bcount; 623 } 624 } 625 626 /* If this was a write and not using DMA, push the data. */ 627 if (d_link->sc_mode != WDM_DMA && 628 (xfer->c_flags & (B_READ|B_WRITE)) == B_WRITE) { 629 if (wait_for_drq(wdc) < 0) { 630 wderror(d_link, NULL, 631 "wdc_ata_start: timeout waiting for drq"); 632 wdcunwedge(wdc); 633 return; 634 } 635 636 if ((wdc->sc_cap & WDC_CAPABILITY_DATA32) == 0) 637 bus_space_write_multi_stream_2(wdc->sc_iot, wdc->sc_ioh, 638 wd_data, xfer->databuf + xfer->c_skip, 639 xfer->c_nbytes >> 1); 640 else 641 bus_space_write_multi_stream_4(wdc->sc_iot, wdc->sc_ioh, 642 wd_data, xfer->databuf + xfer->c_skip, 643 xfer->c_nbytes >> 2); 644 } 645 646 wdc->sc_flags |= WDCF_IRQ_WAIT; 647 WDDEBUG_PRINT(("wdc_ata_start: timeout ")); 648 timeout(wdctimeout, wdc, WAITTIME); 649 WDDEBUG_PRINT(("done\n")); 650 } 651 652 int 653 wdc_ata_intr(wdc,xfer) 654 struct wdc_softc *wdc; 655 struct wdc_xfer *xfer; 656 { 657 struct wd_link *d_link; 658 659 d_link = xfer->d_link; 660 661 if (wait_for_unbusy(wdc) < 0) { 662 wdcerror(wdc, "wdcintr: timeout waiting for unbusy"); 663 return 0; 664 } 665 666 wdc->sc_flags &= ~WDCF_IRQ_WAIT; 667 untimeout(wdctimeout, wdc); 668 669 /* Is it not a transfer, but a control operation? */ 670 if (d_link->sc_state < READY) { 671 if (wdccontrol(wdc, d_link) == 0) { 672 /* The drive is busy. Wait. */ 673 return 1; 674 } 675 WDDEBUG_PRINT(("wdc_ata_start from wdc_ata_intr(open) flags 0x%x\n", 676 wdc->sc_flags)); 677 wdc_ata_start(wdc,xfer); 678 return 1; 679 } 680 681 /* Turn off the DMA channel. */ 682 if (d_link->sc_mode == WDM_DMA) 683 (*wdc->sc_dma_finish)(wdc->sc_dma_arg); 684 685 /* Have we an error? */ 686 if (wdc->sc_status & WDCS_ERR) { 687 #ifdef WDDEBUG 688 wderror(d_link, NULL, "wdc_ata_start"); 689 #endif 690 if ((wdc->sc_flags & WDCF_SINGLE) == 0) { 691 wdc->sc_flags |= WDCF_ERROR; 692 goto restart; 693 } 694 695 #ifdef B_FORMAT 696 if (bp->b_flags & B_FORMAT) 697 goto bad; 698 #endif 699 700 if (++wdc->sc_errors < WDIORETRIES) { 701 if (wdc->sc_errors == (WDIORETRIES + 1) / 2) { 702 #if 0 703 wderror(wd, NULL, "wedgie"); 704 #endif 705 wdcunwedge(wdc); 706 return 1; 707 } 708 goto restart; 709 } 710 wderror(d_link, xfer->c_bp, "wdc_ata_intr hard error"); 711 712 #ifdef B_FORMAT 713 bad: 714 #endif 715 xfer->c_flags |= C_ERROR; 716 goto done; 717 } 718 719 /* If this was a read and not using DMA, fetch the data. */ 720 if (d_link->sc_mode != WDM_DMA && 721 (xfer->c_flags & (B_READ|B_WRITE)) == B_READ) { 722 if ((wdc->sc_status & (WDCS_DRDY | WDCS_DSC | WDCS_DRQ)) 723 != (WDCS_DRDY | WDCS_DSC | WDCS_DRQ)) { 724 wderror(d_link, NULL, "wdcintr: read intr before drq"); 725 wdcunwedge(wdc); 726 return 1; 727 } 728 729 /* Pull in data. */ 730 if ((wdc->sc_cap & WDC_CAPABILITY_DATA32) == 0) 731 bus_space_read_multi_stream_2(wdc->sc_iot, wdc->sc_ioh, 732 wd_data, xfer->databuf + xfer->c_skip, 733 xfer->c_nbytes >> 1); 734 else 735 bus_space_read_multi_stream_4(wdc->sc_iot, wdc->sc_ioh, 736 wd_data, xfer->databuf + xfer->c_skip, 737 xfer->c_nbytes >> 2); 738 } 739 740 /* If we encountered any abnormalities, flag it as a soft error. */ 741 if (wdc->sc_errors > 0 || 742 (wdc->sc_status & WDCS_CORR) != 0) { 743 wderror(d_link, xfer->c_bp, "soft error (corrected)"); 744 wdc->sc_errors = 0; 745 } 746 747 /* Adjust pointers for the next block, if any. */ 748 xfer->c_blkno += xfer->c_nblks; 749 xfer->c_skip += xfer->c_nbytes; 750 xfer->c_bcount -= xfer->c_nbytes; 751 752 /* See if this transfer is complete. */ 753 if (xfer->c_bcount > 0) 754 goto restart; 755 756 done: 757 /* Done with this transfer, with or without error. */ 758 wdc_ata_done(wdc, xfer); 759 return 1; 760 761 restart: 762 /* Start the next operation */ 763 WDDEBUG_PRINT(("wdc_ata_start from wdcintr flags 0x%x\n", 764 wdc->sc_flags)); 765 wdc_ata_start(wdc, xfer); 766 767 return 1; 768 } 769 770 void 771 wdc_ata_done(wdc, xfer) 772 struct wdc_softc *wdc; 773 struct wdc_xfer *xfer; 774 { 775 struct buf *bp = xfer->c_bp; 776 struct wd_link *d_link = xfer->d_link; 777 int s; 778 779 WDDEBUG_PRINT(("wdc_ata_done\n")); 780 781 if (wdc->sc_cap & WDC_CAPABILITY_HWLOCK) 782 (*wdc->sc_free_hw)(wdc); 783 784 /* remove this command from xfer queue */ 785 s = splbio(); 786 TAILQ_REMOVE(&wdc->sc_xfer, xfer, c_xferchain); 787 wdc->sc_flags &= ~(WDCF_SINGLE | WDCF_ERROR | WDCF_ACTIVE); 788 wdc->sc_errors = 0; 789 if (bp) { 790 if (xfer->c_flags & C_ERROR) { 791 bp->b_flags |= B_ERROR; 792 bp->b_error = EIO; 793 } 794 bp->b_resid = xfer->c_bcount; 795 wddone(d_link, bp); 796 biodone(bp); 797 } else { 798 wakeup(xfer->databuf); 799 } 800 xfer->c_skip = 0; 801 wdc_free_xfer(xfer); 802 d_link->openings++; 803 wdstart((void*)d_link->wd_softc); 804 WDDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", 805 wdc->sc_flags)); 806 wdcstart(wdc); 807 splx(s); 808 } 809 810 /* 811 * Get the drive parameters, if ESDI or ATA, or create fake ones for ST506. 812 */ 813 int 814 wdc_get_parms(wdc, d_link) 815 struct wdc_softc * wdc; 816 struct wd_link *d_link; 817 { 818 int i; 819 char tb[DEV_BSIZE]; 820 int s, error; 821 822 /* 823 * XXX 824 * The locking done here, and the length of time this may keep the rest 825 * of the system suspended, is a kluge. This should be rewritten to 826 * set up a transfer and queue it through wdstart(), but it's called 827 * infrequently enough that this isn't a pressing matter. 828 */ 829 830 s = splbio(); 831 832 while ((wdc->sc_flags & WDCF_ACTIVE) != 0) { 833 wdc->sc_flags |= WDCF_WANTED; 834 if ((error = tsleep(wdc, PRIBIO | PCATCH, "wdprm", 0)) != 0) { 835 splx(s); 836 return error; 837 } 838 } 839 if (wdc->sc_cap & WDC_CAPABILITY_HWLOCK) 840 if (!(*wdc->sc_claim_hw)(wdc, 1)) 841 panic("wdc_get_parms: Cannot claim wd-hardware"); 842 843 wdc->sc_flags |= WDCF_ACTIVE; 844 845 if (wdccommandshort(wdc, d_link->drive, WDCC_IDENTIFY) != 0 || 846 wait_for_drq(wdc) != 0) { 847 /* 848 * We `know' there's a drive here; just assume it's old. 849 * This geometry is only used to read the MBR and print a 850 * (false) attach message. 851 */ 852 strncpy(d_link->sc_lp->d_typename, "ST506", 853 sizeof d_link->sc_lp->d_typename); 854 d_link->sc_lp->d_type = DTYPE_ST506; 855 856 strncpy(d_link->sc_params.wdp_model, "unknown", 857 sizeof d_link->sc_params.wdp_model); 858 d_link->sc_params.wdp_config = WD_CFG_FIXED; 859 d_link->sc_params.wdp_cylinders = 1024; 860 d_link->sc_params.wdp_heads = 8; 861 d_link->sc_params.wdp_sectors = 17; 862 d_link->sc_params.wdp_maxmulti = 0; 863 d_link->sc_params.wdp_usedmovsd = 0; 864 d_link->sc_params.wdp_capabilities = 0; 865 } else { 866 strncpy(d_link->sc_lp->d_typename, "ESDI/IDE", 867 sizeof d_link->sc_lp->d_typename); 868 d_link->sc_lp->d_type = DTYPE_ESDI; 869 870 /* Read in parameter block. */ 871 bus_space_read_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data, 872 (u_int16_t *)tb, sizeof(tb) >> 1); 873 bcopy(tb, &d_link->sc_params, sizeof(struct wdparams)); 874 875 /* Shuffle string byte order. */ 876 for (i = 0; i < sizeof(d_link->sc_params.wdp_model); i += 2) { 877 u_short *p; 878 p = (u_short *)(d_link->sc_params.wdp_model + i); 879 *p = ntohs(*p); 880 } 881 } 882 883 /* Clear any leftover interrupt. */ 884 (void) bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status); 885 886 if (wdc->sc_cap & WDC_CAPABILITY_HWLOCK) 887 (*wdc->sc_free_hw)(wdc); 888 889 /* Restart the queue. */ 890 WDDEBUG_PRINT(("wdcstart from wdc_get_parms flags 0x%x\n", 891 wdc->sc_flags)); 892 wdc->sc_flags &= ~WDCF_ACTIVE; 893 wdcstart(wdc); 894 895 splx(s); 896 return 0; 897 } 898 899 /* 900 * Implement operations needed before read/write. 901 * Returns 0 if operation still in progress, 1 if completed. 902 */ 903 int 904 wdccontrol(wdc, d_link) 905 struct wdc_softc *wdc; 906 struct wd_link *d_link; 907 { 908 WDDEBUG_PRINT(("wdccontrol\n")); 909 910 switch (d_link->sc_state) { 911 case RECAL: /* Set SDH, step rate, do recal. */ 912 if (wdccommandshort(wdc, d_link->drive, WDCC_RECAL) != 0) { 913 wderror(d_link, NULL, "wdccontrol: recal failed (1)"); 914 goto bad; 915 } 916 d_link->sc_state = RECAL_WAIT; 917 break; 918 919 case RECAL_WAIT: 920 if (wdc->sc_status & WDCS_ERR) { 921 wderror(d_link, NULL, "wdccontrol: recal failed (2)"); 922 goto bad; 923 } 924 /* fall through */ 925 926 case GEOMETRY: 927 if ((d_link->sc_params.wdp_capabilities & WD_CAP_LBA) != 0) 928 goto multimode; 929 if (wdsetctlr(d_link) != 0) { 930 /* Already printed a message. */ 931 goto bad; 932 } 933 d_link->sc_state = GEOMETRY_WAIT; 934 break; 935 936 case GEOMETRY_WAIT: 937 if (wdc->sc_status & WDCS_ERR) { 938 wderror(d_link, NULL, "wdccontrol: geometry failed"); 939 goto bad; 940 } 941 /* fall through */ 942 943 case MULTIMODE: 944 multimode: 945 if (d_link->sc_mode != WDM_PIOMULTI) 946 goto ready; 947 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_seccnt, d_link->sc_multiple); 948 if (wdccommandshort(wdc, d_link->drive, 949 WDCC_SETMULTI) != 0) { 950 wderror(d_link, NULL, 951 "wdccontrol: setmulti failed (1)"); 952 goto bad; 953 } 954 d_link->sc_state = MULTIMODE_WAIT; 955 break; 956 957 case MULTIMODE_WAIT: 958 if (wdc->sc_status & WDCS_ERR) { 959 wderror(d_link, NULL, 960 "wdccontrol: setmulti failed (2)"); 961 goto bad; 962 } 963 /* fall through */ 964 965 case READY: 966 ready: 967 wdc->sc_errors = 0; 968 d_link->sc_state = READY; 969 /* 970 * The rest of the initialization can be done by normal means. 971 */ 972 return 1; 973 974 bad: 975 wdcunwedge(wdc); 976 return 0; 977 } 978 979 wdc->sc_flags |= WDCF_IRQ_WAIT; 980 timeout(wdctimeout, wdc, WAITTIME); 981 return 0; 982 } 983 984 #endif /* NWD > 0 */ 985 986 987 /* 988 * Interrupt routine for the controller. Acknowledge the interrupt, check for 989 * errors on the current operation, mark it done if necessary, and start the 990 * next request. Also check for a partially done transfer, and continue with 991 * the next chunk if so. 992 */ 993 int 994 wdcintr(arg) 995 void *arg; 996 { 997 struct wdc_softc *wdc = arg; 998 struct wdc_xfer *xfer; 999 1000 if ((wdc->sc_flags & WDCF_IRQ_WAIT) == 0) { 1001 /* Clear the pending interrupt and abort. */ 1002 u_char s = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status); 1003 1004 #ifdef ATAPI_DEBUG_WDC 1005 u_char e = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1006 u_char i = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_seccnt); 1007 printf("wdcintr: inactive controller, " 1008 "punting st=%02x er=%02x irr=%02x\n", s, e, i); 1009 #else 1010 bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1011 bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_seccnt); 1012 #endif 1013 1014 if (s & WDCS_DRQ) { 1015 int len = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_lo) + 1016 256 * bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_hi); 1017 #ifdef ATAPI_DEBUG_WDC 1018 printf ("wdcintr: clearing up %d bytes\n", len); 1019 #endif 1020 wdcbit_bucket (wdc, len); 1021 } 1022 return 0; 1023 } 1024 1025 WDDEBUG_PRINT(("wdcintr\n")); 1026 1027 xfer = wdc->sc_xfer.tqh_first; 1028 #if NATAPIBUS > 0 && NWD > 0 1029 if (xfer->c_flags & C_ATAPI) { 1030 return wdc_atapi_intr(wdc,xfer); 1031 } else 1032 return wdc_ata_intr(wdc,xfer); 1033 #else /* NATAPIBUS > 0 && NWD > 0 */ 1034 #if NATAPIBUS > 0 1035 return wdc_atapi_intr(wdc,xfer); 1036 #endif /* NATAPIBUS > 0 */ 1037 #if NWD > 0 1038 return wdc_ata_intr(wdc,xfer); 1039 #endif /* NWD > 0 */ 1040 #endif /* NATAPIBUS > 0 && NWD > 0 */ 1041 } 1042 1043 int 1044 wdcreset(wdc, verb) 1045 struct wdc_softc *wdc; 1046 int verb; 1047 { 1048 1049 /* Reset the device. */ 1050 bus_space_write_1(wdc->sc_auxiot, wdc->sc_auxioh, wd_aux_ctlr, 1051 WDCTL_RST | WDCTL_IDS); 1052 delay(1000); 1053 bus_space_write_1(wdc->sc_auxiot, wdc->sc_auxioh, wd_aux_ctlr, 1054 WDCTL_IDS); 1055 delay(1000); 1056 (void) bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1057 bus_space_write_1(wdc->sc_auxiot, wdc->sc_auxioh, wd_aux_ctlr, 1058 WDCTL_4BIT); 1059 1060 if (wait_for_unbusy(wdc) < 0) { 1061 if (verb) 1062 printf("%s: reset failed\n", wdc->sc_dev.dv_xname); 1063 return 1; 1064 } 1065 1066 return 0; 1067 } 1068 1069 void 1070 wdcrestart(arg) 1071 void *arg; 1072 { 1073 struct wdc_softc *wdc = arg; 1074 int s; 1075 1076 s = splbio(); 1077 wdcstart(wdc); 1078 splx(s); 1079 } 1080 1081 /* 1082 * Unwedge the controller after an unexpected error. We do this by resetting 1083 * it, marking all drives for recalibration, and stalling the queue for a short 1084 * period to give the reset time to finish. 1085 * NOTE: We use a timeout here, so this routine must not be called during 1086 * autoconfig or dump. 1087 */ 1088 void 1089 wdcunwedge(wdc) 1090 struct wdc_softc *wdc; 1091 { 1092 int unit; 1093 1094 #ifdef ATAPI_DEBUG 1095 printf("wdcunwedge\n"); 1096 #endif 1097 1098 untimeout(wdctimeout, wdc); 1099 wdc->sc_flags &= ~WDCF_IRQ_WAIT; 1100 (void) wdcreset(wdc, VERBOSE); 1101 1102 /* Schedule recalibrate for all drives on this controller. */ 1103 for (unit = 0; unit < 2; unit++) { 1104 if (!wdc->d_link[unit]) 1105 wdccommandshort(wdc, unit, ATAPI_SOFT_RESET); 1106 else if (wdc->d_link[unit]->sc_state > RECAL) 1107 wdc->d_link[unit]->sc_state = RECAL; 1108 } 1109 1110 wdc->sc_flags |= WDCF_ERROR; 1111 ++wdc->sc_errors; 1112 1113 /* Wake up in a little bit and restart the operation. */ 1114 WDDEBUG_PRINT(("wdcrestart from wdcunwedge\n")); 1115 wdc->sc_flags &= ~WDCF_ACTIVE; 1116 timeout(wdcrestart, wdc, RECOVERYTIME); 1117 } 1118 1119 int 1120 wdcwait(wdc, mask) 1121 struct wdc_softc *wdc; 1122 int mask; 1123 { 1124 int timeout = 0; 1125 u_char status; 1126 #ifdef WDCNDELAY_DEBUG 1127 extern int cold; 1128 #endif 1129 1130 WDDEBUG_PRINT(("wdcwait\n")); 1131 1132 for (;;) { 1133 wdc->sc_status = status = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status); 1134 /* 1135 * XXX 1136 * If a single slave ATAPI device is attached, it may 1137 * have released the bus. Select it and try again. 1138 */ 1139 if (status == 0xff && wdc->sc_flags & WDCF_ONESLAVE) { 1140 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM | 0x10); 1141 wdc->sc_status = status = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status); 1142 } 1143 if ((status & WDCS_BSY) == 0 && (status & mask) == mask) 1144 break; 1145 if (++timeout > WDCNDELAY) { 1146 #ifdef ATAPI_DEBUG 1147 printf("wdcwait: timeout, status %x error %x\n", status, bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error)); 1148 #endif 1149 return -1; 1150 } 1151 delay(WDCDELAY); 1152 } 1153 if (status & WDCS_ERR) { 1154 wdc->sc_error = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1155 return WDCS_ERR; 1156 } 1157 #ifdef WDCNDELAY_DEBUG 1158 /* After autoconfig, there should be no long delays. */ 1159 if (!cold && timeout > WDCNDELAY_DEBUG) { 1160 struct wdc_xfer *xfer = wdc->sc_xfer.tqh_first; 1161 if (xfer == NULL) 1162 printf("%s: warning: busy-wait took %dus\n", 1163 wdc->sc_dev.dv_xname, WDCDELAY * timeout); 1164 else 1165 printf("%s(%s): warning: busy-wait took %dus\n", 1166 wdc->sc_dev.dv_xname, 1167 ((struct device*)xfer->d_link->wd_softc)->dv_xname, 1168 WDCDELAY * timeout); 1169 } 1170 #endif 1171 return 0; 1172 } 1173 1174 void 1175 wdctimeout(arg) 1176 void *arg; 1177 { 1178 struct wdc_softc *wdc = (struct wdc_softc *)arg; 1179 struct wdc_xfer *xfer = wdc->sc_xfer.tqh_first; 1180 int s; 1181 1182 WDDEBUG_PRINT(("wdctimeout\n")); 1183 1184 s = splbio(); 1185 if ((wdc->sc_flags & WDCF_IRQ_WAIT) != 0) { 1186 wdcerror(wdc, "lost interrupt"); 1187 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? "atapi":"ata"); 1188 printf("\tc_bcount: %d\n", xfer->c_bcount); 1189 printf("\tc_skip: %d\n", xfer->c_skip); 1190 wdcintr(wdc); 1191 wdc->sc_flags &= ~WDCF_IRQ_WAIT; 1192 wdcunwedge(wdc); 1193 } else 1194 wdcerror(wdc, "missing untimeout"); 1195 splx(s); 1196 } 1197 1198 /* 1199 * Wait for the drive to become ready and send a command. 1200 * Return -1 if busy for too long or 0 otherwise. 1201 * Assumes interrupts are blocked. 1202 */ 1203 int 1204 wdccommand(wdc, d_link, command, drive, cylin, head, sector, count) 1205 struct wdc_softc *wdc; 1206 struct wd_link *d_link; 1207 int command; 1208 int drive, cylin, head, sector, count; 1209 { 1210 int stat; 1211 1212 WDDEBUG_PRINT(("wdccommand drive %d\n", drive)); 1213 1214 #if defined(DIAGNOSTIC) && defined(WDCDEBUG) 1215 if ((wdc->sc_flags & WDCF_ACTIVE) == 0) 1216 printf("wdccommand: controler not active (drive %d)\n", drive); 1217 #endif 1218 1219 /* Select drive, head, and addressing mode. */ 1220 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM | (drive << 4) | head); 1221 1222 /* Wait for it to become ready to accept a command. */ 1223 if (command == WDCC_IDP || d_link->type == ATAPI) 1224 stat = wait_for_unbusy(wdc); 1225 else 1226 stat = wdcwait(wdc, WDCS_DRDY); 1227 1228 if (stat < 0) { 1229 #ifdef ATAPI_DEBUG 1230 printf("wdcommand: xfer failed (wait_for_unbusy) status %d\n", 1231 stat); 1232 #endif 1233 return -1; 1234 } 1235 1236 /* Load parameters. */ 1237 if (d_link->type == ATA && d_link->sc_lp->d_type == DTYPE_ST506) 1238 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_precomp, d_link->sc_lp->d_precompcyl / 4); 1239 else 1240 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_features, 0); 1241 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_lo, cylin); 1242 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_hi, cylin >> 8); 1243 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sector, sector); 1244 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_seccnt, count); 1245 1246 /* Send command. */ 1247 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_command, command); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Simplified version of wdccommand(). 1254 */ 1255 int 1256 wdccommandshort(wdc, drive, command) 1257 struct wdc_softc *wdc; 1258 int drive; 1259 int command; 1260 { 1261 1262 WDDEBUG_PRINT(("wdccommandshort\n")); 1263 1264 #if defined(DIAGNOSTIC) && defined(WDCDEBUG) 1265 if ((wdc->sc_flags & WDCF_ACTIVE) == 0) 1266 printf("wdccommandshort: controller not active (drive %d)\n", 1267 drive); 1268 #endif 1269 1270 /* Select drive. */ 1271 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_sdh, WDSD_IBM | (drive << 4)); 1272 1273 if (wdcwait(wdc, WDCS_DRDY) < 0) 1274 return -1; 1275 1276 bus_space_write_1(wdc->sc_iot, wdc->sc_ioh, wd_command, command); 1277 1278 return 0; 1279 } 1280 1281 void 1282 wdc_exec_xfer(wdc, d_link, xfer) 1283 struct wdc_softc *wdc; 1284 struct wd_link *d_link; 1285 struct wdc_xfer *xfer; 1286 { 1287 int s; 1288 1289 WDDEBUG_PRINT(("wdc_exec_xfer\n")); 1290 1291 s = splbio(); 1292 1293 /* insert at the end of command list */ 1294 TAILQ_INSERT_TAIL(&wdc->sc_xfer,xfer , c_xferchain); 1295 WDDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1296 wdc->sc_flags)); 1297 wdcstart(wdc); 1298 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1299 splx(s); 1300 } 1301 1302 struct wdc_xfer * 1303 wdc_get_xfer(flags) 1304 int flags; 1305 { 1306 struct wdc_xfer *xfer; 1307 int s; 1308 1309 s = splbio(); 1310 if ((xfer = xfer_free_list.lh_first) != NULL) { 1311 LIST_REMOVE(xfer, free_list); 1312 splx(s); 1313 #ifdef DIAGNOSTIC 1314 if ((xfer->c_flags & C_INUSE) != 0) 1315 panic("wdc_get_xfer: xfer already in use\n"); 1316 #endif 1317 } else { 1318 splx(s); 1319 #ifdef ATAPI_DEBUG2 1320 printf("wdc:making xfer %d\n",wdc_nxfer); 1321 #endif 1322 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1323 ((flags & IDE_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1324 if (xfer == NULL) 1325 return 0; 1326 1327 #ifdef DIAGNOSTIC 1328 xfer->c_flags &= ~C_INUSE; 1329 #endif 1330 #ifdef ATAPI_DEBUG2 1331 wdc_nxfer++; 1332 #endif 1333 } 1334 #ifdef DIAGNOSTIC 1335 if ((xfer->c_flags & C_INUSE) != 0) 1336 panic("wdc_get_xfer: xfer already in use\n"); 1337 #endif 1338 bzero(xfer,sizeof(struct wdc_xfer)); 1339 xfer->c_flags = C_INUSE; 1340 return xfer; 1341 } 1342 1343 void 1344 wdc_free_xfer(xfer) 1345 struct wdc_xfer *xfer; 1346 { 1347 int s; 1348 1349 s = splbio(); 1350 xfer->c_flags &= ~C_INUSE; 1351 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1352 splx(s); 1353 } 1354 1355 void 1356 wdcerror(wdc, msg) 1357 struct wdc_softc *wdc; 1358 char *msg; 1359 { 1360 struct wdc_xfer *xfer = wdc->sc_xfer.tqh_first; 1361 if (xfer == NULL) 1362 printf("%s: %s\n", wdc->sc_dev.dv_xname, msg); 1363 else 1364 printf("%s(%d): %s\n", wdc->sc_dev.dv_xname, 1365 xfer->d_link->drive, msg); 1366 } 1367 1368 /* 1369 * the bit bucket 1370 */ 1371 void 1372 wdcbit_bucket(wdc, size) 1373 struct wdc_softc *wdc; 1374 int size; 1375 { 1376 1377 for (; size >= 2; size -= 2) 1378 (void)bus_space_read_2(wdc->sc_iot, wdc->sc_ioh, wd_data); 1379 if (size) 1380 (void)bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_data); 1381 } 1382 1383 1384 #if NATAPIBUS > 0 1385 1386 void 1387 wdc_atapi_minphys (struct buf *bp) 1388 { 1389 if(bp->b_bcount > MAX_SIZE) 1390 bp->b_bcount = MAX_SIZE; 1391 minphys(bp); 1392 } 1393 1394 1395 void 1396 wdc_atapi_start(wdc, xfer) 1397 struct wdc_softc *wdc; 1398 struct wdc_xfer *xfer; 1399 { 1400 struct scsipi_xfer *sc_xfer = xfer->atapi_cmd; 1401 1402 #ifdef ATAPI_DEBUG_WDC 1403 printf("wdc_atapi_start, acp flags %x \n",sc_xfer->flags); 1404 #endif 1405 if (wdc->sc_errors >= WDIORETRIES) { 1406 if ((wdc->sc_status & WDCS_ERR) == 0) { 1407 sc_xfer->error = XS_DRIVER_STUFFUP; /* XXX do we know more ? */ 1408 } else { 1409 sc_xfer->error = XS_SENSE; 1410 sc_xfer->sense.atapi_sense = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1411 } 1412 wdc_atapi_done(wdc, xfer); 1413 return; 1414 } 1415 if (wait_for_unbusy(wdc) != 0) { 1416 if ((wdc->sc_status & WDCS_ERR) == 0) { 1417 printf("wdc_atapi_start: not ready, st = %02x\n", 1418 wdc->sc_status); 1419 sc_xfer->error = XS_SELTIMEOUT; 1420 } 1421 #if 0 /* don't get the sense yet, as this may be just UNIT ATTENTION */ 1422 else { 1423 #ifdef ATAPI_DEBUG_WDC 1424 printf("wdc_atapi_start: sense %02x\n", wdc->sc_error); 1425 #endif 1426 sc_xfer->error = XS_SENSE; 1427 sc_xfer->sense.atapi_sense = wdc->sc_error; 1428 } 1429 wdc_atapi_done(wdc, xfer); 1430 return; 1431 #endif 1432 } 1433 1434 /* 1435 * Limit length to what can be stuffed into the cylinder register 1436 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1437 * but not all devices do that and it's not obvious from the 1438 * ATAPI spec that that behaviour should be expected. If more 1439 * data is necessary, multiple data transfer phases will be done. 1440 */ 1441 if (wdccommand(wdc, (struct wd_link*)xfer->d_link, ATAPI_PACKET_COMMAND, 1442 sc_xfer->sc_link->scsipi_atapi.drive, 1443 sc_xfer->datalen <= 0xffff ? sc_xfer->datalen : 0xffff, 1444 0, 0, 0) != 0) { 1445 printf("wdc_atapi_start: can't send atapi packet command\n"); 1446 sc_xfer->error = XS_DRIVER_STUFFUP; 1447 wdc_atapi_done(wdc, xfer); 1448 return; 1449 } 1450 if ((sc_xfer->sc_link->scsipi_atapi.cap & 0x0300) != ACAP_DRQ_INTR) { 1451 int i, phase; 1452 for (i=20000; i>0; --i) { 1453 phase = (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_ireason) & 1454 (WDCI_CMD | WDCI_IN)) | 1455 (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status) & WDCS_DRQ); 1456 if (phase == PHASE_CMDOUT) 1457 break; 1458 delay(10); 1459 } 1460 if (phase != PHASE_CMDOUT ) { 1461 printf("wdc_atapi_start: timeout waiting PHASE_CMDOUT"); 1462 sc_xfer->error = XS_SELTIMEOUT; 1463 wdc_atapi_done(wdc, xfer); 1464 return; 1465 } 1466 bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data, 1467 (u_int16_t *)sc_xfer->cmd, sc_xfer->cmdlen >> 1); 1468 } 1469 wdc->sc_flags |= WDCF_IRQ_WAIT; 1470 1471 #ifdef ATAPI_DEBUG2 1472 printf("wdc_atapi_start: timeout\n"); 1473 #endif 1474 timeout(wdctimeout, wdc, WAITTIME); 1475 return; 1476 } 1477 1478 1479 int 1480 wdc_atapi_get_params(ab_link, drive, id) 1481 struct scsipi_link *ab_link; 1482 u_int8_t drive; 1483 struct atapi_identify *id; 1484 { 1485 struct wdc_softc *wdc = (void*)ab_link->adapter_softc; 1486 int status, len, excess = 0; 1487 int s, error; 1488 1489 /* if a disk is already present, skip */ 1490 if ((wdc->sc_drives_mask & (1 << drive)) != 0) { 1491 #ifdef ATAPI_DEBUG_PROBE 1492 printf("wdc_atapi_get_params: drive %d present\n", drive); 1493 #endif 1494 return 0; 1495 } 1496 1497 /* 1498 * If there is only one ATAPI slave on the bus,don't probe 1499 * drive 0 (master) 1500 */ 1501 1502 if (wdc->sc_flags & WDCF_ONESLAVE && drive != 1) 1503 return 0; 1504 1505 #ifdef ATAPI_DEBUG_PROBE 1506 printf("wdc_atapi_get_params: probing drive %d\n", drive); 1507 #endif 1508 1509 /* 1510 * XXX 1511 * The locking done here, and the length of time this may keep the rest 1512 * of the system suspended, is a kluge. This should be rewritten to 1513 * set up a transfer and queue it through wdstart(), but it's called 1514 * infrequently enough that this isn't a pressing matter. 1515 */ 1516 1517 s = splbio(); 1518 1519 while ((wdc->sc_flags & WDCF_ACTIVE) != 0) { 1520 wdc->sc_flags |= WDCF_WANTED; 1521 if ((error = tsleep(wdc, PRIBIO | PCATCH, "atprm", 0)) != 0) { 1522 splx(s); 1523 return error; 1524 } 1525 } 1526 1527 wdc->sc_flags |= WDCF_ACTIVE; 1528 error = 1; 1529 (void)wdcreset(wdc, VERBOSE); 1530 if ((status = wdccommand(wdc, (struct wd_link*)(&(ab_link->scsipi_atapi)), 1531 ATAPI_SOFT_RESET, drive, 0, 0, 0, 0)) != 0) { 1532 #ifdef ATAPI_DEBUG 1533 printf("wdc_atapi_get_params: ATAPI_SOFT_RESET" 1534 "failed for drive %d: status %d error %d\n", 1535 drive, status, wdc->sc_error); 1536 #endif 1537 error = 0; 1538 goto end; 1539 } 1540 if ((status = wait_for_unbusy(wdc)) != 0) { 1541 #ifdef ATAPI_DEBUG 1542 printf("wdc_atapi_get_params: wait_for_unbusy failed " 1543 "for drive %d: status %d error %d\n", 1544 drive, status, wdc->sc_error); 1545 #endif 1546 error = 0; 1547 goto end; 1548 } 1549 1550 /* Some ATAPI devices seem a bit more time after software reset. */ 1551 delay(5000); 1552 1553 if (wdccommand(wdc, (struct wd_link*)(&(ab_link->scsipi_atapi)), 1554 ATAPI_IDENTIFY_DEVICE, drive, sizeof(struct atapi_identify), 1555 0, 0, 0) != 0 || 1556 atapi_ready(wdc) != 0) { 1557 #ifdef ATAPI_DEBUG_PROBE 1558 printf("ATAPI_IDENTIFY_DEVICE failed for drive %d\n", drive); 1559 #endif 1560 error = 0; 1561 goto end; 1562 } 1563 len = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_lo) + 256 * 1564 bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_hi); 1565 if (len != sizeof(struct atapi_identify)) { 1566 printf("Warning drive %d returned %d/%d of " 1567 "indentify device data\n", drive, len, 1568 sizeof(struct atapi_identify)); 1569 excess = len - sizeof(struct atapi_identify); 1570 if (excess < 0) 1571 excess = 0; 1572 } 1573 bus_space_read_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data, 1574 (u_int16_t *)id, sizeof(struct atapi_identify) >> 1); 1575 wdcbit_bucket(wdc, excess); 1576 wdc->sc_drives_mask |= (1 << drive); 1577 1578 end: /* Restart the queue. */ 1579 WDDEBUG_PRINT(("wdcstart from wdc_atapi_get_parms flags 0x%x\n", 1580 wdc->sc_flags)); 1581 wdc->sc_flags &= ~WDCF_ACTIVE; 1582 wdcstart(wdc); 1583 splx(s); 1584 return error; 1585 } 1586 1587 int 1588 wdc_atapi_send_command_packet(sc_xfer) 1589 struct scsipi_xfer *sc_xfer; 1590 { 1591 struct scsipi_link *sc_link = sc_xfer->sc_link; 1592 struct wdc_softc *wdc = (void*)sc_link->adapter_softc; 1593 struct wdc_xfer *xfer; 1594 int flags = sc_xfer->flags; 1595 1596 if (flags & SCSI_POLL) { /* should use the queue and wdc_atapi_start */ 1597 struct wdc_xfer xfer_s; 1598 int i, s; 1599 1600 s = splbio(); 1601 #ifdef ATAPI_DEBUG_WDC 1602 printf("wdc_atapi_send_cmd: " 1603 "flags 0x%x drive %d cmdlen %d datalen %d", 1604 sc_xfer->flags, sc_link->scsipi_atapi.drive, sc_xfer->cmdlen, 1605 sc_xfer->datalen); 1606 #endif 1607 xfer = &xfer_s; 1608 bzero(xfer, sizeof(xfer_s)); 1609 xfer->c_flags = C_INUSE|C_ATAPI|flags; 1610 xfer->d_link = (struct wd_link *)(&sc_link->scsipi_atapi); 1611 xfer->c_bp = sc_xfer->bp; 1612 xfer->atapi_cmd = sc_xfer; 1613 xfer->c_blkno = 0; 1614 xfer->databuf = sc_xfer->data; 1615 xfer->c_bcount = sc_xfer->datalen; 1616 1617 if (wait_for_unbusy (wdc) != 0) { 1618 if ((wdc->sc_status & WDCS_ERR) == 0) { 1619 printf("wdc_atapi_send_command: not ready, " 1620 "st = %02x\n", wdc->sc_status); 1621 sc_xfer->error = XS_SELTIMEOUT; 1622 } else { 1623 sc_xfer->error = XS_SENSE; 1624 sc_xfer->sense.atapi_sense = wdc->sc_error; 1625 } 1626 splx(s); 1627 return COMPLETE; 1628 } 1629 1630 /* 1631 * Limit length to what can be stuffed into the cylinder 1632 * register (16 bits). Some CD-ROMs seem to interpret '0' 1633 * as 65536, but not all devices do that and it's not 1634 * obvious from the ATAPI spec that that behaviour should 1635 * be expected. If more data is necessary, multiple data 1636 * transfer phases will be done. 1637 */ 1638 if (wdccommand(wdc, (struct wd_link*)(&sc_link->scsipi_atapi), 1639 ATAPI_PACKET_COMMAND, sc_link->scsipi_atapi.drive, 1640 sc_xfer->datalen <= 0xffff ? sc_xfer->datalen : 0xffff, 1641 0, 0, 0) != 0) { 1642 printf("can't send atapi packet command\n"); 1643 sc_xfer->error = XS_DRIVER_STUFFUP; 1644 splx(s); 1645 return COMPLETE; 1646 } 1647 1648 /* Wait for cmd i/o phase. */ 1649 for (i = 20000; i > 0; --i) { 1650 int phase; 1651 phase = (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_ireason) & 1652 (WDCI_CMD | WDCI_IN)) | 1653 (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status) & WDCS_DRQ); 1654 if (phase == PHASE_CMDOUT) 1655 break; 1656 delay(10); 1657 } 1658 #ifdef ATAPI_DEBUG_WDC 1659 printf("Wait for cmd i/o phase: i = %d\n", i); 1660 #endif 1661 1662 bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data, 1663 (u_int16_t *)sc_xfer->cmd, sc_xfer->cmdlen >> 1); 1664 1665 /* Wait for data i/o phase. */ 1666 for ( i= 20000; i > 0; --i) { 1667 int phase; 1668 phase = (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_ireason) & 1669 (WDCI_CMD | WDCI_IN)) | 1670 (bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status) & WDCS_DRQ); 1671 if (phase != PHASE_CMDOUT) 1672 break; 1673 delay(10); 1674 } 1675 1676 #ifdef ATAPI_DEBUG_WDC 1677 printf("Wait for data i/o phase: i = %d\n", i); 1678 #endif 1679 wdc->sc_flags |= WDCF_IRQ_WAIT; 1680 while ((sc_xfer->flags & ITSDONE) == 0) { 1681 wdc_atapi_intr(wdc, xfer); 1682 for (i = 2000; i > 0; --i) 1683 if ((bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status) 1684 & WDCS_DRQ) == 0) 1685 break; 1686 #ifdef ATAPI_DEBUG_WDC 1687 printf("wdc_atapi_intr: i = %d\n", i); 1688 #endif 1689 } 1690 wdc->sc_flags &= ~(WDCF_IRQ_WAIT | WDCF_SINGLE | WDCF_ERROR); 1691 wdc->sc_errors = 0; 1692 xfer->c_skip = 0; 1693 splx(s); 1694 return COMPLETE; 1695 } else { /* POLLED */ 1696 xfer = wdc_get_xfer(flags & SCSI_NOSLEEP ? IDE_NOSLEEP : 0); 1697 if (xfer == NULL) { 1698 return TRY_AGAIN_LATER; 1699 } 1700 xfer->c_flags |= C_ATAPI|sc_xfer->flags; 1701 xfer->d_link = (struct wd_link*)(&sc_link->scsipi_atapi); 1702 xfer->c_bp = sc_xfer->bp; 1703 xfer->atapi_cmd = sc_xfer; 1704 xfer->c_blkno = 0; 1705 xfer->databuf = sc_xfer->data; 1706 xfer->c_bcount = sc_xfer->datalen; 1707 wdc_exec_xfer(wdc, xfer->d_link, xfer); 1708 #ifdef ATAPI_DEBUG_WDC 1709 printf("wdc_atapi_send_command_packet: wdc_exec_xfer, flags 0x%x\n", 1710 sc_xfer->flags); 1711 #endif 1712 return (sc_xfer->flags & ITSDONE) ? COMPLETE : SUCCESSFULLY_QUEUED; 1713 } 1714 } 1715 1716 int 1717 wdc_atapi_intr(wdc, xfer) 1718 struct wdc_softc *wdc; 1719 struct wdc_xfer *xfer; 1720 { 1721 struct scsipi_xfer *sc_xfer = xfer->atapi_cmd; 1722 int len, phase, i, retries=0; 1723 int err, st, ire; 1724 1725 #ifdef ATAPI_DEBUG2 1726 printf("wdc_atapi_intr: %s\n", wdc->sc_dev.dv_xname); 1727 #endif 1728 1729 if (wait_for_unbusy(wdc) < 0) { 1730 if ((wdc->sc_status & WDCS_ERR) == 0) { 1731 printf("wdc_atapi_intr: controller busy\n"); 1732 return 0; 1733 } else { 1734 sc_xfer->error = XS_SENSE; 1735 sc_xfer->sense.atapi_sense = wdc->sc_error; 1736 } 1737 #ifdef ATAPI_DEBUG_WDC 1738 printf("wdc_atapi_intr: wdc_atapi_done(), error %d\n", 1739 sc_xfer->error); 1740 #endif 1741 wdc_atapi_done(wdc, xfer); 1742 return 0; 1743 } 1744 1745 1746 again: 1747 len = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_lo) + 1748 256 * bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_cyl_hi); 1749 1750 st = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_status); 1751 err = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1752 ire = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_ireason); 1753 1754 phase = (ire & (WDCI_CMD | WDCI_IN)) | (st & WDCS_DRQ); 1755 #ifdef ATAPI_DEBUG_WDC 1756 printf("wdc_atapi_intr: len %d st %d err %d ire %d :", 1757 len, st, err, ire); 1758 #endif 1759 switch (phase) { 1760 case PHASE_CMDOUT: 1761 /* send packet command */ 1762 #ifdef ATAPI_DEBUG_WDC 1763 printf("PHASE_CMDOUT\n"); 1764 #endif 1765 1766 #ifdef ATAPI_DEBUG_WDC 1767 { 1768 int i; 1769 char *c = (char *)sc_xfer->cmd; 1770 printf("wdc_atapi_intr: cmd "); 1771 for (i = 0; i < sc_xfer->cmdlen; i++) 1772 printf("%x ", c[i]); 1773 printf("\n"); 1774 } 1775 #endif 1776 1777 bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, wd_data, 1778 (u_int16_t *)sc_xfer->cmd, sc_xfer->cmdlen >> 1); 1779 return 1; 1780 1781 case PHASE_DATAOUT: 1782 /* write data */ 1783 #ifdef ATAPI_DEBUG_WDC 1784 printf("PHASE_DATAOUT\n"); 1785 #endif 1786 if ((sc_xfer->flags & SCSI_DATA_OUT) == 0) { 1787 printf("wdc_atapi_intr: bad data phase\n"); 1788 sc_xfer->error = XS_DRIVER_STUFFUP; 1789 return 0; 1790 } 1791 if (xfer->c_bcount < len) { 1792 printf("wdc_atapi_intr: warning: write only " 1793 "%d of %d requested bytes\n", xfer->c_bcount, len); 1794 bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, 1795 wd_data, xfer->databuf + xfer->c_skip, 1796 xfer->c_bcount >> 1); 1797 for (i = xfer->c_bcount; i < len; i += 2) 1798 bus_space_write_2(wdc->sc_iot, wdc->sc_ioh, 1799 wd_data, 0); 1800 xfer->c_skip += xfer->c_bcount; 1801 xfer->c_bcount = 0; 1802 } else { 1803 bus_space_write_multi_2(wdc->sc_iot, wdc->sc_ioh, 1804 wd_data, xfer->databuf + xfer->c_skip, len >> 1); 1805 xfer->c_skip += len; 1806 xfer->c_bcount -= len; 1807 } 1808 return 1; 1809 1810 case PHASE_DATAIN: 1811 /* Read data */ 1812 #ifdef ATAPI_DEBUG_WDC 1813 printf("PHASE_DATAIN\n"); 1814 #endif 1815 if ((sc_xfer->flags & SCSI_DATA_IN) == 0) { 1816 printf("wdc_atapi_intr: bad data phase\n"); 1817 sc_xfer->error = XS_DRIVER_STUFFUP; 1818 return 0; 1819 } 1820 if (xfer->c_bcount < len) { 1821 printf("wdc_atapi_intr: warning: reading only " 1822 "%d of %d bytes\n", xfer->c_bcount, len); 1823 bus_space_read_multi_2(wdc->sc_iot, wdc->sc_ioh, 1824 wd_data, xfer->databuf + xfer->c_skip, 1825 xfer->c_bcount >> 1); 1826 wdcbit_bucket(wdc, len - xfer->c_bcount); 1827 xfer->c_skip += xfer->c_bcount; 1828 xfer->c_bcount = 0; 1829 } else { 1830 bus_space_read_multi_2(wdc->sc_iot, wdc->sc_ioh, 1831 wd_data, xfer->databuf + xfer->c_skip, len >> 1); 1832 xfer->c_skip += len; 1833 xfer->c_bcount -=len; 1834 } 1835 return 1; 1836 1837 case PHASE_ABORTED: 1838 case PHASE_COMPLETED: 1839 #ifdef ATAPI_DEBUG_WDC 1840 printf("PHASE_COMPLETED\n"); 1841 #endif 1842 if (st & WDCS_ERR) { 1843 sc_xfer->error = XS_SENSE; 1844 sc_xfer->sense.atapi_sense = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1845 } 1846 #ifdef ATAPI_DEBUG_WDC 1847 if (xfer->c_bcount != 0) { 1848 printf("wdc_atapi_intr warning: bcount value " 1849 "is %d after io\n", xfer->c_bcount); 1850 } 1851 #endif 1852 break; 1853 1854 default: 1855 if (++retries<500) { 1856 DELAY(100); 1857 goto again; 1858 } 1859 printf("wdc_atapi_intr: unknown phase %d\n", phase); 1860 if (st & WDCS_ERR) { 1861 sc_xfer->error = XS_SENSE; 1862 sc_xfer->sense.atapi_sense = bus_space_read_1(wdc->sc_iot, wdc->sc_ioh, wd_error); 1863 } else { 1864 sc_xfer->error = XS_DRIVER_STUFFUP; 1865 } 1866 } 1867 1868 #ifdef ATAPI_DEBUG_WDC 1869 printf("wdc_atapi_intr: wdc_atapi_done() (end), error %d\n", 1870 sc_xfer->error); 1871 #endif 1872 wdc_atapi_done(wdc, xfer); 1873 return (1); 1874 } 1875 1876 1877 void 1878 wdc_atapi_done(wdc, xfer) 1879 struct wdc_softc *wdc; 1880 struct wdc_xfer *xfer; 1881 { 1882 struct scsipi_xfer *sc_xfer = xfer->atapi_cmd; 1883 int s; 1884 int need_done = xfer->c_flags & C_NEEDDONE; 1885 1886 if (wdc->sc_cap & WDC_CAPABILITY_HWLOCK) 1887 (*wdc->sc_free_hw)(wdc); 1888 1889 #ifdef ATAPI_DEBUG 1890 printf("wdc_atapi_done: flags 0x%x\n", (u_int)xfer->c_flags); 1891 #endif 1892 sc_xfer->resid = xfer->c_bcount; 1893 wdc->sc_flags &= ~WDCF_IRQ_WAIT; 1894 1895 /* remove this command from xfer queue */ 1896 wdc->sc_errors = 0; 1897 xfer->c_skip = 0; 1898 if ((xfer->c_flags & SCSI_POLL) == 0) { 1899 s = splbio(); 1900 untimeout(wdctimeout, wdc); 1901 TAILQ_REMOVE(&wdc->sc_xfer, xfer, c_xferchain); 1902 wdc->sc_flags &= ~(WDCF_SINGLE | WDCF_ERROR | WDCF_ACTIVE); 1903 wdc_free_xfer(xfer); 1904 sc_xfer->flags |= ITSDONE; 1905 if (need_done) { 1906 #ifdef ATAPI_DEBUG 1907 printf("wdc_atapi_done: scsipi_done\n"); 1908 #endif 1909 scsipi_done(sc_xfer); 1910 } 1911 #ifdef WDDEBUG 1912 printf("wdcstart from wdc_atapi_intr, flags 0x%x\n", 1913 wdc->sc_flags); 1914 #endif 1915 wdcstart(wdc); 1916 splx(s); 1917 } else { 1918 wdc->sc_flags &= ~(WDCF_SINGLE | WDCF_ERROR | WDCF_ACTIVE); 1919 sc_xfer->flags |= ITSDONE; 1920 } 1921 } 1922 1923 #endif /* NATAPIBUS > 0 */ 1924
Indexes created Wed Sep 24 14:09:57 GMT 2025