wdc.c revision 1.190
1 /* $NetBSD: wdc.c,v 1.190 2004/08/11 17:49:27 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.190 2004/08/11 17:49:27 mycroft Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct wdc_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct wdc_channel *, int, int, int); 156 157 #define DEBUG_INTR 0x01 158 #define DEBUG_XFERS 0x02 159 #define DEBUG_STATUS 0x04 160 #define DEBUG_FUNCS 0x08 161 #define DEBUG_PROBE 0x10 162 #define DEBUG_DETACH 0x20 163 #define DEBUG_DELAY 0x40 164 #ifdef WDCDEBUG 165 int wdcdebug_mask = 0; 166 int wdc_nxfer = 0; 167 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 168 #else 169 #define WDCDEBUG_PRINT(args, level) 170 #endif 171 172 /* 173 * A queue of atabus instances, used to ensure the same bus probe order 174 * for a given hardware configuration at each boot. 175 */ 176 struct atabus_initq_head atabus_initq_head = 177 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 178 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 179 180 /* 181 * Initialize the "shadow register" handles for a standard wdc controller. 182 */ 183 void 184 wdc_init_shadow_regs(struct wdc_channel *chp) 185 { 186 187 chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command]; 188 chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error]; 189 } 190 191 /* Test to see controller with at last one attached drive is there. 192 * Returns a bit for each possible drive found (0x01 for drive 0, 193 * 0x02 for drive 1). 194 * Logic: 195 * - If a status register is at 0xff, assume there is no drive here 196 * (ISA has pull-up resistors). Similarly if the status register has 197 * the value we last wrote to the bus (for IDE interfaces without pullups). 198 * If no drive at all -> return. 199 * - reset the controller, wait for it to complete (may take up to 31s !). 200 * If timeout -> return. 201 * - test ATA/ATAPI signatures. If at last one drive found -> return. 202 * - try an ATA command on the master. 203 */ 204 205 static void 206 wdc_drvprobe(struct wdc_channel *chp) 207 { 208 struct ataparams params; 209 struct wdc_softc *wdc = chp->ch_wdc; 210 u_int8_t st0 = 0, st1 = 0; 211 int i, error; 212 213 if (wdcprobe1(chp, 0) == 0) { 214 /* No drives, abort the attach here. */ 215 return; 216 } 217 218 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 219 for (i = 0; i < mstohz(3000); i++) { 220 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 221 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 222 wdc->select(chp,0); 223 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 224 0, WDSD_IBM); 225 delay(10); /* 400ns delay */ 226 st0 = bus_space_read_1(chp->cmd_iot, 227 chp->cmd_iohs[wd_status], 0); 228 } 229 230 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 231 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 232 wdc->select(chp,1); 233 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 234 0, WDSD_IBM | 0x10); 235 delay(10); /* 400ns delay */ 236 st1 = bus_space_read_1(chp->cmd_iot, 237 chp->cmd_iohs[wd_status], 0); 238 } 239 240 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 241 == 0 || 242 (st0 & WDCS_DRDY)) && 243 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 244 == 0 || 245 (st1 & WDCS_DRDY))) 246 break; 247 tsleep(¶ms, PRIBIO, "atadrdy", 1); 248 } 249 if ((st0 & WDCS_DRDY) == 0) 250 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 251 if ((st1 & WDCS_DRDY) == 0) 252 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 253 254 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 255 wdc->sc_dev.dv_xname, 256 chp->ch_channel, st0, st1), DEBUG_PROBE); 257 258 /* Wait a bit, some devices are weird just after a reset. */ 259 delay(5000); 260 261 for (i = 0; i < 2; i++) { 262 /* XXX This should be done by other code. */ 263 chp->ch_drive[i].chnl_softc = chp; 264 chp->ch_drive[i].drive = i; 265 266 /* 267 * Init error counter so that an error withing the first xfers 268 * will trigger a downgrade 269 */ 270 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 271 272 /* If controller can't do 16bit flag the drives as 32bit */ 273 if ((wdc->cap & 274 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 275 WDC_CAPABILITY_DATA32) 276 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 277 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 278 continue; 279 280 /* Shortcut in case we've been shutdown */ 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 return; 283 284 /* issue an identify, to try to detect ghosts */ 285 error = ata_get_params(&chp->ch_drive[i], 286 AT_WAIT | AT_POLL, ¶ms); 287 if (error != CMD_OK) { 288 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 289 290 /* Shortcut in case we've been shutdown */ 291 if (chp->ch_flags & WDCF_SHUTDOWN) 292 return; 293 294 error = ata_get_params(&chp->ch_drive[i], 295 AT_WAIT | AT_POLL, ¶ms); 296 } 297 if (error == CMD_OK) { 298 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 299 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 300 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 301 } else { 302 chp->ch_drive[i].drive_flags &= 303 ~(DRIVE_ATA | DRIVE_ATAPI); 304 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 305 wdc->sc_dev.dv_xname, 306 chp->ch_channel, i, error), DEBUG_PROBE); 307 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 308 continue; 309 /* 310 * Pre-ATA drive ? 311 * Test registers writability (Error register not 312 * writable, but cyllo is), then try an ATA command. 313 */ 314 if (wdc->cap & WDC_CAPABILITY_SELECT) 315 wdc->select(chp,i); 316 bus_space_write_1(chp->cmd_iot, 317 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 318 delay(10); /* 400ns delay */ 319 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 320 0, 0x58); 321 bus_space_write_1(chp->cmd_iot, 322 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 323 if (bus_space_read_1(chp->cmd_iot, 324 chp->cmd_iohs[wd_error], 0) == 0x58 || 325 bus_space_read_1(chp->cmd_iot, 326 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 327 WDCDEBUG_PRINT(("%s:%d:%d: register " 328 "writability failed\n", 329 wdc->sc_dev.dv_xname, 330 chp->ch_channel, i), DEBUG_PROBE); 331 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 332 continue; 333 } 334 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 335 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 336 wdc->sc_dev.dv_xname, 337 chp->ch_channel, i), DEBUG_PROBE); 338 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 339 continue; 340 } 341 bus_space_write_1(chp->cmd_iot, 342 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 343 delay(10); /* 400ns delay */ 344 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 345 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 346 wdc->sc_dev.dv_xname, 347 chp->ch_channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 } else { 350 chp->ch_drive[0].drive_flags &= 351 ~(DRIVE_ATA | DRIVE_ATAPI); 352 chp->ch_drive[1].drive_flags &= 353 ~(DRIVE_ATA | DRIVE_ATAPI); 354 } 355 } 356 } 357 } 358 359 void 360 atabusconfig(struct atabus_softc *atabus_sc) 361 { 362 struct wdc_channel *chp = atabus_sc->sc_chan; 363 struct wdc_softc *wdc = chp->ch_wdc; 364 int i; 365 struct atabus_initq *atabus_initq = NULL; 366 367 /* Probe for the drives. */ 368 (*wdc->drv_probe)(chp); 369 370 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 371 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 372 DEBUG_PROBE); 373 374 /* If no drives, abort here */ 375 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 376 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 377 goto out; 378 379 /* Shortcut in case we've been shutdown */ 380 if (chp->ch_flags & WDCF_SHUTDOWN) 381 goto out; 382 383 /* Make sure the devices probe in atabus order to avoid jitter. */ 384 simple_lock(&atabus_interlock); 385 while(1) { 386 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 387 if (atabus_initq->atabus_sc == atabus_sc) 388 break; 389 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 390 &atabus_interlock); 391 } 392 simple_unlock(&atabus_interlock); 393 394 /* 395 * Attach an ATAPI bus, if needed. 396 */ 397 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 398 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 399 #if NATAPIBUS > 0 400 wdc_atapibus_attach(atabus_sc); 401 #else 402 /* 403 * Fake the autoconfig "not configured" message 404 */ 405 aprint_normal("atapibus at %s not configured\n", 406 wdc->sc_dev.dv_xname); 407 chp->atapibus = NULL; 408 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 409 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 410 #endif 411 } 412 413 for (i = 0; i < 2; i++) { 414 struct ata_device adev; 415 if ((chp->ch_drive[i].drive_flags & 416 (DRIVE_ATA | DRIVE_OLD)) == 0) { 417 continue; 418 } 419 memset(&adev, 0, sizeof(struct ata_device)); 420 adev.adev_bustype = &wdc_ata_bustype; 421 adev.adev_channel = chp->ch_channel; 422 adev.adev_openings = 1; 423 adev.adev_drv_data = &chp->ch_drive[i]; 424 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 425 &adev, ataprint); 426 if (chp->ata_drives[i] != NULL) 427 wdc_probe_caps(&chp->ch_drive[i]); 428 else 429 chp->ch_drive[i].drive_flags &= 430 ~(DRIVE_ATA | DRIVE_OLD); 431 } 432 433 /* now that we know the drives, the controller can set its modes */ 434 if (wdc->cap & WDC_CAPABILITY_MODE) { 435 wdc->set_modes(chp); 436 wdc_print_modes(chp); 437 } 438 #if NATARAID > 0 439 if (wdc->cap & WDC_CAPABILITY_RAID) 440 for (i = 0; i < 2; i++) 441 if (chp->ata_drives[i] != NULL) 442 ata_raid_check_component(chp->ata_drives[i]); 443 #endif /* NATARAID > 0 */ 444 445 /* 446 * reset drive_flags for unattached devices, reset state for attached 447 * ones 448 */ 449 for (i = 0; i < 2; i++) { 450 if (chp->ch_drive[i].drv_softc == NULL) 451 chp->ch_drive[i].drive_flags = 0; 452 else 453 chp->ch_drive[i].state = 0; 454 } 455 456 out: 457 if (atabus_initq == NULL) { 458 simple_lock(&atabus_interlock); 459 while(1) { 460 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 461 if (atabus_initq->atabus_sc == atabus_sc) 462 break; 463 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 464 &atabus_interlock); 465 } 466 simple_unlock(&atabus_interlock); 467 } 468 simple_lock(&atabus_interlock); 469 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 470 simple_unlock(&atabus_interlock); 471 472 free(atabus_initq, M_DEVBUF); 473 wakeup(&atabus_initq_head); 474 475 config_pending_decr(); 476 477 wdc_delref(chp); 478 } 479 480 int 481 wdcprobe(struct wdc_channel *chp) 482 { 483 484 return (wdcprobe1(chp, 1)); 485 } 486 487 static int 488 wdcprobe1(struct wdc_channel *chp, int poll) 489 { 490 struct wdc_softc *wdc = chp->ch_wdc; 491 u_int8_t st0, st1, sc, sn, cl, ch; 492 u_int8_t ret_value = 0x03; 493 u_int8_t drive; 494 int s; 495 496 /* 497 * Sanity check to see if the wdc channel responds at all. 498 */ 499 500 s = splbio(); 501 if (wdc == NULL || 502 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 503 504 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 505 wdc->select(chp,0); 506 507 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 508 WDSD_IBM); 509 delay(10); /* 400ns delay */ 510 st0 = bus_space_read_1(chp->cmd_iot, 511 chp->cmd_iohs[wd_status], 0); 512 513 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 514 wdc->select(chp,1); 515 516 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 517 WDSD_IBM | 0x10); 518 delay(10); /* 400ns delay */ 519 st1 = bus_space_read_1(chp->cmd_iot, 520 chp->cmd_iohs[wd_status], 0); 521 522 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 523 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 524 chp->ch_channel, st0, st1), DEBUG_PROBE); 525 526 if (st0 == 0xff || st0 == WDSD_IBM) 527 ret_value &= ~0x01; 528 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 529 ret_value &= ~0x02; 530 /* Register writability test, drive 0. */ 531 if (ret_value & 0x01) { 532 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 533 wdc->select(chp,0); 534 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 535 0, WDSD_IBM); 536 bus_space_write_1(chp->cmd_iot, 537 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 538 cl = bus_space_read_1(chp->cmd_iot, 539 chp->cmd_iohs[wd_cyl_lo], 0); 540 if (cl != 0x02) { 541 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 542 "got 0x%x != 0x02\n", 543 wdc != NULL ? 544 wdc->sc_dev.dv_xname : "wdcprobe", 545 chp->ch_channel, cl), 546 DEBUG_PROBE); 547 ret_value &= ~0x01; 548 } 549 bus_space_write_1(chp->cmd_iot, 550 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 551 cl = bus_space_read_1(chp->cmd_iot, 552 chp->cmd_iohs[wd_cyl_lo], 0); 553 if (cl != 0x01) { 554 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 555 "got 0x%x != 0x01\n", 556 wdc != NULL ? 557 wdc->sc_dev.dv_xname : "wdcprobe", 558 chp->ch_channel, cl), 559 DEBUG_PROBE); 560 ret_value &= ~0x01; 561 } 562 bus_space_write_1(chp->cmd_iot, 563 chp->cmd_iohs[wd_sector], 0, 0x01); 564 cl = bus_space_read_1(chp->cmd_iot, 565 chp->cmd_iohs[wd_sector], 0); 566 if (cl != 0x01) { 567 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 568 "got 0x%x != 0x01\n", 569 wdc != NULL ? 570 wdc->sc_dev.dv_xname : "wdcprobe", 571 chp->ch_channel, cl), 572 DEBUG_PROBE); 573 ret_value &= ~0x01; 574 } 575 bus_space_write_1(chp->cmd_iot, 576 chp->cmd_iohs[wd_sector], 0, 0x02); 577 cl = bus_space_read_1(chp->cmd_iot, 578 chp->cmd_iohs[wd_sector], 0); 579 if (cl != 0x02) { 580 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 581 "got 0x%x != 0x02\n", 582 wdc != NULL ? 583 wdc->sc_dev.dv_xname : "wdcprobe", 584 chp->ch_channel, cl), 585 DEBUG_PROBE); 586 ret_value &= ~0x01; 587 } 588 cl = bus_space_read_1(chp->cmd_iot, 589 chp->cmd_iohs[wd_cyl_lo], 0); 590 if (cl != 0x01) { 591 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 592 "got 0x%x != 0x01\n", 593 wdc != NULL ? 594 wdc->sc_dev.dv_xname : "wdcprobe", 595 chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 } 600 /* Register writability test, drive 1. */ 601 if (ret_value & 0x02) { 602 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 603 wdc->select(chp,1); 604 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 605 0, WDSD_IBM | 0x10); 606 bus_space_write_1(chp->cmd_iot, 607 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 608 cl = bus_space_read_1(chp->cmd_iot, 609 chp->cmd_iohs[wd_cyl_lo], 0); 610 if (cl != 0x02) { 611 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 612 "got 0x%x != 0x02\n", 613 wdc != NULL ? 614 wdc->sc_dev.dv_xname : "wdcprobe", 615 chp->ch_channel, cl), 616 DEBUG_PROBE); 617 ret_value &= ~0x02; 618 } 619 bus_space_write_1(chp->cmd_iot, 620 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 621 cl = bus_space_read_1(chp->cmd_iot, 622 chp->cmd_iohs[wd_cyl_lo], 0); 623 if (cl != 0x01) { 624 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 625 "got 0x%x != 0x01\n", 626 wdc != NULL ? 627 wdc->sc_dev.dv_xname : "wdcprobe", 628 chp->ch_channel, cl), 629 DEBUG_PROBE); 630 ret_value &= ~0x02; 631 } 632 bus_space_write_1(chp->cmd_iot, 633 chp->cmd_iohs[wd_sector], 0, 0x01); 634 cl = bus_space_read_1(chp->cmd_iot, 635 chp->cmd_iohs[wd_sector], 0); 636 if (cl != 0x01) { 637 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 638 "got 0x%x != 0x01\n", 639 wdc != NULL ? 640 wdc->sc_dev.dv_xname : "wdcprobe", 641 chp->ch_channel, cl), 642 DEBUG_PROBE); 643 ret_value &= ~0x02; 644 } 645 bus_space_write_1(chp->cmd_iot, 646 chp->cmd_iohs[wd_sector], 0, 0x02); 647 cl = bus_space_read_1(chp->cmd_iot, 648 chp->cmd_iohs[wd_sector], 0); 649 if (cl != 0x02) { 650 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 651 "got 0x%x != 0x02\n", 652 wdc != NULL ? 653 wdc->sc_dev.dv_xname : "wdcprobe", 654 chp->ch_channel, cl), 655 DEBUG_PROBE); 656 ret_value &= ~0x02; 657 } 658 cl = bus_space_read_1(chp->cmd_iot, 659 chp->cmd_iohs[wd_cyl_lo], 0); 660 if (cl != 0x01) { 661 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 662 "got 0x%x != 0x01\n", 663 wdc != NULL ? 664 wdc->sc_dev.dv_xname : "wdcprobe", 665 chp->ch_channel, cl), 666 DEBUG_PROBE); 667 ret_value &= ~0x02; 668 } 669 } 670 671 if (ret_value == 0) { 672 splx(s); 673 return 0; 674 } 675 } 676 677 678 #if 0 /* XXX this break some ATA or ATAPI devices */ 679 /* 680 * reset bus. Also send an ATAPI_RESET to devices, in case there are 681 * ATAPI device out there which don't react to the bus reset 682 */ 683 if (ret_value & 0x01) { 684 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 685 wdc->select(chp,0); 686 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 687 0, WDSD_IBM); 688 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 689 ATAPI_SOFT_RESET); 690 } 691 if (ret_value & 0x02) { 692 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 693 wdc->select(chp,0); 694 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 695 0, WDSD_IBM | 0x10); 696 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 697 ATAPI_SOFT_RESET); 698 } 699 700 delay(5000); 701 #endif 702 703 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 704 wdc->select(chp,0); 705 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 706 delay(10); /* 400ns delay */ 707 /* assert SRST, wait for reset to complete */ 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 710 DELAY(1000); 711 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 712 WDCTL_IDS | WDCTL_4BIT); 713 DELAY(2000); 714 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 715 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 716 delay(10); /* 400ns delay */ 717 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 718 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 719 wdc->irqack(chp); 720 splx(s); 721 722 ret_value = __wdcwait_reset(chp, ret_value, poll); 723 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 724 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 725 ret_value), DEBUG_PROBE); 726 727 /* if reset failed, there's nothing here */ 728 if (ret_value == 0) 729 return 0; 730 731 /* 732 * Test presence of drives. First test register signatures looking 733 * for ATAPI devices. If it's not an ATAPI and reset said there may 734 * be something here assume it's ATA or OLD. Ghost will be killed 735 * later in attach routine. 736 */ 737 for (drive = 0; drive < 2; drive++) { 738 if ((ret_value & (0x01 << drive)) == 0) 739 continue; 740 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 741 wdc->select(chp,drive); 742 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 743 WDSD_IBM | (drive << 4)); 744 delay(10); /* 400ns delay */ 745 /* Save registers contents */ 746 sc = bus_space_read_1(chp->cmd_iot, 747 chp->cmd_iohs[wd_seccnt], 0); 748 sn = bus_space_read_1(chp->cmd_iot, 749 chp->cmd_iohs[wd_sector], 0); 750 cl = bus_space_read_1(chp->cmd_iot, 751 chp->cmd_iohs[wd_cyl_lo], 0); 752 ch = bus_space_read_1(chp->cmd_iot, 753 chp->cmd_iohs[wd_cyl_hi], 0); 754 755 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 756 "cl=0x%x ch=0x%x\n", 757 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 758 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 759 /* 760 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 761 * we get wrong values here, so ignore it. 762 */ 763 if (cl == 0x14 && ch == 0xeb) { 764 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 765 } else { 766 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 767 if (wdc == NULL || 768 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 769 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 770 } 771 } 772 return (ret_value); 773 } 774 775 void 776 wdcattach(struct wdc_channel *chp) 777 { 778 struct wdc_softc *wdc = chp->ch_wdc; 779 static int inited = 0; 780 781 if (chp->ch_flags & WDCF_DISABLED) 782 return; 783 784 /* initialise global data */ 785 callout_init(&chp->ch_callout); 786 if (wdc->drv_probe == NULL) 787 wdc->drv_probe = wdc_drvprobe; 788 if (inited == 0) { 789 /* Initialize the ata_xfer pool. */ 790 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 791 0, 0, "wdcspl", NULL); 792 inited++; 793 } 794 TAILQ_INIT(&chp->ch_queue->queue_xfer); 795 chp->ch_queue->queue_freeze = 0; 796 chp->ch_queue->active_xfer = NULL; 797 798 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 799 } 800 801 int 802 wdcactivate(struct device *self, enum devact act) 803 { 804 struct wdc_softc *wdc = (struct wdc_softc *)self; 805 int s, i, error = 0; 806 807 s = splbio(); 808 switch (act) { 809 case DVACT_ACTIVATE: 810 error = EOPNOTSUPP; 811 break; 812 813 case DVACT_DEACTIVATE: 814 for (i = 0; i < wdc->nchannels; i++) { 815 error = config_deactivate(wdc->channels[i]->atabus); 816 if (error) 817 break; 818 } 819 break; 820 } 821 splx(s); 822 return (error); 823 } 824 825 int 826 wdcdetach(struct device *self, int flags) 827 { 828 struct wdc_softc *wdc = (struct wdc_softc *)self; 829 struct wdc_channel *chp; 830 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 831 int i, error = 0; 832 833 for (i = 0; i < wdc->nchannels; i++) { 834 chp = wdc->channels[i]; 835 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 837 error = config_detach(chp->atabus, flags); 838 if (error) 839 break; 840 } 841 if (adapt->adapt_refcnt != 0) { 842 #ifdef DIAGNOSTIC 843 printf("wdcdetach: refcnt should be 0 here??\n"); 844 #endif 845 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 846 } 847 return (error); 848 } 849 850 /* 851 * Start I/O on a controller, for the given channel. 852 * The first xfer may be not for our channel if the channel queues 853 * are shared. 854 */ 855 void 856 wdcstart(struct wdc_channel *chp) 857 { 858 struct wdc_softc *wdc = chp->ch_wdc; 859 struct ata_xfer *xfer; 860 861 #ifdef WDC_DIAGNOSTIC 862 int spl1, spl2; 863 864 spl1 = splbio(); 865 spl2 = splbio(); 866 if (spl2 != spl1) { 867 printf("wdcstart: not at splbio()\n"); 868 panic("wdcstart"); 869 } 870 splx(spl2); 871 splx(spl1); 872 #endif /* WDC_DIAGNOSTIC */ 873 874 /* is there a xfer ? */ 875 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 876 return; 877 878 /* adjust chp, in case we have a shared queue */ 879 chp = xfer->c_chp; 880 881 if (chp->ch_queue->active_xfer != NULL) { 882 return; /* channel aleady active */ 883 } 884 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 885 return; /* queue froozen */ 886 } 887 #ifdef DIAGNOSTIC 888 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 889 panic("wdcstart: channel waiting for irq"); 890 #endif 891 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 892 if (!(*wdc->claim_hw)(chp, 0)) 893 return; 894 895 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 896 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 897 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 898 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 899 chp->ch_drive[xfer->c_drive].state = 0; 900 } 901 chp->ch_queue->active_xfer = xfer; 902 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 903 904 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 905 KASSERT(xfer->c_flags & C_POLL); 906 xfer->c_start(chp, xfer); 907 } 908 909 /* restart an interrupted I/O */ 910 void 911 wdcrestart(void *v) 912 { 913 struct wdc_channel *chp = v; 914 int s; 915 916 s = splbio(); 917 wdcstart(chp); 918 splx(s); 919 } 920 921 922 /* 923 * Interrupt routine for the controller. Acknowledge the interrupt, check for 924 * errors on the current operation, mark it done if necessary, and start the 925 * next request. Also check for a partially done transfer, and continue with 926 * the next chunk if so. 927 */ 928 int 929 wdcintr(void *arg) 930 { 931 struct wdc_channel *chp = arg; 932 struct wdc_softc *wdc = chp->ch_wdc; 933 struct ata_xfer *xfer; 934 int ret; 935 936 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 937 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 938 DEBUG_INTR); 939 return (0); 940 } 941 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 942 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 943 /* try to clear the pending interrupt anyway */ 944 (void)bus_space_read_1(chp->cmd_iot, 945 chp->cmd_iohs[wd_status], 0); 946 return (0); 947 } 948 949 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 950 xfer = chp->ch_queue->active_xfer; 951 #ifdef DIAGNOSTIC 952 if (xfer == NULL) 953 panic("wdcintr: no xfer"); 954 #endif 955 if (chp->ch_flags & WDCF_DMA_WAIT) { 956 wdc->dma_status = 957 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 958 xfer->c_drive, WDC_DMAEND_END); 959 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 960 /* IRQ not for us, not detected by DMA engine */ 961 return 0; 962 } 963 chp->ch_flags &= ~WDCF_DMA_WAIT; 964 } 965 chp->ch_flags &= ~WDCF_IRQ_WAIT; 966 ret = xfer->c_intr(chp, xfer, 1); 967 if (ret == 0) /* irq was not for us, still waiting for irq */ 968 chp->ch_flags |= WDCF_IRQ_WAIT; 969 return (ret); 970 } 971 972 /* Put all disk in RESET state */ 973 void 974 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 975 { 976 struct wdc_channel *chp = drvp->chnl_softc; 977 struct wdc_softc *wdc = chp->ch_wdc; 978 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 979 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 980 DEBUG_FUNCS); 981 982 983 wdc_reset_channel(chp, flags); 984 } 985 986 void 987 wdc_reset_channel(struct wdc_channel *chp, int flags) 988 { 989 TAILQ_HEAD(, ata_xfer) reset_xfer; 990 struct ata_xfer *xfer, *next_xfer; 991 int drive; 992 993 chp->ch_queue->queue_freeze++; 994 TAILQ_INIT(&reset_xfer); 995 996 /* if we can poll or wait it's OK, otherwise wake up the kernel 997 * thread 998 */ 999 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 1000 if (chp->ch_flags & WDCF_TH_RESET) { 1001 /* no need to schedule a reset more than one time */ 1002 return; 1003 } 1004 chp->ch_flags |= WDCF_TH_RESET; 1005 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1006 wakeup(&chp->ch_thread); 1007 return; 1008 } 1009 1010 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1011 /* 1012 * if the current command if on an ATAPI device, issue a 1013 * ATAPI_SOFT_RESET 1014 */ 1015 xfer = chp->ch_queue->active_xfer; 1016 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1017 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1018 if (flags & AT_WAIT) 1019 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1020 else 1021 delay(1000); 1022 } 1023 1024 /* reset the channel */ 1025 if (flags & AT_WAIT) 1026 (void) wdcreset(chp, RESET_SLEEP); 1027 else 1028 (void) wdcreset(chp, RESET_POLL); 1029 1030 /* 1031 * wait a bit after reset; in case the DMA engines needs some time 1032 * to recover. 1033 */ 1034 if (flags & AT_WAIT) 1035 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1036 else 1037 delay(1000); 1038 /* 1039 * look for pending xfers. If we have a shared queue, we'll also reset 1040 * the other channel if the current xfer is running on it. 1041 * Then we'll dequeue only the xfers for this channel. 1042 */ 1043 if ((flags & AT_RST_NOCMD) == 0) { 1044 /* 1045 * move all xfers queued for this channel to the reset queue, 1046 * and then process the current xfer and then the reset queue. 1047 * We have to use a temporary queue because c_kill_xfer() 1048 * may requeue commands. 1049 */ 1050 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1051 xfer != NULL; xfer = next_xfer) { 1052 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1053 if (xfer->c_chp != chp) 1054 continue; 1055 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1056 xfer, c_xferchain); 1057 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1058 } 1059 xfer = chp->ch_queue->active_xfer; 1060 if (xfer) { 1061 if (xfer->c_chp != chp) 1062 wdc_reset_channel(xfer->c_chp, flags); 1063 else { 1064 callout_stop(&chp->ch_callout); 1065 /* 1066 * If we're waiting for DMA, stop the 1067 * DMA engine 1068 */ 1069 if (chp->ch_flags & WDCF_DMA_WAIT) { 1070 (*chp->ch_wdc->dma_finish)( 1071 chp->ch_wdc->dma_arg, 1072 chp->ch_channel, 1073 xfer->c_drive, 1074 WDC_DMAEND_ABRT_QUIET); 1075 chp->ch_flags &= ~WDCF_DMA_WAIT; 1076 } 1077 chp->ch_queue->active_xfer = NULL; 1078 if ((flags & AT_RST_EMERG) == 0) 1079 xfer->c_kill_xfer( 1080 chp, xfer, KILL_RESET); 1081 } 1082 } 1083 1084 for (xfer = TAILQ_FIRST(&reset_xfer); 1085 xfer != NULL; xfer = next_xfer) { 1086 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1087 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1088 if ((flags & AT_RST_EMERG) == 0) 1089 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1090 } 1091 } 1092 for (drive = 0; drive < 2; drive++) { 1093 chp->ch_drive[drive].state = 0; 1094 } 1095 chp->ch_flags &= ~WDCF_TH_RESET; 1096 if ((flags & AT_RST_EMERG) == 0) { 1097 chp->ch_queue->queue_freeze--; 1098 wdcstart(chp); 1099 } else { 1100 /* make sure that we can use polled commands */ 1101 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1102 chp->ch_queue->queue_freeze = 0; 1103 chp->ch_queue->active_xfer = NULL; 1104 } 1105 } 1106 1107 int 1108 wdcreset(struct wdc_channel *chp, int poll) 1109 { 1110 struct wdc_softc *wdc = chp->ch_wdc; 1111 int drv_mask1, drv_mask2; 1112 int s = 0; 1113 1114 if (wdc->cap & WDC_CAPABILITY_SELECT) 1115 wdc->select(chp,0); 1116 if (poll != RESET_SLEEP) 1117 s = splbio(); 1118 /* master */ 1119 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1120 delay(10); /* 400ns delay */ 1121 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1122 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1123 delay(2000); 1124 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1125 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1126 WDCTL_4BIT | WDCTL_IDS); 1127 delay(10); /* 400ns delay */ 1128 if (poll != RESET_SLEEP) { 1129 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1130 wdc->irqack(chp); 1131 splx(s); 1132 } 1133 1134 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1135 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1136 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1137 (poll == RESET_SLEEP) ? 0 : 1); 1138 if (drv_mask2 != drv_mask1) { 1139 printf("%s channel %d: reset failed for", 1140 wdc->sc_dev.dv_xname, chp->ch_channel); 1141 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1142 printf(" drive 0"); 1143 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1144 printf(" drive 1"); 1145 printf("\n"); 1146 } 1147 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1148 return (drv_mask1 != drv_mask2) ? 1 : 0; 1149 } 1150 1151 static int 1152 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1153 { 1154 struct wdc_softc *wdc = chp->ch_wdc; 1155 int timeout, nloop; 1156 u_int8_t st0 = 0, st1 = 0; 1157 #ifdef WDCDEBUG 1158 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1159 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1160 #endif 1161 1162 if (poll) 1163 nloop = WDCNDELAY_RST; 1164 else 1165 nloop = WDC_RESET_WAIT * hz / 1000; 1166 /* wait for BSY to deassert */ 1167 for (timeout = 0; timeout < nloop; timeout++) { 1168 if ((drv_mask & 0x01) != 0) { 1169 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1170 wdc->select(chp,0); 1171 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1172 0, WDSD_IBM); /* master */ 1173 delay(10); 1174 st0 = bus_space_read_1(chp->cmd_iot, 1175 chp->cmd_iohs[wd_status], 0); 1176 #ifdef WDCDEBUG 1177 sc0 = bus_space_read_1(chp->cmd_iot, 1178 chp->cmd_iohs[wd_seccnt], 0); 1179 sn0 = bus_space_read_1(chp->cmd_iot, 1180 chp->cmd_iohs[wd_sector], 0); 1181 cl0 = bus_space_read_1(chp->cmd_iot, 1182 chp->cmd_iohs[wd_cyl_lo], 0); 1183 ch0 = bus_space_read_1(chp->cmd_iot, 1184 chp->cmd_iohs[wd_cyl_hi], 0); 1185 #endif 1186 } 1187 if ((drv_mask & 0x02) != 0) { 1188 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1189 wdc->select(chp,1); 1190 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1191 0, WDSD_IBM | 0x10); /* slave */ 1192 delay(10); 1193 st1 = bus_space_read_1(chp->cmd_iot, 1194 chp->cmd_iohs[wd_status], 0); 1195 #ifdef WDCDEBUG 1196 sc1 = bus_space_read_1(chp->cmd_iot, 1197 chp->cmd_iohs[wd_seccnt], 0); 1198 sn1 = bus_space_read_1(chp->cmd_iot, 1199 chp->cmd_iohs[wd_sector], 0); 1200 cl1 = bus_space_read_1(chp->cmd_iot, 1201 chp->cmd_iohs[wd_cyl_lo], 0); 1202 ch1 = bus_space_read_1(chp->cmd_iot, 1203 chp->cmd_iohs[wd_cyl_hi], 0); 1204 #endif 1205 } 1206 1207 if ((drv_mask & 0x01) == 0) { 1208 /* no master */ 1209 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1210 /* No master, slave is ready, it's done */ 1211 goto end; 1212 } 1213 } else if ((drv_mask & 0x02) == 0) { 1214 /* no slave */ 1215 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1216 /* No slave, master is ready, it's done */ 1217 goto end; 1218 } 1219 } else { 1220 /* Wait for both master and slave to be ready */ 1221 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1222 goto end; 1223 } 1224 } 1225 if (poll) 1226 delay(WDCDELAY); 1227 else 1228 tsleep(&nloop, PRIBIO, "atarst", 1); 1229 } 1230 /* Reset timed out. Maybe it's because drv_mask was not right */ 1231 if (st0 & WDCS_BSY) 1232 drv_mask &= ~0x01; 1233 if (st1 & WDCS_BSY) 1234 drv_mask &= ~0x02; 1235 end: 1236 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1237 "cl=0x%x ch=0x%x\n", 1238 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1239 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1240 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1241 "cl=0x%x ch=0x%x\n", 1242 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1243 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1244 1245 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1246 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1247 st0, st1), DEBUG_PROBE); 1248 1249 return drv_mask; 1250 } 1251 1252 /* 1253 * Wait for a drive to be !BSY, and have mask in its status register. 1254 * return -1 for a timeout after "timeout" ms. 1255 */ 1256 static int 1257 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1258 { 1259 struct wdc_softc *wdc = chp->ch_wdc; 1260 u_char status; 1261 int time = 0; 1262 1263 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1264 wdc->sc_dev.dv_xname : "none", 1265 chp->ch_channel), DEBUG_STATUS); 1266 chp->ch_error = 0; 1267 1268 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1269 1270 for (;;) { 1271 chp->ch_status = status = 1272 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1273 if ((status & (WDCS_BSY | mask)) == bits) 1274 break; 1275 if (++time > timeout) { 1276 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1277 "status %x error %x (mask 0x%x bits 0x%x)\n", 1278 time, status, 1279 bus_space_read_1(chp->cmd_iot, 1280 chp->cmd_iohs[wd_error], 0), mask, bits), 1281 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1282 return(WDCWAIT_TOUT); 1283 } 1284 delay(WDCDELAY); 1285 } 1286 #ifdef WDCDEBUG 1287 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1288 printf("__wdcwait: did busy-wait, time=%d\n", time); 1289 #endif 1290 if (status & WDCS_ERR) 1291 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1292 chp->cmd_iohs[wd_error], 0); 1293 #ifdef WDCNDELAY_DEBUG 1294 /* After autoconfig, there should be no long delays. */ 1295 if (!cold && time > WDCNDELAY_DEBUG) { 1296 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1297 if (xfer == NULL) 1298 printf("%s channel %d: warning: busy-wait took %dus\n", 1299 wdc->sc_dev.dv_xname, chp->ch_channel, 1300 WDCDELAY * time); 1301 else 1302 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1303 wdc->sc_dev.dv_xname, chp->ch_channel, 1304 xfer->drive, 1305 WDCDELAY * time); 1306 } 1307 #endif 1308 return(WDCWAIT_OK); 1309 } 1310 1311 /* 1312 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1313 * thread if possible 1314 */ 1315 int 1316 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1317 { 1318 int error, i, timeout_hz = mstohz(timeout); 1319 1320 if (timeout_hz == 0 || 1321 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1322 error = __wdcwait(chp, mask, bits, timeout); 1323 else { 1324 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1325 if (error != 0) { 1326 if ((chp->ch_flags & WDCF_TH_RUN) || 1327 (flags & AT_WAIT)) { 1328 /* 1329 * we're running in the channel thread 1330 * or some userland thread context 1331 */ 1332 for (i = 0; i < timeout_hz; i++) { 1333 if (__wdcwait(chp, mask, bits, 1334 WDCDELAY_POLL) == 0) { 1335 error = 0; 1336 break; 1337 } 1338 tsleep(&chp, PRIBIO, "atapoll", 1); 1339 } 1340 } else { 1341 /* 1342 * we're probably in interrupt context, 1343 * ask the thread to come back here 1344 */ 1345 #ifdef DIAGNOSTIC 1346 if (chp->ch_queue->queue_freeze > 0) 1347 panic("wdcwait: queue_freeze"); 1348 #endif 1349 chp->ch_queue->queue_freeze++; 1350 wakeup(&chp->ch_thread); 1351 return(WDCWAIT_THR); 1352 } 1353 } 1354 } 1355 return (error); 1356 } 1357 1358 1359 /* 1360 * Busy-wait for DMA to complete 1361 */ 1362 int 1363 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1364 { 1365 struct wdc_softc *wdc = chp->ch_wdc; 1366 int time; 1367 1368 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1369 wdc->dma_status = 1370 (*wdc->dma_finish)(wdc->dma_arg, 1371 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1372 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1373 return 0; 1374 delay(WDCDELAY); 1375 } 1376 /* timeout, force a DMA halt */ 1377 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1378 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1379 return 1; 1380 } 1381 1382 void 1383 wdctimeout(void *arg) 1384 { 1385 struct wdc_channel *chp = (struct wdc_channel *)arg; 1386 struct wdc_softc *wdc = chp->ch_wdc; 1387 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1388 int s; 1389 1390 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1391 1392 s = splbio(); 1393 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1394 __wdcerror(chp, "lost interrupt"); 1395 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1396 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1397 xfer->c_bcount, 1398 xfer->c_skip); 1399 if (chp->ch_flags & WDCF_DMA_WAIT) { 1400 wdc->dma_status = 1401 (*wdc->dma_finish)(wdc->dma_arg, 1402 chp->ch_channel, xfer->c_drive, 1403 WDC_DMAEND_ABRT); 1404 chp->ch_flags &= ~WDCF_DMA_WAIT; 1405 } 1406 /* 1407 * Call the interrupt routine. If we just missed an interrupt, 1408 * it will do what's needed. Else, it will take the needed 1409 * action (reset the device). 1410 * Before that we need to reinstall the timeout callback, 1411 * in case it will miss another irq while in this transfer 1412 * We arbitray chose it to be 1s 1413 */ 1414 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1415 xfer->c_flags |= C_TIMEOU; 1416 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1417 xfer->c_intr(chp, xfer, 1); 1418 } else 1419 __wdcerror(chp, "missing untimeout"); 1420 splx(s); 1421 } 1422 1423 /* 1424 * Probe drive's capabilities, for use by the controller later 1425 * Assumes drvp points to an existing drive. 1426 * XXX this should be a controller-indep function 1427 */ 1428 void 1429 wdc_probe_caps(struct ata_drive_datas *drvp) 1430 { 1431 struct ataparams params, params2; 1432 struct wdc_channel *chp = drvp->chnl_softc; 1433 struct wdc_softc *wdc = chp->ch_wdc; 1434 struct device *drv_dev = drvp->drv_softc; 1435 int i, printed; 1436 char *sep = ""; 1437 int cf_flags; 1438 1439 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1440 /* IDENTIFY failed. Can't tell more about the device */ 1441 return; 1442 } 1443 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1444 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1445 /* 1446 * Controller claims 16 and 32 bit transfers. 1447 * Re-do an IDENTIFY with 32-bit transfers, 1448 * and compare results. 1449 */ 1450 drvp->drive_flags |= DRIVE_CAP32; 1451 ata_get_params(drvp, AT_WAIT, ¶ms2); 1452 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1453 /* Not good. fall back to 16bits */ 1454 drvp->drive_flags &= ~DRIVE_CAP32; 1455 } else { 1456 aprint_normal("%s: 32-bit data port\n", 1457 drv_dev->dv_xname); 1458 } 1459 } 1460 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1461 if (params.atap_ata_major > 0x01 && 1462 params.atap_ata_major != 0xffff) { 1463 for (i = 14; i > 0; i--) { 1464 if (params.atap_ata_major & (1 << i)) { 1465 aprint_normal("%s: ATA version %d\n", 1466 drv_dev->dv_xname, i); 1467 drvp->ata_vers = i; 1468 break; 1469 } 1470 } 1471 } 1472 #endif 1473 1474 /* An ATAPI device is at last PIO mode 3 */ 1475 if (drvp->drive_flags & DRIVE_ATAPI) 1476 drvp->PIO_mode = 3; 1477 1478 /* 1479 * It's not in the specs, but it seems that some drive 1480 * returns 0xffff in atap_extensions when this field is invalid 1481 */ 1482 if (params.atap_extensions != 0xffff && 1483 (params.atap_extensions & WDC_EXT_MODES)) { 1484 printed = 0; 1485 /* 1486 * XXX some drives report something wrong here (they claim to 1487 * support PIO mode 8 !). As mode is coded on 3 bits in 1488 * SET FEATURE, limit it to 7 (so limit i to 4). 1489 * If higher mode than 7 is found, abort. 1490 */ 1491 for (i = 7; i >= 0; i--) { 1492 if ((params.atap_piomode_supp & (1 << i)) == 0) 1493 continue; 1494 if (i > 4) 1495 return; 1496 /* 1497 * See if mode is accepted. 1498 * If the controller can't set its PIO mode, 1499 * assume the defaults are good, so don't try 1500 * to set it 1501 */ 1502 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1503 /* 1504 * It's OK to pool here, it's fast enouth 1505 * to not bother waiting for interrupt 1506 */ 1507 if (ata_set_mode(drvp, 0x08 | (i + 3), 1508 AT_WAIT) != CMD_OK) 1509 continue; 1510 if (!printed) { 1511 aprint_normal("%s: drive supports PIO mode %d", 1512 drv_dev->dv_xname, i + 3); 1513 sep = ","; 1514 printed = 1; 1515 } 1516 /* 1517 * If controller's driver can't set its PIO mode, 1518 * get the highter one for the drive. 1519 */ 1520 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1521 wdc->PIO_cap >= i + 3) { 1522 drvp->PIO_mode = i + 3; 1523 drvp->PIO_cap = i + 3; 1524 break; 1525 } 1526 } 1527 if (!printed) { 1528 /* 1529 * We didn't find a valid PIO mode. 1530 * Assume the values returned for DMA are buggy too 1531 */ 1532 return; 1533 } 1534 drvp->drive_flags |= DRIVE_MODE; 1535 printed = 0; 1536 for (i = 7; i >= 0; i--) { 1537 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1538 continue; 1539 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1540 (wdc->cap & WDC_CAPABILITY_MODE)) 1541 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1542 != CMD_OK) 1543 continue; 1544 if (!printed) { 1545 aprint_normal("%s DMA mode %d", sep, i); 1546 sep = ","; 1547 printed = 1; 1548 } 1549 if (wdc->cap & WDC_CAPABILITY_DMA) { 1550 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1551 wdc->DMA_cap < i) 1552 continue; 1553 drvp->DMA_mode = i; 1554 drvp->DMA_cap = i; 1555 drvp->drive_flags |= DRIVE_DMA; 1556 } 1557 break; 1558 } 1559 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1560 printed = 0; 1561 for (i = 7; i >= 0; i--) { 1562 if ((params.atap_udmamode_supp & (1 << i)) 1563 == 0) 1564 continue; 1565 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1566 (wdc->cap & WDC_CAPABILITY_UDMA)) 1567 if (ata_set_mode(drvp, 0x40 | i, 1568 AT_WAIT) != CMD_OK) 1569 continue; 1570 if (!printed) { 1571 aprint_normal("%s Ultra-DMA mode %d", 1572 sep, i); 1573 if (i == 2) 1574 aprint_normal(" (Ultra/33)"); 1575 else if (i == 4) 1576 aprint_normal(" (Ultra/66)"); 1577 else if (i == 5) 1578 aprint_normal(" (Ultra/100)"); 1579 else if (i == 6) 1580 aprint_normal(" (Ultra/133)"); 1581 sep = ","; 1582 printed = 1; 1583 } 1584 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1585 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1586 wdc->UDMA_cap < i) 1587 continue; 1588 drvp->UDMA_mode = i; 1589 drvp->UDMA_cap = i; 1590 drvp->drive_flags |= DRIVE_UDMA; 1591 } 1592 break; 1593 } 1594 } 1595 aprint_normal("\n"); 1596 } 1597 1598 drvp->drive_flags &= ~DRIVE_NOSTREAM; 1599 if (drvp->drive_flags & DRIVE_ATAPI) { 1600 if (wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM) 1601 drvp->drive_flags |= DRIVE_NOSTREAM; 1602 } else { 1603 if (wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM) 1604 drvp->drive_flags |= DRIVE_NOSTREAM; 1605 } 1606 1607 /* Try to guess ATA version here, if it didn't get reported */ 1608 if (drvp->ata_vers == 0) { 1609 if (drvp->drive_flags & DRIVE_UDMA) 1610 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1611 else if (drvp->PIO_cap > 2) 1612 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1613 } 1614 cf_flags = drv_dev->dv_cfdata->cf_flags; 1615 if (cf_flags & ATA_CONFIG_PIO_SET) { 1616 drvp->PIO_mode = 1617 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1618 drvp->drive_flags |= DRIVE_MODE; 1619 } 1620 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1621 /* don't care about DMA modes */ 1622 return; 1623 } 1624 if (cf_flags & ATA_CONFIG_DMA_SET) { 1625 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1626 ATA_CONFIG_DMA_DISABLE) { 1627 drvp->drive_flags &= ~DRIVE_DMA; 1628 } else { 1629 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1630 ATA_CONFIG_DMA_OFF; 1631 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1632 } 1633 } 1634 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1635 /* don't care about UDMA modes */ 1636 return; 1637 } 1638 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1639 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1640 ATA_CONFIG_UDMA_DISABLE) { 1641 drvp->drive_flags &= ~DRIVE_UDMA; 1642 } else { 1643 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1644 ATA_CONFIG_UDMA_OFF; 1645 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1646 } 1647 } 1648 } 1649 1650 /* 1651 * downgrade the transfer mode of a drive after an error. return 1 if 1652 * downgrade was possible, 0 otherwise. 1653 */ 1654 int 1655 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1656 { 1657 struct wdc_channel *chp = drvp->chnl_softc; 1658 struct wdc_softc *wdc = chp->ch_wdc; 1659 struct device *drv_dev = drvp->drv_softc; 1660 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1661 1662 /* if drive or controller don't know its mode, we can't do much */ 1663 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1664 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1665 return 0; 1666 /* current drive mode was set by a config flag, let it this way */ 1667 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1668 (cf_flags & ATA_CONFIG_DMA_SET) || 1669 (cf_flags & ATA_CONFIG_UDMA_SET)) 1670 return 0; 1671 1672 /* 1673 * If we were using Ultra-DMA mode, downgrade to the next lower mode. 1674 */ 1675 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1676 drvp->UDMA_mode--; 1677 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1678 drv_dev->dv_xname, drvp->UDMA_mode); 1679 } 1680 1681 /* 1682 * If we were using ultra-DMA, don't downgrade to multiword DMA. 1683 */ 1684 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1685 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1686 drvp->PIO_mode = drvp->PIO_cap; 1687 printf("%s: transfer error, downgrading to PIO mode %d\n", 1688 drv_dev->dv_xname, drvp->PIO_mode); 1689 } else /* already using PIO, can't downgrade */ 1690 return 0; 1691 1692 wdc->set_modes(chp); 1693 wdc_print_modes(chp); 1694 /* reset the channel, which will shedule all drives for setup */ 1695 wdc_reset_channel(chp, flags | AT_RST_NOCMD); 1696 return 1; 1697 } 1698 1699 int 1700 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1701 { 1702 struct wdc_channel *chp = drvp->chnl_softc; 1703 struct wdc_softc *wdc = chp->ch_wdc; 1704 struct ata_xfer *xfer; 1705 int s, ret; 1706 1707 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1708 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1709 DEBUG_FUNCS); 1710 1711 /* set up an xfer and queue. Wait for completion */ 1712 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1713 WDC_NOSLEEP); 1714 if (xfer == NULL) { 1715 return WDC_TRY_AGAIN; 1716 } 1717 1718 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1719 wdc_c->flags |= AT_POLL; 1720 if (wdc_c->flags & AT_POLL) 1721 xfer->c_flags |= C_POLL; 1722 xfer->c_drive = drvp->drive; 1723 xfer->c_databuf = wdc_c->data; 1724 xfer->c_bcount = wdc_c->bcount; 1725 xfer->c_cmd = wdc_c; 1726 xfer->c_start = __wdccommand_start; 1727 xfer->c_intr = __wdccommand_intr; 1728 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1729 1730 s = splbio(); 1731 wdc_exec_xfer(chp, xfer); 1732 #ifdef DIAGNOSTIC 1733 if ((wdc_c->flags & AT_POLL) != 0 && 1734 (wdc_c->flags & AT_DONE) == 0) 1735 panic("wdc_exec_command: polled command not done"); 1736 #endif 1737 if (wdc_c->flags & AT_DONE) { 1738 ret = WDC_COMPLETE; 1739 } else { 1740 if (wdc_c->flags & AT_WAIT) { 1741 while ((wdc_c->flags & AT_DONE) == 0) { 1742 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1743 } 1744 ret = WDC_COMPLETE; 1745 } else { 1746 ret = WDC_QUEUED; 1747 } 1748 } 1749 splx(s); 1750 return ret; 1751 } 1752 1753 static void 1754 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1755 { 1756 struct wdc_softc *wdc = chp->ch_wdc; 1757 int drive = xfer->c_drive; 1758 struct wdc_command *wdc_c = xfer->c_cmd; 1759 1760 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1761 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1762 DEBUG_FUNCS); 1763 1764 if (wdc->cap & WDC_CAPABILITY_SELECT) 1765 wdc->select(chp,drive); 1766 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1767 WDSD_IBM | (drive << 4)); 1768 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1769 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1770 case WDCWAIT_OK: 1771 break; 1772 case WDCWAIT_TOUT: 1773 wdc_c->flags |= AT_TIMEOU; 1774 __wdccommand_done(chp, xfer); 1775 return; 1776 case WDCWAIT_THR: 1777 return; 1778 } 1779 if (wdc_c->flags & AT_POLL) { 1780 /* polled command, disable interrupts */ 1781 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1782 WDCTL_4BIT | WDCTL_IDS); 1783 } 1784 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1785 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features); 1786 1787 if ((wdc_c->flags & AT_POLL) == 0) { 1788 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1789 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1790 wdctimeout, chp); 1791 return; 1792 } 1793 /* 1794 * Polled command. Wait for drive ready or drq. Done in intr(). 1795 * Wait for at last 400ns for status bit to be valid. 1796 */ 1797 delay(10); /* 400ns delay */ 1798 __wdccommand_intr(chp, xfer, 0); 1799 } 1800 1801 static int 1802 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1803 { 1804 struct wdc_softc *wdc = chp->ch_wdc; 1805 struct wdc_command *wdc_c = xfer->c_cmd; 1806 int bcount = wdc_c->bcount; 1807 char *data = wdc_c->data; 1808 int wflags; 1809 1810 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1811 /* both wait and poll, we can tsleep here */ 1812 wflags = AT_WAIT | AT_POLL; 1813 } else { 1814 wflags = AT_POLL; 1815 } 1816 1817 again: 1818 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1819 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1820 DEBUG_INTR); 1821 /* 1822 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1823 * Reselect again, it doesn't hurt for others commands, and the time 1824 * penalty for the extra regiter write is acceptable, 1825 * wdc_exec_command() isn't called often (mosly for autoconfig) 1826 */ 1827 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1828 WDSD_IBM | (xfer->c_drive << 4)); 1829 if ((wdc_c->flags & AT_XFDONE) != 0) { 1830 /* 1831 * We have completed a data xfer. The drive should now be 1832 * in its initial state 1833 */ 1834 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1835 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1836 wflags) == WDCWAIT_TOUT) { 1837 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1838 return 0; /* IRQ was not for us */ 1839 wdc_c->flags |= AT_TIMEOU; 1840 } 1841 goto out; 1842 } 1843 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1844 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1845 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1846 return 0; /* IRQ was not for us */ 1847 wdc_c->flags |= AT_TIMEOU; 1848 goto out; 1849 } 1850 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1851 wdc->irqack(chp); 1852 if (wdc_c->flags & AT_READ) { 1853 if ((chp->ch_status & WDCS_DRQ) == 0) { 1854 wdc_c->flags |= AT_TIMEOU; 1855 goto out; 1856 } 1857 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1858 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1859 0, (u_int32_t*)data, bcount >> 2); 1860 data += bcount & 0xfffffffc; 1861 bcount = bcount & 0x03; 1862 } 1863 if (bcount > 0) 1864 wdc_datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1865 /* at this point the drive should be in its initial state */ 1866 wdc_c->flags |= AT_XFDONE; 1867 /* XXX should read status register here ? */ 1868 } else if (wdc_c->flags & AT_WRITE) { 1869 if ((chp->ch_status & WDCS_DRQ) == 0) { 1870 wdc_c->flags |= AT_TIMEOU; 1871 goto out; 1872 } 1873 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1874 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1875 0, (u_int32_t*)data, bcount >> 2); 1876 data += bcount & 0xfffffffc; 1877 bcount = bcount & 0x03; 1878 } 1879 if (bcount > 0) 1880 wdc_dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1881 wdc_c->flags |= AT_XFDONE; 1882 if ((wdc_c->flags & AT_POLL) == 0) { 1883 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1884 callout_reset(&chp->ch_callout, 1885 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1886 return 1; 1887 } else { 1888 goto again; 1889 } 1890 } 1891 out: 1892 __wdccommand_done(chp, xfer); 1893 return 1; 1894 } 1895 1896 static void 1897 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1898 { 1899 struct wdc_softc *wdc = chp->ch_wdc; 1900 struct wdc_command *wdc_c = xfer->c_cmd; 1901 1902 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1903 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1904 DEBUG_FUNCS); 1905 1906 1907 if (chp->ch_status & WDCS_DWF) 1908 wdc_c->flags |= AT_DF; 1909 if (chp->ch_status & WDCS_ERR) { 1910 wdc_c->flags |= AT_ERROR; 1911 wdc_c->r_error = chp->ch_error; 1912 } 1913 if ((wdc_c->flags & AT_READREG) != 0 && 1914 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1915 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1916 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1917 chp->cmd_iohs[wd_sdh], 0); 1918 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1919 chp->cmd_iohs[wd_seccnt], 0); 1920 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1921 chp->cmd_iohs[wd_sector], 0); 1922 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1923 chp->cmd_iohs[wd_cyl_lo], 0); 1924 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1925 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1926 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1927 chp->cmd_iohs[wd_error], 0); 1928 wdc_c->r_features = bus_space_read_1(chp->cmd_iot, 1929 chp->cmd_iohs[wd_features], 0); 1930 } 1931 callout_stop(&chp->ch_callout); 1932 chp->ch_queue->active_xfer = NULL; 1933 if (wdc_c->flags & AT_POLL) { 1934 /* enable interrupts */ 1935 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1936 WDCTL_4BIT); 1937 delay(10); /* some drives need a little delay here */ 1938 } 1939 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1940 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1941 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1942 wakeup(&chp->ch_queue->active_xfer); 1943 } else 1944 __wdccommand_done_end(chp, xfer); 1945 } 1946 1947 static void 1948 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1949 { 1950 struct wdc_command *wdc_c = xfer->c_cmd; 1951 1952 wdc_c->flags |= AT_DONE; 1953 wdc_free_xfer(chp, xfer); 1954 if (wdc_c->flags & AT_WAIT) 1955 wakeup(wdc_c); 1956 else if (wdc_c->callback) 1957 wdc_c->callback(wdc_c->callback_arg); 1958 wdcstart(chp); 1959 return; 1960 } 1961 1962 static void 1963 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1964 int reason) 1965 { 1966 struct wdc_command *wdc_c = xfer->c_cmd; 1967 1968 switch (reason) { 1969 case KILL_GONE: 1970 wdc_c->flags |= AT_GONE; 1971 break; 1972 case KILL_RESET: 1973 wdc_c->flags |= AT_RESET; 1974 break; 1975 default: 1976 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1977 reason); 1978 panic("__wdccommand_kill_xfer"); 1979 } 1980 __wdccommand_done_end(chp, xfer); 1981 } 1982 1983 /* 1984 * Send a command. The drive should be ready. 1985 * Assumes interrupts are blocked. 1986 */ 1987 void 1988 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1989 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1990 u_int8_t features) 1991 { 1992 struct wdc_softc *wdc = chp->ch_wdc; 1993 1994 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1995 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1996 chp->ch_channel, drive, command, cylin, head, sector, count, 1997 features), DEBUG_FUNCS); 1998 1999 if (wdc->cap & WDC_CAPABILITY_SELECT) 2000 wdc->select(chp,drive); 2001 2002 /* Select drive, head, and addressing mode. */ 2003 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2004 WDSD_IBM | (drive << 4) | head); 2005 /* Load parameters into the wd_features register. */ 2006 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 2007 features); 2008 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2009 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 2010 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 2011 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 2012 0, cylin >> 8); 2013 2014 /* Send command. */ 2015 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2016 return; 2017 } 2018 2019 /* 2020 * Send a 48-bit addressing command. The drive should be ready. 2021 * Assumes interrupts are blocked. 2022 */ 2023 void 2024 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 2025 u_int64_t blkno, u_int16_t count) 2026 { 2027 struct wdc_softc *wdc = chp->ch_wdc; 2028 2029 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 2030 "count=%d\n", wdc->sc_dev.dv_xname, 2031 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 2032 DEBUG_FUNCS); 2033 2034 if (wdc->cap & WDC_CAPABILITY_SELECT) 2035 wdc->select(chp,drive); 2036 2037 /* Select drive, head, and addressing mode. */ 2038 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2039 (drive << 4) | WDSD_LBA); 2040 2041 /* previous */ 2042 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2043 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 2044 0, count >> 8); 2045 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 2046 0, blkno >> 24); 2047 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2048 0, blkno >> 32); 2049 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2050 0, blkno >> 40); 2051 2052 /* current */ 2053 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 2054 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 2055 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 2056 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 2057 0, blkno >> 8); 2058 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 2059 0, blkno >> 16); 2060 2061 /* Send command. */ 2062 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2063 return; 2064 } 2065 2066 /* 2067 * Simplified version of wdccommand(). Unbusy/ready/drq must be 2068 * tested by the caller. 2069 */ 2070 void 2071 wdccommandshort(struct wdc_channel *chp, int drive, int command) 2072 { 2073 struct wdc_softc *wdc = chp->ch_wdc; 2074 2075 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 2076 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 2077 DEBUG_FUNCS); 2078 2079 if (wdc->cap & WDC_CAPABILITY_SELECT) 2080 wdc->select(chp,drive); 2081 2082 /* Select drive. */ 2083 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 2084 WDSD_IBM | (drive << 4)); 2085 2086 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2087 } 2088 2089 /* Add a command to the queue and start controller. Must be called at splbio */ 2090 void 2091 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2092 { 2093 2094 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2095 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 2096 2097 /* complete xfer setup */ 2098 xfer->c_chp = chp; 2099 2100 /* insert at the end of command list */ 2101 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2102 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2103 chp->ch_flags), DEBUG_XFERS); 2104 wdcstart(chp); 2105 } 2106 2107 struct ata_xfer * 2108 wdc_get_xfer(int flags) 2109 { 2110 struct ata_xfer *xfer; 2111 int s; 2112 2113 s = splbio(); 2114 xfer = pool_get(&wdc_xfer_pool, 2115 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2116 splx(s); 2117 if (xfer != NULL) { 2118 memset(xfer, 0, sizeof(struct ata_xfer)); 2119 } 2120 return xfer; 2121 } 2122 2123 void 2124 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2125 { 2126 struct wdc_softc *wdc = chp->ch_wdc; 2127 int s; 2128 2129 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2130 (*wdc->free_hw)(chp); 2131 s = splbio(); 2132 pool_put(&wdc_xfer_pool, xfer); 2133 splx(s); 2134 } 2135 2136 /* 2137 * Kill off all pending xfers for a wdc_channel. 2138 * 2139 * Must be called at splbio(). 2140 */ 2141 void 2142 wdc_kill_pending(struct ata_drive_datas *drvp) 2143 { 2144 struct wdc_channel *chp = drvp->chnl_softc; 2145 struct ata_xfer *xfer, *next_xfer; 2146 int s = splbio(); 2147 2148 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2149 xfer != NULL; xfer = next_xfer) { 2150 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 2151 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive) 2152 continue; 2153 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2154 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 2155 } 2156 2157 while ((xfer = chp->ch_queue->active_xfer) != NULL) { 2158 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) { 2159 drvp->drive_flags |= DRIVE_WAITDRAIN; 2160 (void) tsleep(&chp->ch_queue->active_xfer, 2161 PRIBIO, "atdrn", 0); 2162 } else { 2163 /* no more xfer for us */ 2164 break; 2165 } 2166 } 2167 splx(s); 2168 } 2169 2170 static void 2171 __wdcerror(struct wdc_channel *chp, char *msg) 2172 { 2173 struct wdc_softc *wdc = chp->ch_wdc; 2174 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2175 2176 if (xfer == NULL) 2177 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2178 msg); 2179 else 2180 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2181 chp->ch_channel, xfer->c_drive, msg); 2182 } 2183 2184 /* 2185 * the bit bucket 2186 */ 2187 void 2188 wdcbit_bucket(struct wdc_channel *chp, int size) 2189 { 2190 2191 for (; size >= 2; size -= 2) 2192 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2193 if (size) 2194 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2195 } 2196 2197 int 2198 wdc_addref(struct wdc_channel *chp) 2199 { 2200 struct wdc_softc *wdc = chp->ch_wdc; 2201 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2202 int s, error = 0; 2203 2204 s = splbio(); 2205 if (adapt->adapt_refcnt++ == 0 && 2206 adapt->adapt_enable != NULL) { 2207 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2208 if (error) 2209 adapt->adapt_refcnt--; 2210 } 2211 splx(s); 2212 return (error); 2213 } 2214 2215 void 2216 wdc_delref(struct wdc_channel *chp) 2217 { 2218 struct wdc_softc *wdc = chp->ch_wdc; 2219 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2220 int s; 2221 2222 s = splbio(); 2223 if (adapt->adapt_refcnt-- == 1 && 2224 adapt->adapt_enable != NULL) 2225 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2226 splx(s); 2227 } 2228 2229 void 2230 wdc_print_modes(struct wdc_channel *chp) 2231 { 2232 struct wdc_softc *wdc = chp->ch_wdc; 2233 int drive; 2234 struct ata_drive_datas *drvp; 2235 2236 for (drive = 0; drive < 2; drive++) { 2237 drvp = &chp->ch_drive[drive]; 2238 if ((drvp->drive_flags & DRIVE) == 0) 2239 continue; 2240 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2241 drvp->drv_softc->dv_xname, 2242 wdc->sc_dev.dv_xname, 2243 chp->ch_channel, drive, drvp->PIO_mode); 2244 if (drvp->drive_flags & DRIVE_DMA) 2245 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2246 if (drvp->drive_flags & DRIVE_UDMA) { 2247 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2248 if (drvp->UDMA_mode == 2) 2249 aprint_normal(" (Ultra/33)"); 2250 else if (drvp->UDMA_mode == 4) 2251 aprint_normal(" (Ultra/66)"); 2252 else if (drvp->UDMA_mode == 5) 2253 aprint_normal(" (Ultra/100)"); 2254 else if (drvp->UDMA_mode == 6) 2255 aprint_normal(" (Ultra/133)"); 2256 } 2257 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2258 aprint_normal(" (using DMA data transfers)"); 2259 aprint_normal("\n"); 2260 } 2261 } 2262 2263 void 2264 wdc_datain_pio(chp, flags, buf, len) 2265 struct wdc_channel *chp; 2266 int flags; 2267 void *buf; 2268 size_t len; 2269 { 2270 2271 if (flags & DRIVE_NOSTREAM) { 2272 if (flags & DRIVE_CAP32) { 2273 bus_space_read_multi_4(chp->data32iot, 2274 chp->data32ioh, 0, buf, len >> 2); 2275 buf = (char *)buf + (len & ~3); 2276 len &= 3; 2277 } 2278 if (len) { 2279 bus_space_read_multi_2(chp->cmd_iot, 2280 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 2281 } 2282 } else { 2283 if (flags & DRIVE_CAP32) { 2284 bus_space_read_multi_stream_4(chp->data32iot, 2285 chp->data32ioh, 0, buf, len >> 2); 2286 buf = (char *)buf + (len & ~3); 2287 len &= 3; 2288 } 2289 if (len) { 2290 bus_space_read_multi_stream_2(chp->cmd_iot, 2291 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 2292 } 2293 } 2294 } 2295 2296 void 2297 wdc_dataout_pio(chp, flags, buf, len) 2298 struct wdc_channel *chp; 2299 int flags; 2300 void *buf; 2301 size_t len; 2302 { 2303 2304 if (flags & DRIVE_NOSTREAM) { 2305 if (flags & DRIVE_CAP32) { 2306 bus_space_write_multi_4(chp->data32iot, 2307 chp->data32ioh, 0, buf, len >> 2); 2308 buf = (char *)buf + (len & ~3); 2309 len &= 3; 2310 } 2311 if (len) { 2312 bus_space_write_multi_2(chp->cmd_iot, 2313 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 2314 } 2315 } else { 2316 if (flags & DRIVE_CAP32) { 2317 bus_space_write_multi_stream_4(chp->data32iot, 2318 chp->data32ioh, 0, buf, len >> 2); 2319 buf = (char *)buf + (len & ~3); 2320 len &= 3; 2321 } 2322 if (len) { 2323 bus_space_write_multi_stream_2(chp->cmd_iot, 2324 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 2325 } 2326 } 2327 } 2328
Indexes created Wed Sep 24 05:09:52 GMT 2025