wdc.c revision 1.201
1 /* $NetBSD: wdc.c,v 1.201 2004/08/13 02:10:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.201 2004/08/13 02:10:43 thorpej Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 #if NWD > 0 128 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 129 #else 130 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 131 const struct ata_bustype wdc_ata_bustype = { 132 SCSIPI_BUSTYPE_ATA, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 NULL 140 }; 141 #endif 142 143 static int wdcprobe1(struct wdc_channel*, int); 144 static void __wdcerror(struct wdc_channel*, char *); 145 static int __wdcwait_reset(struct wdc_channel *, int, int); 146 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 147 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 148 static void __wdccommand_kill_xfer(struct wdc_channel *, 149 struct ata_xfer *, int); 150 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 152 static int __wdcwait(struct wdc_channel *, int, int, int); 153 154 #define DEBUG_INTR 0x01 155 #define DEBUG_XFERS 0x02 156 #define DEBUG_STATUS 0x04 157 #define DEBUG_FUNCS 0x08 158 #define DEBUG_PROBE 0x10 159 #define DEBUG_DETACH 0x20 160 #define DEBUG_DELAY 0x40 161 #ifdef WDCDEBUG 162 int wdcdebug_mask = 0; 163 int wdc_nxfer = 0; 164 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 165 #else 166 #define WDCDEBUG_PRINT(args, level) 167 #endif 168 169 /* 170 * A queue of atabus instances, used to ensure the same bus probe order 171 * for a given hardware configuration at each boot. 172 */ 173 struct atabus_initq_head atabus_initq_head = 174 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 175 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct wdc_channel *chp) 182 { 183 184 chp->cmd_iohs[wd_status] = chp->cmd_iohs[wd_command]; 185 chp->cmd_iohs[wd_features] = chp->cmd_iohs[wd_error]; 186 } 187 188 /* Test to see controller with at last one attached drive is there. 189 * Returns a bit for each possible drive found (0x01 for drive 0, 190 * 0x02 for drive 1). 191 * Logic: 192 * - If a status register is at 0xff, assume there is no drive here 193 * (ISA has pull-up resistors). Similarly if the status register has 194 * the value we last wrote to the bus (for IDE interfaces without pullups). 195 * If no drive at all -> return. 196 * - reset the controller, wait for it to complete (may take up to 31s !). 197 * If timeout -> return. 198 * - test ATA/ATAPI signatures. If at last one drive found -> return. 199 * - try an ATA command on the master. 200 */ 201 202 static void 203 wdc_drvprobe(struct wdc_channel *chp) 204 { 205 struct ataparams params; 206 struct wdc_softc *wdc = chp->ch_wdc; 207 u_int8_t st0 = 0, st1 = 0; 208 int i, error; 209 210 if (wdcprobe1(chp, 0) == 0) { 211 /* No drives, abort the attach here. */ 212 return; 213 } 214 215 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 216 for (i = 0; i < mstohz(3000); i++) { 217 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 218 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 219 wdc->select(chp,0); 220 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 221 0, WDSD_IBM); 222 delay(10); /* 400ns delay */ 223 st0 = bus_space_read_1(chp->cmd_iot, 224 chp->cmd_iohs[wd_status], 0); 225 } 226 227 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 228 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 229 wdc->select(chp,1); 230 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 231 0, WDSD_IBM | 0x10); 232 delay(10); /* 400ns delay */ 233 st1 = bus_space_read_1(chp->cmd_iot, 234 chp->cmd_iohs[wd_status], 0); 235 } 236 237 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 238 == 0 || 239 (st0 & WDCS_DRDY)) && 240 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 241 == 0 || 242 (st1 & WDCS_DRDY))) 243 break; 244 tsleep(¶ms, PRIBIO, "atadrdy", 1); 245 } 246 if ((st0 & WDCS_DRDY) == 0) 247 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 248 if ((st1 & WDCS_DRDY) == 0) 249 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 250 251 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 252 wdc->sc_dev.dv_xname, 253 chp->ch_channel, st0, st1), DEBUG_PROBE); 254 255 /* Wait a bit, some devices are weird just after a reset. */ 256 delay(5000); 257 258 for (i = 0; i < 2; i++) { 259 /* XXX This should be done by other code. */ 260 chp->ch_drive[i].chnl_softc = chp; 261 chp->ch_drive[i].drive = i; 262 263 /* 264 * Init error counter so that an error withing the first xfers 265 * will trigger a downgrade 266 */ 267 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 268 269 /* If controller can't do 16bit flag the drives as 32bit */ 270 if ((wdc->cap & 271 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 272 WDC_CAPABILITY_DATA32) 273 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 274 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 275 continue; 276 277 /* Shortcut in case we've been shutdown */ 278 if (chp->ch_flags & WDCF_SHUTDOWN) 279 return; 280 281 /* issue an identify, to try to detect ghosts */ 282 error = ata_get_params(&chp->ch_drive[i], 283 AT_WAIT | AT_POLL, ¶ms); 284 if (error != CMD_OK) { 285 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 286 287 /* Shortcut in case we've been shutdown */ 288 if (chp->ch_flags & WDCF_SHUTDOWN) 289 return; 290 291 error = ata_get_params(&chp->ch_drive[i], 292 AT_WAIT | AT_POLL, ¶ms); 293 } 294 if (error == CMD_OK) { 295 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 296 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 297 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 298 } else { 299 chp->ch_drive[i].drive_flags &= 300 ~(DRIVE_ATA | DRIVE_ATAPI); 301 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 302 wdc->sc_dev.dv_xname, 303 chp->ch_channel, i, error), DEBUG_PROBE); 304 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 305 continue; 306 /* 307 * Pre-ATA drive ? 308 * Test registers writability (Error register not 309 * writable, but cyllo is), then try an ATA command. 310 */ 311 if (wdc->cap & WDC_CAPABILITY_SELECT) 312 wdc->select(chp,i); 313 bus_space_write_1(chp->cmd_iot, 314 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 315 delay(10); /* 400ns delay */ 316 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 317 0, 0x58); 318 bus_space_write_1(chp->cmd_iot, 319 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 320 if (bus_space_read_1(chp->cmd_iot, 321 chp->cmd_iohs[wd_error], 0) == 0x58 || 322 bus_space_read_1(chp->cmd_iot, 323 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 324 WDCDEBUG_PRINT(("%s:%d:%d: register " 325 "writability failed\n", 326 wdc->sc_dev.dv_xname, 327 chp->ch_channel, i), DEBUG_PROBE); 328 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 329 continue; 330 } 331 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 332 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 333 wdc->sc_dev.dv_xname, 334 chp->ch_channel, i), DEBUG_PROBE); 335 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 336 continue; 337 } 338 bus_space_write_1(chp->cmd_iot, 339 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 340 delay(10); /* 400ns delay */ 341 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 342 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 343 wdc->sc_dev.dv_xname, 344 chp->ch_channel, i), DEBUG_PROBE); 345 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 346 } else { 347 chp->ch_drive[0].drive_flags &= 348 ~(DRIVE_ATA | DRIVE_ATAPI); 349 chp->ch_drive[1].drive_flags &= 350 ~(DRIVE_ATA | DRIVE_ATAPI); 351 } 352 } 353 } 354 } 355 356 void 357 atabusconfig(struct atabus_softc *atabus_sc) 358 { 359 struct wdc_channel *chp = atabus_sc->sc_chan; 360 struct wdc_softc *wdc = chp->ch_wdc; 361 int i; 362 struct atabus_initq *atabus_initq = NULL; 363 364 /* Probe for the drives. */ 365 (*wdc->drv_probe)(chp); 366 367 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 368 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 369 DEBUG_PROBE); 370 371 /* If no drives, abort here */ 372 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 373 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 374 goto out; 375 376 /* Shortcut in case we've been shutdown */ 377 if (chp->ch_flags & WDCF_SHUTDOWN) 378 goto out; 379 380 /* Make sure the devices probe in atabus order to avoid jitter. */ 381 simple_lock(&atabus_interlock); 382 while(1) { 383 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 384 if (atabus_initq->atabus_sc == atabus_sc) 385 break; 386 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 387 &atabus_interlock); 388 } 389 simple_unlock(&atabus_interlock); 390 391 /* 392 * Attach an ATAPI bus, if needed. 393 */ 394 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 395 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 396 #if NATAPIBUS > 0 397 wdc_atapibus_attach(atabus_sc); 398 #else 399 /* 400 * Fake the autoconfig "not configured" message 401 */ 402 aprint_normal("atapibus at %s not configured\n", 403 wdc->sc_dev.dv_xname); 404 chp->atapibus = NULL; 405 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 406 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 407 #endif 408 } 409 410 for (i = 0; i < 2; i++) { 411 struct ata_device adev; 412 if ((chp->ch_drive[i].drive_flags & 413 (DRIVE_ATA | DRIVE_OLD)) == 0) { 414 continue; 415 } 416 memset(&adev, 0, sizeof(struct ata_device)); 417 adev.adev_bustype = &wdc_ata_bustype; 418 adev.adev_channel = chp->ch_channel; 419 adev.adev_openings = 1; 420 adev.adev_drv_data = &chp->ch_drive[i]; 421 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 422 &adev, ataprint); 423 if (chp->ata_drives[i] != NULL) 424 ata_probe_caps(&chp->ch_drive[i]); 425 else 426 chp->ch_drive[i].drive_flags &= 427 ~(DRIVE_ATA | DRIVE_OLD); 428 } 429 430 /* now that we know the drives, the controller can set its modes */ 431 if (wdc->cap & WDC_CAPABILITY_MODE) { 432 wdc->set_modes(chp); 433 ata_print_modes(chp); 434 } 435 #if NATARAID > 0 436 if (wdc->cap & WDC_CAPABILITY_RAID) 437 for (i = 0; i < 2; i++) 438 if (chp->ata_drives[i] != NULL) 439 ata_raid_check_component(chp->ata_drives[i]); 440 #endif /* NATARAID > 0 */ 441 442 /* 443 * reset drive_flags for unattached devices, reset state for attached 444 * ones 445 */ 446 for (i = 0; i < 2; i++) { 447 if (chp->ch_drive[i].drv_softc == NULL) 448 chp->ch_drive[i].drive_flags = 0; 449 else 450 chp->ch_drive[i].state = 0; 451 } 452 453 out: 454 if (atabus_initq == NULL) { 455 simple_lock(&atabus_interlock); 456 while(1) { 457 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 458 if (atabus_initq->atabus_sc == atabus_sc) 459 break; 460 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 461 &atabus_interlock); 462 } 463 simple_unlock(&atabus_interlock); 464 } 465 simple_lock(&atabus_interlock); 466 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 467 simple_unlock(&atabus_interlock); 468 469 free(atabus_initq, M_DEVBUF); 470 wakeup(&atabus_initq_head); 471 472 ata_delref(chp); 473 474 config_pending_decr(); 475 } 476 477 int 478 wdcprobe(struct wdc_channel *chp) 479 { 480 481 return (wdcprobe1(chp, 1)); 482 } 483 484 static int 485 wdcprobe1(struct wdc_channel *chp, int poll) 486 { 487 struct wdc_softc *wdc = chp->ch_wdc; 488 u_int8_t st0, st1, sc, sn, cl, ch; 489 u_int8_t ret_value = 0x03; 490 u_int8_t drive; 491 int s; 492 493 /* 494 * Sanity check to see if the wdc channel responds at all. 495 */ 496 497 s = splbio(); 498 if (wdc == NULL || 499 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 500 501 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 502 wdc->select(chp,0); 503 504 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 505 WDSD_IBM); 506 delay(10); /* 400ns delay */ 507 st0 = bus_space_read_1(chp->cmd_iot, 508 chp->cmd_iohs[wd_status], 0); 509 510 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 511 wdc->select(chp,1); 512 513 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 514 WDSD_IBM | 0x10); 515 delay(10); /* 400ns delay */ 516 st1 = bus_space_read_1(chp->cmd_iot, 517 chp->cmd_iohs[wd_status], 0); 518 519 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 520 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 521 chp->ch_channel, st0, st1), DEBUG_PROBE); 522 523 if (st0 == 0xff || st0 == WDSD_IBM) 524 ret_value &= ~0x01; 525 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 526 ret_value &= ~0x02; 527 /* Register writability test, drive 0. */ 528 if (ret_value & 0x01) { 529 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 530 wdc->select(chp,0); 531 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 532 0, WDSD_IBM); 533 bus_space_write_1(chp->cmd_iot, 534 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 535 cl = bus_space_read_1(chp->cmd_iot, 536 chp->cmd_iohs[wd_cyl_lo], 0); 537 if (cl != 0x02) { 538 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 539 "got 0x%x != 0x02\n", 540 wdc != NULL ? 541 wdc->sc_dev.dv_xname : "wdcprobe", 542 chp->ch_channel, cl), 543 DEBUG_PROBE); 544 ret_value &= ~0x01; 545 } 546 bus_space_write_1(chp->cmd_iot, 547 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 548 cl = bus_space_read_1(chp->cmd_iot, 549 chp->cmd_iohs[wd_cyl_lo], 0); 550 if (cl != 0x01) { 551 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 552 "got 0x%x != 0x01\n", 553 wdc != NULL ? 554 wdc->sc_dev.dv_xname : "wdcprobe", 555 chp->ch_channel, cl), 556 DEBUG_PROBE); 557 ret_value &= ~0x01; 558 } 559 bus_space_write_1(chp->cmd_iot, 560 chp->cmd_iohs[wd_sector], 0, 0x01); 561 cl = bus_space_read_1(chp->cmd_iot, 562 chp->cmd_iohs[wd_sector], 0); 563 if (cl != 0x01) { 564 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 565 "got 0x%x != 0x01\n", 566 wdc != NULL ? 567 wdc->sc_dev.dv_xname : "wdcprobe", 568 chp->ch_channel, cl), 569 DEBUG_PROBE); 570 ret_value &= ~0x01; 571 } 572 bus_space_write_1(chp->cmd_iot, 573 chp->cmd_iohs[wd_sector], 0, 0x02); 574 cl = bus_space_read_1(chp->cmd_iot, 575 chp->cmd_iohs[wd_sector], 0); 576 if (cl != 0x02) { 577 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 578 "got 0x%x != 0x02\n", 579 wdc != NULL ? 580 wdc->sc_dev.dv_xname : "wdcprobe", 581 chp->ch_channel, cl), 582 DEBUG_PROBE); 583 ret_value &= ~0x01; 584 } 585 cl = bus_space_read_1(chp->cmd_iot, 586 chp->cmd_iohs[wd_cyl_lo], 0); 587 if (cl != 0x01) { 588 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 589 "got 0x%x != 0x01\n", 590 wdc != NULL ? 591 wdc->sc_dev.dv_xname : "wdcprobe", 592 chp->ch_channel, cl), 593 DEBUG_PROBE); 594 ret_value &= ~0x01; 595 } 596 } 597 /* Register writability test, drive 1. */ 598 if (ret_value & 0x02) { 599 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 600 wdc->select(chp,1); 601 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 602 0, WDSD_IBM | 0x10); 603 bus_space_write_1(chp->cmd_iot, 604 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 605 cl = bus_space_read_1(chp->cmd_iot, 606 chp->cmd_iohs[wd_cyl_lo], 0); 607 if (cl != 0x02) { 608 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 609 "got 0x%x != 0x02\n", 610 wdc != NULL ? 611 wdc->sc_dev.dv_xname : "wdcprobe", 612 chp->ch_channel, cl), 613 DEBUG_PROBE); 614 ret_value &= ~0x02; 615 } 616 bus_space_write_1(chp->cmd_iot, 617 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 618 cl = bus_space_read_1(chp->cmd_iot, 619 chp->cmd_iohs[wd_cyl_lo], 0); 620 if (cl != 0x01) { 621 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 622 "got 0x%x != 0x01\n", 623 wdc != NULL ? 624 wdc->sc_dev.dv_xname : "wdcprobe", 625 chp->ch_channel, cl), 626 DEBUG_PROBE); 627 ret_value &= ~0x02; 628 } 629 bus_space_write_1(chp->cmd_iot, 630 chp->cmd_iohs[wd_sector], 0, 0x01); 631 cl = bus_space_read_1(chp->cmd_iot, 632 chp->cmd_iohs[wd_sector], 0); 633 if (cl != 0x01) { 634 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 635 "got 0x%x != 0x01\n", 636 wdc != NULL ? 637 wdc->sc_dev.dv_xname : "wdcprobe", 638 chp->ch_channel, cl), 639 DEBUG_PROBE); 640 ret_value &= ~0x02; 641 } 642 bus_space_write_1(chp->cmd_iot, 643 chp->cmd_iohs[wd_sector], 0, 0x02); 644 cl = bus_space_read_1(chp->cmd_iot, 645 chp->cmd_iohs[wd_sector], 0); 646 if (cl != 0x02) { 647 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 648 "got 0x%x != 0x02\n", 649 wdc != NULL ? 650 wdc->sc_dev.dv_xname : "wdcprobe", 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 cl = bus_space_read_1(chp->cmd_iot, 656 chp->cmd_iohs[wd_cyl_lo], 0); 657 if (cl != 0x01) { 658 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 659 "got 0x%x != 0x01\n", 660 wdc != NULL ? 661 wdc->sc_dev.dv_xname : "wdcprobe", 662 chp->ch_channel, cl), 663 DEBUG_PROBE); 664 ret_value &= ~0x02; 665 } 666 } 667 668 if (ret_value == 0) { 669 splx(s); 670 return 0; 671 } 672 } 673 674 675 #if 0 /* XXX this break some ATA or ATAPI devices */ 676 /* 677 * reset bus. Also send an ATAPI_RESET to devices, in case there are 678 * ATAPI device out there which don't react to the bus reset 679 */ 680 if (ret_value & 0x01) { 681 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 682 wdc->select(chp,0); 683 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 684 0, WDSD_IBM); 685 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 686 ATAPI_SOFT_RESET); 687 } 688 if (ret_value & 0x02) { 689 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 690 wdc->select(chp,0); 691 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 692 0, WDSD_IBM | 0x10); 693 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 694 ATAPI_SOFT_RESET); 695 } 696 697 delay(5000); 698 #endif 699 700 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 701 wdc->select(chp,0); 702 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 703 delay(10); /* 400ns delay */ 704 /* assert SRST, wait for reset to complete */ 705 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 706 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 707 DELAY(1000); 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_IDS | WDCTL_4BIT); 710 DELAY(2000); 711 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 712 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 713 delay(10); /* 400ns delay */ 714 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 715 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 716 wdc->irqack(chp); 717 splx(s); 718 719 ret_value = __wdcwait_reset(chp, ret_value, poll); 720 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 721 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 722 ret_value), DEBUG_PROBE); 723 724 /* if reset failed, there's nothing here */ 725 if (ret_value == 0) 726 return 0; 727 728 /* 729 * Test presence of drives. First test register signatures looking 730 * for ATAPI devices. If it's not an ATAPI and reset said there may 731 * be something here assume it's ATA or OLD. Ghost will be killed 732 * later in attach routine. 733 */ 734 for (drive = 0; drive < 2; drive++) { 735 if ((ret_value & (0x01 << drive)) == 0) 736 continue; 737 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 738 wdc->select(chp,drive); 739 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 740 WDSD_IBM | (drive << 4)); 741 delay(10); /* 400ns delay */ 742 /* Save registers contents */ 743 sc = bus_space_read_1(chp->cmd_iot, 744 chp->cmd_iohs[wd_seccnt], 0); 745 sn = bus_space_read_1(chp->cmd_iot, 746 chp->cmd_iohs[wd_sector], 0); 747 cl = bus_space_read_1(chp->cmd_iot, 748 chp->cmd_iohs[wd_cyl_lo], 0); 749 ch = bus_space_read_1(chp->cmd_iot, 750 chp->cmd_iohs[wd_cyl_hi], 0); 751 752 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 753 "cl=0x%x ch=0x%x\n", 754 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 755 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 756 /* 757 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 758 * we get wrong values here, so ignore it. 759 */ 760 if (cl == 0x14 && ch == 0xeb) { 761 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 762 } else { 763 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 764 if (wdc == NULL || 765 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 766 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 767 } 768 } 769 return (ret_value); 770 } 771 772 void 773 wdcattach(struct wdc_channel *chp) 774 { 775 struct wdc_softc *wdc = chp->ch_wdc; 776 777 if (chp->ch_flags & WDCF_DISABLED) 778 return; 779 780 /* default data transfer methods */ 781 if (!wdc->datain_pio) 782 wdc->datain_pio = wdc_datain_pio; 783 if (!wdc->dataout_pio) 784 wdc->dataout_pio = wdc_dataout_pio; 785 786 /* initialise global data */ 787 callout_init(&chp->ch_callout); 788 if (wdc->drv_probe == NULL) 789 wdc->drv_probe = wdc_drvprobe; 790 791 TAILQ_INIT(&chp->ch_queue->queue_xfer); 792 chp->ch_queue->queue_freeze = 0; 793 chp->ch_queue->active_xfer = NULL; 794 795 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 796 } 797 798 int 799 wdcactivate(struct device *self, enum devact act) 800 { 801 struct wdc_softc *wdc = (struct wdc_softc *)self; 802 int s, i, error = 0; 803 804 s = splbio(); 805 switch (act) { 806 case DVACT_ACTIVATE: 807 error = EOPNOTSUPP; 808 break; 809 810 case DVACT_DEACTIVATE: 811 for (i = 0; i < wdc->nchannels; i++) { 812 error = config_deactivate(wdc->channels[i]->atabus); 813 if (error) 814 break; 815 } 816 break; 817 } 818 splx(s); 819 return (error); 820 } 821 822 int 823 wdcdetach(struct device *self, int flags) 824 { 825 struct wdc_softc *wdc = (struct wdc_softc *)self; 826 struct wdc_channel *chp; 827 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 828 int i, error = 0; 829 830 for (i = 0; i < wdc->nchannels; i++) { 831 chp = wdc->channels[i]; 832 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 833 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 834 error = config_detach(chp->atabus, flags); 835 if (error) 836 break; 837 } 838 if (adapt->adapt_refcnt != 0) { 839 #ifdef DIAGNOSTIC 840 printf("wdcdetach: refcnt should be 0 here??\n"); 841 #endif 842 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 843 } 844 return (error); 845 } 846 847 /* 848 * Start I/O on a controller, for the given channel. 849 * The first xfer may be not for our channel if the channel queues 850 * are shared. 851 */ 852 void 853 wdcstart(struct wdc_channel *chp) 854 { 855 struct wdc_softc *wdc = chp->ch_wdc; 856 struct ata_xfer *xfer; 857 858 #ifdef WDC_DIAGNOSTIC 859 int spl1, spl2; 860 861 spl1 = splbio(); 862 spl2 = splbio(); 863 if (spl2 != spl1) { 864 printf("wdcstart: not at splbio()\n"); 865 panic("wdcstart"); 866 } 867 splx(spl2); 868 splx(spl1); 869 #endif /* WDC_DIAGNOSTIC */ 870 871 /* is there a xfer ? */ 872 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 873 return; 874 875 /* adjust chp, in case we have a shared queue */ 876 chp = xfer->c_chp; 877 878 if (chp->ch_queue->active_xfer != NULL) { 879 return; /* channel aleady active */ 880 } 881 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 882 return; /* queue froozen */ 883 } 884 #ifdef DIAGNOSTIC 885 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 886 panic("wdcstart: channel waiting for irq"); 887 #endif 888 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 889 if (!(*wdc->claim_hw)(chp, 0)) 890 return; 891 892 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 893 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 894 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 895 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 896 chp->ch_drive[xfer->c_drive].state = 0; 897 } 898 chp->ch_queue->active_xfer = xfer; 899 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 900 901 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 902 KASSERT(xfer->c_flags & C_POLL); 903 xfer->c_start(chp, xfer); 904 } 905 906 /* restart an interrupted I/O */ 907 void 908 wdcrestart(void *v) 909 { 910 struct wdc_channel *chp = v; 911 int s; 912 913 s = splbio(); 914 wdcstart(chp); 915 splx(s); 916 } 917 918 919 /* 920 * Interrupt routine for the controller. Acknowledge the interrupt, check for 921 * errors on the current operation, mark it done if necessary, and start the 922 * next request. Also check for a partially done transfer, and continue with 923 * the next chunk if so. 924 */ 925 int 926 wdcintr(void *arg) 927 { 928 struct wdc_channel *chp = arg; 929 struct wdc_softc *wdc = chp->ch_wdc; 930 struct ata_xfer *xfer; 931 int ret; 932 933 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 934 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 935 DEBUG_INTR); 936 return (0); 937 } 938 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 939 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 940 /* try to clear the pending interrupt anyway */ 941 (void)bus_space_read_1(chp->cmd_iot, 942 chp->cmd_iohs[wd_status], 0); 943 return (0); 944 } 945 946 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 947 xfer = chp->ch_queue->active_xfer; 948 #ifdef DIAGNOSTIC 949 if (xfer == NULL) 950 panic("wdcintr: no xfer"); 951 #endif 952 if (chp->ch_flags & WDCF_DMA_WAIT) { 953 wdc->dma_status = 954 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 955 xfer->c_drive, WDC_DMAEND_END); 956 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 957 /* IRQ not for us, not detected by DMA engine */ 958 return 0; 959 } 960 chp->ch_flags &= ~WDCF_DMA_WAIT; 961 } 962 chp->ch_flags &= ~WDCF_IRQ_WAIT; 963 ret = xfer->c_intr(chp, xfer, 1); 964 if (ret == 0) /* irq was not for us, still waiting for irq */ 965 chp->ch_flags |= WDCF_IRQ_WAIT; 966 return (ret); 967 } 968 969 /* Put all disk in RESET state */ 970 void 971 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 972 { 973 struct wdc_channel *chp = drvp->chnl_softc; 974 struct wdc_softc *wdc = chp->ch_wdc; 975 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 976 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 977 DEBUG_FUNCS); 978 979 980 wdc_reset_channel(chp, flags); 981 } 982 983 void 984 wdc_reset_channel(struct wdc_channel *chp, int flags) 985 { 986 TAILQ_HEAD(, ata_xfer) reset_xfer; 987 struct ata_xfer *xfer, *next_xfer; 988 int drive; 989 990 chp->ch_queue->queue_freeze++; 991 TAILQ_INIT(&reset_xfer); 992 993 /* if we can poll or wait it's OK, otherwise wake up the kernel 994 * thread 995 */ 996 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 997 if (chp->ch_flags & WDCF_TH_RESET) { 998 /* no need to schedule a reset more than one time */ 999 return; 1000 } 1001 chp->ch_flags |= WDCF_TH_RESET; 1002 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 1003 wakeup(&chp->ch_thread); 1004 return; 1005 } 1006 1007 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1008 /* 1009 * if the current command if on an ATAPI device, issue a 1010 * ATAPI_SOFT_RESET 1011 */ 1012 xfer = chp->ch_queue->active_xfer; 1013 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1014 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1015 if (flags & AT_WAIT) 1016 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1017 else 1018 delay(1000); 1019 } 1020 1021 /* reset the channel */ 1022 if (flags & AT_WAIT) 1023 (void) wdcreset(chp, RESET_SLEEP); 1024 else 1025 (void) wdcreset(chp, RESET_POLL); 1026 1027 /* 1028 * wait a bit after reset; in case the DMA engines needs some time 1029 * to recover. 1030 */ 1031 if (flags & AT_WAIT) 1032 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 1033 else 1034 delay(1000); 1035 /* 1036 * look for pending xfers. If we have a shared queue, we'll also reset 1037 * the other channel if the current xfer is running on it. 1038 * Then we'll dequeue only the xfers for this channel. 1039 */ 1040 if ((flags & AT_RST_NOCMD) == 0) { 1041 /* 1042 * move all xfers queued for this channel to the reset queue, 1043 * and then process the current xfer and then the reset queue. 1044 * We have to use a temporary queue because c_kill_xfer() 1045 * may requeue commands. 1046 */ 1047 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1048 xfer != NULL; xfer = next_xfer) { 1049 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1050 if (xfer->c_chp != chp) 1051 continue; 1052 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1053 xfer, c_xferchain); 1054 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1055 } 1056 xfer = chp->ch_queue->active_xfer; 1057 if (xfer) { 1058 if (xfer->c_chp != chp) 1059 wdc_reset_channel(xfer->c_chp, flags); 1060 else { 1061 callout_stop(&chp->ch_callout); 1062 /* 1063 * If we're waiting for DMA, stop the 1064 * DMA engine 1065 */ 1066 if (chp->ch_flags & WDCF_DMA_WAIT) { 1067 (*chp->ch_wdc->dma_finish)( 1068 chp->ch_wdc->dma_arg, 1069 chp->ch_channel, 1070 xfer->c_drive, 1071 WDC_DMAEND_ABRT_QUIET); 1072 chp->ch_flags &= ~WDCF_DMA_WAIT; 1073 } 1074 chp->ch_queue->active_xfer = NULL; 1075 if ((flags & AT_RST_EMERG) == 0) 1076 xfer->c_kill_xfer( 1077 chp, xfer, KILL_RESET); 1078 } 1079 } 1080 1081 for (xfer = TAILQ_FIRST(&reset_xfer); 1082 xfer != NULL; xfer = next_xfer) { 1083 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1084 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1085 if ((flags & AT_RST_EMERG) == 0) 1086 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1087 } 1088 } 1089 for (drive = 0; drive < 2; drive++) { 1090 chp->ch_drive[drive].state = 0; 1091 } 1092 chp->ch_flags &= ~WDCF_TH_RESET; 1093 if ((flags & AT_RST_EMERG) == 0) { 1094 chp->ch_queue->queue_freeze--; 1095 wdcstart(chp); 1096 } else { 1097 /* make sure that we can use polled commands */ 1098 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1099 chp->ch_queue->queue_freeze = 0; 1100 chp->ch_queue->active_xfer = NULL; 1101 } 1102 } 1103 1104 int 1105 wdcreset(struct wdc_channel *chp, int poll) 1106 { 1107 struct wdc_softc *wdc = chp->ch_wdc; 1108 int drv_mask1, drv_mask2; 1109 int s = 0; 1110 1111 if (wdc->cap & WDC_CAPABILITY_SELECT) 1112 wdc->select(chp,0); 1113 if (poll != RESET_SLEEP) 1114 s = splbio(); 1115 /* master */ 1116 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1117 delay(10); /* 400ns delay */ 1118 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1119 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1120 delay(2000); 1121 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1122 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1123 WDCTL_4BIT | WDCTL_IDS); 1124 delay(10); /* 400ns delay */ 1125 if (poll != RESET_SLEEP) { 1126 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1127 wdc->irqack(chp); 1128 splx(s); 1129 } 1130 1131 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1132 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1133 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1134 (poll == RESET_SLEEP) ? 0 : 1); 1135 if (drv_mask2 != drv_mask1) { 1136 printf("%s channel %d: reset failed for", 1137 wdc->sc_dev.dv_xname, chp->ch_channel); 1138 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1139 printf(" drive 0"); 1140 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1141 printf(" drive 1"); 1142 printf("\n"); 1143 } 1144 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1145 return (drv_mask1 != drv_mask2) ? 1 : 0; 1146 } 1147 1148 static int 1149 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1150 { 1151 struct wdc_softc *wdc = chp->ch_wdc; 1152 int timeout, nloop; 1153 u_int8_t st0 = 0, st1 = 0; 1154 #ifdef WDCDEBUG 1155 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1156 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1157 #endif 1158 1159 if (poll) 1160 nloop = WDCNDELAY_RST; 1161 else 1162 nloop = WDC_RESET_WAIT * hz / 1000; 1163 /* wait for BSY to deassert */ 1164 for (timeout = 0; timeout < nloop; timeout++) { 1165 if ((drv_mask & 0x01) != 0) { 1166 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1167 wdc->select(chp,0); 1168 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1169 0, WDSD_IBM); /* master */ 1170 delay(10); 1171 st0 = bus_space_read_1(chp->cmd_iot, 1172 chp->cmd_iohs[wd_status], 0); 1173 #ifdef WDCDEBUG 1174 sc0 = bus_space_read_1(chp->cmd_iot, 1175 chp->cmd_iohs[wd_seccnt], 0); 1176 sn0 = bus_space_read_1(chp->cmd_iot, 1177 chp->cmd_iohs[wd_sector], 0); 1178 cl0 = bus_space_read_1(chp->cmd_iot, 1179 chp->cmd_iohs[wd_cyl_lo], 0); 1180 ch0 = bus_space_read_1(chp->cmd_iot, 1181 chp->cmd_iohs[wd_cyl_hi], 0); 1182 #endif 1183 } 1184 if ((drv_mask & 0x02) != 0) { 1185 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1186 wdc->select(chp,1); 1187 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1188 0, WDSD_IBM | 0x10); /* slave */ 1189 delay(10); 1190 st1 = bus_space_read_1(chp->cmd_iot, 1191 chp->cmd_iohs[wd_status], 0); 1192 #ifdef WDCDEBUG 1193 sc1 = bus_space_read_1(chp->cmd_iot, 1194 chp->cmd_iohs[wd_seccnt], 0); 1195 sn1 = bus_space_read_1(chp->cmd_iot, 1196 chp->cmd_iohs[wd_sector], 0); 1197 cl1 = bus_space_read_1(chp->cmd_iot, 1198 chp->cmd_iohs[wd_cyl_lo], 0); 1199 ch1 = bus_space_read_1(chp->cmd_iot, 1200 chp->cmd_iohs[wd_cyl_hi], 0); 1201 #endif 1202 } 1203 1204 if ((drv_mask & 0x01) == 0) { 1205 /* no master */ 1206 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1207 /* No master, slave is ready, it's done */ 1208 goto end; 1209 } 1210 } else if ((drv_mask & 0x02) == 0) { 1211 /* no slave */ 1212 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1213 /* No slave, master is ready, it's done */ 1214 goto end; 1215 } 1216 } else { 1217 /* Wait for both master and slave to be ready */ 1218 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1219 goto end; 1220 } 1221 } 1222 if (poll) 1223 delay(WDCDELAY); 1224 else 1225 tsleep(&nloop, PRIBIO, "atarst", 1); 1226 } 1227 /* Reset timed out. Maybe it's because drv_mask was not right */ 1228 if (st0 & WDCS_BSY) 1229 drv_mask &= ~0x01; 1230 if (st1 & WDCS_BSY) 1231 drv_mask &= ~0x02; 1232 end: 1233 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1234 "cl=0x%x ch=0x%x\n", 1235 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1236 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1237 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1238 "cl=0x%x ch=0x%x\n", 1239 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1240 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1241 1242 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1243 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1244 st0, st1), DEBUG_PROBE); 1245 1246 return drv_mask; 1247 } 1248 1249 /* 1250 * Wait for a drive to be !BSY, and have mask in its status register. 1251 * return -1 for a timeout after "timeout" ms. 1252 */ 1253 static int 1254 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1255 { 1256 struct wdc_softc *wdc = chp->ch_wdc; 1257 u_char status; 1258 int time = 0; 1259 1260 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1261 wdc->sc_dev.dv_xname : "none", 1262 chp->ch_channel), DEBUG_STATUS); 1263 chp->ch_error = 0; 1264 1265 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1266 1267 for (;;) { 1268 chp->ch_status = status = 1269 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1270 if ((status & (WDCS_BSY | mask)) == bits) 1271 break; 1272 if (++time > timeout) { 1273 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1274 "status %x error %x (mask 0x%x bits 0x%x)\n", 1275 time, status, 1276 bus_space_read_1(chp->cmd_iot, 1277 chp->cmd_iohs[wd_error], 0), mask, bits), 1278 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1279 return(WDCWAIT_TOUT); 1280 } 1281 delay(WDCDELAY); 1282 } 1283 #ifdef WDCDEBUG 1284 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1285 printf("__wdcwait: did busy-wait, time=%d\n", time); 1286 #endif 1287 if (status & WDCS_ERR) 1288 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1289 chp->cmd_iohs[wd_error], 0); 1290 #ifdef WDCNDELAY_DEBUG 1291 /* After autoconfig, there should be no long delays. */ 1292 if (!cold && time > WDCNDELAY_DEBUG) { 1293 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1294 if (xfer == NULL) 1295 printf("%s channel %d: warning: busy-wait took %dus\n", 1296 wdc->sc_dev.dv_xname, chp->ch_channel, 1297 WDCDELAY * time); 1298 else 1299 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1300 wdc->sc_dev.dv_xname, chp->ch_channel, 1301 xfer->drive, 1302 WDCDELAY * time); 1303 } 1304 #endif 1305 return(WDCWAIT_OK); 1306 } 1307 1308 /* 1309 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1310 * thread if possible 1311 */ 1312 int 1313 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1314 { 1315 int error, i, timeout_hz = mstohz(timeout); 1316 1317 if (timeout_hz == 0 || 1318 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1319 error = __wdcwait(chp, mask, bits, timeout); 1320 else { 1321 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1322 if (error != 0) { 1323 if ((chp->ch_flags & WDCF_TH_RUN) || 1324 (flags & AT_WAIT)) { 1325 /* 1326 * we're running in the channel thread 1327 * or some userland thread context 1328 */ 1329 for (i = 0; i < timeout_hz; i++) { 1330 if (__wdcwait(chp, mask, bits, 1331 WDCDELAY_POLL) == 0) { 1332 error = 0; 1333 break; 1334 } 1335 tsleep(&chp, PRIBIO, "atapoll", 1); 1336 } 1337 } else { 1338 /* 1339 * we're probably in interrupt context, 1340 * ask the thread to come back here 1341 */ 1342 #ifdef DIAGNOSTIC 1343 if (chp->ch_queue->queue_freeze > 0) 1344 panic("wdcwait: queue_freeze"); 1345 #endif 1346 chp->ch_queue->queue_freeze++; 1347 wakeup(&chp->ch_thread); 1348 return(WDCWAIT_THR); 1349 } 1350 } 1351 } 1352 return (error); 1353 } 1354 1355 1356 /* 1357 * Busy-wait for DMA to complete 1358 */ 1359 int 1360 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1361 { 1362 struct wdc_softc *wdc = chp->ch_wdc; 1363 int time; 1364 1365 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1366 wdc->dma_status = 1367 (*wdc->dma_finish)(wdc->dma_arg, 1368 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1369 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1370 return 0; 1371 delay(WDCDELAY); 1372 } 1373 /* timeout, force a DMA halt */ 1374 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1375 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1376 return 1; 1377 } 1378 1379 void 1380 wdctimeout(void *arg) 1381 { 1382 struct wdc_channel *chp = (struct wdc_channel *)arg; 1383 struct wdc_softc *wdc = chp->ch_wdc; 1384 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1385 int s; 1386 1387 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1388 1389 s = splbio(); 1390 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1391 __wdcerror(chp, "lost interrupt"); 1392 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1393 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1394 xfer->c_bcount, 1395 xfer->c_skip); 1396 if (chp->ch_flags & WDCF_DMA_WAIT) { 1397 wdc->dma_status = 1398 (*wdc->dma_finish)(wdc->dma_arg, 1399 chp->ch_channel, xfer->c_drive, 1400 WDC_DMAEND_ABRT); 1401 chp->ch_flags &= ~WDCF_DMA_WAIT; 1402 } 1403 /* 1404 * Call the interrupt routine. If we just missed an interrupt, 1405 * it will do what's needed. Else, it will take the needed 1406 * action (reset the device). 1407 * Before that we need to reinstall the timeout callback, 1408 * in case it will miss another irq while in this transfer 1409 * We arbitray chose it to be 1s 1410 */ 1411 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1412 xfer->c_flags |= C_TIMEOU; 1413 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1414 xfer->c_intr(chp, xfer, 1); 1415 } else 1416 __wdcerror(chp, "missing untimeout"); 1417 splx(s); 1418 } 1419 1420 int 1421 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1422 { 1423 struct wdc_channel *chp = drvp->chnl_softc; 1424 struct wdc_softc *wdc = chp->ch_wdc; 1425 struct ata_xfer *xfer; 1426 int s, ret; 1427 1428 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1429 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1430 DEBUG_FUNCS); 1431 1432 /* set up an xfer and queue. Wait for completion */ 1433 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1434 ATAXF_NOSLEEP); 1435 if (xfer == NULL) { 1436 return ATACMD_TRY_AGAIN; 1437 } 1438 1439 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1440 ata_c->flags |= AT_POLL; 1441 if (ata_c->flags & AT_POLL) 1442 xfer->c_flags |= C_POLL; 1443 xfer->c_drive = drvp->drive; 1444 xfer->c_databuf = ata_c->data; 1445 xfer->c_bcount = ata_c->bcount; 1446 xfer->c_cmd = ata_c; 1447 xfer->c_start = __wdccommand_start; 1448 xfer->c_intr = __wdccommand_intr; 1449 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1450 1451 s = splbio(); 1452 ata_exec_xfer(chp, xfer); 1453 #ifdef DIAGNOSTIC 1454 if ((ata_c->flags & AT_POLL) != 0 && 1455 (ata_c->flags & AT_DONE) == 0) 1456 panic("wdc_exec_command: polled command not done"); 1457 #endif 1458 if (ata_c->flags & AT_DONE) { 1459 ret = ATACMD_COMPLETE; 1460 } else { 1461 if (ata_c->flags & AT_WAIT) { 1462 while ((ata_c->flags & AT_DONE) == 0) { 1463 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1464 } 1465 ret = ATACMD_COMPLETE; 1466 } else { 1467 ret = ATACMD_QUEUED; 1468 } 1469 } 1470 splx(s); 1471 return ret; 1472 } 1473 1474 static void 1475 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1476 { 1477 struct wdc_softc *wdc = chp->ch_wdc; 1478 int drive = xfer->c_drive; 1479 struct ata_command *ata_c = xfer->c_cmd; 1480 1481 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1482 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1483 DEBUG_FUNCS); 1484 1485 if (wdc->cap & WDC_CAPABILITY_SELECT) 1486 wdc->select(chp,drive); 1487 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1488 WDSD_IBM | (drive << 4)); 1489 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1490 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1491 case WDCWAIT_OK: 1492 break; 1493 case WDCWAIT_TOUT: 1494 ata_c->flags |= AT_TIMEOU; 1495 __wdccommand_done(chp, xfer); 1496 return; 1497 case WDCWAIT_THR: 1498 return; 1499 } 1500 if (ata_c->flags & AT_POLL) { 1501 /* polled command, disable interrupts */ 1502 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1503 WDCTL_4BIT | WDCTL_IDS); 1504 } 1505 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1506 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1507 1508 if ((ata_c->flags & AT_POLL) == 0) { 1509 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1510 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1511 wdctimeout, chp); 1512 return; 1513 } 1514 /* 1515 * Polled command. Wait for drive ready or drq. Done in intr(). 1516 * Wait for at last 400ns for status bit to be valid. 1517 */ 1518 delay(10); /* 400ns delay */ 1519 __wdccommand_intr(chp, xfer, 0); 1520 } 1521 1522 static int 1523 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1524 { 1525 struct wdc_softc *wdc = chp->ch_wdc; 1526 struct ata_command *ata_c = xfer->c_cmd; 1527 int bcount = ata_c->bcount; 1528 char *data = ata_c->data; 1529 int wflags; 1530 1531 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1532 /* both wait and poll, we can tsleep here */ 1533 wflags = AT_WAIT | AT_POLL; 1534 } else { 1535 wflags = AT_POLL; 1536 } 1537 1538 again: 1539 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1540 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1541 DEBUG_INTR); 1542 /* 1543 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1544 * Reselect again, it doesn't hurt for others commands, and the time 1545 * penalty for the extra regiter write is acceptable, 1546 * wdc_exec_command() isn't called often (mosly for autoconfig) 1547 */ 1548 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1549 WDSD_IBM | (xfer->c_drive << 4)); 1550 if ((ata_c->flags & AT_XFDONE) != 0) { 1551 /* 1552 * We have completed a data xfer. The drive should now be 1553 * in its initial state 1554 */ 1555 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1556 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1557 wflags) == WDCWAIT_TOUT) { 1558 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1559 return 0; /* IRQ was not for us */ 1560 ata_c->flags |= AT_TIMEOU; 1561 } 1562 goto out; 1563 } 1564 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1565 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1566 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1567 return 0; /* IRQ was not for us */ 1568 ata_c->flags |= AT_TIMEOU; 1569 goto out; 1570 } 1571 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1572 wdc->irqack(chp); 1573 if (ata_c->flags & AT_READ) { 1574 if ((chp->ch_status & WDCS_DRQ) == 0) { 1575 ata_c->flags |= AT_TIMEOU; 1576 goto out; 1577 } 1578 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1579 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1580 0, (u_int32_t*)data, bcount >> 2); 1581 data += bcount & 0xfffffffc; 1582 bcount = bcount & 0x03; 1583 } 1584 if (bcount > 0) 1585 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1586 /* at this point the drive should be in its initial state */ 1587 ata_c->flags |= AT_XFDONE; 1588 /* XXX should read status register here ? */ 1589 } else if (ata_c->flags & AT_WRITE) { 1590 if ((chp->ch_status & WDCS_DRQ) == 0) { 1591 ata_c->flags |= AT_TIMEOU; 1592 goto out; 1593 } 1594 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1595 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1596 0, (u_int32_t*)data, bcount >> 2); 1597 data += bcount & 0xfffffffc; 1598 bcount = bcount & 0x03; 1599 } 1600 if (bcount > 0) 1601 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1602 ata_c->flags |= AT_XFDONE; 1603 if ((ata_c->flags & AT_POLL) == 0) { 1604 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1605 callout_reset(&chp->ch_callout, 1606 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1607 return 1; 1608 } else { 1609 goto again; 1610 } 1611 } 1612 out: 1613 __wdccommand_done(chp, xfer); 1614 return 1; 1615 } 1616 1617 static void 1618 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1619 { 1620 struct wdc_softc *wdc = chp->ch_wdc; 1621 struct ata_command *ata_c = xfer->c_cmd; 1622 1623 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1624 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1625 DEBUG_FUNCS); 1626 1627 1628 if (chp->ch_status & WDCS_DWF) 1629 ata_c->flags |= AT_DF; 1630 if (chp->ch_status & WDCS_ERR) { 1631 ata_c->flags |= AT_ERROR; 1632 ata_c->r_error = chp->ch_error; 1633 } 1634 if ((ata_c->flags & AT_READREG) != 0 && 1635 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1636 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1637 ata_c->r_head = bus_space_read_1(chp->cmd_iot, 1638 chp->cmd_iohs[wd_sdh], 0); 1639 ata_c->r_count = bus_space_read_1(chp->cmd_iot, 1640 chp->cmd_iohs[wd_seccnt], 0); 1641 ata_c->r_sector = bus_space_read_1(chp->cmd_iot, 1642 chp->cmd_iohs[wd_sector], 0); 1643 ata_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1644 chp->cmd_iohs[wd_cyl_lo], 0); 1645 ata_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1646 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1647 ata_c->r_error = bus_space_read_1(chp->cmd_iot, 1648 chp->cmd_iohs[wd_error], 0); 1649 ata_c->r_features = bus_space_read_1(chp->cmd_iot, 1650 chp->cmd_iohs[wd_features], 0); 1651 } 1652 callout_stop(&chp->ch_callout); 1653 chp->ch_queue->active_xfer = NULL; 1654 if (ata_c->flags & AT_POLL) { 1655 /* enable interrupts */ 1656 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1657 WDCTL_4BIT); 1658 delay(10); /* some drives need a little delay here */ 1659 } 1660 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1661 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1662 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1663 wakeup(&chp->ch_queue->active_xfer); 1664 } else 1665 __wdccommand_done_end(chp, xfer); 1666 } 1667 1668 static void 1669 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1670 { 1671 struct ata_command *ata_c = xfer->c_cmd; 1672 1673 ata_c->flags |= AT_DONE; 1674 ata_free_xfer(chp, xfer); 1675 if (ata_c->flags & AT_WAIT) 1676 wakeup(ata_c); 1677 else if (ata_c->callback) 1678 ata_c->callback(ata_c->callback_arg); 1679 wdcstart(chp); 1680 return; 1681 } 1682 1683 static void 1684 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1685 int reason) 1686 { 1687 struct ata_command *ata_c = xfer->c_cmd; 1688 1689 switch (reason) { 1690 case KILL_GONE: 1691 ata_c->flags |= AT_GONE; 1692 break; 1693 case KILL_RESET: 1694 ata_c->flags |= AT_RESET; 1695 break; 1696 default: 1697 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1698 reason); 1699 panic("__wdccommand_kill_xfer"); 1700 } 1701 __wdccommand_done_end(chp, xfer); 1702 } 1703 1704 /* 1705 * Send a command. The drive should be ready. 1706 * Assumes interrupts are blocked. 1707 */ 1708 void 1709 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1710 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1711 u_int8_t features) 1712 { 1713 struct wdc_softc *wdc = chp->ch_wdc; 1714 1715 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1716 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1717 chp->ch_channel, drive, command, cylin, head, sector, count, 1718 features), DEBUG_FUNCS); 1719 1720 if (wdc->cap & WDC_CAPABILITY_SELECT) 1721 wdc->select(chp,drive); 1722 1723 /* Select drive, head, and addressing mode. */ 1724 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1725 WDSD_IBM | (drive << 4) | head); 1726 /* Load parameters into the wd_features register. */ 1727 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 1728 features); 1729 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1730 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1731 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1732 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1733 0, cylin >> 8); 1734 1735 /* Send command. */ 1736 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1737 return; 1738 } 1739 1740 /* 1741 * Send a 48-bit addressing command. The drive should be ready. 1742 * Assumes interrupts are blocked. 1743 */ 1744 void 1745 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1746 u_int64_t blkno, u_int16_t count) 1747 { 1748 struct wdc_softc *wdc = chp->ch_wdc; 1749 1750 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1751 "count=%d\n", wdc->sc_dev.dv_xname, 1752 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1753 DEBUG_FUNCS); 1754 1755 if (wdc->cap & WDC_CAPABILITY_SELECT) 1756 wdc->select(chp,drive); 1757 1758 /* Select drive, head, and addressing mode. */ 1759 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1760 (drive << 4) | WDSD_LBA); 1761 1762 /* previous */ 1763 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1764 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1765 0, count >> 8); 1766 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1767 0, blkno >> 24); 1768 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1769 0, blkno >> 32); 1770 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1771 0, blkno >> 40); 1772 1773 /* current */ 1774 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1775 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1776 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1777 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1778 0, blkno >> 8); 1779 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1780 0, blkno >> 16); 1781 1782 /* Send command. */ 1783 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1784 return; 1785 } 1786 1787 /* 1788 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1789 * tested by the caller. 1790 */ 1791 void 1792 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1793 { 1794 struct wdc_softc *wdc = chp->ch_wdc; 1795 1796 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1797 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1798 DEBUG_FUNCS); 1799 1800 if (wdc->cap & WDC_CAPABILITY_SELECT) 1801 wdc->select(chp,drive); 1802 1803 /* Select drive. */ 1804 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1805 WDSD_IBM | (drive << 4)); 1806 1807 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1808 } 1809 1810 static void 1811 __wdcerror(struct wdc_channel *chp, char *msg) 1812 { 1813 struct wdc_softc *wdc = chp->ch_wdc; 1814 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1815 1816 if (xfer == NULL) 1817 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 1818 msg); 1819 else 1820 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 1821 chp->ch_channel, xfer->c_drive, msg); 1822 } 1823 1824 /* 1825 * the bit bucket 1826 */ 1827 void 1828 wdcbit_bucket(struct wdc_channel *chp, int size) 1829 { 1830 1831 for (; size >= 2; size -= 2) 1832 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1833 if (size) 1834 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 1835 } 1836 1837 void 1838 wdc_datain_pio(chp, flags, buf, len) 1839 struct wdc_channel *chp; 1840 int flags; 1841 void *buf; 1842 size_t len; 1843 { 1844 1845 if (flags & DRIVE_NOSTREAM) { 1846 if (flags & DRIVE_CAP32) { 1847 bus_space_read_multi_4(chp->data32iot, 1848 chp->data32ioh, 0, buf, len >> 2); 1849 buf = (char *)buf + (len & ~3); 1850 len &= 3; 1851 } 1852 if (len) { 1853 bus_space_read_multi_2(chp->cmd_iot, 1854 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 1855 } 1856 } else { 1857 if (flags & DRIVE_CAP32) { 1858 bus_space_read_multi_stream_4(chp->data32iot, 1859 chp->data32ioh, 0, buf, len >> 2); 1860 buf = (char *)buf + (len & ~3); 1861 len &= 3; 1862 } 1863 if (len) { 1864 bus_space_read_multi_stream_2(chp->cmd_iot, 1865 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 1866 } 1867 } 1868 } 1869 1870 void 1871 wdc_dataout_pio(chp, flags, buf, len) 1872 struct wdc_channel *chp; 1873 int flags; 1874 void *buf; 1875 size_t len; 1876 { 1877 1878 if (flags & DRIVE_NOSTREAM) { 1879 if (flags & DRIVE_CAP32) { 1880 bus_space_write_multi_4(chp->data32iot, 1881 chp->data32ioh, 0, buf, len >> 2); 1882 buf = (char *)buf + (len & ~3); 1883 len &= 3; 1884 } 1885 if (len) { 1886 bus_space_write_multi_2(chp->cmd_iot, 1887 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 1888 } 1889 } else { 1890 if (flags & DRIVE_CAP32) { 1891 bus_space_write_multi_stream_4(chp->data32iot, 1892 chp->data32ioh, 0, buf, len >> 2); 1893 buf = (char *)buf + (len & ~3); 1894 len &= 3; 1895 } 1896 if (len) { 1897 bus_space_write_multi_stream_2(chp->cmd_iot, 1898 chp->cmd_iohs[wd_data], 0, buf, len >> 1); 1899 } 1900 } 1901 } 1902
Indexes created Tue Sep 23 23:09:58 GMT 2025