wdc.c revision 1.205
1 /* $NetBSD: wdc.c,v 1.205 2004/08/14 15:08:05 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.205 2004/08/14 15:08:05 thorpej Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 #if NWD > 0 128 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 129 #else 130 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 131 const struct ata_bustype wdc_ata_bustype = { 132 SCSIPI_BUSTYPE_ATA, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 NULL 140 }; 141 #endif 142 143 static int wdcprobe1(struct ata_channel*, int); 144 static void __wdcerror(struct ata_channel*, char *); 145 static int __wdcwait_reset(struct ata_channel *, int, int); 146 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 147 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_kill_xfer(struct ata_channel *, 149 struct ata_xfer *, int); 150 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 152 static int __wdcwait(struct ata_channel *, int, int, int); 153 154 #define DEBUG_INTR 0x01 155 #define DEBUG_XFERS 0x02 156 #define DEBUG_STATUS 0x04 157 #define DEBUG_FUNCS 0x08 158 #define DEBUG_PROBE 0x10 159 #define DEBUG_DETACH 0x20 160 #define DEBUG_DELAY 0x40 161 #ifdef ATADEBUG 162 extern int atadebug_mask; /* init'ed in ata.c */ 163 int wdc_nxfer = 0; 164 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 165 #else 166 #define ATADEBUG_PRINT(args, level) 167 #endif 168 169 /* 170 * A queue of atabus instances, used to ensure the same bus probe order 171 * for a given hardware configuration at each boot. 172 */ 173 struct atabus_initq_head atabus_initq_head = 174 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 175 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct ata_channel *chp) 182 { 183 struct wdc_regs *wdr = &chp->ch_wdc->regs[chp->ch_channel]; 184 185 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 186 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 187 } 188 189 /* 190 * Allocate a wdc_regs array, based on the number of channels. 191 */ 192 void 193 wdc_allocate_regs(struct wdc_softc *wdc) 194 { 195 196 wdc->regs = malloc(wdc->nchannels * sizeof(struct wdc_regs), 197 M_DEVBUF, M_WAITOK); 198 } 199 200 /* Test to see controller with at last one attached drive is there. 201 * Returns a bit for each possible drive found (0x01 for drive 0, 202 * 0x02 for drive 1). 203 * Logic: 204 * - If a status register is at 0xff, assume there is no drive here 205 * (ISA has pull-up resistors). Similarly if the status register has 206 * the value we last wrote to the bus (for IDE interfaces without pullups). 207 * If no drive at all -> return. 208 * - reset the controller, wait for it to complete (may take up to 31s !). 209 * If timeout -> return. 210 * - test ATA/ATAPI signatures. If at last one drive found -> return. 211 * - try an ATA command on the master. 212 */ 213 214 static void 215 wdc_drvprobe(struct ata_channel *chp) 216 { 217 struct ataparams params; 218 struct wdc_softc *wdc = chp->ch_wdc; 219 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 220 u_int8_t st0 = 0, st1 = 0; 221 int i, error; 222 223 if (wdcprobe1(chp, 0) == 0) { 224 /* No drives, abort the attach here. */ 225 return; 226 } 227 228 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 229 for (i = 0; i < mstohz(3000); i++) { 230 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 231 if (wdc != NULL && wdc->select) 232 wdc->select(chp,0); 233 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 234 0, WDSD_IBM); 235 delay(10); /* 400ns delay */ 236 st0 = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_status], 0); 238 } 239 240 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 241 if (wdc != NULL && wdc->select) 242 wdc->select(chp,1); 243 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 244 0, WDSD_IBM | 0x10); 245 delay(10); /* 400ns delay */ 246 st1 = bus_space_read_1(wdr->cmd_iot, 247 wdr->cmd_iohs[wd_status], 0); 248 } 249 250 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 251 == 0 || 252 (st0 & WDCS_DRDY)) && 253 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 254 == 0 || 255 (st1 & WDCS_DRDY))) 256 break; 257 tsleep(¶ms, PRIBIO, "atadrdy", 1); 258 } 259 if ((st0 & WDCS_DRDY) == 0) 260 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 261 if ((st1 & WDCS_DRDY) == 0) 262 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 263 264 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 265 wdc->sc_dev.dv_xname, 266 chp->ch_channel, st0, st1), DEBUG_PROBE); 267 268 /* Wait a bit, some devices are weird just after a reset. */ 269 delay(5000); 270 271 for (i = 0; i < 2; i++) { 272 /* XXX This should be done by other code. */ 273 chp->ch_drive[i].chnl_softc = chp; 274 chp->ch_drive[i].drive = i; 275 276 /* 277 * Init error counter so that an error withing the first xfers 278 * will trigger a downgrade 279 */ 280 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 281 282 /* If controller can't do 16bit flag the drives as 32bit */ 283 if ((wdc->cap & 284 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 285 WDC_CAPABILITY_DATA32) 286 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 287 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 288 continue; 289 290 /* Shortcut in case we've been shutdown */ 291 if (chp->ch_flags & ATACH_SHUTDOWN) 292 return; 293 294 /* issue an identify, to try to detect ghosts */ 295 error = ata_get_params(&chp->ch_drive[i], 296 AT_WAIT | AT_POLL, ¶ms); 297 if (error != CMD_OK) { 298 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 299 300 /* Shortcut in case we've been shutdown */ 301 if (chp->ch_flags & ATACH_SHUTDOWN) 302 return; 303 304 error = ata_get_params(&chp->ch_drive[i], 305 AT_WAIT | AT_POLL, ¶ms); 306 } 307 if (error == CMD_OK) { 308 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 309 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 310 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 311 } else { 312 chp->ch_drive[i].drive_flags &= 313 ~(DRIVE_ATA | DRIVE_ATAPI); 314 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 315 wdc->sc_dev.dv_xname, 316 chp->ch_channel, i, error), DEBUG_PROBE); 317 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 318 continue; 319 /* 320 * Pre-ATA drive ? 321 * Test registers writability (Error register not 322 * writable, but cyllo is), then try an ATA command. 323 */ 324 if (wdc->select) 325 wdc->select(chp,i); 326 bus_space_write_1(wdr->cmd_iot, 327 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 328 delay(10); /* 400ns delay */ 329 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 330 0, 0x58); 331 bus_space_write_1(wdr->cmd_iot, 332 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 333 if (bus_space_read_1(wdr->cmd_iot, 334 wdr->cmd_iohs[wd_error], 0) == 0x58 || 335 bus_space_read_1(wdr->cmd_iot, 336 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 337 ATADEBUG_PRINT(("%s:%d:%d: register " 338 "writability failed\n", 339 wdc->sc_dev.dv_xname, 340 chp->ch_channel, i), DEBUG_PROBE); 341 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 342 continue; 343 } 344 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 345 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 346 wdc->sc_dev.dv_xname, 347 chp->ch_channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 continue; 350 } 351 bus_space_write_1(wdr->cmd_iot, 352 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 353 delay(10); /* 400ns delay */ 354 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 355 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 356 wdc->sc_dev.dv_xname, 357 chp->ch_channel, i), DEBUG_PROBE); 358 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 359 } else { 360 chp->ch_drive[0].drive_flags &= 361 ~(DRIVE_ATA | DRIVE_ATAPI); 362 chp->ch_drive[1].drive_flags &= 363 ~(DRIVE_ATA | DRIVE_ATAPI); 364 } 365 } 366 } 367 } 368 369 void 370 atabusconfig(struct atabus_softc *atabus_sc) 371 { 372 struct ata_channel *chp = atabus_sc->sc_chan; 373 struct wdc_softc *wdc = chp->ch_wdc; 374 int i; 375 struct atabus_initq *atabus_initq = NULL; 376 377 /* Probe for the drives. */ 378 (*wdc->drv_probe)(chp); 379 380 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 381 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 382 DEBUG_PROBE); 383 384 /* If no drives, abort here */ 385 for (i = 0; i < chp->ch_ndrive; i++) 386 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 387 break; 388 if (i == chp->ch_ndrive) 389 goto out; 390 391 /* Shortcut in case we've been shutdown */ 392 if (chp->ch_flags & ATACH_SHUTDOWN) 393 goto out; 394 395 /* Make sure the devices probe in atabus order to avoid jitter. */ 396 simple_lock(&atabus_interlock); 397 while(1) { 398 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 399 if (atabus_initq->atabus_sc == atabus_sc) 400 break; 401 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 402 &atabus_interlock); 403 } 404 simple_unlock(&atabus_interlock); 405 406 /* 407 * Attach an ATAPI bus, if needed. 408 */ 409 for (i = 0; i < chp->ch_ndrive; i++) { 410 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 411 #if NATAPIBUS > 0 412 wdc_atapibus_attach(atabus_sc); 413 #else 414 /* 415 * Fake the autoconfig "not configured" message 416 */ 417 aprint_normal("atapibus at %s not configured\n", 418 wdc->sc_dev.dv_xname); 419 chp->atapibus = NULL; 420 for (i = 0; i < chp->ch_ndrive; i++) 421 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 422 #endif 423 break; 424 } 425 } 426 427 for (i = 0; i < chp->ch_ndrive; i++) { 428 struct ata_device adev; 429 if ((chp->ch_drive[i].drive_flags & 430 (DRIVE_ATA | DRIVE_OLD)) == 0) { 431 continue; 432 } 433 memset(&adev, 0, sizeof(struct ata_device)); 434 adev.adev_bustype = &wdc_ata_bustype; 435 adev.adev_channel = chp->ch_channel; 436 adev.adev_openings = 1; 437 adev.adev_drv_data = &chp->ch_drive[i]; 438 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 439 &adev, ataprint); 440 if (chp->ata_drives[i] != NULL) 441 ata_probe_caps(&chp->ch_drive[i]); 442 else 443 chp->ch_drive[i].drive_flags &= 444 ~(DRIVE_ATA | DRIVE_OLD); 445 } 446 447 /* now that we know the drives, the controller can set its modes */ 448 if (wdc->set_modes) { 449 wdc->set_modes(chp); 450 ata_print_modes(chp); 451 } 452 #if NATARAID > 0 453 if (wdc->cap & WDC_CAPABILITY_RAID) 454 for (i = 0; i < chp->ch_ndrive; i++) 455 if (chp->ata_drives[i] != NULL) 456 ata_raid_check_component(chp->ata_drives[i]); 457 #endif /* NATARAID > 0 */ 458 459 /* 460 * reset drive_flags for unattached devices, reset state for attached 461 * ones 462 */ 463 for (i = 0; i < chp->ch_ndrive; i++) { 464 if (chp->ch_drive[i].drv_softc == NULL) 465 chp->ch_drive[i].drive_flags = 0; 466 else 467 chp->ch_drive[i].state = 0; 468 } 469 470 out: 471 if (atabus_initq == NULL) { 472 simple_lock(&atabus_interlock); 473 while(1) { 474 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 475 if (atabus_initq->atabus_sc == atabus_sc) 476 break; 477 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 478 &atabus_interlock); 479 } 480 simple_unlock(&atabus_interlock); 481 } 482 simple_lock(&atabus_interlock); 483 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 484 simple_unlock(&atabus_interlock); 485 486 free(atabus_initq, M_DEVBUF); 487 wakeup(&atabus_initq_head); 488 489 ata_delref(chp); 490 491 config_pending_decr(); 492 } 493 494 int 495 wdcprobe(struct ata_channel *chp) 496 { 497 498 return (wdcprobe1(chp, 1)); 499 } 500 501 static int 502 wdcprobe1(struct ata_channel *chp, int poll) 503 { 504 struct wdc_softc *wdc = chp->ch_wdc; 505 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 506 u_int8_t st0, st1, sc, sn, cl, ch; 507 u_int8_t ret_value = 0x03; 508 u_int8_t drive; 509 int s; 510 511 /* 512 * Sanity check to see if the wdc channel responds at all. 513 */ 514 515 s = splbio(); 516 if (wdc == NULL || 517 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 518 519 if (wdc != NULL && wdc->select) 520 wdc->select(chp,0); 521 522 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 523 WDSD_IBM); 524 delay(10); /* 400ns delay */ 525 st0 = bus_space_read_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_status], 0); 527 528 if (wdc != NULL && wdc->select) 529 wdc->select(chp,1); 530 531 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 532 WDSD_IBM | 0x10); 533 delay(10); /* 400ns delay */ 534 st1 = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_status], 0); 536 537 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 538 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 539 chp->ch_channel, st0, st1), DEBUG_PROBE); 540 541 if (st0 == 0xff || st0 == WDSD_IBM) 542 ret_value &= ~0x01; 543 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 544 ret_value &= ~0x02; 545 /* Register writability test, drive 0. */ 546 if (ret_value & 0x01) { 547 if (wdc != NULL && wdc->select) 548 wdc->select(chp,0); 549 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 550 0, WDSD_IBM); 551 bus_space_write_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 553 cl = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_cyl_lo], 0); 555 if (cl != 0x02) { 556 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 557 "got 0x%x != 0x02\n", 558 wdc != NULL ? 559 wdc->sc_dev.dv_xname : "wdcprobe", 560 chp->ch_channel, cl), 561 DEBUG_PROBE); 562 ret_value &= ~0x01; 563 } 564 bus_space_write_1(wdr->cmd_iot, 565 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 566 cl = bus_space_read_1(wdr->cmd_iot, 567 wdr->cmd_iohs[wd_cyl_lo], 0); 568 if (cl != 0x01) { 569 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 570 "got 0x%x != 0x01\n", 571 wdc != NULL ? 572 wdc->sc_dev.dv_xname : "wdcprobe", 573 chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 bus_space_write_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_sector], 0, 0x01); 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0); 581 if (cl != 0x01) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 583 "got 0x%x != 0x01\n", 584 wdc != NULL ? 585 wdc->sc_dev.dv_xname : "wdcprobe", 586 chp->ch_channel, cl), 587 DEBUG_PROBE); 588 ret_value &= ~0x01; 589 } 590 bus_space_write_1(wdr->cmd_iot, 591 wdr->cmd_iohs[wd_sector], 0, 0x02); 592 cl = bus_space_read_1(wdr->cmd_iot, 593 wdr->cmd_iohs[wd_sector], 0); 594 if (cl != 0x02) { 595 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 596 "got 0x%x != 0x02\n", 597 wdc != NULL ? 598 wdc->sc_dev.dv_xname : "wdcprobe", 599 chp->ch_channel, cl), 600 DEBUG_PROBE); 601 ret_value &= ~0x01; 602 } 603 cl = bus_space_read_1(wdr->cmd_iot, 604 wdr->cmd_iohs[wd_cyl_lo], 0); 605 if (cl != 0x01) { 606 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 607 "got 0x%x != 0x01\n", 608 wdc != NULL ? 609 wdc->sc_dev.dv_xname : "wdcprobe", 610 chp->ch_channel, cl), 611 DEBUG_PROBE); 612 ret_value &= ~0x01; 613 } 614 } 615 /* Register writability test, drive 1. */ 616 if (ret_value & 0x02) { 617 if (wdc != NULL && wdc->select) 618 wdc->select(chp,1); 619 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 620 0, WDSD_IBM | 0x10); 621 bus_space_write_1(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 623 cl = bus_space_read_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_cyl_lo], 0); 625 if (cl != 0x02) { 626 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 627 "got 0x%x != 0x02\n", 628 wdc != NULL ? 629 wdc->sc_dev.dv_xname : "wdcprobe", 630 chp->ch_channel, cl), 631 DEBUG_PROBE); 632 ret_value &= ~0x02; 633 } 634 bus_space_write_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 636 cl = bus_space_read_1(wdr->cmd_iot, 637 wdr->cmd_iohs[wd_cyl_lo], 0); 638 if (cl != 0x01) { 639 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 640 "got 0x%x != 0x01\n", 641 wdc != NULL ? 642 wdc->sc_dev.dv_xname : "wdcprobe", 643 chp->ch_channel, cl), 644 DEBUG_PROBE); 645 ret_value &= ~0x02; 646 } 647 bus_space_write_1(wdr->cmd_iot, 648 wdr->cmd_iohs[wd_sector], 0, 0x01); 649 cl = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0); 651 if (cl != 0x01) { 652 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 653 "got 0x%x != 0x01\n", 654 wdc != NULL ? 655 wdc->sc_dev.dv_xname : "wdcprobe", 656 chp->ch_channel, cl), 657 DEBUG_PROBE); 658 ret_value &= ~0x02; 659 } 660 bus_space_write_1(wdr->cmd_iot, 661 wdr->cmd_iohs[wd_sector], 0, 0x02); 662 cl = bus_space_read_1(wdr->cmd_iot, 663 wdr->cmd_iohs[wd_sector], 0); 664 if (cl != 0x02) { 665 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 666 "got 0x%x != 0x02\n", 667 wdc != NULL ? 668 wdc->sc_dev.dv_xname : "wdcprobe", 669 chp->ch_channel, cl), 670 DEBUG_PROBE); 671 ret_value &= ~0x02; 672 } 673 cl = bus_space_read_1(wdr->cmd_iot, 674 wdr->cmd_iohs[wd_cyl_lo], 0); 675 if (cl != 0x01) { 676 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 677 "got 0x%x != 0x01\n", 678 wdc != NULL ? 679 wdc->sc_dev.dv_xname : "wdcprobe", 680 chp->ch_channel, cl), 681 DEBUG_PROBE); 682 ret_value &= ~0x02; 683 } 684 } 685 686 if (ret_value == 0) { 687 splx(s); 688 return 0; 689 } 690 } 691 692 693 #if 0 /* XXX this break some ATA or ATAPI devices */ 694 /* 695 * reset bus. Also send an ATAPI_RESET to devices, in case there are 696 * ATAPI device out there which don't react to the bus reset 697 */ 698 if (ret_value & 0x01) { 699 if (wdc != NULL && wdc->select) 700 wdc->select(chp,0); 701 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 702 0, WDSD_IBM); 703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 704 ATAPI_SOFT_RESET); 705 } 706 if (ret_value & 0x02) { 707 if (wdc != NULL && wdc->select) 708 wdc->select(chp,0); 709 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 710 0, WDSD_IBM | 0x10); 711 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 712 ATAPI_SOFT_RESET); 713 } 714 715 delay(5000); 716 #endif 717 718 if (wdc != NULL && wdc->select) 719 wdc->select(chp,0); 720 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 721 delay(10); /* 400ns delay */ 722 /* assert SRST, wait for reset to complete */ 723 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 724 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 725 DELAY(1000); 726 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 727 WDCTL_IDS | WDCTL_4BIT); 728 DELAY(2000); 729 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 730 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 731 delay(10); /* 400ns delay */ 732 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 733 if (wdc != NULL && wdc->irqack != NULL) 734 wdc->irqack(chp); 735 splx(s); 736 737 ret_value = __wdcwait_reset(chp, ret_value, poll); 738 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 739 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 740 ret_value), DEBUG_PROBE); 741 742 /* if reset failed, there's nothing here */ 743 if (ret_value == 0) 744 return 0; 745 746 /* 747 * Test presence of drives. First test register signatures looking 748 * for ATAPI devices. If it's not an ATAPI and reset said there may 749 * be something here assume it's ATA or OLD. Ghost will be killed 750 * later in attach routine. 751 */ 752 for (drive = 0; drive < 2; drive++) { 753 if ((ret_value & (0x01 << drive)) == 0) 754 continue; 755 if (wdc != NULL && wdc->select) 756 wdc->select(chp,drive); 757 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 758 WDSD_IBM | (drive << 4)); 759 delay(10); /* 400ns delay */ 760 /* Save registers contents */ 761 sc = bus_space_read_1(wdr->cmd_iot, 762 wdr->cmd_iohs[wd_seccnt], 0); 763 sn = bus_space_read_1(wdr->cmd_iot, 764 wdr->cmd_iohs[wd_sector], 0); 765 cl = bus_space_read_1(wdr->cmd_iot, 766 wdr->cmd_iohs[wd_cyl_lo], 0); 767 ch = bus_space_read_1(wdr->cmd_iot, 768 wdr->cmd_iohs[wd_cyl_hi], 0); 769 770 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 771 "cl=0x%x ch=0x%x\n", 772 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 773 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 774 /* 775 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 776 * we get wrong values here, so ignore it. 777 */ 778 if (cl == 0x14 && ch == 0xeb) { 779 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 780 } else { 781 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 782 if (wdc == NULL || 783 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 784 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 785 } 786 } 787 return (ret_value); 788 } 789 790 void 791 wdcattach(struct ata_channel *chp) 792 { 793 struct wdc_softc *wdc = chp->ch_wdc; 794 795 if (chp->ch_flags & ATACH_DISABLED) 796 return; 797 798 /* 799 * Start out assuming 2 drives. This may change as we probe 800 * drives. 801 */ 802 chp->ch_ndrive = 2; 803 804 /* default data transfer methods */ 805 if (!wdc->datain_pio) 806 wdc->datain_pio = wdc_datain_pio; 807 if (!wdc->dataout_pio) 808 wdc->dataout_pio = wdc_dataout_pio; 809 810 /* initialise global data */ 811 callout_init(&chp->ch_callout); 812 if (wdc->drv_probe == NULL) 813 wdc->drv_probe = wdc_drvprobe; 814 815 TAILQ_INIT(&chp->ch_queue->queue_xfer); 816 chp->ch_queue->queue_freeze = 0; 817 chp->ch_queue->active_xfer = NULL; 818 819 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 820 } 821 822 int 823 wdcactivate(struct device *self, enum devact act) 824 { 825 struct wdc_softc *wdc = (struct wdc_softc *)self; 826 int s, i, error = 0; 827 828 s = splbio(); 829 switch (act) { 830 case DVACT_ACTIVATE: 831 error = EOPNOTSUPP; 832 break; 833 834 case DVACT_DEACTIVATE: 835 for (i = 0; i < wdc->nchannels; i++) { 836 error = config_deactivate(wdc->channels[i]->atabus); 837 if (error) 838 break; 839 } 840 break; 841 } 842 splx(s); 843 return (error); 844 } 845 846 int 847 wdcdetach(struct device *self, int flags) 848 { 849 struct wdc_softc *wdc = (struct wdc_softc *)self; 850 struct ata_channel *chp; 851 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 852 int i, error = 0; 853 854 for (i = 0; i < wdc->nchannels; i++) { 855 chp = wdc->channels[i]; 856 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 857 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 858 error = config_detach(chp->atabus, flags); 859 if (error) 860 break; 861 } 862 if (adapt->adapt_refcnt != 0) { 863 #ifdef DIAGNOSTIC 864 printf("wdcdetach: refcnt should be 0 here??\n"); 865 #endif 866 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 867 } 868 return (error); 869 } 870 871 /* restart an interrupted I/O */ 872 void 873 wdcrestart(void *v) 874 { 875 struct ata_channel *chp = v; 876 int s; 877 878 s = splbio(); 879 atastart(chp); 880 splx(s); 881 } 882 883 884 /* 885 * Interrupt routine for the controller. Acknowledge the interrupt, check for 886 * errors on the current operation, mark it done if necessary, and start the 887 * next request. Also check for a partially done transfer, and continue with 888 * the next chunk if so. 889 */ 890 int 891 wdcintr(void *arg) 892 { 893 struct ata_channel *chp = arg; 894 struct wdc_softc *wdc = chp->ch_wdc; 895 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 896 struct ata_xfer *xfer; 897 int ret; 898 899 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 900 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 901 DEBUG_INTR); 902 return (0); 903 } 904 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 905 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 906 /* try to clear the pending interrupt anyway */ 907 (void)bus_space_read_1(wdr->cmd_iot, 908 wdr->cmd_iohs[wd_status], 0); 909 return (0); 910 } 911 912 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 913 xfer = chp->ch_queue->active_xfer; 914 #ifdef DIAGNOSTIC 915 if (xfer == NULL) 916 panic("wdcintr: no xfer"); 917 #endif 918 if (chp->ch_flags & ATACH_DMA_WAIT) { 919 wdc->dma_status = 920 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 921 xfer->c_drive, WDC_DMAEND_END); 922 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 923 /* IRQ not for us, not detected by DMA engine */ 924 return 0; 925 } 926 chp->ch_flags &= ~ATACH_DMA_WAIT; 927 } 928 chp->ch_flags &= ~ATACH_IRQ_WAIT; 929 ret = xfer->c_intr(chp, xfer, 1); 930 if (ret == 0) /* irq was not for us, still waiting for irq */ 931 chp->ch_flags |= ATACH_IRQ_WAIT; 932 return (ret); 933 } 934 935 /* Put all disk in RESET state */ 936 void 937 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 938 { 939 struct ata_channel *chp = drvp->chnl_softc; 940 struct wdc_softc *wdc = chp->ch_wdc; 941 ATADEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 942 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 943 DEBUG_FUNCS); 944 945 946 wdc_reset_channel(chp, flags); 947 } 948 949 void 950 wdc_reset_channel(struct ata_channel *chp, int flags) 951 { 952 TAILQ_HEAD(, ata_xfer) reset_xfer; 953 struct ata_xfer *xfer, *next_xfer; 954 int drive; 955 956 chp->ch_queue->queue_freeze++; 957 TAILQ_INIT(&reset_xfer); 958 959 /* if we can poll or wait it's OK, otherwise wake up the kernel 960 * thread 961 */ 962 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 963 if (chp->ch_flags & ATACH_TH_RESET) { 964 /* no need to schedule a reset more than one time */ 965 return; 966 } 967 chp->ch_flags |= ATACH_TH_RESET; 968 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 969 wakeup(&chp->ch_thread); 970 return; 971 } 972 973 chp->ch_flags &= ~ATACH_IRQ_WAIT; 974 /* 975 * if the current command if on an ATAPI device, issue a 976 * ATAPI_SOFT_RESET 977 */ 978 xfer = chp->ch_queue->active_xfer; 979 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 980 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 981 if (flags & AT_WAIT) 982 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 983 else 984 delay(1000); 985 } 986 987 /* reset the channel */ 988 if (flags & AT_WAIT) 989 (void) wdcreset(chp, RESET_SLEEP); 990 else 991 (void) wdcreset(chp, RESET_POLL); 992 993 /* 994 * wait a bit after reset; in case the DMA engines needs some time 995 * to recover. 996 */ 997 if (flags & AT_WAIT) 998 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 999 else 1000 delay(1000); 1001 /* 1002 * look for pending xfers. If we have a shared queue, we'll also reset 1003 * the other channel if the current xfer is running on it. 1004 * Then we'll dequeue only the xfers for this channel. 1005 */ 1006 if ((flags & AT_RST_NOCMD) == 0) { 1007 /* 1008 * move all xfers queued for this channel to the reset queue, 1009 * and then process the current xfer and then the reset queue. 1010 * We have to use a temporary queue because c_kill_xfer() 1011 * may requeue commands. 1012 */ 1013 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1014 xfer != NULL; xfer = next_xfer) { 1015 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1016 if (xfer->c_chp != chp) 1017 continue; 1018 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1019 xfer, c_xferchain); 1020 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1021 } 1022 xfer = chp->ch_queue->active_xfer; 1023 if (xfer) { 1024 if (xfer->c_chp != chp) 1025 wdc_reset_channel(xfer->c_chp, flags); 1026 else { 1027 callout_stop(&chp->ch_callout); 1028 /* 1029 * If we're waiting for DMA, stop the 1030 * DMA engine 1031 */ 1032 if (chp->ch_flags & ATACH_DMA_WAIT) { 1033 (*chp->ch_wdc->dma_finish)( 1034 chp->ch_wdc->dma_arg, 1035 chp->ch_channel, 1036 xfer->c_drive, 1037 WDC_DMAEND_ABRT_QUIET); 1038 chp->ch_flags &= ~ATACH_DMA_WAIT; 1039 } 1040 chp->ch_queue->active_xfer = NULL; 1041 if ((flags & AT_RST_EMERG) == 0) 1042 xfer->c_kill_xfer( 1043 chp, xfer, KILL_RESET); 1044 } 1045 } 1046 1047 for (xfer = TAILQ_FIRST(&reset_xfer); 1048 xfer != NULL; xfer = next_xfer) { 1049 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1050 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1051 if ((flags & AT_RST_EMERG) == 0) 1052 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1053 } 1054 } 1055 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1056 chp->ch_drive[drive].state = 0; 1057 } 1058 chp->ch_flags &= ~ATACH_TH_RESET; 1059 if ((flags & AT_RST_EMERG) == 0) { 1060 chp->ch_queue->queue_freeze--; 1061 atastart(chp); 1062 } else { 1063 /* make sure that we can use polled commands */ 1064 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1065 chp->ch_queue->queue_freeze = 0; 1066 chp->ch_queue->active_xfer = NULL; 1067 } 1068 } 1069 1070 int 1071 wdcreset(struct ata_channel *chp, int poll) 1072 { 1073 struct wdc_softc *wdc = chp->ch_wdc; 1074 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1075 int drv_mask1, drv_mask2; 1076 int s = 0; 1077 1078 if (wdc->select) 1079 wdc->select(chp,0); 1080 if (poll != RESET_SLEEP) 1081 s = splbio(); 1082 /* master */ 1083 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1084 delay(10); /* 400ns delay */ 1085 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1086 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1087 delay(2000); 1088 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1089 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1090 WDCTL_4BIT | WDCTL_IDS); 1091 delay(10); /* 400ns delay */ 1092 if (poll != RESET_SLEEP) { 1093 if (wdc->irqack) 1094 wdc->irqack(chp); 1095 splx(s); 1096 } 1097 1098 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1099 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1100 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1101 (poll == RESET_SLEEP) ? 0 : 1); 1102 if (drv_mask2 != drv_mask1) { 1103 printf("%s channel %d: reset failed for", 1104 wdc->sc_dev.dv_xname, chp->ch_channel); 1105 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1106 printf(" drive 0"); 1107 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1108 printf(" drive 1"); 1109 printf("\n"); 1110 } 1111 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1112 return (drv_mask1 != drv_mask2) ? 1 : 0; 1113 } 1114 1115 static int 1116 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1117 { 1118 struct wdc_softc *wdc = chp->ch_wdc; 1119 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1120 int timeout, nloop; 1121 u_int8_t st0 = 0, st1 = 0; 1122 #ifdef ATADEBUG 1123 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1124 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1125 #endif 1126 1127 if (poll) 1128 nloop = WDCNDELAY_RST; 1129 else 1130 nloop = WDC_RESET_WAIT * hz / 1000; 1131 /* wait for BSY to deassert */ 1132 for (timeout = 0; timeout < nloop; timeout++) { 1133 if ((drv_mask & 0x01) != 0) { 1134 if (wdc && wdc->select) 1135 wdc->select(chp,0); 1136 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1137 0, WDSD_IBM); /* master */ 1138 delay(10); 1139 st0 = bus_space_read_1(wdr->cmd_iot, 1140 wdr->cmd_iohs[wd_status], 0); 1141 #ifdef ATADEBUG 1142 sc0 = bus_space_read_1(wdr->cmd_iot, 1143 wdr->cmd_iohs[wd_seccnt], 0); 1144 sn0 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_sector], 0); 1146 cl0 = bus_space_read_1(wdr->cmd_iot, 1147 wdr->cmd_iohs[wd_cyl_lo], 0); 1148 ch0 = bus_space_read_1(wdr->cmd_iot, 1149 wdr->cmd_iohs[wd_cyl_hi], 0); 1150 #endif 1151 } 1152 if ((drv_mask & 0x02) != 0) { 1153 if (wdc && wdc->select) 1154 wdc->select(chp,1); 1155 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1156 0, WDSD_IBM | 0x10); /* slave */ 1157 delay(10); 1158 st1 = bus_space_read_1(wdr->cmd_iot, 1159 wdr->cmd_iohs[wd_status], 0); 1160 #ifdef ATADEBUG 1161 sc1 = bus_space_read_1(wdr->cmd_iot, 1162 wdr->cmd_iohs[wd_seccnt], 0); 1163 sn1 = bus_space_read_1(wdr->cmd_iot, 1164 wdr->cmd_iohs[wd_sector], 0); 1165 cl1 = bus_space_read_1(wdr->cmd_iot, 1166 wdr->cmd_iohs[wd_cyl_lo], 0); 1167 ch1 = bus_space_read_1(wdr->cmd_iot, 1168 wdr->cmd_iohs[wd_cyl_hi], 0); 1169 #endif 1170 } 1171 1172 if ((drv_mask & 0x01) == 0) { 1173 /* no master */ 1174 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1175 /* No master, slave is ready, it's done */ 1176 goto end; 1177 } 1178 } else if ((drv_mask & 0x02) == 0) { 1179 /* no slave */ 1180 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1181 /* No slave, master is ready, it's done */ 1182 goto end; 1183 } 1184 } else { 1185 /* Wait for both master and slave to be ready */ 1186 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1187 goto end; 1188 } 1189 } 1190 if (poll) 1191 delay(WDCDELAY); 1192 else 1193 tsleep(&nloop, PRIBIO, "atarst", 1); 1194 } 1195 /* Reset timed out. Maybe it's because drv_mask was not right */ 1196 if (st0 & WDCS_BSY) 1197 drv_mask &= ~0x01; 1198 if (st1 & WDCS_BSY) 1199 drv_mask &= ~0x02; 1200 end: 1201 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1202 "cl=0x%x ch=0x%x\n", 1203 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1204 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1205 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1206 "cl=0x%x ch=0x%x\n", 1207 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1208 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1209 1210 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1211 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1212 st0, st1), DEBUG_PROBE); 1213 1214 return drv_mask; 1215 } 1216 1217 /* 1218 * Wait for a drive to be !BSY, and have mask in its status register. 1219 * return -1 for a timeout after "timeout" ms. 1220 */ 1221 static int 1222 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1223 { 1224 struct wdc_softc *wdc = chp->ch_wdc; 1225 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1226 u_char status; 1227 int time = 0; 1228 1229 ATADEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1230 wdc->sc_dev.dv_xname : "none", 1231 chp->ch_channel), DEBUG_STATUS); 1232 chp->ch_error = 0; 1233 1234 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1235 1236 for (;;) { 1237 chp->ch_status = status = 1238 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1239 if ((status & (WDCS_BSY | mask)) == bits) 1240 break; 1241 if (++time > timeout) { 1242 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1243 "status %x error %x (mask 0x%x bits 0x%x)\n", 1244 time, status, 1245 bus_space_read_1(wdr->cmd_iot, 1246 wdr->cmd_iohs[wd_error], 0), mask, bits), 1247 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1248 return(WDCWAIT_TOUT); 1249 } 1250 delay(WDCDELAY); 1251 } 1252 #ifdef ATADEBUG 1253 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1254 printf("__wdcwait: did busy-wait, time=%d\n", time); 1255 #endif 1256 if (status & WDCS_ERR) 1257 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1258 wdr->cmd_iohs[wd_error], 0); 1259 #ifdef WDCNDELAY_DEBUG 1260 /* After autoconfig, there should be no long delays. */ 1261 if (!cold && time > WDCNDELAY_DEBUG) { 1262 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1263 if (xfer == NULL) 1264 printf("%s channel %d: warning: busy-wait took %dus\n", 1265 wdc->sc_dev.dv_xname, chp->ch_channel, 1266 WDCDELAY * time); 1267 else 1268 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1269 wdc->sc_dev.dv_xname, chp->ch_channel, 1270 xfer->drive, 1271 WDCDELAY * time); 1272 } 1273 #endif 1274 return(WDCWAIT_OK); 1275 } 1276 1277 /* 1278 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1279 * thread if possible 1280 */ 1281 int 1282 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1283 { 1284 int error, i, timeout_hz = mstohz(timeout); 1285 1286 if (timeout_hz == 0 || 1287 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1288 error = __wdcwait(chp, mask, bits, timeout); 1289 else { 1290 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1291 if (error != 0) { 1292 if ((chp->ch_flags & ATACH_TH_RUN) || 1293 (flags & AT_WAIT)) { 1294 /* 1295 * we're running in the channel thread 1296 * or some userland thread context 1297 */ 1298 for (i = 0; i < timeout_hz; i++) { 1299 if (__wdcwait(chp, mask, bits, 1300 WDCDELAY_POLL) == 0) { 1301 error = 0; 1302 break; 1303 } 1304 tsleep(&chp, PRIBIO, "atapoll", 1); 1305 } 1306 } else { 1307 /* 1308 * we're probably in interrupt context, 1309 * ask the thread to come back here 1310 */ 1311 #ifdef DIAGNOSTIC 1312 if (chp->ch_queue->queue_freeze > 0) 1313 panic("wdcwait: queue_freeze"); 1314 #endif 1315 chp->ch_queue->queue_freeze++; 1316 wakeup(&chp->ch_thread); 1317 return(WDCWAIT_THR); 1318 } 1319 } 1320 } 1321 return (error); 1322 } 1323 1324 1325 /* 1326 * Busy-wait for DMA to complete 1327 */ 1328 int 1329 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1330 { 1331 struct wdc_softc *wdc = chp->ch_wdc; 1332 int time; 1333 1334 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1335 wdc->dma_status = 1336 (*wdc->dma_finish)(wdc->dma_arg, 1337 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1338 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1339 return 0; 1340 delay(WDCDELAY); 1341 } 1342 /* timeout, force a DMA halt */ 1343 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1344 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1345 return 1; 1346 } 1347 1348 void 1349 wdctimeout(void *arg) 1350 { 1351 struct ata_channel *chp = (struct ata_channel *)arg; 1352 struct wdc_softc *wdc = chp->ch_wdc; 1353 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1354 int s; 1355 1356 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1357 1358 s = splbio(); 1359 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1360 __wdcerror(chp, "lost interrupt"); 1361 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1362 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1363 xfer->c_bcount, 1364 xfer->c_skip); 1365 if (chp->ch_flags & ATACH_DMA_WAIT) { 1366 wdc->dma_status = 1367 (*wdc->dma_finish)(wdc->dma_arg, 1368 chp->ch_channel, xfer->c_drive, 1369 WDC_DMAEND_ABRT); 1370 chp->ch_flags &= ~ATACH_DMA_WAIT; 1371 } 1372 /* 1373 * Call the interrupt routine. If we just missed an interrupt, 1374 * it will do what's needed. Else, it will take the needed 1375 * action (reset the device). 1376 * Before that we need to reinstall the timeout callback, 1377 * in case it will miss another irq while in this transfer 1378 * We arbitray chose it to be 1s 1379 */ 1380 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1381 xfer->c_flags |= C_TIMEOU; 1382 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1383 xfer->c_intr(chp, xfer, 1); 1384 } else 1385 __wdcerror(chp, "missing untimeout"); 1386 splx(s); 1387 } 1388 1389 int 1390 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1391 { 1392 struct ata_channel *chp = drvp->chnl_softc; 1393 struct wdc_softc *wdc = chp->ch_wdc; 1394 struct ata_xfer *xfer; 1395 int s, ret; 1396 1397 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1398 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1399 DEBUG_FUNCS); 1400 1401 /* set up an xfer and queue. Wait for completion */ 1402 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1403 ATAXF_NOSLEEP); 1404 if (xfer == NULL) { 1405 return ATACMD_TRY_AGAIN; 1406 } 1407 1408 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1409 ata_c->flags |= AT_POLL; 1410 if (ata_c->flags & AT_POLL) 1411 xfer->c_flags |= C_POLL; 1412 xfer->c_drive = drvp->drive; 1413 xfer->c_databuf = ata_c->data; 1414 xfer->c_bcount = ata_c->bcount; 1415 xfer->c_cmd = ata_c; 1416 xfer->c_start = __wdccommand_start; 1417 xfer->c_intr = __wdccommand_intr; 1418 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1419 1420 s = splbio(); 1421 ata_exec_xfer(chp, xfer); 1422 #ifdef DIAGNOSTIC 1423 if ((ata_c->flags & AT_POLL) != 0 && 1424 (ata_c->flags & AT_DONE) == 0) 1425 panic("wdc_exec_command: polled command not done"); 1426 #endif 1427 if (ata_c->flags & AT_DONE) { 1428 ret = ATACMD_COMPLETE; 1429 } else { 1430 if (ata_c->flags & AT_WAIT) { 1431 while ((ata_c->flags & AT_DONE) == 0) { 1432 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1433 } 1434 ret = ATACMD_COMPLETE; 1435 } else { 1436 ret = ATACMD_QUEUED; 1437 } 1438 } 1439 splx(s); 1440 return ret; 1441 } 1442 1443 static void 1444 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1445 { 1446 struct wdc_softc *wdc = chp->ch_wdc; 1447 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1448 int drive = xfer->c_drive; 1449 struct ata_command *ata_c = xfer->c_cmd; 1450 1451 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1452 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1453 DEBUG_FUNCS); 1454 1455 if (wdc->select) 1456 wdc->select(chp,drive); 1457 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1458 WDSD_IBM | (drive << 4)); 1459 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1460 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1461 case WDCWAIT_OK: 1462 break; 1463 case WDCWAIT_TOUT: 1464 ata_c->flags |= AT_TIMEOU; 1465 __wdccommand_done(chp, xfer); 1466 return; 1467 case WDCWAIT_THR: 1468 return; 1469 } 1470 if (ata_c->flags & AT_POLL) { 1471 /* polled command, disable interrupts */ 1472 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1473 WDCTL_4BIT | WDCTL_IDS); 1474 } 1475 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1476 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1477 1478 if ((ata_c->flags & AT_POLL) == 0) { 1479 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1480 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1481 wdctimeout, chp); 1482 return; 1483 } 1484 /* 1485 * Polled command. Wait for drive ready or drq. Done in intr(). 1486 * Wait for at last 400ns for status bit to be valid. 1487 */ 1488 delay(10); /* 400ns delay */ 1489 __wdccommand_intr(chp, xfer, 0); 1490 } 1491 1492 static int 1493 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1494 { 1495 struct wdc_softc *wdc = chp->ch_wdc; 1496 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1497 struct ata_command *ata_c = xfer->c_cmd; 1498 int bcount = ata_c->bcount; 1499 char *data = ata_c->data; 1500 int wflags; 1501 1502 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1503 /* both wait and poll, we can tsleep here */ 1504 wflags = AT_WAIT | AT_POLL; 1505 } else { 1506 wflags = AT_POLL; 1507 } 1508 1509 again: 1510 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1511 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1512 DEBUG_INTR); 1513 /* 1514 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1515 * Reselect again, it doesn't hurt for others commands, and the time 1516 * penalty for the extra regiter write is acceptable, 1517 * wdc_exec_command() isn't called often (mosly for autoconfig) 1518 */ 1519 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1520 WDSD_IBM | (xfer->c_drive << 4)); 1521 if ((ata_c->flags & AT_XFDONE) != 0) { 1522 /* 1523 * We have completed a data xfer. The drive should now be 1524 * in its initial state 1525 */ 1526 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1527 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1528 wflags) == WDCWAIT_TOUT) { 1529 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1530 return 0; /* IRQ was not for us */ 1531 ata_c->flags |= AT_TIMEOU; 1532 } 1533 goto out; 1534 } 1535 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1536 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1537 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1538 return 0; /* IRQ was not for us */ 1539 ata_c->flags |= AT_TIMEOU; 1540 goto out; 1541 } 1542 if (wdc->irqack) 1543 wdc->irqack(chp); 1544 if (ata_c->flags & AT_READ) { 1545 if ((chp->ch_status & WDCS_DRQ) == 0) { 1546 ata_c->flags |= AT_TIMEOU; 1547 goto out; 1548 } 1549 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1550 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1551 0, (u_int32_t*)data, bcount >> 2); 1552 data += bcount & 0xfffffffc; 1553 bcount = bcount & 0x03; 1554 } 1555 if (bcount > 0) 1556 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1557 /* at this point the drive should be in its initial state */ 1558 ata_c->flags |= AT_XFDONE; 1559 /* XXX should read status register here ? */ 1560 } else if (ata_c->flags & AT_WRITE) { 1561 if ((chp->ch_status & WDCS_DRQ) == 0) { 1562 ata_c->flags |= AT_TIMEOU; 1563 goto out; 1564 } 1565 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1566 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1567 0, (u_int32_t*)data, bcount >> 2); 1568 data += bcount & 0xfffffffc; 1569 bcount = bcount & 0x03; 1570 } 1571 if (bcount > 0) 1572 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1573 ata_c->flags |= AT_XFDONE; 1574 if ((ata_c->flags & AT_POLL) == 0) { 1575 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1576 callout_reset(&chp->ch_callout, 1577 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1578 return 1; 1579 } else { 1580 goto again; 1581 } 1582 } 1583 out: 1584 __wdccommand_done(chp, xfer); 1585 return 1; 1586 } 1587 1588 static void 1589 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1590 { 1591 struct wdc_softc *wdc = chp->ch_wdc; 1592 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1593 struct ata_command *ata_c = xfer->c_cmd; 1594 1595 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1596 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1597 DEBUG_FUNCS); 1598 1599 1600 if (chp->ch_status & WDCS_DWF) 1601 ata_c->flags |= AT_DF; 1602 if (chp->ch_status & WDCS_ERR) { 1603 ata_c->flags |= AT_ERROR; 1604 ata_c->r_error = chp->ch_error; 1605 } 1606 if ((ata_c->flags & AT_READREG) != 0 && 1607 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1608 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1609 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1610 wdr->cmd_iohs[wd_sdh], 0); 1611 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1612 wdr->cmd_iohs[wd_seccnt], 0); 1613 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1614 wdr->cmd_iohs[wd_sector], 0); 1615 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1616 wdr->cmd_iohs[wd_cyl_lo], 0); 1617 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1618 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1619 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1620 wdr->cmd_iohs[wd_error], 0); 1621 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1622 wdr->cmd_iohs[wd_features], 0); 1623 } 1624 callout_stop(&chp->ch_callout); 1625 chp->ch_queue->active_xfer = NULL; 1626 if (ata_c->flags & AT_POLL) { 1627 /* enable interrupts */ 1628 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1629 WDCTL_4BIT); 1630 delay(10); /* some drives need a little delay here */ 1631 } 1632 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1633 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1634 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1635 wakeup(&chp->ch_queue->active_xfer); 1636 } else 1637 __wdccommand_done_end(chp, xfer); 1638 } 1639 1640 static void 1641 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1642 { 1643 struct ata_command *ata_c = xfer->c_cmd; 1644 1645 ata_c->flags |= AT_DONE; 1646 ata_free_xfer(chp, xfer); 1647 if (ata_c->flags & AT_WAIT) 1648 wakeup(ata_c); 1649 else if (ata_c->callback) 1650 ata_c->callback(ata_c->callback_arg); 1651 atastart(chp); 1652 return; 1653 } 1654 1655 static void 1656 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1657 int reason) 1658 { 1659 struct ata_command *ata_c = xfer->c_cmd; 1660 1661 switch (reason) { 1662 case KILL_GONE: 1663 ata_c->flags |= AT_GONE; 1664 break; 1665 case KILL_RESET: 1666 ata_c->flags |= AT_RESET; 1667 break; 1668 default: 1669 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1670 reason); 1671 panic("__wdccommand_kill_xfer"); 1672 } 1673 __wdccommand_done_end(chp, xfer); 1674 } 1675 1676 /* 1677 * Send a command. The drive should be ready. 1678 * Assumes interrupts are blocked. 1679 */ 1680 void 1681 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1682 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1683 u_int8_t features) 1684 { 1685 struct wdc_softc *wdc = chp->ch_wdc; 1686 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1687 1688 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1689 "sector=%d count=%d features=%d\n", wdc->sc_dev.dv_xname, 1690 chp->ch_channel, drive, command, cylin, head, sector, count, 1691 features), DEBUG_FUNCS); 1692 1693 if (wdc->select) 1694 wdc->select(chp,drive); 1695 1696 /* Select drive, head, and addressing mode. */ 1697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1698 WDSD_IBM | (drive << 4) | head); 1699 /* Load parameters into the wd_features register. */ 1700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1701 features); 1702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1704 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1705 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1706 0, cylin >> 8); 1707 1708 /* Send command. */ 1709 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1710 return; 1711 } 1712 1713 /* 1714 * Send a 48-bit addressing command. The drive should be ready. 1715 * Assumes interrupts are blocked. 1716 */ 1717 void 1718 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1719 u_int64_t blkno, u_int16_t count) 1720 { 1721 struct wdc_softc *wdc = chp->ch_wdc; 1722 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1723 1724 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1725 "count=%d\n", wdc->sc_dev.dv_xname, 1726 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1727 DEBUG_FUNCS); 1728 1729 if (wdc->select) 1730 wdc->select(chp,drive); 1731 1732 /* Select drive, head, and addressing mode. */ 1733 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1734 (drive << 4) | WDSD_LBA); 1735 1736 /* previous */ 1737 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1739 0, count >> 8); 1740 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1741 0, blkno >> 24); 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1743 0, blkno >> 32); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1745 0, blkno >> 40); 1746 1747 /* current */ 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1749 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1751 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1752 0, blkno >> 8); 1753 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1754 0, blkno >> 16); 1755 1756 /* Send command. */ 1757 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1758 return; 1759 } 1760 1761 /* 1762 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1763 * tested by the caller. 1764 */ 1765 void 1766 wdccommandshort(struct ata_channel *chp, int drive, int command) 1767 { 1768 struct wdc_softc *wdc = chp->ch_wdc; 1769 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1770 1771 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1772 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1773 DEBUG_FUNCS); 1774 1775 if (wdc->select) 1776 wdc->select(chp,drive); 1777 1778 /* Select drive. */ 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1780 WDSD_IBM | (drive << 4)); 1781 1782 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1783 } 1784 1785 static void 1786 __wdcerror(struct ata_channel *chp, char *msg) 1787 { 1788 struct wdc_softc *wdc = chp->ch_wdc; 1789 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1790 1791 if (xfer == NULL) 1792 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 1793 msg); 1794 else 1795 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 1796 chp->ch_channel, xfer->c_drive, msg); 1797 } 1798 1799 /* 1800 * the bit bucket 1801 */ 1802 void 1803 wdcbit_bucket(struct ata_channel *chp, int size) 1804 { 1805 struct wdc_regs *wdr = &chp->ch_wdc->regs[chp->ch_channel]; 1806 1807 for (; size >= 2; size -= 2) 1808 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1809 if (size) 1810 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1811 } 1812 1813 void 1814 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1815 { 1816 struct wdc_regs *wdr = &chp->ch_wdc->regs[chp->ch_channel]; 1817 1818 if (flags & DRIVE_NOSTREAM) { 1819 if (flags & DRIVE_CAP32) { 1820 bus_space_read_multi_4(wdr->data32iot, 1821 wdr->data32ioh, 0, buf, len >> 2); 1822 buf = (char *)buf + (len & ~3); 1823 len &= 3; 1824 } 1825 if (len) { 1826 bus_space_read_multi_2(wdr->cmd_iot, 1827 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1828 } 1829 } else { 1830 if (flags & DRIVE_CAP32) { 1831 bus_space_read_multi_stream_4(wdr->data32iot, 1832 wdr->data32ioh, 0, buf, len >> 2); 1833 buf = (char *)buf + (len & ~3); 1834 len &= 3; 1835 } 1836 if (len) { 1837 bus_space_read_multi_stream_2(wdr->cmd_iot, 1838 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1839 } 1840 } 1841 } 1842 1843 void 1844 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1845 { 1846 struct wdc_regs *wdr = &chp->ch_wdc->regs[chp->ch_channel]; 1847 1848 if (flags & DRIVE_NOSTREAM) { 1849 if (flags & DRIVE_CAP32) { 1850 bus_space_write_multi_4(wdr->data32iot, 1851 wdr->data32ioh, 0, buf, len >> 2); 1852 buf = (char *)buf + (len & ~3); 1853 len &= 3; 1854 } 1855 if (len) { 1856 bus_space_write_multi_2(wdr->cmd_iot, 1857 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1858 } 1859 } else { 1860 if (flags & DRIVE_CAP32) { 1861 bus_space_write_multi_stream_4(wdr->data32iot, 1862 wdr->data32ioh, 0, buf, len >> 2); 1863 buf = (char *)buf + (len & ~3); 1864 len &= 3; 1865 } 1866 if (len) { 1867 bus_space_write_multi_stream_2(wdr->cmd_iot, 1868 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1869 } 1870 } 1871 } 1872
Indexes created Thu Sep 25 08:09:54 GMT 2025