wdc.c revision 1.207
1 /* $NetBSD: wdc.c,v 1.207 2004/08/20 06:39:38 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.207 2004/08/20 06:39:38 thorpej Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "ataraid.h" 107 #include "atapibus.h" 108 #include "wd.h" 109 110 #if NATARAID > 0 111 #include <dev/ata/ata_raidvar.h> 112 #endif 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 #if NWD > 0 128 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 129 #else 130 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 131 const struct ata_bustype wdc_ata_bustype = { 132 SCSIPI_BUSTYPE_ATA, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 NULL 140 }; 141 #endif 142 143 static int wdcprobe1(struct ata_channel*, int); 144 static void __wdcerror(struct ata_channel*, char *); 145 static int __wdcwait_reset(struct ata_channel *, int, int); 146 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 147 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_kill_xfer(struct ata_channel *, 149 struct ata_xfer *, int); 150 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 151 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 152 static int __wdcwait(struct ata_channel *, int, int, int); 153 154 #define DEBUG_INTR 0x01 155 #define DEBUG_XFERS 0x02 156 #define DEBUG_STATUS 0x04 157 #define DEBUG_FUNCS 0x08 158 #define DEBUG_PROBE 0x10 159 #define DEBUG_DETACH 0x20 160 #define DEBUG_DELAY 0x40 161 #ifdef ATADEBUG 162 extern int atadebug_mask; /* init'ed in ata.c */ 163 int wdc_nxfer = 0; 164 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 165 #else 166 #define ATADEBUG_PRINT(args, level) 167 #endif 168 169 /* 170 * A queue of atabus instances, used to ensure the same bus probe order 171 * for a given hardware configuration at each boot. 172 */ 173 struct atabus_initq_head atabus_initq_head = 174 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 175 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct ata_channel *chp) 182 { 183 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 184 185 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 186 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 187 } 188 189 /* 190 * Allocate a wdc_regs array, based on the number of channels. 191 */ 192 void 193 wdc_allocate_regs(struct wdc_softc *wdc) 194 { 195 196 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 197 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 198 } 199 200 /* Test to see controller with at last one attached drive is there. 201 * Returns a bit for each possible drive found (0x01 for drive 0, 202 * 0x02 for drive 1). 203 * Logic: 204 * - If a status register is at 0xff, assume there is no drive here 205 * (ISA has pull-up resistors). Similarly if the status register has 206 * the value we last wrote to the bus (for IDE interfaces without pullups). 207 * If no drive at all -> return. 208 * - reset the controller, wait for it to complete (may take up to 31s !). 209 * If timeout -> return. 210 * - test ATA/ATAPI signatures. If at last one drive found -> return. 211 * - try an ATA command on the master. 212 */ 213 214 static void 215 wdc_drvprobe(struct ata_channel *chp) 216 { 217 struct ataparams params; 218 struct atac_softc *atac = chp->ch_atac; 219 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 220 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 221 u_int8_t st0 = 0, st1 = 0; 222 int i, error; 223 224 if (wdcprobe1(chp, 0) == 0) { 225 /* No drives, abort the attach here. */ 226 return; 227 } 228 229 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 230 for (i = 0; i < mstohz(3000); i++) { 231 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 232 if (wdc->select) 233 wdc->select(chp,0); 234 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 235 0, WDSD_IBM); 236 delay(10); /* 400ns delay */ 237 st0 = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_status], 0); 239 } 240 241 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 242 if (wdc->select) 243 wdc->select(chp,1); 244 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 245 0, WDSD_IBM | 0x10); 246 delay(10); /* 400ns delay */ 247 st1 = bus_space_read_1(wdr->cmd_iot, 248 wdr->cmd_iohs[wd_status], 0); 249 } 250 251 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 252 == 0 || 253 (st0 & WDCS_DRDY)) && 254 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 255 == 0 || 256 (st1 & WDCS_DRDY))) 257 break; 258 tsleep(¶ms, PRIBIO, "atadrdy", 1); 259 } 260 if ((st0 & WDCS_DRDY) == 0) 261 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 262 if ((st1 & WDCS_DRDY) == 0) 263 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 264 265 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 266 atac->atac_dev.dv_xname, 267 chp->ch_channel, st0, st1), DEBUG_PROBE); 268 269 /* Wait a bit, some devices are weird just after a reset. */ 270 delay(5000); 271 272 for (i = 0; i < 2; i++) { 273 /* XXX This should be done by other code. */ 274 chp->ch_drive[i].chnl_softc = chp; 275 chp->ch_drive[i].drive = i; 276 277 /* 278 * Init error counter so that an error withing the first xfers 279 * will trigger a downgrade 280 */ 281 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 282 283 /* If controller can't do 16bit flag the drives as 32bit */ 284 if ((atac->atac_cap & 285 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) 286 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 287 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 288 continue; 289 290 /* Shortcut in case we've been shutdown */ 291 if (chp->ch_flags & ATACH_SHUTDOWN) 292 return; 293 294 /* issue an identify, to try to detect ghosts */ 295 error = ata_get_params(&chp->ch_drive[i], 296 AT_WAIT | AT_POLL, ¶ms); 297 if (error != CMD_OK) { 298 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 299 300 /* Shortcut in case we've been shutdown */ 301 if (chp->ch_flags & ATACH_SHUTDOWN) 302 return; 303 304 error = ata_get_params(&chp->ch_drive[i], 305 AT_WAIT | AT_POLL, ¶ms); 306 } 307 if (error == CMD_OK) { 308 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 309 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 310 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 311 } else { 312 chp->ch_drive[i].drive_flags &= 313 ~(DRIVE_ATA | DRIVE_ATAPI); 314 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 315 atac->atac_dev.dv_xname, 316 chp->ch_channel, i, error), DEBUG_PROBE); 317 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 318 continue; 319 /* 320 * Pre-ATA drive ? 321 * Test registers writability (Error register not 322 * writable, but cyllo is), then try an ATA command. 323 */ 324 if (wdc->select) 325 wdc->select(chp,i); 326 bus_space_write_1(wdr->cmd_iot, 327 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 328 delay(10); /* 400ns delay */ 329 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 330 0, 0x58); 331 bus_space_write_1(wdr->cmd_iot, 332 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 333 if (bus_space_read_1(wdr->cmd_iot, 334 wdr->cmd_iohs[wd_error], 0) == 0x58 || 335 bus_space_read_1(wdr->cmd_iot, 336 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 337 ATADEBUG_PRINT(("%s:%d:%d: register " 338 "writability failed\n", 339 atac->atac_dev.dv_xname, 340 chp->ch_channel, i), DEBUG_PROBE); 341 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 342 continue; 343 } 344 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 345 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 346 atac->atac_dev.dv_xname, 347 chp->ch_channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 continue; 350 } 351 bus_space_write_1(wdr->cmd_iot, 352 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 353 delay(10); /* 400ns delay */ 354 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 355 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 356 atac->atac_dev.dv_xname, 357 chp->ch_channel, i), DEBUG_PROBE); 358 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 359 } else { 360 chp->ch_drive[0].drive_flags &= 361 ~(DRIVE_ATA | DRIVE_ATAPI); 362 chp->ch_drive[1].drive_flags &= 363 ~(DRIVE_ATA | DRIVE_ATAPI); 364 } 365 } 366 } 367 } 368 369 void 370 atabusconfig(struct atabus_softc *atabus_sc) 371 { 372 struct ata_channel *chp = atabus_sc->sc_chan; 373 struct atac_softc *atac = chp->ch_atac; 374 int i; 375 struct atabus_initq *atabus_initq = NULL; 376 377 /* Probe for the drives. */ 378 (*atac->atac_probe)(chp); 379 380 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 381 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 382 DEBUG_PROBE); 383 384 /* If no drives, abort here */ 385 for (i = 0; i < chp->ch_ndrive; i++) 386 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0) 387 break; 388 if (i == chp->ch_ndrive) 389 goto out; 390 391 /* Shortcut in case we've been shutdown */ 392 if (chp->ch_flags & ATACH_SHUTDOWN) 393 goto out; 394 395 /* Make sure the devices probe in atabus order to avoid jitter. */ 396 simple_lock(&atabus_interlock); 397 while(1) { 398 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 399 if (atabus_initq->atabus_sc == atabus_sc) 400 break; 401 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 402 &atabus_interlock); 403 } 404 simple_unlock(&atabus_interlock); 405 406 /* 407 * Attach an ATAPI bus, if needed. 408 */ 409 for (i = 0; i < chp->ch_ndrive; i++) { 410 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) { 411 #if NATAPIBUS > 0 412 wdc_atapibus_attach(atabus_sc); 413 #else 414 /* 415 * Fake the autoconfig "not configured" message 416 */ 417 aprint_normal("atapibus at %s not configured\n", 418 atac->atac_dev.dv_xname); 419 chp->atapibus = NULL; 420 for (i = 0; i < chp->ch_ndrive; i++) 421 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI; 422 #endif 423 break; 424 } 425 } 426 427 for (i = 0; i < chp->ch_ndrive; i++) { 428 struct ata_device adev; 429 if ((chp->ch_drive[i].drive_flags & 430 (DRIVE_ATA | DRIVE_OLD)) == 0) { 431 continue; 432 } 433 memset(&adev, 0, sizeof(struct ata_device)); 434 adev.adev_bustype = &wdc_ata_bustype; 435 adev.adev_channel = chp->ch_channel; 436 adev.adev_openings = 1; 437 adev.adev_drv_data = &chp->ch_drive[i]; 438 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 439 &adev, ataprint); 440 if (chp->ata_drives[i] != NULL) 441 ata_probe_caps(&chp->ch_drive[i]); 442 else 443 chp->ch_drive[i].drive_flags &= 444 ~(DRIVE_ATA | DRIVE_OLD); 445 } 446 447 /* now that we know the drives, the controller can set its modes */ 448 if (atac->atac_set_modes) { 449 (*atac->atac_set_modes)(chp); 450 ata_print_modes(chp); 451 } 452 #if NATARAID > 0 453 if (atac->atac_cap & ATAC_CAP_RAID) 454 for (i = 0; i < chp->ch_ndrive; i++) 455 if (chp->ata_drives[i] != NULL) 456 ata_raid_check_component(chp->ata_drives[i]); 457 #endif /* NATARAID > 0 */ 458 459 /* 460 * reset drive_flags for unattached devices, reset state for attached 461 * ones 462 */ 463 for (i = 0; i < chp->ch_ndrive; i++) { 464 if (chp->ch_drive[i].drv_softc == NULL) 465 chp->ch_drive[i].drive_flags = 0; 466 else 467 chp->ch_drive[i].state = 0; 468 } 469 470 out: 471 if (atabus_initq == NULL) { 472 simple_lock(&atabus_interlock); 473 while(1) { 474 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 475 if (atabus_initq->atabus_sc == atabus_sc) 476 break; 477 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 478 &atabus_interlock); 479 } 480 simple_unlock(&atabus_interlock); 481 } 482 simple_lock(&atabus_interlock); 483 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 484 simple_unlock(&atabus_interlock); 485 486 free(atabus_initq, M_DEVBUF); 487 wakeup(&atabus_initq_head); 488 489 ata_delref(chp); 490 491 config_pending_decr(); 492 } 493 494 int 495 wdcprobe(struct ata_channel *chp) 496 { 497 498 return (wdcprobe1(chp, 1)); 499 } 500 501 static int 502 wdcprobe1(struct ata_channel *chp, int poll) 503 { 504 struct atac_softc *atac = chp->ch_atac; 505 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 506 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 507 u_int8_t st0, st1, sc, sn, cl, ch; 508 u_int8_t ret_value = 0x03; 509 u_int8_t drive; 510 int s; 511 512 /* 513 * Sanity check to see if the wdc channel responds at all. 514 */ 515 516 s = splbio(); 517 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 518 519 if (wdc->select) 520 wdc->select(chp,0); 521 522 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 523 WDSD_IBM); 524 delay(10); /* 400ns delay */ 525 st0 = bus_space_read_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_status], 0); 527 528 if (wdc->select) 529 wdc->select(chp,1); 530 531 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 532 WDSD_IBM | 0x10); 533 delay(10); /* 400ns delay */ 534 st1 = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_status], 0); 536 537 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 538 atac->atac_dev.dv_xname, 539 chp->ch_channel, st0, st1), DEBUG_PROBE); 540 541 if (st0 == 0xff || st0 == WDSD_IBM) 542 ret_value &= ~0x01; 543 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 544 ret_value &= ~0x02; 545 /* Register writability test, drive 0. */ 546 if (ret_value & 0x01) { 547 if (wdc->select) 548 wdc->select(chp,0); 549 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 550 0, WDSD_IBM); 551 bus_space_write_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 553 cl = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_cyl_lo], 0); 555 if (cl != 0x02) { 556 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 557 "got 0x%x != 0x02\n", 558 atac->atac_dev.dv_xname, 559 chp->ch_channel, cl), 560 DEBUG_PROBE); 561 ret_value &= ~0x01; 562 } 563 bus_space_write_1(wdr->cmd_iot, 564 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 565 cl = bus_space_read_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_cyl_lo], 0); 567 if (cl != 0x01) { 568 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 569 "got 0x%x != 0x01\n", 570 atac->atac_dev.dv_xname, 571 chp->ch_channel, cl), 572 DEBUG_PROBE); 573 ret_value &= ~0x01; 574 } 575 bus_space_write_1(wdr->cmd_iot, 576 wdr->cmd_iohs[wd_sector], 0, 0x01); 577 cl = bus_space_read_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_sector], 0); 579 if (cl != 0x01) { 580 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 581 "got 0x%x != 0x01\n", 582 atac->atac_dev.dv_xname, 583 chp->ch_channel, cl), 584 DEBUG_PROBE); 585 ret_value &= ~0x01; 586 } 587 bus_space_write_1(wdr->cmd_iot, 588 wdr->cmd_iohs[wd_sector], 0, 0x02); 589 cl = bus_space_read_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_sector], 0); 591 if (cl != 0x02) { 592 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 593 "got 0x%x != 0x02\n", 594 atac->atac_dev.dv_xname, 595 chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x01) { 602 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 603 "got 0x%x != 0x01\n", 604 atac->atac_dev.dv_xname, 605 chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x01; 608 } 609 } 610 /* Register writability test, drive 1. */ 611 if (ret_value & 0x02) { 612 if (wdc->select) 613 wdc->select(chp,1); 614 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 615 0, WDSD_IBM | 0x10); 616 bus_space_write_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 618 cl = bus_space_read_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0); 620 if (cl != 0x02) { 621 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 622 "got 0x%x != 0x02\n", 623 atac->atac_dev.dv_xname, 624 chp->ch_channel, cl), 625 DEBUG_PROBE); 626 ret_value &= ~0x02; 627 } 628 bus_space_write_1(wdr->cmd_iot, 629 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 630 cl = bus_space_read_1(wdr->cmd_iot, 631 wdr->cmd_iohs[wd_cyl_lo], 0); 632 if (cl != 0x01) { 633 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 634 "got 0x%x != 0x01\n", 635 atac->atac_dev.dv_xname, 636 chp->ch_channel, cl), 637 DEBUG_PROBE); 638 ret_value &= ~0x02; 639 } 640 bus_space_write_1(wdr->cmd_iot, 641 wdr->cmd_iohs[wd_sector], 0, 0x01); 642 cl = bus_space_read_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_sector], 0); 644 if (cl != 0x01) { 645 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 646 "got 0x%x != 0x01\n", 647 atac->atac_dev.dv_xname, 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 bus_space_write_1(wdr->cmd_iot, 653 wdr->cmd_iohs[wd_sector], 0, 0x02); 654 cl = bus_space_read_1(wdr->cmd_iot, 655 wdr->cmd_iohs[wd_sector], 0); 656 if (cl != 0x02) { 657 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 658 "got 0x%x != 0x02\n", 659 atac->atac_dev.dv_xname, 660 chp->ch_channel, cl), 661 DEBUG_PROBE); 662 ret_value &= ~0x02; 663 } 664 cl = bus_space_read_1(wdr->cmd_iot, 665 wdr->cmd_iohs[wd_cyl_lo], 0); 666 if (cl != 0x01) { 667 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 668 "got 0x%x != 0x01\n", 669 atac->atac_dev.dv_xname, 670 chp->ch_channel, cl), 671 DEBUG_PROBE); 672 ret_value &= ~0x02; 673 } 674 } 675 676 if (ret_value == 0) { 677 splx(s); 678 return 0; 679 } 680 } 681 682 683 #if 0 /* XXX this break some ATA or ATAPI devices */ 684 /* 685 * reset bus. Also send an ATAPI_RESET to devices, in case there are 686 * ATAPI device out there which don't react to the bus reset 687 */ 688 if (ret_value & 0x01) { 689 if (wdc->select) 690 wdc->select(chp,0); 691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 692 0, WDSD_IBM); 693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 694 ATAPI_SOFT_RESET); 695 } 696 if (ret_value & 0x02) { 697 if (wdc->select) 698 wdc->select(chp,0); 699 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 700 0, WDSD_IBM | 0x10); 701 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 702 ATAPI_SOFT_RESET); 703 } 704 705 delay(5000); 706 #endif 707 708 if (wdc->select) 709 wdc->select(chp,0); 710 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 711 delay(10); /* 400ns delay */ 712 /* assert SRST, wait for reset to complete */ 713 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 714 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 715 DELAY(1000); 716 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 717 WDCTL_IDS | WDCTL_4BIT); 718 DELAY(2000); 719 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 720 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 721 delay(10); /* 400ns delay */ 722 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 723 if (wdc->irqack != NULL) 724 wdc->irqack(chp); 725 splx(s); 726 727 ret_value = __wdcwait_reset(chp, ret_value, poll); 728 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 729 atac->atac_dev.dv_xname, chp->ch_channel, 730 ret_value), DEBUG_PROBE); 731 732 /* if reset failed, there's nothing here */ 733 if (ret_value == 0) 734 return 0; 735 736 /* 737 * Test presence of drives. First test register signatures looking 738 * for ATAPI devices. If it's not an ATAPI and reset said there may 739 * be something here assume it's ATA or OLD. Ghost will be killed 740 * later in attach routine. 741 */ 742 for (drive = 0; drive < 2; drive++) { 743 if ((ret_value & (0x01 << drive)) == 0) 744 continue; 745 if (wdc->select) 746 wdc->select(chp,drive); 747 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 748 WDSD_IBM | (drive << 4)); 749 delay(10); /* 400ns delay */ 750 /* Save registers contents */ 751 sc = bus_space_read_1(wdr->cmd_iot, 752 wdr->cmd_iohs[wd_seccnt], 0); 753 sn = bus_space_read_1(wdr->cmd_iot, 754 wdr->cmd_iohs[wd_sector], 0); 755 cl = bus_space_read_1(wdr->cmd_iot, 756 wdr->cmd_iohs[wd_cyl_lo], 0); 757 ch = bus_space_read_1(wdr->cmd_iot, 758 wdr->cmd_iohs[wd_cyl_hi], 0); 759 760 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 761 "cl=0x%x ch=0x%x\n", 762 atac->atac_dev.dv_xname, 763 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 764 /* 765 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 766 * we get wrong values here, so ignore it. 767 */ 768 if (cl == 0x14 && ch == 0xeb) { 769 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 770 } else { 771 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 772 if (wdc == NULL || 773 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 774 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 775 } 776 } 777 return (ret_value); 778 } 779 780 void 781 wdcattach(struct ata_channel *chp) 782 { 783 struct atac_softc *atac = chp->ch_atac; 784 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 785 786 if (chp->ch_flags & ATACH_DISABLED) 787 return; 788 789 /* 790 * Start out assuming 2 drives. This may change as we probe 791 * drives. 792 */ 793 chp->ch_ndrive = 2; 794 795 /* default data transfer methods */ 796 if (!wdc->datain_pio) 797 wdc->datain_pio = wdc_datain_pio; 798 if (!wdc->dataout_pio) 799 wdc->dataout_pio = wdc_dataout_pio; 800 801 /* initialise global data */ 802 callout_init(&chp->ch_callout); 803 if (atac->atac_probe == NULL) 804 atac->atac_probe = wdc_drvprobe; 805 806 TAILQ_INIT(&chp->ch_queue->queue_xfer); 807 chp->ch_queue->queue_freeze = 0; 808 chp->ch_queue->active_xfer = NULL; 809 810 chp->atabus = config_found(&atac->atac_dev, chp, atabusprint); 811 } 812 813 int 814 wdcactivate(struct device *self, enum devact act) 815 { 816 struct atac_softc *atac = (struct atac_softc *) self; 817 int s, i, error = 0; 818 819 s = splbio(); 820 switch (act) { 821 case DVACT_ACTIVATE: 822 error = EOPNOTSUPP; 823 break; 824 825 case DVACT_DEACTIVATE: 826 for (i = 0; i < atac->atac_nchannels; i++) { 827 error = 828 config_deactivate(atac->atac_channels[i]->atabus); 829 if (error) 830 break; 831 } 832 break; 833 } 834 splx(s); 835 return (error); 836 } 837 838 int 839 wdcdetach(struct device *self, int flags) 840 { 841 struct atac_softc *atac = (struct atac_softc *) self; 842 struct ata_channel *chp; 843 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 844 int i, error = 0; 845 846 for (i = 0; i < atac->atac_nchannels; i++) { 847 chp = atac->atac_channels[i]; 848 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 849 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 850 DEBUG_DETACH); 851 error = config_detach(chp->atabus, flags); 852 if (error) 853 break; 854 } 855 if (adapt->adapt_refcnt != 0) { 856 #ifdef DIAGNOSTIC 857 printf("wdcdetach: refcnt should be 0 here??\n"); 858 #endif 859 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 860 } 861 return (error); 862 } 863 864 /* restart an interrupted I/O */ 865 void 866 wdcrestart(void *v) 867 { 868 struct ata_channel *chp = v; 869 int s; 870 871 s = splbio(); 872 atastart(chp); 873 splx(s); 874 } 875 876 877 /* 878 * Interrupt routine for the controller. Acknowledge the interrupt, check for 879 * errors on the current operation, mark it done if necessary, and start the 880 * next request. Also check for a partially done transfer, and continue with 881 * the next chunk if so. 882 */ 883 int 884 wdcintr(void *arg) 885 { 886 struct ata_channel *chp = arg; 887 struct atac_softc *atac = chp->ch_atac; 888 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 889 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 890 struct ata_xfer *xfer; 891 int ret; 892 893 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 894 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 895 DEBUG_INTR); 896 return (0); 897 } 898 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 899 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 900 /* try to clear the pending interrupt anyway */ 901 (void)bus_space_read_1(wdr->cmd_iot, 902 wdr->cmd_iohs[wd_status], 0); 903 return (0); 904 } 905 906 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 907 xfer = chp->ch_queue->active_xfer; 908 #ifdef DIAGNOSTIC 909 if (xfer == NULL) 910 panic("wdcintr: no xfer"); 911 #endif 912 if (chp->ch_flags & ATACH_DMA_WAIT) { 913 wdc->dma_status = 914 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 915 xfer->c_drive, WDC_DMAEND_END); 916 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 917 /* IRQ not for us, not detected by DMA engine */ 918 return 0; 919 } 920 chp->ch_flags &= ~ATACH_DMA_WAIT; 921 } 922 chp->ch_flags &= ~ATACH_IRQ_WAIT; 923 ret = xfer->c_intr(chp, xfer, 1); 924 if (ret == 0) /* irq was not for us, still waiting for irq */ 925 chp->ch_flags |= ATACH_IRQ_WAIT; 926 return (ret); 927 } 928 929 /* Put all disk in RESET state */ 930 void 931 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 932 { 933 struct ata_channel *chp = drvp->chnl_softc; 934 struct atac_softc *atac = chp->ch_atac; 935 936 ATADEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 937 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 938 DEBUG_FUNCS); 939 940 941 wdc_reset_channel(chp, flags); 942 } 943 944 void 945 wdc_reset_channel(struct ata_channel *chp, int flags) 946 { 947 TAILQ_HEAD(, ata_xfer) reset_xfer; 948 struct ata_xfer *xfer, *next_xfer; 949 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 950 int drive; 951 952 chp->ch_queue->queue_freeze++; 953 TAILQ_INIT(&reset_xfer); 954 955 /* if we can poll or wait it's OK, otherwise wake up the kernel 956 * thread 957 */ 958 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 959 if (chp->ch_flags & ATACH_TH_RESET) { 960 /* no need to schedule a reset more than one time */ 961 return; 962 } 963 chp->ch_flags |= ATACH_TH_RESET; 964 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 965 wakeup(&chp->ch_thread); 966 return; 967 } 968 969 chp->ch_flags &= ~ATACH_IRQ_WAIT; 970 /* 971 * if the current command if on an ATAPI device, issue a 972 * ATAPI_SOFT_RESET 973 */ 974 xfer = chp->ch_queue->active_xfer; 975 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 976 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 977 if (flags & AT_WAIT) 978 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 979 else 980 delay(1000); 981 } 982 983 /* reset the channel */ 984 if (flags & AT_WAIT) 985 (void) wdcreset(chp, RESET_SLEEP); 986 else 987 (void) wdcreset(chp, RESET_POLL); 988 989 /* 990 * wait a bit after reset; in case the DMA engines needs some time 991 * to recover. 992 */ 993 if (flags & AT_WAIT) 994 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 995 else 996 delay(1000); 997 /* 998 * look for pending xfers. If we have a shared queue, we'll also reset 999 * the other channel if the current xfer is running on it. 1000 * Then we'll dequeue only the xfers for this channel. 1001 */ 1002 if ((flags & AT_RST_NOCMD) == 0) { 1003 /* 1004 * move all xfers queued for this channel to the reset queue, 1005 * and then process the current xfer and then the reset queue. 1006 * We have to use a temporary queue because c_kill_xfer() 1007 * may requeue commands. 1008 */ 1009 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1010 xfer != NULL; xfer = next_xfer) { 1011 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1012 if (xfer->c_chp != chp) 1013 continue; 1014 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1015 xfer, c_xferchain); 1016 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1017 } 1018 xfer = chp->ch_queue->active_xfer; 1019 if (xfer) { 1020 if (xfer->c_chp != chp) 1021 wdc_reset_channel(xfer->c_chp, flags); 1022 else { 1023 callout_stop(&chp->ch_callout); 1024 /* 1025 * If we're waiting for DMA, stop the 1026 * DMA engine 1027 */ 1028 if (chp->ch_flags & ATACH_DMA_WAIT) { 1029 (*wdc->dma_finish)( 1030 wdc->dma_arg, 1031 chp->ch_channel, 1032 xfer->c_drive, 1033 WDC_DMAEND_ABRT_QUIET); 1034 chp->ch_flags &= ~ATACH_DMA_WAIT; 1035 } 1036 chp->ch_queue->active_xfer = NULL; 1037 if ((flags & AT_RST_EMERG) == 0) 1038 xfer->c_kill_xfer( 1039 chp, xfer, KILL_RESET); 1040 } 1041 } 1042 1043 for (xfer = TAILQ_FIRST(&reset_xfer); 1044 xfer != NULL; xfer = next_xfer) { 1045 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1046 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1047 if ((flags & AT_RST_EMERG) == 0) 1048 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1049 } 1050 } 1051 for (drive = 0; drive < chp->ch_ndrive; drive++) { 1052 chp->ch_drive[drive].state = 0; 1053 } 1054 chp->ch_flags &= ~ATACH_TH_RESET; 1055 if ((flags & AT_RST_EMERG) == 0) { 1056 chp->ch_queue->queue_freeze--; 1057 atastart(chp); 1058 } else { 1059 /* make sure that we can use polled commands */ 1060 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1061 chp->ch_queue->queue_freeze = 0; 1062 chp->ch_queue->active_xfer = NULL; 1063 } 1064 } 1065 1066 int 1067 wdcreset(struct ata_channel *chp, int poll) 1068 { 1069 struct atac_softc *atac = chp->ch_atac; 1070 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1071 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1072 int drv_mask1, drv_mask2; 1073 int s = 0; 1074 1075 if (wdc->select) 1076 wdc->select(chp,0); 1077 if (poll != RESET_SLEEP) 1078 s = splbio(); 1079 /* master */ 1080 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1081 delay(10); /* 400ns delay */ 1082 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1083 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1084 delay(2000); 1085 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1086 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1087 WDCTL_4BIT | WDCTL_IDS); 1088 delay(10); /* 400ns delay */ 1089 if (poll != RESET_SLEEP) { 1090 if (wdc->irqack) 1091 wdc->irqack(chp); 1092 splx(s); 1093 } 1094 1095 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1096 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1097 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1098 (poll == RESET_SLEEP) ? 0 : 1); 1099 if (drv_mask2 != drv_mask1) { 1100 printf("%s channel %d: reset failed for", 1101 atac->atac_dev.dv_xname, chp->ch_channel); 1102 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1103 printf(" drive 0"); 1104 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1105 printf(" drive 1"); 1106 printf("\n"); 1107 } 1108 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1109 return (drv_mask1 != drv_mask2) ? 1 : 0; 1110 } 1111 1112 static int 1113 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1114 { 1115 struct atac_softc *atac = chp->ch_atac; 1116 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1117 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1118 int timeout, nloop; 1119 u_int8_t st0 = 0, st1 = 0; 1120 #ifdef ATADEBUG 1121 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1122 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1123 #endif 1124 1125 if (poll) 1126 nloop = WDCNDELAY_RST; 1127 else 1128 nloop = WDC_RESET_WAIT * hz / 1000; 1129 /* wait for BSY to deassert */ 1130 for (timeout = 0; timeout < nloop; timeout++) { 1131 if ((drv_mask & 0x01) != 0) { 1132 if (wdc && wdc->select) 1133 wdc->select(chp,0); 1134 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1135 0, WDSD_IBM); /* master */ 1136 delay(10); 1137 st0 = bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_status], 0); 1139 #ifdef ATADEBUG 1140 sc0 = bus_space_read_1(wdr->cmd_iot, 1141 wdr->cmd_iohs[wd_seccnt], 0); 1142 sn0 = bus_space_read_1(wdr->cmd_iot, 1143 wdr->cmd_iohs[wd_sector], 0); 1144 cl0 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_cyl_lo], 0); 1146 ch0 = bus_space_read_1(wdr->cmd_iot, 1147 wdr->cmd_iohs[wd_cyl_hi], 0); 1148 #endif 1149 } 1150 if ((drv_mask & 0x02) != 0) { 1151 if (wdc && wdc->select) 1152 wdc->select(chp,1); 1153 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1154 0, WDSD_IBM | 0x10); /* slave */ 1155 delay(10); 1156 st1 = bus_space_read_1(wdr->cmd_iot, 1157 wdr->cmd_iohs[wd_status], 0); 1158 #ifdef ATADEBUG 1159 sc1 = bus_space_read_1(wdr->cmd_iot, 1160 wdr->cmd_iohs[wd_seccnt], 0); 1161 sn1 = bus_space_read_1(wdr->cmd_iot, 1162 wdr->cmd_iohs[wd_sector], 0); 1163 cl1 = bus_space_read_1(wdr->cmd_iot, 1164 wdr->cmd_iohs[wd_cyl_lo], 0); 1165 ch1 = bus_space_read_1(wdr->cmd_iot, 1166 wdr->cmd_iohs[wd_cyl_hi], 0); 1167 #endif 1168 } 1169 1170 if ((drv_mask & 0x01) == 0) { 1171 /* no master */ 1172 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1173 /* No master, slave is ready, it's done */ 1174 goto end; 1175 } 1176 } else if ((drv_mask & 0x02) == 0) { 1177 /* no slave */ 1178 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1179 /* No slave, master is ready, it's done */ 1180 goto end; 1181 } 1182 } else { 1183 /* Wait for both master and slave to be ready */ 1184 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1185 goto end; 1186 } 1187 } 1188 if (poll) 1189 delay(WDCDELAY); 1190 else 1191 tsleep(&nloop, PRIBIO, "atarst", 1); 1192 } 1193 /* Reset timed out. Maybe it's because drv_mask was not right */ 1194 if (st0 & WDCS_BSY) 1195 drv_mask &= ~0x01; 1196 if (st1 & WDCS_BSY) 1197 drv_mask &= ~0x02; 1198 end: 1199 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1200 "cl=0x%x ch=0x%x\n", 1201 atac->atac_dev.dv_xname, 1202 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1203 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1204 "cl=0x%x ch=0x%x\n", 1205 atac->atac_dev.dv_xname, 1206 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1207 1208 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1209 atac->atac_dev.dv_xname, chp->ch_channel, 1210 st0, st1), DEBUG_PROBE); 1211 1212 return drv_mask; 1213 } 1214 1215 /* 1216 * Wait for a drive to be !BSY, and have mask in its status register. 1217 * return -1 for a timeout after "timeout" ms. 1218 */ 1219 static int 1220 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1221 { 1222 struct atac_softc *atac = chp->ch_atac; 1223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1225 u_char status; 1226 int time = 0; 1227 1228 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1229 atac->atac_dev.dv_xname, 1230 chp->ch_channel), DEBUG_STATUS); 1231 chp->ch_error = 0; 1232 1233 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1234 1235 for (;;) { 1236 chp->ch_status = status = 1237 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1238 if ((status & (WDCS_BSY | mask)) == bits) 1239 break; 1240 if (++time > timeout) { 1241 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1242 "status %x error %x (mask 0x%x bits 0x%x)\n", 1243 time, status, 1244 bus_space_read_1(wdr->cmd_iot, 1245 wdr->cmd_iohs[wd_error], 0), mask, bits), 1246 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1247 return(WDCWAIT_TOUT); 1248 } 1249 delay(WDCDELAY); 1250 } 1251 #ifdef ATADEBUG 1252 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1253 printf("__wdcwait: did busy-wait, time=%d\n", time); 1254 #endif 1255 if (status & WDCS_ERR) 1256 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1257 wdr->cmd_iohs[wd_error], 0); 1258 #ifdef WDCNDELAY_DEBUG 1259 /* After autoconfig, there should be no long delays. */ 1260 if (!cold && time > WDCNDELAY_DEBUG) { 1261 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1262 if (xfer == NULL) 1263 printf("%s channel %d: warning: busy-wait took %dus\n", 1264 atac->atac_dev.dv_xname, chp->ch_channel, 1265 WDCDELAY * time); 1266 else 1267 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1268 atac->atac_dev.dv_xname, chp->ch_channel, 1269 xfer->drive, 1270 WDCDELAY * time); 1271 } 1272 #endif 1273 return(WDCWAIT_OK); 1274 } 1275 1276 /* 1277 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1278 * thread if possible 1279 */ 1280 int 1281 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1282 { 1283 int error, i, timeout_hz = mstohz(timeout); 1284 1285 if (timeout_hz == 0 || 1286 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1287 error = __wdcwait(chp, mask, bits, timeout); 1288 else { 1289 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1290 if (error != 0) { 1291 if ((chp->ch_flags & ATACH_TH_RUN) || 1292 (flags & AT_WAIT)) { 1293 /* 1294 * we're running in the channel thread 1295 * or some userland thread context 1296 */ 1297 for (i = 0; i < timeout_hz; i++) { 1298 if (__wdcwait(chp, mask, bits, 1299 WDCDELAY_POLL) == 0) { 1300 error = 0; 1301 break; 1302 } 1303 tsleep(&chp, PRIBIO, "atapoll", 1); 1304 } 1305 } else { 1306 /* 1307 * we're probably in interrupt context, 1308 * ask the thread to come back here 1309 */ 1310 #ifdef DIAGNOSTIC 1311 if (chp->ch_queue->queue_freeze > 0) 1312 panic("wdcwait: queue_freeze"); 1313 #endif 1314 chp->ch_queue->queue_freeze++; 1315 wakeup(&chp->ch_thread); 1316 return(WDCWAIT_THR); 1317 } 1318 } 1319 } 1320 return (error); 1321 } 1322 1323 1324 /* 1325 * Busy-wait for DMA to complete 1326 */ 1327 int 1328 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1329 { 1330 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1331 int time; 1332 1333 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1334 wdc->dma_status = 1335 (*wdc->dma_finish)(wdc->dma_arg, 1336 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1337 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1338 return 0; 1339 delay(WDCDELAY); 1340 } 1341 /* timeout, force a DMA halt */ 1342 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1343 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1344 return 1; 1345 } 1346 1347 void 1348 wdctimeout(void *arg) 1349 { 1350 struct ata_channel *chp = (struct ata_channel *)arg; 1351 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1352 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1353 int s; 1354 1355 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1356 1357 s = splbio(); 1358 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1359 __wdcerror(chp, "lost interrupt"); 1360 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1361 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1362 xfer->c_bcount, 1363 xfer->c_skip); 1364 if (chp->ch_flags & ATACH_DMA_WAIT) { 1365 wdc->dma_status = 1366 (*wdc->dma_finish)(wdc->dma_arg, 1367 chp->ch_channel, xfer->c_drive, 1368 WDC_DMAEND_ABRT); 1369 chp->ch_flags &= ~ATACH_DMA_WAIT; 1370 } 1371 /* 1372 * Call the interrupt routine. If we just missed an interrupt, 1373 * it will do what's needed. Else, it will take the needed 1374 * action (reset the device). 1375 * Before that we need to reinstall the timeout callback, 1376 * in case it will miss another irq while in this transfer 1377 * We arbitray chose it to be 1s 1378 */ 1379 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1380 xfer->c_flags |= C_TIMEOU; 1381 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1382 xfer->c_intr(chp, xfer, 1); 1383 } else 1384 __wdcerror(chp, "missing untimeout"); 1385 splx(s); 1386 } 1387 1388 int 1389 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1390 { 1391 struct ata_channel *chp = drvp->chnl_softc; 1392 struct atac_softc *atac = chp->ch_atac; 1393 struct ata_xfer *xfer; 1394 int s, ret; 1395 1396 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1397 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1398 DEBUG_FUNCS); 1399 1400 /* set up an xfer and queue. Wait for completion */ 1401 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1402 ATAXF_NOSLEEP); 1403 if (xfer == NULL) { 1404 return ATACMD_TRY_AGAIN; 1405 } 1406 1407 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1408 ata_c->flags |= AT_POLL; 1409 if (ata_c->flags & AT_POLL) 1410 xfer->c_flags |= C_POLL; 1411 xfer->c_drive = drvp->drive; 1412 xfer->c_databuf = ata_c->data; 1413 xfer->c_bcount = ata_c->bcount; 1414 xfer->c_cmd = ata_c; 1415 xfer->c_start = __wdccommand_start; 1416 xfer->c_intr = __wdccommand_intr; 1417 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1418 1419 s = splbio(); 1420 ata_exec_xfer(chp, xfer); 1421 #ifdef DIAGNOSTIC 1422 if ((ata_c->flags & AT_POLL) != 0 && 1423 (ata_c->flags & AT_DONE) == 0) 1424 panic("wdc_exec_command: polled command not done"); 1425 #endif 1426 if (ata_c->flags & AT_DONE) { 1427 ret = ATACMD_COMPLETE; 1428 } else { 1429 if (ata_c->flags & AT_WAIT) { 1430 while ((ata_c->flags & AT_DONE) == 0) { 1431 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1432 } 1433 ret = ATACMD_COMPLETE; 1434 } else { 1435 ret = ATACMD_QUEUED; 1436 } 1437 } 1438 splx(s); 1439 return ret; 1440 } 1441 1442 static void 1443 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1444 { 1445 struct atac_softc *atac = chp->ch_atac; 1446 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1447 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1448 int drive = xfer->c_drive; 1449 struct ata_command *ata_c = xfer->c_cmd; 1450 1451 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1452 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1453 DEBUG_FUNCS); 1454 1455 if (wdc->select) 1456 wdc->select(chp,drive); 1457 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1458 WDSD_IBM | (drive << 4)); 1459 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1460 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1461 case WDCWAIT_OK: 1462 break; 1463 case WDCWAIT_TOUT: 1464 ata_c->flags |= AT_TIMEOU; 1465 __wdccommand_done(chp, xfer); 1466 return; 1467 case WDCWAIT_THR: 1468 return; 1469 } 1470 if (ata_c->flags & AT_POLL) { 1471 /* polled command, disable interrupts */ 1472 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1473 WDCTL_4BIT | WDCTL_IDS); 1474 } 1475 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1476 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1477 1478 if ((ata_c->flags & AT_POLL) == 0) { 1479 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1480 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1481 wdctimeout, chp); 1482 return; 1483 } 1484 /* 1485 * Polled command. Wait for drive ready or drq. Done in intr(). 1486 * Wait for at last 400ns for status bit to be valid. 1487 */ 1488 delay(10); /* 400ns delay */ 1489 __wdccommand_intr(chp, xfer, 0); 1490 } 1491 1492 static int 1493 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1494 { 1495 struct atac_softc *atac = chp->ch_atac; 1496 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1497 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1498 struct ata_command *ata_c = xfer->c_cmd; 1499 int bcount = ata_c->bcount; 1500 char *data = ata_c->data; 1501 int wflags; 1502 1503 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1504 /* both wait and poll, we can tsleep here */ 1505 wflags = AT_WAIT | AT_POLL; 1506 } else { 1507 wflags = AT_POLL; 1508 } 1509 1510 again: 1511 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1512 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1513 DEBUG_INTR); 1514 /* 1515 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1516 * Reselect again, it doesn't hurt for others commands, and the time 1517 * penalty for the extra regiter write is acceptable, 1518 * wdc_exec_command() isn't called often (mosly for autoconfig) 1519 */ 1520 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1521 WDSD_IBM | (xfer->c_drive << 4)); 1522 if ((ata_c->flags & AT_XFDONE) != 0) { 1523 /* 1524 * We have completed a data xfer. The drive should now be 1525 * in its initial state 1526 */ 1527 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1528 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1529 wflags) == WDCWAIT_TOUT) { 1530 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1531 return 0; /* IRQ was not for us */ 1532 ata_c->flags |= AT_TIMEOU; 1533 } 1534 goto out; 1535 } 1536 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1537 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1538 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1539 return 0; /* IRQ was not for us */ 1540 ata_c->flags |= AT_TIMEOU; 1541 goto out; 1542 } 1543 if (wdc->irqack) 1544 wdc->irqack(chp); 1545 if (ata_c->flags & AT_READ) { 1546 if ((chp->ch_status & WDCS_DRQ) == 0) { 1547 ata_c->flags |= AT_TIMEOU; 1548 goto out; 1549 } 1550 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1551 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1552 0, (u_int32_t*)data, bcount >> 2); 1553 data += bcount & 0xfffffffc; 1554 bcount = bcount & 0x03; 1555 } 1556 if (bcount > 0) 1557 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1558 /* at this point the drive should be in its initial state */ 1559 ata_c->flags |= AT_XFDONE; 1560 /* XXX should read status register here ? */ 1561 } else if (ata_c->flags & AT_WRITE) { 1562 if ((chp->ch_status & WDCS_DRQ) == 0) { 1563 ata_c->flags |= AT_TIMEOU; 1564 goto out; 1565 } 1566 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1567 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1568 0, (u_int32_t*)data, bcount >> 2); 1569 data += bcount & 0xfffffffc; 1570 bcount = bcount & 0x03; 1571 } 1572 if (bcount > 0) 1573 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1574 ata_c->flags |= AT_XFDONE; 1575 if ((ata_c->flags & AT_POLL) == 0) { 1576 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1577 callout_reset(&chp->ch_callout, 1578 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1579 return 1; 1580 } else { 1581 goto again; 1582 } 1583 } 1584 out: 1585 __wdccommand_done(chp, xfer); 1586 return 1; 1587 } 1588 1589 static void 1590 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1591 { 1592 struct atac_softc *atac = chp->ch_atac; 1593 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1594 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1595 struct ata_command *ata_c = xfer->c_cmd; 1596 1597 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1598 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1599 DEBUG_FUNCS); 1600 1601 1602 if (chp->ch_status & WDCS_DWF) 1603 ata_c->flags |= AT_DF; 1604 if (chp->ch_status & WDCS_ERR) { 1605 ata_c->flags |= AT_ERROR; 1606 ata_c->r_error = chp->ch_error; 1607 } 1608 if ((ata_c->flags & AT_READREG) != 0 && 1609 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1610 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1611 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1612 wdr->cmd_iohs[wd_sdh], 0); 1613 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1614 wdr->cmd_iohs[wd_seccnt], 0); 1615 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1616 wdr->cmd_iohs[wd_sector], 0); 1617 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1618 wdr->cmd_iohs[wd_cyl_lo], 0); 1619 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1620 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1621 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1622 wdr->cmd_iohs[wd_error], 0); 1623 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1624 wdr->cmd_iohs[wd_features], 0); 1625 } 1626 callout_stop(&chp->ch_callout); 1627 chp->ch_queue->active_xfer = NULL; 1628 if (ata_c->flags & AT_POLL) { 1629 /* enable interrupts */ 1630 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1631 WDCTL_4BIT); 1632 delay(10); /* some drives need a little delay here */ 1633 } 1634 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1635 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1636 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1637 wakeup(&chp->ch_queue->active_xfer); 1638 } else 1639 __wdccommand_done_end(chp, xfer); 1640 } 1641 1642 static void 1643 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1644 { 1645 struct ata_command *ata_c = xfer->c_cmd; 1646 1647 ata_c->flags |= AT_DONE; 1648 ata_free_xfer(chp, xfer); 1649 if (ata_c->flags & AT_WAIT) 1650 wakeup(ata_c); 1651 else if (ata_c->callback) 1652 ata_c->callback(ata_c->callback_arg); 1653 atastart(chp); 1654 return; 1655 } 1656 1657 static void 1658 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1659 int reason) 1660 { 1661 struct ata_command *ata_c = xfer->c_cmd; 1662 1663 switch (reason) { 1664 case KILL_GONE: 1665 ata_c->flags |= AT_GONE; 1666 break; 1667 case KILL_RESET: 1668 ata_c->flags |= AT_RESET; 1669 break; 1670 default: 1671 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1672 reason); 1673 panic("__wdccommand_kill_xfer"); 1674 } 1675 __wdccommand_done_end(chp, xfer); 1676 } 1677 1678 /* 1679 * Send a command. The drive should be ready. 1680 * Assumes interrupts are blocked. 1681 */ 1682 void 1683 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1684 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1685 u_int8_t features) 1686 { 1687 struct atac_softc *atac = chp->ch_atac; 1688 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1689 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1690 1691 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1692 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1693 chp->ch_channel, drive, command, cylin, head, sector, count, 1694 features), DEBUG_FUNCS); 1695 1696 if (wdc->select) 1697 wdc->select(chp,drive); 1698 1699 /* Select drive, head, and addressing mode. */ 1700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1701 WDSD_IBM | (drive << 4) | head); 1702 /* Load parameters into the wd_features register. */ 1703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1704 features); 1705 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1707 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1708 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1709 0, cylin >> 8); 1710 1711 /* Send command. */ 1712 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1713 return; 1714 } 1715 1716 /* 1717 * Send a 48-bit addressing command. The drive should be ready. 1718 * Assumes interrupts are blocked. 1719 */ 1720 void 1721 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1722 u_int64_t blkno, u_int16_t count) 1723 { 1724 struct atac_softc *atac = chp->ch_atac; 1725 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1726 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1727 1728 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1729 "count=%d\n", atac->atac_dev.dv_xname, 1730 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1731 DEBUG_FUNCS); 1732 1733 if (wdc->select) 1734 wdc->select(chp,drive); 1735 1736 /* Select drive, head, and addressing mode. */ 1737 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1738 (drive << 4) | WDSD_LBA); 1739 1740 /* previous */ 1741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1743 0, count >> 8); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1745 0, blkno >> 24); 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1747 0, blkno >> 32); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1749 0, blkno >> 40); 1750 1751 /* current */ 1752 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1753 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1755 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1756 0, blkno >> 8); 1757 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1758 0, blkno >> 16); 1759 1760 /* Send command. */ 1761 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1762 return; 1763 } 1764 1765 /* 1766 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1767 * tested by the caller. 1768 */ 1769 void 1770 wdccommandshort(struct ata_channel *chp, int drive, int command) 1771 { 1772 struct atac_softc *atac = chp->ch_atac; 1773 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1774 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1775 1776 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1777 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1778 DEBUG_FUNCS); 1779 1780 if (wdc->select) 1781 wdc->select(chp,drive); 1782 1783 /* Select drive. */ 1784 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1785 WDSD_IBM | (drive << 4)); 1786 1787 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1788 } 1789 1790 static void 1791 __wdcerror(struct ata_channel *chp, char *msg) 1792 { 1793 struct atac_softc *atac = chp->ch_atac; 1794 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1795 1796 if (xfer == NULL) 1797 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1798 msg); 1799 else 1800 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1801 chp->ch_channel, xfer->c_drive, msg); 1802 } 1803 1804 /* 1805 * the bit bucket 1806 */ 1807 void 1808 wdcbit_bucket(struct ata_channel *chp, int size) 1809 { 1810 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1811 1812 for (; size >= 2; size -= 2) 1813 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1814 if (size) 1815 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1816 } 1817 1818 void 1819 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1820 { 1821 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1822 1823 if (flags & DRIVE_NOSTREAM) { 1824 if (flags & DRIVE_CAP32) { 1825 bus_space_read_multi_4(wdr->data32iot, 1826 wdr->data32ioh, 0, buf, len >> 2); 1827 buf = (char *)buf + (len & ~3); 1828 len &= 3; 1829 } 1830 if (len) { 1831 bus_space_read_multi_2(wdr->cmd_iot, 1832 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1833 } 1834 } else { 1835 if (flags & DRIVE_CAP32) { 1836 bus_space_read_multi_stream_4(wdr->data32iot, 1837 wdr->data32ioh, 0, buf, len >> 2); 1838 buf = (char *)buf + (len & ~3); 1839 len &= 3; 1840 } 1841 if (len) { 1842 bus_space_read_multi_stream_2(wdr->cmd_iot, 1843 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1844 } 1845 } 1846 } 1847 1848 void 1849 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1850 { 1851 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1852 1853 if (flags & DRIVE_NOSTREAM) { 1854 if (flags & DRIVE_CAP32) { 1855 bus_space_write_multi_4(wdr->data32iot, 1856 wdr->data32ioh, 0, buf, len >> 2); 1857 buf = (char *)buf + (len & ~3); 1858 len &= 3; 1859 } 1860 if (len) { 1861 bus_space_write_multi_2(wdr->cmd_iot, 1862 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1863 } 1864 } else { 1865 if (flags & DRIVE_CAP32) { 1866 bus_space_write_multi_stream_4(wdr->data32iot, 1867 wdr->data32ioh, 0, buf, len >> 2); 1868 buf = (char *)buf + (len & ~3); 1869 len &= 3; 1870 } 1871 if (len) { 1872 bus_space_write_multi_stream_2(wdr->cmd_iot, 1873 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1874 } 1875 } 1876 } 1877
Indexes created Tue Sep 23 22:09:46 GMT 2025