wdc.c revision 1.210
1 /* $NetBSD: wdc.c,v 1.210 2004/08/20 22:17:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.210 2004/08/20 22:17:06 thorpej Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, 129 NULL, 130 NULL, 131 NULL, 132 NULL, 133 NULL, 134 NULL 135 }; 136 #endif 137 138 static int wdcprobe1(struct ata_channel*, int); 139 static void __wdcerror(struct ata_channel*, char *); 140 static int __wdcwait_reset(struct ata_channel *, int, int); 141 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 142 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 143 static void __wdccommand_kill_xfer(struct ata_channel *, 144 struct ata_xfer *, int); 145 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 146 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 147 static int __wdcwait(struct ata_channel *, int, int, int); 148 149 #define DEBUG_INTR 0x01 150 #define DEBUG_XFERS 0x02 151 #define DEBUG_STATUS 0x04 152 #define DEBUG_FUNCS 0x08 153 #define DEBUG_PROBE 0x10 154 #define DEBUG_DETACH 0x20 155 #define DEBUG_DELAY 0x40 156 #ifdef ATADEBUG 157 extern int atadebug_mask; /* init'ed in ata.c */ 158 int wdc_nxfer = 0; 159 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 160 #else 161 #define ATADEBUG_PRINT(args, level) 162 #endif 163 164 /* 165 * Initialize the "shadow register" handles for a standard wdc controller. 166 */ 167 void 168 wdc_init_shadow_regs(struct ata_channel *chp) 169 { 170 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 171 172 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 173 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 174 } 175 176 /* 177 * Allocate a wdc_regs array, based on the number of channels. 178 */ 179 void 180 wdc_allocate_regs(struct wdc_softc *wdc) 181 { 182 183 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 184 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 185 } 186 187 /* Test to see controller with at last one attached drive is there. 188 * Returns a bit for each possible drive found (0x01 for drive 0, 189 * 0x02 for drive 1). 190 * Logic: 191 * - If a status register is at 0xff, assume there is no drive here 192 * (ISA has pull-up resistors). Similarly if the status register has 193 * the value we last wrote to the bus (for IDE interfaces without pullups). 194 * If no drive at all -> return. 195 * - reset the controller, wait for it to complete (may take up to 31s !). 196 * If timeout -> return. 197 * - test ATA/ATAPI signatures. If at last one drive found -> return. 198 * - try an ATA command on the master. 199 */ 200 201 static void 202 wdc_drvprobe(struct ata_channel *chp) 203 { 204 struct ataparams params; 205 struct atac_softc *atac = chp->ch_atac; 206 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 207 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 208 u_int8_t st0 = 0, st1 = 0; 209 int i, error; 210 211 if (wdcprobe1(chp, 0) == 0) { 212 /* No drives, abort the attach here. */ 213 return; 214 } 215 216 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 217 for (i = 0; i < mstohz(3000); i++) { 218 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 219 if (wdc->select) 220 wdc->select(chp,0); 221 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 222 0, WDSD_IBM); 223 delay(10); /* 400ns delay */ 224 st0 = bus_space_read_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_status], 0); 226 } 227 228 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 229 if (wdc->select) 230 wdc->select(chp,1); 231 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 232 0, WDSD_IBM | 0x10); 233 delay(10); /* 400ns delay */ 234 st1 = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_status], 0); 236 } 237 238 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 239 == 0 || 240 (st0 & WDCS_DRDY)) && 241 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 242 == 0 || 243 (st1 & WDCS_DRDY))) 244 break; 245 tsleep(¶ms, PRIBIO, "atadrdy", 1); 246 } 247 if ((st0 & WDCS_DRDY) == 0) 248 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 249 if ((st1 & WDCS_DRDY) == 0) 250 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 251 252 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 253 atac->atac_dev.dv_xname, 254 chp->ch_channel, st0, st1), DEBUG_PROBE); 255 256 /* Wait a bit, some devices are weird just after a reset. */ 257 delay(5000); 258 259 for (i = 0; i < 2; i++) { 260 /* XXX This should be done by other code. */ 261 chp->ch_drive[i].chnl_softc = chp; 262 chp->ch_drive[i].drive = i; 263 264 /* 265 * Init error counter so that an error withing the first xfers 266 * will trigger a downgrade 267 */ 268 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 269 270 /* If controller can't do 16bit flag the drives as 32bit */ 271 if ((atac->atac_cap & 272 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) 273 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 274 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 275 continue; 276 277 /* Shortcut in case we've been shutdown */ 278 if (chp->ch_flags & ATACH_SHUTDOWN) 279 return; 280 281 /* issue an identify, to try to detect ghosts */ 282 error = ata_get_params(&chp->ch_drive[i], 283 AT_WAIT | AT_POLL, ¶ms); 284 if (error != CMD_OK) { 285 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 286 287 /* Shortcut in case we've been shutdown */ 288 if (chp->ch_flags & ATACH_SHUTDOWN) 289 return; 290 291 error = ata_get_params(&chp->ch_drive[i], 292 AT_WAIT | AT_POLL, ¶ms); 293 } 294 if (error == CMD_OK) { 295 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 296 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 297 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 298 } else { 299 chp->ch_drive[i].drive_flags &= 300 ~(DRIVE_ATA | DRIVE_ATAPI); 301 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 302 atac->atac_dev.dv_xname, 303 chp->ch_channel, i, error), DEBUG_PROBE); 304 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 305 continue; 306 /* 307 * Pre-ATA drive ? 308 * Test registers writability (Error register not 309 * writable, but cyllo is), then try an ATA command. 310 */ 311 if (wdc->select) 312 wdc->select(chp,i); 313 bus_space_write_1(wdr->cmd_iot, 314 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 315 delay(10); /* 400ns delay */ 316 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 317 0, 0x58); 318 bus_space_write_1(wdr->cmd_iot, 319 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 320 if (bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_error], 0) == 0x58 || 322 bus_space_read_1(wdr->cmd_iot, 323 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 324 ATADEBUG_PRINT(("%s:%d:%d: register " 325 "writability failed\n", 326 atac->atac_dev.dv_xname, 327 chp->ch_channel, i), DEBUG_PROBE); 328 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 329 continue; 330 } 331 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 332 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 333 atac->atac_dev.dv_xname, 334 chp->ch_channel, i), DEBUG_PROBE); 335 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 336 continue; 337 } 338 bus_space_write_1(wdr->cmd_iot, 339 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 340 delay(10); /* 400ns delay */ 341 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 342 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 343 atac->atac_dev.dv_xname, 344 chp->ch_channel, i), DEBUG_PROBE); 345 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 346 } else { 347 chp->ch_drive[0].drive_flags &= 348 ~(DRIVE_ATA | DRIVE_ATAPI); 349 chp->ch_drive[1].drive_flags &= 350 ~(DRIVE_ATA | DRIVE_ATAPI); 351 } 352 } 353 } 354 } 355 356 int 357 wdcprobe(struct ata_channel *chp) 358 { 359 360 return (wdcprobe1(chp, 1)); 361 } 362 363 static int 364 wdcprobe1(struct ata_channel *chp, int poll) 365 { 366 struct atac_softc *atac = chp->ch_atac; 367 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 368 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 369 u_int8_t st0, st1, sc, sn, cl, ch; 370 u_int8_t ret_value = 0x03; 371 u_int8_t drive; 372 int s; 373 374 /* 375 * Sanity check to see if the wdc channel responds at all. 376 */ 377 378 s = splbio(); 379 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 380 381 if (wdc->select) 382 wdc->select(chp,0); 383 384 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 385 WDSD_IBM); 386 delay(10); /* 400ns delay */ 387 st0 = bus_space_read_1(wdr->cmd_iot, 388 wdr->cmd_iohs[wd_status], 0); 389 390 if (wdc->select) 391 wdc->select(chp,1); 392 393 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 394 WDSD_IBM | 0x10); 395 delay(10); /* 400ns delay */ 396 st1 = bus_space_read_1(wdr->cmd_iot, 397 wdr->cmd_iohs[wd_status], 0); 398 399 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 400 atac->atac_dev.dv_xname, 401 chp->ch_channel, st0, st1), DEBUG_PROBE); 402 403 if (st0 == 0xff || st0 == WDSD_IBM) 404 ret_value &= ~0x01; 405 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 406 ret_value &= ~0x02; 407 /* Register writability test, drive 0. */ 408 if (ret_value & 0x01) { 409 if (wdc->select) 410 wdc->select(chp,0); 411 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 412 0, WDSD_IBM); 413 bus_space_write_1(wdr->cmd_iot, 414 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 415 cl = bus_space_read_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_cyl_lo], 0); 417 if (cl != 0x02) { 418 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 419 "got 0x%x != 0x02\n", 420 atac->atac_dev.dv_xname, 421 chp->ch_channel, cl), 422 DEBUG_PROBE); 423 ret_value &= ~0x01; 424 } 425 bus_space_write_1(wdr->cmd_iot, 426 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 427 cl = bus_space_read_1(wdr->cmd_iot, 428 wdr->cmd_iohs[wd_cyl_lo], 0); 429 if (cl != 0x01) { 430 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 431 "got 0x%x != 0x01\n", 432 atac->atac_dev.dv_xname, 433 chp->ch_channel, cl), 434 DEBUG_PROBE); 435 ret_value &= ~0x01; 436 } 437 bus_space_write_1(wdr->cmd_iot, 438 wdr->cmd_iohs[wd_sector], 0, 0x01); 439 cl = bus_space_read_1(wdr->cmd_iot, 440 wdr->cmd_iohs[wd_sector], 0); 441 if (cl != 0x01) { 442 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 443 "got 0x%x != 0x01\n", 444 atac->atac_dev.dv_xname, 445 chp->ch_channel, cl), 446 DEBUG_PROBE); 447 ret_value &= ~0x01; 448 } 449 bus_space_write_1(wdr->cmd_iot, 450 wdr->cmd_iohs[wd_sector], 0, 0x02); 451 cl = bus_space_read_1(wdr->cmd_iot, 452 wdr->cmd_iohs[wd_sector], 0); 453 if (cl != 0x02) { 454 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 455 "got 0x%x != 0x02\n", 456 atac->atac_dev.dv_xname, 457 chp->ch_channel, cl), 458 DEBUG_PROBE); 459 ret_value &= ~0x01; 460 } 461 cl = bus_space_read_1(wdr->cmd_iot, 462 wdr->cmd_iohs[wd_cyl_lo], 0); 463 if (cl != 0x01) { 464 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 465 "got 0x%x != 0x01\n", 466 atac->atac_dev.dv_xname, 467 chp->ch_channel, cl), 468 DEBUG_PROBE); 469 ret_value &= ~0x01; 470 } 471 } 472 /* Register writability test, drive 1. */ 473 if (ret_value & 0x02) { 474 if (wdc->select) 475 wdc->select(chp,1); 476 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 477 0, WDSD_IBM | 0x10); 478 bus_space_write_1(wdr->cmd_iot, 479 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 480 cl = bus_space_read_1(wdr->cmd_iot, 481 wdr->cmd_iohs[wd_cyl_lo], 0); 482 if (cl != 0x02) { 483 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 484 "got 0x%x != 0x02\n", 485 atac->atac_dev.dv_xname, 486 chp->ch_channel, cl), 487 DEBUG_PROBE); 488 ret_value &= ~0x02; 489 } 490 bus_space_write_1(wdr->cmd_iot, 491 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 492 cl = bus_space_read_1(wdr->cmd_iot, 493 wdr->cmd_iohs[wd_cyl_lo], 0); 494 if (cl != 0x01) { 495 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 496 "got 0x%x != 0x01\n", 497 atac->atac_dev.dv_xname, 498 chp->ch_channel, cl), 499 DEBUG_PROBE); 500 ret_value &= ~0x02; 501 } 502 bus_space_write_1(wdr->cmd_iot, 503 wdr->cmd_iohs[wd_sector], 0, 0x01); 504 cl = bus_space_read_1(wdr->cmd_iot, 505 wdr->cmd_iohs[wd_sector], 0); 506 if (cl != 0x01) { 507 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 508 "got 0x%x != 0x01\n", 509 atac->atac_dev.dv_xname, 510 chp->ch_channel, cl), 511 DEBUG_PROBE); 512 ret_value &= ~0x02; 513 } 514 bus_space_write_1(wdr->cmd_iot, 515 wdr->cmd_iohs[wd_sector], 0, 0x02); 516 cl = bus_space_read_1(wdr->cmd_iot, 517 wdr->cmd_iohs[wd_sector], 0); 518 if (cl != 0x02) { 519 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 520 "got 0x%x != 0x02\n", 521 atac->atac_dev.dv_xname, 522 chp->ch_channel, cl), 523 DEBUG_PROBE); 524 ret_value &= ~0x02; 525 } 526 cl = bus_space_read_1(wdr->cmd_iot, 527 wdr->cmd_iohs[wd_cyl_lo], 0); 528 if (cl != 0x01) { 529 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 530 "got 0x%x != 0x01\n", 531 atac->atac_dev.dv_xname, 532 chp->ch_channel, cl), 533 DEBUG_PROBE); 534 ret_value &= ~0x02; 535 } 536 } 537 538 if (ret_value == 0) { 539 splx(s); 540 return 0; 541 } 542 } 543 544 545 #if 0 /* XXX this break some ATA or ATAPI devices */ 546 /* 547 * reset bus. Also send an ATAPI_RESET to devices, in case there are 548 * ATAPI device out there which don't react to the bus reset 549 */ 550 if (ret_value & 0x01) { 551 if (wdc->select) 552 wdc->select(chp,0); 553 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 554 0, WDSD_IBM); 555 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 556 ATAPI_SOFT_RESET); 557 } 558 if (ret_value & 0x02) { 559 if (wdc->select) 560 wdc->select(chp,0); 561 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 562 0, WDSD_IBM | 0x10); 563 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 564 ATAPI_SOFT_RESET); 565 } 566 567 delay(5000); 568 #endif 569 570 if (wdc->select) 571 wdc->select(chp,0); 572 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 573 delay(10); /* 400ns delay */ 574 /* assert SRST, wait for reset to complete */ 575 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 576 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 577 DELAY(1000); 578 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 579 WDCTL_IDS | WDCTL_4BIT); 580 DELAY(2000); 581 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 582 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 583 delay(10); /* 400ns delay */ 584 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 585 if (wdc->irqack != NULL) 586 wdc->irqack(chp); 587 splx(s); 588 589 ret_value = __wdcwait_reset(chp, ret_value, poll); 590 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 591 atac->atac_dev.dv_xname, chp->ch_channel, 592 ret_value), DEBUG_PROBE); 593 594 /* if reset failed, there's nothing here */ 595 if (ret_value == 0) 596 return 0; 597 598 /* 599 * Test presence of drives. First test register signatures looking 600 * for ATAPI devices. If it's not an ATAPI and reset said there may 601 * be something here assume it's ATA or OLD. Ghost will be killed 602 * later in attach routine. 603 */ 604 for (drive = 0; drive < 2; drive++) { 605 if ((ret_value & (0x01 << drive)) == 0) 606 continue; 607 if (wdc->select) 608 wdc->select(chp,drive); 609 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 610 WDSD_IBM | (drive << 4)); 611 delay(10); /* 400ns delay */ 612 /* Save registers contents */ 613 sc = bus_space_read_1(wdr->cmd_iot, 614 wdr->cmd_iohs[wd_seccnt], 0); 615 sn = bus_space_read_1(wdr->cmd_iot, 616 wdr->cmd_iohs[wd_sector], 0); 617 cl = bus_space_read_1(wdr->cmd_iot, 618 wdr->cmd_iohs[wd_cyl_lo], 0); 619 ch = bus_space_read_1(wdr->cmd_iot, 620 wdr->cmd_iohs[wd_cyl_hi], 0); 621 622 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 623 "cl=0x%x ch=0x%x\n", 624 atac->atac_dev.dv_xname, 625 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 626 /* 627 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 628 * we get wrong values here, so ignore it. 629 */ 630 if (cl == 0x14 && ch == 0xeb) { 631 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 632 } else { 633 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 634 if (wdc == NULL || 635 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 636 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 637 } 638 } 639 return (ret_value); 640 } 641 642 void 643 wdcattach(struct ata_channel *chp) 644 { 645 struct atac_softc *atac = chp->ch_atac; 646 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 647 648 /* 649 * Start out assuming 2 drives. This may change as we probe 650 * drives. 651 */ 652 chp->ch_ndrive = 2; 653 654 /* default data transfer methods */ 655 if (wdc->datain_pio == NULL) 656 wdc->datain_pio = wdc_datain_pio; 657 if (wdc->dataout_pio == NULL) 658 wdc->dataout_pio = wdc_dataout_pio; 659 660 /* initialise global data */ 661 if (atac->atac_bustype_ata == NULL) 662 atac->atac_bustype_ata = &wdc_ata_bustype; 663 if (atac->atac_probe == NULL) 664 atac->atac_probe = wdc_drvprobe; 665 #if NATAPIBUS > 0 666 if (atac->atac_atapibus_attach == NULL) 667 atac->atac_atapibus_attach = wdc_atapibus_attach; 668 #endif 669 670 ata_channel_attach(chp); 671 } 672 673 int 674 wdcactivate(struct device *self, enum devact act) 675 { 676 struct atac_softc *atac = (struct atac_softc *) self; 677 int s, i, error = 0; 678 679 s = splbio(); 680 switch (act) { 681 case DVACT_ACTIVATE: 682 error = EOPNOTSUPP; 683 break; 684 685 case DVACT_DEACTIVATE: 686 for (i = 0; i < atac->atac_nchannels; i++) { 687 error = 688 config_deactivate(atac->atac_channels[i]->atabus); 689 if (error) 690 break; 691 } 692 break; 693 } 694 splx(s); 695 return (error); 696 } 697 698 int 699 wdcdetach(struct device *self, int flags) 700 { 701 struct atac_softc *atac = (struct atac_softc *) self; 702 struct ata_channel *chp; 703 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 704 int i, error = 0; 705 706 for (i = 0; i < atac->atac_nchannels; i++) { 707 chp = atac->atac_channels[i]; 708 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 709 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 710 DEBUG_DETACH); 711 error = config_detach(chp->atabus, flags); 712 if (error) 713 break; 714 } 715 if (adapt->adapt_refcnt != 0) { 716 #ifdef DIAGNOSTIC 717 printf("wdcdetach: refcnt should be 0 here??\n"); 718 #endif 719 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 720 } 721 return (error); 722 } 723 724 /* restart an interrupted I/O */ 725 void 726 wdcrestart(void *v) 727 { 728 struct ata_channel *chp = v; 729 int s; 730 731 s = splbio(); 732 atastart(chp); 733 splx(s); 734 } 735 736 737 /* 738 * Interrupt routine for the controller. Acknowledge the interrupt, check for 739 * errors on the current operation, mark it done if necessary, and start the 740 * next request. Also check for a partially done transfer, and continue with 741 * the next chunk if so. 742 */ 743 int 744 wdcintr(void *arg) 745 { 746 struct ata_channel *chp = arg; 747 struct atac_softc *atac = chp->ch_atac; 748 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 749 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 750 struct ata_xfer *xfer; 751 int ret; 752 753 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 754 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 755 DEBUG_INTR); 756 return (0); 757 } 758 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 759 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 760 /* try to clear the pending interrupt anyway */ 761 (void)bus_space_read_1(wdr->cmd_iot, 762 wdr->cmd_iohs[wd_status], 0); 763 return (0); 764 } 765 766 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 767 xfer = chp->ch_queue->active_xfer; 768 #ifdef DIAGNOSTIC 769 if (xfer == NULL) 770 panic("wdcintr: no xfer"); 771 #endif 772 if (chp->ch_flags & ATACH_DMA_WAIT) { 773 wdc->dma_status = 774 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 775 xfer->c_drive, WDC_DMAEND_END); 776 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 777 /* IRQ not for us, not detected by DMA engine */ 778 return 0; 779 } 780 chp->ch_flags &= ~ATACH_DMA_WAIT; 781 } 782 chp->ch_flags &= ~ATACH_IRQ_WAIT; 783 ret = xfer->c_intr(chp, xfer, 1); 784 if (ret == 0) /* irq was not for us, still waiting for irq */ 785 chp->ch_flags |= ATACH_IRQ_WAIT; 786 return (ret); 787 } 788 789 /* Put all disk in RESET state */ 790 void 791 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 792 { 793 struct ata_channel *chp = drvp->chnl_softc; 794 struct atac_softc *atac = chp->ch_atac; 795 796 ATADEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 797 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 798 DEBUG_FUNCS); 799 800 801 wdc_reset_channel(chp, flags); 802 } 803 804 void 805 wdc_reset_channel(struct ata_channel *chp, int flags) 806 { 807 TAILQ_HEAD(, ata_xfer) reset_xfer; 808 struct ata_xfer *xfer, *next_xfer; 809 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 810 int drive; 811 812 chp->ch_queue->queue_freeze++; 813 TAILQ_INIT(&reset_xfer); 814 815 /* if we can poll or wait it's OK, otherwise wake up the kernel 816 * thread 817 */ 818 if ((flags & (AT_POLL | AT_WAIT)) == 0) { 819 if (chp->ch_flags & ATACH_TH_RESET) { 820 /* no need to schedule a reset more than one time */ 821 return; 822 } 823 chp->ch_flags |= ATACH_TH_RESET; 824 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD); 825 wakeup(&chp->ch_thread); 826 return; 827 } 828 829 chp->ch_flags &= ~ATACH_IRQ_WAIT; 830 /* 831 * if the current command if on an ATAPI device, issue a 832 * ATAPI_SOFT_RESET 833 */ 834 xfer = chp->ch_queue->active_xfer; 835 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 836 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 837 if (flags & AT_WAIT) 838 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 839 else 840 delay(1000); 841 } 842 843 /* reset the channel */ 844 if (flags & AT_WAIT) 845 (void) wdcreset(chp, RESET_SLEEP); 846 else 847 (void) wdcreset(chp, RESET_POLL); 848 849 /* 850 * wait a bit after reset; in case the DMA engines needs some time 851 * to recover. 852 */ 853 if (flags & AT_WAIT) 854 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 855 else 856 delay(1000); 857 /* 858 * look for pending xfers. If we have a shared queue, we'll also reset 859 * the other channel if the current xfer is running on it. 860 * Then we'll dequeue only the xfers for this channel. 861 */ 862 if ((flags & AT_RST_NOCMD) == 0) { 863 /* 864 * move all xfers queued for this channel to the reset queue, 865 * and then process the current xfer and then the reset queue. 866 * We have to use a temporary queue because c_kill_xfer() 867 * may requeue commands. 868 */ 869 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 870 xfer != NULL; xfer = next_xfer) { 871 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 872 if (xfer->c_chp != chp) 873 continue; 874 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 875 xfer, c_xferchain); 876 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 877 } 878 xfer = chp->ch_queue->active_xfer; 879 if (xfer) { 880 if (xfer->c_chp != chp) 881 wdc_reset_channel(xfer->c_chp, flags); 882 else { 883 callout_stop(&chp->ch_callout); 884 /* 885 * If we're waiting for DMA, stop the 886 * DMA engine 887 */ 888 if (chp->ch_flags & ATACH_DMA_WAIT) { 889 (*wdc->dma_finish)( 890 wdc->dma_arg, 891 chp->ch_channel, 892 xfer->c_drive, 893 WDC_DMAEND_ABRT_QUIET); 894 chp->ch_flags &= ~ATACH_DMA_WAIT; 895 } 896 chp->ch_queue->active_xfer = NULL; 897 if ((flags & AT_RST_EMERG) == 0) 898 xfer->c_kill_xfer( 899 chp, xfer, KILL_RESET); 900 } 901 } 902 903 for (xfer = TAILQ_FIRST(&reset_xfer); 904 xfer != NULL; xfer = next_xfer) { 905 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 906 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 907 if ((flags & AT_RST_EMERG) == 0) 908 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 909 } 910 } 911 for (drive = 0; drive < chp->ch_ndrive; drive++) { 912 chp->ch_drive[drive].state = 0; 913 } 914 chp->ch_flags &= ~ATACH_TH_RESET; 915 if ((flags & AT_RST_EMERG) == 0) { 916 chp->ch_queue->queue_freeze--; 917 atastart(chp); 918 } else { 919 /* make sure that we can use polled commands */ 920 TAILQ_INIT(&chp->ch_queue->queue_xfer); 921 chp->ch_queue->queue_freeze = 0; 922 chp->ch_queue->active_xfer = NULL; 923 } 924 } 925 926 int 927 wdcreset(struct ata_channel *chp, int poll) 928 { 929 struct atac_softc *atac = chp->ch_atac; 930 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 931 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 932 int drv_mask1, drv_mask2; 933 int s = 0; 934 935 if (wdc->select) 936 wdc->select(chp,0); 937 if (poll != RESET_SLEEP) 938 s = splbio(); 939 /* master */ 940 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 941 delay(10); /* 400ns delay */ 942 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 943 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 944 delay(2000); 945 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 946 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 947 WDCTL_4BIT | WDCTL_IDS); 948 delay(10); /* 400ns delay */ 949 if (poll != RESET_SLEEP) { 950 if (wdc->irqack) 951 wdc->irqack(chp); 952 splx(s); 953 } 954 955 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 956 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 957 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 958 (poll == RESET_SLEEP) ? 0 : 1); 959 if (drv_mask2 != drv_mask1) { 960 printf("%s channel %d: reset failed for", 961 atac->atac_dev.dv_xname, chp->ch_channel); 962 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 963 printf(" drive 0"); 964 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 965 printf(" drive 1"); 966 printf("\n"); 967 } 968 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 969 return (drv_mask1 != drv_mask2) ? 1 : 0; 970 } 971 972 static int 973 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 974 { 975 struct atac_softc *atac = chp->ch_atac; 976 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 977 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 978 int timeout, nloop; 979 u_int8_t st0 = 0, st1 = 0; 980 #ifdef ATADEBUG 981 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 982 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 983 #endif 984 985 if (poll) 986 nloop = WDCNDELAY_RST; 987 else 988 nloop = WDC_RESET_WAIT * hz / 1000; 989 /* wait for BSY to deassert */ 990 for (timeout = 0; timeout < nloop; timeout++) { 991 if ((drv_mask & 0x01) != 0) { 992 if (wdc && wdc->select) 993 wdc->select(chp,0); 994 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 995 0, WDSD_IBM); /* master */ 996 delay(10); 997 st0 = bus_space_read_1(wdr->cmd_iot, 998 wdr->cmd_iohs[wd_status], 0); 999 #ifdef ATADEBUG 1000 sc0 = bus_space_read_1(wdr->cmd_iot, 1001 wdr->cmd_iohs[wd_seccnt], 0); 1002 sn0 = bus_space_read_1(wdr->cmd_iot, 1003 wdr->cmd_iohs[wd_sector], 0); 1004 cl0 = bus_space_read_1(wdr->cmd_iot, 1005 wdr->cmd_iohs[wd_cyl_lo], 0); 1006 ch0 = bus_space_read_1(wdr->cmd_iot, 1007 wdr->cmd_iohs[wd_cyl_hi], 0); 1008 #endif 1009 } 1010 if ((drv_mask & 0x02) != 0) { 1011 if (wdc && wdc->select) 1012 wdc->select(chp,1); 1013 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1014 0, WDSD_IBM | 0x10); /* slave */ 1015 delay(10); 1016 st1 = bus_space_read_1(wdr->cmd_iot, 1017 wdr->cmd_iohs[wd_status], 0); 1018 #ifdef ATADEBUG 1019 sc1 = bus_space_read_1(wdr->cmd_iot, 1020 wdr->cmd_iohs[wd_seccnt], 0); 1021 sn1 = bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_sector], 0); 1023 cl1 = bus_space_read_1(wdr->cmd_iot, 1024 wdr->cmd_iohs[wd_cyl_lo], 0); 1025 ch1 = bus_space_read_1(wdr->cmd_iot, 1026 wdr->cmd_iohs[wd_cyl_hi], 0); 1027 #endif 1028 } 1029 1030 if ((drv_mask & 0x01) == 0) { 1031 /* no master */ 1032 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1033 /* No master, slave is ready, it's done */ 1034 goto end; 1035 } 1036 } else if ((drv_mask & 0x02) == 0) { 1037 /* no slave */ 1038 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1039 /* No slave, master is ready, it's done */ 1040 goto end; 1041 } 1042 } else { 1043 /* Wait for both master and slave to be ready */ 1044 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1045 goto end; 1046 } 1047 } 1048 if (poll) 1049 delay(WDCDELAY); 1050 else 1051 tsleep(&nloop, PRIBIO, "atarst", 1); 1052 } 1053 /* Reset timed out. Maybe it's because drv_mask was not right */ 1054 if (st0 & WDCS_BSY) 1055 drv_mask &= ~0x01; 1056 if (st1 & WDCS_BSY) 1057 drv_mask &= ~0x02; 1058 end: 1059 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1060 "cl=0x%x ch=0x%x\n", 1061 atac->atac_dev.dv_xname, 1062 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1063 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1064 "cl=0x%x ch=0x%x\n", 1065 atac->atac_dev.dv_xname, 1066 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1067 1068 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1069 atac->atac_dev.dv_xname, chp->ch_channel, 1070 st0, st1), DEBUG_PROBE); 1071 1072 return drv_mask; 1073 } 1074 1075 /* 1076 * Wait for a drive to be !BSY, and have mask in its status register. 1077 * return -1 for a timeout after "timeout" ms. 1078 */ 1079 static int 1080 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1081 { 1082 struct atac_softc *atac = chp->ch_atac; 1083 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1084 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1085 u_char status; 1086 int time = 0; 1087 1088 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1089 atac->atac_dev.dv_xname, 1090 chp->ch_channel), DEBUG_STATUS); 1091 chp->ch_error = 0; 1092 1093 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1094 1095 for (;;) { 1096 chp->ch_status = status = 1097 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1098 if ((status & (WDCS_BSY | mask)) == bits) 1099 break; 1100 if (++time > timeout) { 1101 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1102 "status %x error %x (mask 0x%x bits 0x%x)\n", 1103 time, status, 1104 bus_space_read_1(wdr->cmd_iot, 1105 wdr->cmd_iohs[wd_error], 0), mask, bits), 1106 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1107 return(WDCWAIT_TOUT); 1108 } 1109 delay(WDCDELAY); 1110 } 1111 #ifdef ATADEBUG 1112 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1113 printf("__wdcwait: did busy-wait, time=%d\n", time); 1114 #endif 1115 if (status & WDCS_ERR) 1116 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_error], 0); 1118 #ifdef WDCNDELAY_DEBUG 1119 /* After autoconfig, there should be no long delays. */ 1120 if (!cold && time > WDCNDELAY_DEBUG) { 1121 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1122 if (xfer == NULL) 1123 printf("%s channel %d: warning: busy-wait took %dus\n", 1124 atac->atac_dev.dv_xname, chp->ch_channel, 1125 WDCDELAY * time); 1126 else 1127 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1128 atac->atac_dev.dv_xname, chp->ch_channel, 1129 xfer->drive, 1130 WDCDELAY * time); 1131 } 1132 #endif 1133 return(WDCWAIT_OK); 1134 } 1135 1136 /* 1137 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1138 * thread if possible 1139 */ 1140 int 1141 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1142 { 1143 int error, i, timeout_hz = mstohz(timeout); 1144 1145 if (timeout_hz == 0 || 1146 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1147 error = __wdcwait(chp, mask, bits, timeout); 1148 else { 1149 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1150 if (error != 0) { 1151 if ((chp->ch_flags & ATACH_TH_RUN) || 1152 (flags & AT_WAIT)) { 1153 /* 1154 * we're running in the channel thread 1155 * or some userland thread context 1156 */ 1157 for (i = 0; i < timeout_hz; i++) { 1158 if (__wdcwait(chp, mask, bits, 1159 WDCDELAY_POLL) == 0) { 1160 error = 0; 1161 break; 1162 } 1163 tsleep(&chp, PRIBIO, "atapoll", 1); 1164 } 1165 } else { 1166 /* 1167 * we're probably in interrupt context, 1168 * ask the thread to come back here 1169 */ 1170 #ifdef DIAGNOSTIC 1171 if (chp->ch_queue->queue_freeze > 0) 1172 panic("wdcwait: queue_freeze"); 1173 #endif 1174 chp->ch_queue->queue_freeze++; 1175 wakeup(&chp->ch_thread); 1176 return(WDCWAIT_THR); 1177 } 1178 } 1179 } 1180 return (error); 1181 } 1182 1183 1184 /* 1185 * Busy-wait for DMA to complete 1186 */ 1187 int 1188 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1189 { 1190 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1191 int time; 1192 1193 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1194 wdc->dma_status = 1195 (*wdc->dma_finish)(wdc->dma_arg, 1196 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1197 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1198 return 0; 1199 delay(WDCDELAY); 1200 } 1201 /* timeout, force a DMA halt */ 1202 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1203 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1204 return 1; 1205 } 1206 1207 void 1208 wdctimeout(void *arg) 1209 { 1210 struct ata_channel *chp = (struct ata_channel *)arg; 1211 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1212 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1213 int s; 1214 1215 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1216 1217 s = splbio(); 1218 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1219 __wdcerror(chp, "lost interrupt"); 1220 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1221 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1222 xfer->c_bcount, 1223 xfer->c_skip); 1224 if (chp->ch_flags & ATACH_DMA_WAIT) { 1225 wdc->dma_status = 1226 (*wdc->dma_finish)(wdc->dma_arg, 1227 chp->ch_channel, xfer->c_drive, 1228 WDC_DMAEND_ABRT); 1229 chp->ch_flags &= ~ATACH_DMA_WAIT; 1230 } 1231 /* 1232 * Call the interrupt routine. If we just missed an interrupt, 1233 * it will do what's needed. Else, it will take the needed 1234 * action (reset the device). 1235 * Before that we need to reinstall the timeout callback, 1236 * in case it will miss another irq while in this transfer 1237 * We arbitray chose it to be 1s 1238 */ 1239 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1240 xfer->c_flags |= C_TIMEOU; 1241 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1242 xfer->c_intr(chp, xfer, 1); 1243 } else 1244 __wdcerror(chp, "missing untimeout"); 1245 splx(s); 1246 } 1247 1248 int 1249 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1250 { 1251 struct ata_channel *chp = drvp->chnl_softc; 1252 struct atac_softc *atac = chp->ch_atac; 1253 struct ata_xfer *xfer; 1254 int s, ret; 1255 1256 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1257 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1258 DEBUG_FUNCS); 1259 1260 /* set up an xfer and queue. Wait for completion */ 1261 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1262 ATAXF_NOSLEEP); 1263 if (xfer == NULL) { 1264 return ATACMD_TRY_AGAIN; 1265 } 1266 1267 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1268 ata_c->flags |= AT_POLL; 1269 if (ata_c->flags & AT_POLL) 1270 xfer->c_flags |= C_POLL; 1271 xfer->c_drive = drvp->drive; 1272 xfer->c_databuf = ata_c->data; 1273 xfer->c_bcount = ata_c->bcount; 1274 xfer->c_cmd = ata_c; 1275 xfer->c_start = __wdccommand_start; 1276 xfer->c_intr = __wdccommand_intr; 1277 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1278 1279 s = splbio(); 1280 ata_exec_xfer(chp, xfer); 1281 #ifdef DIAGNOSTIC 1282 if ((ata_c->flags & AT_POLL) != 0 && 1283 (ata_c->flags & AT_DONE) == 0) 1284 panic("wdc_exec_command: polled command not done"); 1285 #endif 1286 if (ata_c->flags & AT_DONE) { 1287 ret = ATACMD_COMPLETE; 1288 } else { 1289 if (ata_c->flags & AT_WAIT) { 1290 while ((ata_c->flags & AT_DONE) == 0) { 1291 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1292 } 1293 ret = ATACMD_COMPLETE; 1294 } else { 1295 ret = ATACMD_QUEUED; 1296 } 1297 } 1298 splx(s); 1299 return ret; 1300 } 1301 1302 static void 1303 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1304 { 1305 struct atac_softc *atac = chp->ch_atac; 1306 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1307 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1308 int drive = xfer->c_drive; 1309 struct ata_command *ata_c = xfer->c_cmd; 1310 1311 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1312 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1313 DEBUG_FUNCS); 1314 1315 if (wdc->select) 1316 wdc->select(chp,drive); 1317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1318 WDSD_IBM | (drive << 4)); 1319 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1320 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1321 case WDCWAIT_OK: 1322 break; 1323 case WDCWAIT_TOUT: 1324 ata_c->flags |= AT_TIMEOU; 1325 __wdccommand_done(chp, xfer); 1326 return; 1327 case WDCWAIT_THR: 1328 return; 1329 } 1330 if (ata_c->flags & AT_POLL) { 1331 /* polled command, disable interrupts */ 1332 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1333 WDCTL_4BIT | WDCTL_IDS); 1334 } 1335 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1336 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1337 1338 if ((ata_c->flags & AT_POLL) == 0) { 1339 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1340 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1341 wdctimeout, chp); 1342 return; 1343 } 1344 /* 1345 * Polled command. Wait for drive ready or drq. Done in intr(). 1346 * Wait for at last 400ns for status bit to be valid. 1347 */ 1348 delay(10); /* 400ns delay */ 1349 __wdccommand_intr(chp, xfer, 0); 1350 } 1351 1352 static int 1353 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1354 { 1355 struct atac_softc *atac = chp->ch_atac; 1356 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1357 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1358 struct ata_command *ata_c = xfer->c_cmd; 1359 int bcount = ata_c->bcount; 1360 char *data = ata_c->data; 1361 int wflags; 1362 1363 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1364 /* both wait and poll, we can tsleep here */ 1365 wflags = AT_WAIT | AT_POLL; 1366 } else { 1367 wflags = AT_POLL; 1368 } 1369 1370 again: 1371 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1372 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1373 DEBUG_INTR); 1374 /* 1375 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1376 * Reselect again, it doesn't hurt for others commands, and the time 1377 * penalty for the extra regiter write is acceptable, 1378 * wdc_exec_command() isn't called often (mosly for autoconfig) 1379 */ 1380 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1381 WDSD_IBM | (xfer->c_drive << 4)); 1382 if ((ata_c->flags & AT_XFDONE) != 0) { 1383 /* 1384 * We have completed a data xfer. The drive should now be 1385 * in its initial state 1386 */ 1387 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1388 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1389 wflags) == WDCWAIT_TOUT) { 1390 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1391 return 0; /* IRQ was not for us */ 1392 ata_c->flags |= AT_TIMEOU; 1393 } 1394 goto out; 1395 } 1396 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1397 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1398 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1399 return 0; /* IRQ was not for us */ 1400 ata_c->flags |= AT_TIMEOU; 1401 goto out; 1402 } 1403 if (wdc->irqack) 1404 wdc->irqack(chp); 1405 if (ata_c->flags & AT_READ) { 1406 if ((chp->ch_status & WDCS_DRQ) == 0) { 1407 ata_c->flags |= AT_TIMEOU; 1408 goto out; 1409 } 1410 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1411 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1412 0, (u_int32_t*)data, bcount >> 2); 1413 data += bcount & 0xfffffffc; 1414 bcount = bcount & 0x03; 1415 } 1416 if (bcount > 0) 1417 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1418 /* at this point the drive should be in its initial state */ 1419 ata_c->flags |= AT_XFDONE; 1420 /* XXX should read status register here ? */ 1421 } else if (ata_c->flags & AT_WRITE) { 1422 if ((chp->ch_status & WDCS_DRQ) == 0) { 1423 ata_c->flags |= AT_TIMEOU; 1424 goto out; 1425 } 1426 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1427 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1428 0, (u_int32_t*)data, bcount >> 2); 1429 data += bcount & 0xfffffffc; 1430 bcount = bcount & 0x03; 1431 } 1432 if (bcount > 0) 1433 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1434 ata_c->flags |= AT_XFDONE; 1435 if ((ata_c->flags & AT_POLL) == 0) { 1436 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1437 callout_reset(&chp->ch_callout, 1438 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1439 return 1; 1440 } else { 1441 goto again; 1442 } 1443 } 1444 out: 1445 __wdccommand_done(chp, xfer); 1446 return 1; 1447 } 1448 1449 static void 1450 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1451 { 1452 struct atac_softc *atac = chp->ch_atac; 1453 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1454 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1455 struct ata_command *ata_c = xfer->c_cmd; 1456 1457 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1458 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1459 DEBUG_FUNCS); 1460 1461 1462 if (chp->ch_status & WDCS_DWF) 1463 ata_c->flags |= AT_DF; 1464 if (chp->ch_status & WDCS_ERR) { 1465 ata_c->flags |= AT_ERROR; 1466 ata_c->r_error = chp->ch_error; 1467 } 1468 if ((ata_c->flags & AT_READREG) != 0 && 1469 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1470 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1471 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1472 wdr->cmd_iohs[wd_sdh], 0); 1473 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1474 wdr->cmd_iohs[wd_seccnt], 0); 1475 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1476 wdr->cmd_iohs[wd_sector], 0); 1477 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1478 wdr->cmd_iohs[wd_cyl_lo], 0); 1479 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1480 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1481 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1482 wdr->cmd_iohs[wd_error], 0); 1483 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1484 wdr->cmd_iohs[wd_features], 0); 1485 } 1486 callout_stop(&chp->ch_callout); 1487 chp->ch_queue->active_xfer = NULL; 1488 if (ata_c->flags & AT_POLL) { 1489 /* enable interrupts */ 1490 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1491 WDCTL_4BIT); 1492 delay(10); /* some drives need a little delay here */ 1493 } 1494 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1495 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1496 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1497 wakeup(&chp->ch_queue->active_xfer); 1498 } else 1499 __wdccommand_done_end(chp, xfer); 1500 } 1501 1502 static void 1503 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1504 { 1505 struct ata_command *ata_c = xfer->c_cmd; 1506 1507 ata_c->flags |= AT_DONE; 1508 ata_free_xfer(chp, xfer); 1509 if (ata_c->flags & AT_WAIT) 1510 wakeup(ata_c); 1511 else if (ata_c->callback) 1512 ata_c->callback(ata_c->callback_arg); 1513 atastart(chp); 1514 return; 1515 } 1516 1517 static void 1518 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1519 int reason) 1520 { 1521 struct ata_command *ata_c = xfer->c_cmd; 1522 1523 switch (reason) { 1524 case KILL_GONE: 1525 ata_c->flags |= AT_GONE; 1526 break; 1527 case KILL_RESET: 1528 ata_c->flags |= AT_RESET; 1529 break; 1530 default: 1531 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1532 reason); 1533 panic("__wdccommand_kill_xfer"); 1534 } 1535 __wdccommand_done_end(chp, xfer); 1536 } 1537 1538 /* 1539 * Send a command. The drive should be ready. 1540 * Assumes interrupts are blocked. 1541 */ 1542 void 1543 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1544 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1545 u_int8_t features) 1546 { 1547 struct atac_softc *atac = chp->ch_atac; 1548 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1549 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1550 1551 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1552 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1553 chp->ch_channel, drive, command, cylin, head, sector, count, 1554 features), DEBUG_FUNCS); 1555 1556 if (wdc->select) 1557 wdc->select(chp,drive); 1558 1559 /* Select drive, head, and addressing mode. */ 1560 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1561 WDSD_IBM | (drive << 4) | head); 1562 /* Load parameters into the wd_features register. */ 1563 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1564 features); 1565 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1566 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1567 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1568 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1569 0, cylin >> 8); 1570 1571 /* Send command. */ 1572 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1573 return; 1574 } 1575 1576 /* 1577 * Send a 48-bit addressing command. The drive should be ready. 1578 * Assumes interrupts are blocked. 1579 */ 1580 void 1581 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1582 u_int64_t blkno, u_int16_t count) 1583 { 1584 struct atac_softc *atac = chp->ch_atac; 1585 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1586 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1587 1588 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1589 "count=%d\n", atac->atac_dev.dv_xname, 1590 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1591 DEBUG_FUNCS); 1592 1593 if (wdc->select) 1594 wdc->select(chp,drive); 1595 1596 /* Select drive, head, and addressing mode. */ 1597 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1598 (drive << 4) | WDSD_LBA); 1599 1600 /* previous */ 1601 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1603 0, count >> 8); 1604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1605 0, blkno >> 24); 1606 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1607 0, blkno >> 32); 1608 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1609 0, blkno >> 40); 1610 1611 /* current */ 1612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1614 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1615 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1616 0, blkno >> 8); 1617 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1618 0, blkno >> 16); 1619 1620 /* Send command. */ 1621 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1622 return; 1623 } 1624 1625 /* 1626 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1627 * tested by the caller. 1628 */ 1629 void 1630 wdccommandshort(struct ata_channel *chp, int drive, int command) 1631 { 1632 struct atac_softc *atac = chp->ch_atac; 1633 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1634 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1635 1636 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1637 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1638 DEBUG_FUNCS); 1639 1640 if (wdc->select) 1641 wdc->select(chp,drive); 1642 1643 /* Select drive. */ 1644 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1645 WDSD_IBM | (drive << 4)); 1646 1647 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1648 } 1649 1650 static void 1651 __wdcerror(struct ata_channel *chp, char *msg) 1652 { 1653 struct atac_softc *atac = chp->ch_atac; 1654 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1655 1656 if (xfer == NULL) 1657 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1658 msg); 1659 else 1660 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1661 chp->ch_channel, xfer->c_drive, msg); 1662 } 1663 1664 /* 1665 * the bit bucket 1666 */ 1667 void 1668 wdcbit_bucket(struct ata_channel *chp, int size) 1669 { 1670 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1671 1672 for (; size >= 2; size -= 2) 1673 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1674 if (size) 1675 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1676 } 1677 1678 void 1679 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1680 { 1681 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1682 1683 if (flags & DRIVE_NOSTREAM) { 1684 if (flags & DRIVE_CAP32) { 1685 bus_space_read_multi_4(wdr->data32iot, 1686 wdr->data32ioh, 0, buf, len >> 2); 1687 buf = (char *)buf + (len & ~3); 1688 len &= 3; 1689 } 1690 if (len) { 1691 bus_space_read_multi_2(wdr->cmd_iot, 1692 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1693 } 1694 } else { 1695 if (flags & DRIVE_CAP32) { 1696 bus_space_read_multi_stream_4(wdr->data32iot, 1697 wdr->data32ioh, 0, buf, len >> 2); 1698 buf = (char *)buf + (len & ~3); 1699 len &= 3; 1700 } 1701 if (len) { 1702 bus_space_read_multi_stream_2(wdr->cmd_iot, 1703 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1704 } 1705 } 1706 } 1707 1708 void 1709 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1710 { 1711 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1712 1713 if (flags & DRIVE_NOSTREAM) { 1714 if (flags & DRIVE_CAP32) { 1715 bus_space_write_multi_4(wdr->data32iot, 1716 wdr->data32ioh, 0, buf, len >> 2); 1717 buf = (char *)buf + (len & ~3); 1718 len &= 3; 1719 } 1720 if (len) { 1721 bus_space_write_multi_2(wdr->cmd_iot, 1722 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1723 } 1724 } else { 1725 if (flags & DRIVE_CAP32) { 1726 bus_space_write_multi_stream_4(wdr->data32iot, 1727 wdr->data32ioh, 0, buf, len >> 2); 1728 buf = (char *)buf + (len & ~3); 1729 len &= 3; 1730 } 1731 if (len) { 1732 bus_space_write_multi_stream_2(wdr->cmd_iot, 1733 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1734 } 1735 } 1736 } 1737
Indexes created Fri Sep 26 08:10:20 GMT 2025