wdc.c revision 1.211
1 /* $NetBSD: wdc.c,v 1.211 2004/08/20 23:26:54 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.211 2004/08/20 23:26:54 thorpej Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, /* wdc_ata_bio */ 129 NULL, /* wdc_reset_drive */ 130 NULL, /* wdc_reset_channel */ 131 NULL, /* wdc_exec_command */ 132 NULL, /* ata_get_params */ 133 NULL, /* wdc_ata_addref */ 134 NULL, /* wdc_ata_delref */ 135 NULL /* ata_kill_pending */ 136 }; 137 #endif 138 139 static int wdcprobe1(struct ata_channel*, int); 140 static void __wdcerror(struct ata_channel*, char *); 141 static int __wdcwait_reset(struct ata_channel *, int, int); 142 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 143 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 144 static void __wdccommand_kill_xfer(struct ata_channel *, 145 struct ata_xfer *, int); 146 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 147 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 148 static int __wdcwait(struct ata_channel *, int, int, int); 149 150 #define DEBUG_INTR 0x01 151 #define DEBUG_XFERS 0x02 152 #define DEBUG_STATUS 0x04 153 #define DEBUG_FUNCS 0x08 154 #define DEBUG_PROBE 0x10 155 #define DEBUG_DETACH 0x20 156 #define DEBUG_DELAY 0x40 157 #ifdef ATADEBUG 158 extern int atadebug_mask; /* init'ed in ata.c */ 159 int wdc_nxfer = 0; 160 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 161 #else 162 #define ATADEBUG_PRINT(args, level) 163 #endif 164 165 /* 166 * Initialize the "shadow register" handles for a standard wdc controller. 167 */ 168 void 169 wdc_init_shadow_regs(struct ata_channel *chp) 170 { 171 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 172 173 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 174 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 175 } 176 177 /* 178 * Allocate a wdc_regs array, based on the number of channels. 179 */ 180 void 181 wdc_allocate_regs(struct wdc_softc *wdc) 182 { 183 184 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 185 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 186 } 187 188 /* Test to see controller with at last one attached drive is there. 189 * Returns a bit for each possible drive found (0x01 for drive 0, 190 * 0x02 for drive 1). 191 * Logic: 192 * - If a status register is at 0xff, assume there is no drive here 193 * (ISA has pull-up resistors). Similarly if the status register has 194 * the value we last wrote to the bus (for IDE interfaces without pullups). 195 * If no drive at all -> return. 196 * - reset the controller, wait for it to complete (may take up to 31s !). 197 * If timeout -> return. 198 * - test ATA/ATAPI signatures. If at last one drive found -> return. 199 * - try an ATA command on the master. 200 */ 201 202 static void 203 wdc_drvprobe(struct ata_channel *chp) 204 { 205 struct ataparams params; 206 struct atac_softc *atac = chp->ch_atac; 207 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 208 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 209 u_int8_t st0 = 0, st1 = 0; 210 int i, error; 211 212 if (wdcprobe1(chp, 0) == 0) { 213 /* No drives, abort the attach here. */ 214 return; 215 } 216 217 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 218 for (i = 0; i < mstohz(3000); i++) { 219 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 220 if (wdc->select) 221 wdc->select(chp,0); 222 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 223 0, WDSD_IBM); 224 delay(10); /* 400ns delay */ 225 st0 = bus_space_read_1(wdr->cmd_iot, 226 wdr->cmd_iohs[wd_status], 0); 227 } 228 229 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 230 if (wdc->select) 231 wdc->select(chp,1); 232 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 233 0, WDSD_IBM | 0x10); 234 delay(10); /* 400ns delay */ 235 st1 = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_status], 0); 237 } 238 239 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 240 == 0 || 241 (st0 & WDCS_DRDY)) && 242 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 243 == 0 || 244 (st1 & WDCS_DRDY))) 245 break; 246 tsleep(¶ms, PRIBIO, "atadrdy", 1); 247 } 248 if ((st0 & WDCS_DRDY) == 0) 249 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 250 if ((st1 & WDCS_DRDY) == 0) 251 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 252 253 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 254 atac->atac_dev.dv_xname, 255 chp->ch_channel, st0, st1), DEBUG_PROBE); 256 257 /* Wait a bit, some devices are weird just after a reset. */ 258 delay(5000); 259 260 for (i = 0; i < 2; i++) { 261 /* XXX This should be done by other code. */ 262 chp->ch_drive[i].chnl_softc = chp; 263 chp->ch_drive[i].drive = i; 264 265 /* 266 * Init error counter so that an error withing the first xfers 267 * will trigger a downgrade 268 */ 269 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 270 271 /* If controller can't do 16bit flag the drives as 32bit */ 272 if ((atac->atac_cap & 273 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) 274 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 275 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 276 continue; 277 278 /* Shortcut in case we've been shutdown */ 279 if (chp->ch_flags & ATACH_SHUTDOWN) 280 return; 281 282 /* issue an identify, to try to detect ghosts */ 283 error = ata_get_params(&chp->ch_drive[i], 284 AT_WAIT | AT_POLL, ¶ms); 285 if (error != CMD_OK) { 286 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 287 288 /* Shortcut in case we've been shutdown */ 289 if (chp->ch_flags & ATACH_SHUTDOWN) 290 return; 291 292 error = ata_get_params(&chp->ch_drive[i], 293 AT_WAIT | AT_POLL, ¶ms); 294 } 295 if (error == CMD_OK) { 296 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 297 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 298 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 299 } else { 300 chp->ch_drive[i].drive_flags &= 301 ~(DRIVE_ATA | DRIVE_ATAPI); 302 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 303 atac->atac_dev.dv_xname, 304 chp->ch_channel, i, error), DEBUG_PROBE); 305 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 306 continue; 307 /* 308 * Pre-ATA drive ? 309 * Test registers writability (Error register not 310 * writable, but cyllo is), then try an ATA command. 311 */ 312 if (wdc->select) 313 wdc->select(chp,i); 314 bus_space_write_1(wdr->cmd_iot, 315 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 316 delay(10); /* 400ns delay */ 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 318 0, 0x58); 319 bus_space_write_1(wdr->cmd_iot, 320 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 321 if (bus_space_read_1(wdr->cmd_iot, 322 wdr->cmd_iohs[wd_error], 0) == 0x58 || 323 bus_space_read_1(wdr->cmd_iot, 324 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 325 ATADEBUG_PRINT(("%s:%d:%d: register " 326 "writability failed\n", 327 atac->atac_dev.dv_xname, 328 chp->ch_channel, i), DEBUG_PROBE); 329 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 330 continue; 331 } 332 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 333 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 334 atac->atac_dev.dv_xname, 335 chp->ch_channel, i), DEBUG_PROBE); 336 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 337 continue; 338 } 339 bus_space_write_1(wdr->cmd_iot, 340 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 341 delay(10); /* 400ns delay */ 342 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 343 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 344 atac->atac_dev.dv_xname, 345 chp->ch_channel, i), DEBUG_PROBE); 346 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 347 } else { 348 chp->ch_drive[0].drive_flags &= 349 ~(DRIVE_ATA | DRIVE_ATAPI); 350 chp->ch_drive[1].drive_flags &= 351 ~(DRIVE_ATA | DRIVE_ATAPI); 352 } 353 } 354 } 355 } 356 357 int 358 wdcprobe(struct ata_channel *chp) 359 { 360 361 return (wdcprobe1(chp, 1)); 362 } 363 364 static int 365 wdcprobe1(struct ata_channel *chp, int poll) 366 { 367 struct atac_softc *atac = chp->ch_atac; 368 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 369 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 370 u_int8_t st0, st1, sc, sn, cl, ch; 371 u_int8_t ret_value = 0x03; 372 u_int8_t drive; 373 int s; 374 375 /* 376 * Sanity check to see if the wdc channel responds at all. 377 */ 378 379 s = splbio(); 380 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 381 382 if (wdc->select) 383 wdc->select(chp,0); 384 385 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 386 WDSD_IBM); 387 delay(10); /* 400ns delay */ 388 st0 = bus_space_read_1(wdr->cmd_iot, 389 wdr->cmd_iohs[wd_status], 0); 390 391 if (wdc->select) 392 wdc->select(chp,1); 393 394 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 395 WDSD_IBM | 0x10); 396 delay(10); /* 400ns delay */ 397 st1 = bus_space_read_1(wdr->cmd_iot, 398 wdr->cmd_iohs[wd_status], 0); 399 400 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 401 atac->atac_dev.dv_xname, 402 chp->ch_channel, st0, st1), DEBUG_PROBE); 403 404 if (st0 == 0xff || st0 == WDSD_IBM) 405 ret_value &= ~0x01; 406 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 407 ret_value &= ~0x02; 408 /* Register writability test, drive 0. */ 409 if (ret_value & 0x01) { 410 if (wdc->select) 411 wdc->select(chp,0); 412 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 413 0, WDSD_IBM); 414 bus_space_write_1(wdr->cmd_iot, 415 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 416 cl = bus_space_read_1(wdr->cmd_iot, 417 wdr->cmd_iohs[wd_cyl_lo], 0); 418 if (cl != 0x02) { 419 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 420 "got 0x%x != 0x02\n", 421 atac->atac_dev.dv_xname, 422 chp->ch_channel, cl), 423 DEBUG_PROBE); 424 ret_value &= ~0x01; 425 } 426 bus_space_write_1(wdr->cmd_iot, 427 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 428 cl = bus_space_read_1(wdr->cmd_iot, 429 wdr->cmd_iohs[wd_cyl_lo], 0); 430 if (cl != 0x01) { 431 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 432 "got 0x%x != 0x01\n", 433 atac->atac_dev.dv_xname, 434 chp->ch_channel, cl), 435 DEBUG_PROBE); 436 ret_value &= ~0x01; 437 } 438 bus_space_write_1(wdr->cmd_iot, 439 wdr->cmd_iohs[wd_sector], 0, 0x01); 440 cl = bus_space_read_1(wdr->cmd_iot, 441 wdr->cmd_iohs[wd_sector], 0); 442 if (cl != 0x01) { 443 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 444 "got 0x%x != 0x01\n", 445 atac->atac_dev.dv_xname, 446 chp->ch_channel, cl), 447 DEBUG_PROBE); 448 ret_value &= ~0x01; 449 } 450 bus_space_write_1(wdr->cmd_iot, 451 wdr->cmd_iohs[wd_sector], 0, 0x02); 452 cl = bus_space_read_1(wdr->cmd_iot, 453 wdr->cmd_iohs[wd_sector], 0); 454 if (cl != 0x02) { 455 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 456 "got 0x%x != 0x02\n", 457 atac->atac_dev.dv_xname, 458 chp->ch_channel, cl), 459 DEBUG_PROBE); 460 ret_value &= ~0x01; 461 } 462 cl = bus_space_read_1(wdr->cmd_iot, 463 wdr->cmd_iohs[wd_cyl_lo], 0); 464 if (cl != 0x01) { 465 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 466 "got 0x%x != 0x01\n", 467 atac->atac_dev.dv_xname, 468 chp->ch_channel, cl), 469 DEBUG_PROBE); 470 ret_value &= ~0x01; 471 } 472 } 473 /* Register writability test, drive 1. */ 474 if (ret_value & 0x02) { 475 if (wdc->select) 476 wdc->select(chp,1); 477 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 478 0, WDSD_IBM | 0x10); 479 bus_space_write_1(wdr->cmd_iot, 480 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 481 cl = bus_space_read_1(wdr->cmd_iot, 482 wdr->cmd_iohs[wd_cyl_lo], 0); 483 if (cl != 0x02) { 484 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 485 "got 0x%x != 0x02\n", 486 atac->atac_dev.dv_xname, 487 chp->ch_channel, cl), 488 DEBUG_PROBE); 489 ret_value &= ~0x02; 490 } 491 bus_space_write_1(wdr->cmd_iot, 492 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 493 cl = bus_space_read_1(wdr->cmd_iot, 494 wdr->cmd_iohs[wd_cyl_lo], 0); 495 if (cl != 0x01) { 496 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 497 "got 0x%x != 0x01\n", 498 atac->atac_dev.dv_xname, 499 chp->ch_channel, cl), 500 DEBUG_PROBE); 501 ret_value &= ~0x02; 502 } 503 bus_space_write_1(wdr->cmd_iot, 504 wdr->cmd_iohs[wd_sector], 0, 0x01); 505 cl = bus_space_read_1(wdr->cmd_iot, 506 wdr->cmd_iohs[wd_sector], 0); 507 if (cl != 0x01) { 508 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 509 "got 0x%x != 0x01\n", 510 atac->atac_dev.dv_xname, 511 chp->ch_channel, cl), 512 DEBUG_PROBE); 513 ret_value &= ~0x02; 514 } 515 bus_space_write_1(wdr->cmd_iot, 516 wdr->cmd_iohs[wd_sector], 0, 0x02); 517 cl = bus_space_read_1(wdr->cmd_iot, 518 wdr->cmd_iohs[wd_sector], 0); 519 if (cl != 0x02) { 520 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 521 "got 0x%x != 0x02\n", 522 atac->atac_dev.dv_xname, 523 chp->ch_channel, cl), 524 DEBUG_PROBE); 525 ret_value &= ~0x02; 526 } 527 cl = bus_space_read_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_cyl_lo], 0); 529 if (cl != 0x01) { 530 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 531 "got 0x%x != 0x01\n", 532 atac->atac_dev.dv_xname, 533 chp->ch_channel, cl), 534 DEBUG_PROBE); 535 ret_value &= ~0x02; 536 } 537 } 538 539 if (ret_value == 0) { 540 splx(s); 541 return 0; 542 } 543 } 544 545 546 #if 0 /* XXX this break some ATA or ATAPI devices */ 547 /* 548 * reset bus. Also send an ATAPI_RESET to devices, in case there are 549 * ATAPI device out there which don't react to the bus reset 550 */ 551 if (ret_value & 0x01) { 552 if (wdc->select) 553 wdc->select(chp,0); 554 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 555 0, WDSD_IBM); 556 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 557 ATAPI_SOFT_RESET); 558 } 559 if (ret_value & 0x02) { 560 if (wdc->select) 561 wdc->select(chp,0); 562 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 563 0, WDSD_IBM | 0x10); 564 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 565 ATAPI_SOFT_RESET); 566 } 567 568 delay(5000); 569 #endif 570 571 if (wdc->select) 572 wdc->select(chp,0); 573 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 574 delay(10); /* 400ns delay */ 575 /* assert SRST, wait for reset to complete */ 576 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 577 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 578 DELAY(1000); 579 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 580 WDCTL_IDS | WDCTL_4BIT); 581 DELAY(2000); 582 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 583 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 584 delay(10); /* 400ns delay */ 585 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 586 if (wdc->irqack != NULL) 587 wdc->irqack(chp); 588 splx(s); 589 590 ret_value = __wdcwait_reset(chp, ret_value, poll); 591 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 592 atac->atac_dev.dv_xname, chp->ch_channel, 593 ret_value), DEBUG_PROBE); 594 595 /* if reset failed, there's nothing here */ 596 if (ret_value == 0) 597 return 0; 598 599 /* 600 * Test presence of drives. First test register signatures looking 601 * for ATAPI devices. If it's not an ATAPI and reset said there may 602 * be something here assume it's ATA or OLD. Ghost will be killed 603 * later in attach routine. 604 */ 605 for (drive = 0; drive < 2; drive++) { 606 if ((ret_value & (0x01 << drive)) == 0) 607 continue; 608 if (wdc->select) 609 wdc->select(chp,drive); 610 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 611 WDSD_IBM | (drive << 4)); 612 delay(10); /* 400ns delay */ 613 /* Save registers contents */ 614 sc = bus_space_read_1(wdr->cmd_iot, 615 wdr->cmd_iohs[wd_seccnt], 0); 616 sn = bus_space_read_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_sector], 0); 618 cl = bus_space_read_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0); 620 ch = bus_space_read_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_hi], 0); 622 623 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 624 "cl=0x%x ch=0x%x\n", 625 atac->atac_dev.dv_xname, 626 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 627 /* 628 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 629 * we get wrong values here, so ignore it. 630 */ 631 if (cl == 0x14 && ch == 0xeb) { 632 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 633 } else { 634 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 635 if (wdc == NULL || 636 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 637 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 638 } 639 } 640 return (ret_value); 641 } 642 643 void 644 wdcattach(struct ata_channel *chp) 645 { 646 struct atac_softc *atac = chp->ch_atac; 647 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 648 649 /* 650 * Start out assuming 2 drives. This may change as we probe 651 * drives. 652 */ 653 chp->ch_ndrive = 2; 654 655 /* default data transfer methods */ 656 if (wdc->datain_pio == NULL) 657 wdc->datain_pio = wdc_datain_pio; 658 if (wdc->dataout_pio == NULL) 659 wdc->dataout_pio = wdc_dataout_pio; 660 661 /* initialise global data */ 662 if (atac->atac_bustype_ata == NULL) 663 atac->atac_bustype_ata = &wdc_ata_bustype; 664 if (atac->atac_probe == NULL) 665 atac->atac_probe = wdc_drvprobe; 666 #if NATAPIBUS > 0 667 if (atac->atac_atapibus_attach == NULL) 668 atac->atac_atapibus_attach = wdc_atapibus_attach; 669 #endif 670 671 ata_channel_attach(chp); 672 } 673 674 int 675 wdcactivate(struct device *self, enum devact act) 676 { 677 struct atac_softc *atac = (struct atac_softc *) self; 678 int s, i, error = 0; 679 680 s = splbio(); 681 switch (act) { 682 case DVACT_ACTIVATE: 683 error = EOPNOTSUPP; 684 break; 685 686 case DVACT_DEACTIVATE: 687 for (i = 0; i < atac->atac_nchannels; i++) { 688 error = 689 config_deactivate(atac->atac_channels[i]->atabus); 690 if (error) 691 break; 692 } 693 break; 694 } 695 splx(s); 696 return (error); 697 } 698 699 int 700 wdcdetach(struct device *self, int flags) 701 { 702 struct atac_softc *atac = (struct atac_softc *) self; 703 struct ata_channel *chp; 704 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 705 int i, error = 0; 706 707 for (i = 0; i < atac->atac_nchannels; i++) { 708 chp = atac->atac_channels[i]; 709 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 710 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 711 DEBUG_DETACH); 712 error = config_detach(chp->atabus, flags); 713 if (error) 714 break; 715 } 716 if (adapt->adapt_refcnt != 0) { 717 #ifdef DIAGNOSTIC 718 printf("wdcdetach: refcnt should be 0 here??\n"); 719 #endif 720 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 721 } 722 return (error); 723 } 724 725 /* restart an interrupted I/O */ 726 void 727 wdcrestart(void *v) 728 { 729 struct ata_channel *chp = v; 730 int s; 731 732 s = splbio(); 733 atastart(chp); 734 splx(s); 735 } 736 737 738 /* 739 * Interrupt routine for the controller. Acknowledge the interrupt, check for 740 * errors on the current operation, mark it done if necessary, and start the 741 * next request. Also check for a partially done transfer, and continue with 742 * the next chunk if so. 743 */ 744 int 745 wdcintr(void *arg) 746 { 747 struct ata_channel *chp = arg; 748 struct atac_softc *atac = chp->ch_atac; 749 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 750 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 751 struct ata_xfer *xfer; 752 int ret; 753 754 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 755 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 756 DEBUG_INTR); 757 return (0); 758 } 759 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 760 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 761 /* try to clear the pending interrupt anyway */ 762 (void)bus_space_read_1(wdr->cmd_iot, 763 wdr->cmd_iohs[wd_status], 0); 764 return (0); 765 } 766 767 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 768 xfer = chp->ch_queue->active_xfer; 769 #ifdef DIAGNOSTIC 770 if (xfer == NULL) 771 panic("wdcintr: no xfer"); 772 #endif 773 if (chp->ch_flags & ATACH_DMA_WAIT) { 774 wdc->dma_status = 775 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 776 xfer->c_drive, WDC_DMAEND_END); 777 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 778 /* IRQ not for us, not detected by DMA engine */ 779 return 0; 780 } 781 chp->ch_flags &= ~ATACH_DMA_WAIT; 782 } 783 chp->ch_flags &= ~ATACH_IRQ_WAIT; 784 ret = xfer->c_intr(chp, xfer, 1); 785 if (ret == 0) /* irq was not for us, still waiting for irq */ 786 chp->ch_flags |= ATACH_IRQ_WAIT; 787 return (ret); 788 } 789 790 /* Put all disk in RESET state */ 791 void 792 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 793 { 794 struct ata_channel *chp = drvp->chnl_softc; 795 struct atac_softc *atac = chp->ch_atac; 796 797 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 798 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 799 DEBUG_FUNCS); 800 801 ata_reset_channel(chp, flags); 802 } 803 804 void 805 wdc_reset_channel(struct ata_channel *chp, int flags) 806 { 807 TAILQ_HEAD(, ata_xfer) reset_xfer; 808 struct ata_xfer *xfer, *next_xfer; 809 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 810 811 TAILQ_INIT(&reset_xfer); 812 813 chp->ch_flags &= ~ATACH_IRQ_WAIT; 814 815 /* 816 * if the current command if on an ATAPI device, issue a 817 * ATAPI_SOFT_RESET 818 */ 819 xfer = chp->ch_queue->active_xfer; 820 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 821 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 822 if (flags & AT_WAIT) 823 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 824 else 825 delay(1000); 826 } 827 828 /* reset the channel */ 829 if (flags & AT_WAIT) 830 (void) wdcreset(chp, RESET_SLEEP); 831 else 832 (void) wdcreset(chp, RESET_POLL); 833 834 /* 835 * wait a bit after reset; in case the DMA engines needs some time 836 * to recover. 837 */ 838 if (flags & AT_WAIT) 839 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 840 else 841 delay(1000); 842 /* 843 * look for pending xfers. If we have a shared queue, we'll also reset 844 * the other channel if the current xfer is running on it. 845 * Then we'll dequeue only the xfers for this channel. 846 */ 847 if ((flags & AT_RST_NOCMD) == 0) { 848 /* 849 * move all xfers queued for this channel to the reset queue, 850 * and then process the current xfer and then the reset queue. 851 * We have to use a temporary queue because c_kill_xfer() 852 * may requeue commands. 853 */ 854 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 855 xfer != NULL; xfer = next_xfer) { 856 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 857 if (xfer->c_chp != chp) 858 continue; 859 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 860 xfer, c_xferchain); 861 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 862 } 863 xfer = chp->ch_queue->active_xfer; 864 if (xfer) { 865 if (xfer->c_chp != chp) 866 ata_reset_channel(xfer->c_chp, flags); 867 else { 868 callout_stop(&chp->ch_callout); 869 /* 870 * If we're waiting for DMA, stop the 871 * DMA engine 872 */ 873 if (chp->ch_flags & ATACH_DMA_WAIT) { 874 (*wdc->dma_finish)( 875 wdc->dma_arg, 876 chp->ch_channel, 877 xfer->c_drive, 878 WDC_DMAEND_ABRT_QUIET); 879 chp->ch_flags &= ~ATACH_DMA_WAIT; 880 } 881 chp->ch_queue->active_xfer = NULL; 882 if ((flags & AT_RST_EMERG) == 0) 883 xfer->c_kill_xfer( 884 chp, xfer, KILL_RESET); 885 } 886 } 887 888 for (xfer = TAILQ_FIRST(&reset_xfer); 889 xfer != NULL; xfer = next_xfer) { 890 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 891 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 892 if ((flags & AT_RST_EMERG) == 0) 893 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 894 } 895 } 896 } 897 898 int 899 wdcreset(struct ata_channel *chp, int poll) 900 { 901 struct atac_softc *atac = chp->ch_atac; 902 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 903 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 904 int drv_mask1, drv_mask2; 905 int s = 0; 906 907 if (wdc->select) 908 wdc->select(chp,0); 909 if (poll != RESET_SLEEP) 910 s = splbio(); 911 /* master */ 912 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 913 delay(10); /* 400ns delay */ 914 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 915 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 916 delay(2000); 917 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 918 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 919 WDCTL_4BIT | WDCTL_IDS); 920 delay(10); /* 400ns delay */ 921 if (poll != RESET_SLEEP) { 922 if (wdc->irqack) 923 wdc->irqack(chp); 924 splx(s); 925 } 926 927 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 928 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 929 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 930 (poll == RESET_SLEEP) ? 0 : 1); 931 if (drv_mask2 != drv_mask1) { 932 printf("%s channel %d: reset failed for", 933 atac->atac_dev.dv_xname, chp->ch_channel); 934 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 935 printf(" drive 0"); 936 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 937 printf(" drive 1"); 938 printf("\n"); 939 } 940 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 941 return (drv_mask1 != drv_mask2) ? 1 : 0; 942 } 943 944 static int 945 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 946 { 947 struct atac_softc *atac = chp->ch_atac; 948 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 949 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 950 int timeout, nloop; 951 u_int8_t st0 = 0, st1 = 0; 952 #ifdef ATADEBUG 953 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 954 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 955 #endif 956 957 if (poll) 958 nloop = WDCNDELAY_RST; 959 else 960 nloop = WDC_RESET_WAIT * hz / 1000; 961 /* wait for BSY to deassert */ 962 for (timeout = 0; timeout < nloop; timeout++) { 963 if ((drv_mask & 0x01) != 0) { 964 if (wdc && wdc->select) 965 wdc->select(chp,0); 966 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 967 0, WDSD_IBM); /* master */ 968 delay(10); 969 st0 = bus_space_read_1(wdr->cmd_iot, 970 wdr->cmd_iohs[wd_status], 0); 971 #ifdef ATADEBUG 972 sc0 = bus_space_read_1(wdr->cmd_iot, 973 wdr->cmd_iohs[wd_seccnt], 0); 974 sn0 = bus_space_read_1(wdr->cmd_iot, 975 wdr->cmd_iohs[wd_sector], 0); 976 cl0 = bus_space_read_1(wdr->cmd_iot, 977 wdr->cmd_iohs[wd_cyl_lo], 0); 978 ch0 = bus_space_read_1(wdr->cmd_iot, 979 wdr->cmd_iohs[wd_cyl_hi], 0); 980 #endif 981 } 982 if ((drv_mask & 0x02) != 0) { 983 if (wdc && wdc->select) 984 wdc->select(chp,1); 985 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 986 0, WDSD_IBM | 0x10); /* slave */ 987 delay(10); 988 st1 = bus_space_read_1(wdr->cmd_iot, 989 wdr->cmd_iohs[wd_status], 0); 990 #ifdef ATADEBUG 991 sc1 = bus_space_read_1(wdr->cmd_iot, 992 wdr->cmd_iohs[wd_seccnt], 0); 993 sn1 = bus_space_read_1(wdr->cmd_iot, 994 wdr->cmd_iohs[wd_sector], 0); 995 cl1 = bus_space_read_1(wdr->cmd_iot, 996 wdr->cmd_iohs[wd_cyl_lo], 0); 997 ch1 = bus_space_read_1(wdr->cmd_iot, 998 wdr->cmd_iohs[wd_cyl_hi], 0); 999 #endif 1000 } 1001 1002 if ((drv_mask & 0x01) == 0) { 1003 /* no master */ 1004 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1005 /* No master, slave is ready, it's done */ 1006 goto end; 1007 } 1008 } else if ((drv_mask & 0x02) == 0) { 1009 /* no slave */ 1010 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1011 /* No slave, master is ready, it's done */ 1012 goto end; 1013 } 1014 } else { 1015 /* Wait for both master and slave to be ready */ 1016 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1017 goto end; 1018 } 1019 } 1020 if (poll) 1021 delay(WDCDELAY); 1022 else 1023 tsleep(&nloop, PRIBIO, "atarst", 1); 1024 } 1025 /* Reset timed out. Maybe it's because drv_mask was not right */ 1026 if (st0 & WDCS_BSY) 1027 drv_mask &= ~0x01; 1028 if (st1 & WDCS_BSY) 1029 drv_mask &= ~0x02; 1030 end: 1031 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1032 "cl=0x%x ch=0x%x\n", 1033 atac->atac_dev.dv_xname, 1034 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1035 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1036 "cl=0x%x ch=0x%x\n", 1037 atac->atac_dev.dv_xname, 1038 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1039 1040 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1041 atac->atac_dev.dv_xname, chp->ch_channel, 1042 st0, st1), DEBUG_PROBE); 1043 1044 return drv_mask; 1045 } 1046 1047 /* 1048 * Wait for a drive to be !BSY, and have mask in its status register. 1049 * return -1 for a timeout after "timeout" ms. 1050 */ 1051 static int 1052 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1053 { 1054 struct atac_softc *atac = chp->ch_atac; 1055 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1056 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1057 u_char status; 1058 int time = 0; 1059 1060 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1061 atac->atac_dev.dv_xname, 1062 chp->ch_channel), DEBUG_STATUS); 1063 chp->ch_error = 0; 1064 1065 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1066 1067 for (;;) { 1068 chp->ch_status = status = 1069 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1070 if ((status & (WDCS_BSY | mask)) == bits) 1071 break; 1072 if (++time > timeout) { 1073 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1074 "status %x error %x (mask 0x%x bits 0x%x)\n", 1075 time, status, 1076 bus_space_read_1(wdr->cmd_iot, 1077 wdr->cmd_iohs[wd_error], 0), mask, bits), 1078 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1079 return(WDCWAIT_TOUT); 1080 } 1081 delay(WDCDELAY); 1082 } 1083 #ifdef ATADEBUG 1084 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1085 printf("__wdcwait: did busy-wait, time=%d\n", time); 1086 #endif 1087 if (status & WDCS_ERR) 1088 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1089 wdr->cmd_iohs[wd_error], 0); 1090 #ifdef WDCNDELAY_DEBUG 1091 /* After autoconfig, there should be no long delays. */ 1092 if (!cold && time > WDCNDELAY_DEBUG) { 1093 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1094 if (xfer == NULL) 1095 printf("%s channel %d: warning: busy-wait took %dus\n", 1096 atac->atac_dev.dv_xname, chp->ch_channel, 1097 WDCDELAY * time); 1098 else 1099 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1100 atac->atac_dev.dv_xname, chp->ch_channel, 1101 xfer->drive, 1102 WDCDELAY * time); 1103 } 1104 #endif 1105 return(WDCWAIT_OK); 1106 } 1107 1108 /* 1109 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1110 * thread if possible 1111 */ 1112 int 1113 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1114 { 1115 int error, i, timeout_hz = mstohz(timeout); 1116 1117 if (timeout_hz == 0 || 1118 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1119 error = __wdcwait(chp, mask, bits, timeout); 1120 else { 1121 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1122 if (error != 0) { 1123 if ((chp->ch_flags & ATACH_TH_RUN) || 1124 (flags & AT_WAIT)) { 1125 /* 1126 * we're running in the channel thread 1127 * or some userland thread context 1128 */ 1129 for (i = 0; i < timeout_hz; i++) { 1130 if (__wdcwait(chp, mask, bits, 1131 WDCDELAY_POLL) == 0) { 1132 error = 0; 1133 break; 1134 } 1135 tsleep(&chp, PRIBIO, "atapoll", 1); 1136 } 1137 } else { 1138 /* 1139 * we're probably in interrupt context, 1140 * ask the thread to come back here 1141 */ 1142 #ifdef DIAGNOSTIC 1143 if (chp->ch_queue->queue_freeze > 0) 1144 panic("wdcwait: queue_freeze"); 1145 #endif 1146 chp->ch_queue->queue_freeze++; 1147 wakeup(&chp->ch_thread); 1148 return(WDCWAIT_THR); 1149 } 1150 } 1151 } 1152 return (error); 1153 } 1154 1155 1156 /* 1157 * Busy-wait for DMA to complete 1158 */ 1159 int 1160 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1161 { 1162 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1163 int time; 1164 1165 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1166 wdc->dma_status = 1167 (*wdc->dma_finish)(wdc->dma_arg, 1168 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1169 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1170 return 0; 1171 delay(WDCDELAY); 1172 } 1173 /* timeout, force a DMA halt */ 1174 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1175 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1176 return 1; 1177 } 1178 1179 void 1180 wdctimeout(void *arg) 1181 { 1182 struct ata_channel *chp = (struct ata_channel *)arg; 1183 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1184 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1185 int s; 1186 1187 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1188 1189 s = splbio(); 1190 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1191 __wdcerror(chp, "lost interrupt"); 1192 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1193 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1194 xfer->c_bcount, 1195 xfer->c_skip); 1196 if (chp->ch_flags & ATACH_DMA_WAIT) { 1197 wdc->dma_status = 1198 (*wdc->dma_finish)(wdc->dma_arg, 1199 chp->ch_channel, xfer->c_drive, 1200 WDC_DMAEND_ABRT); 1201 chp->ch_flags &= ~ATACH_DMA_WAIT; 1202 } 1203 /* 1204 * Call the interrupt routine. If we just missed an interrupt, 1205 * it will do what's needed. Else, it will take the needed 1206 * action (reset the device). 1207 * Before that we need to reinstall the timeout callback, 1208 * in case it will miss another irq while in this transfer 1209 * We arbitray chose it to be 1s 1210 */ 1211 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1212 xfer->c_flags |= C_TIMEOU; 1213 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1214 xfer->c_intr(chp, xfer, 1); 1215 } else 1216 __wdcerror(chp, "missing untimeout"); 1217 splx(s); 1218 } 1219 1220 int 1221 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1222 { 1223 struct ata_channel *chp = drvp->chnl_softc; 1224 struct atac_softc *atac = chp->ch_atac; 1225 struct ata_xfer *xfer; 1226 int s, ret; 1227 1228 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1229 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1230 DEBUG_FUNCS); 1231 1232 /* set up an xfer and queue. Wait for completion */ 1233 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1234 ATAXF_NOSLEEP); 1235 if (xfer == NULL) { 1236 return ATACMD_TRY_AGAIN; 1237 } 1238 1239 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1240 ata_c->flags |= AT_POLL; 1241 if (ata_c->flags & AT_POLL) 1242 xfer->c_flags |= C_POLL; 1243 xfer->c_drive = drvp->drive; 1244 xfer->c_databuf = ata_c->data; 1245 xfer->c_bcount = ata_c->bcount; 1246 xfer->c_cmd = ata_c; 1247 xfer->c_start = __wdccommand_start; 1248 xfer->c_intr = __wdccommand_intr; 1249 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1250 1251 s = splbio(); 1252 ata_exec_xfer(chp, xfer); 1253 #ifdef DIAGNOSTIC 1254 if ((ata_c->flags & AT_POLL) != 0 && 1255 (ata_c->flags & AT_DONE) == 0) 1256 panic("wdc_exec_command: polled command not done"); 1257 #endif 1258 if (ata_c->flags & AT_DONE) { 1259 ret = ATACMD_COMPLETE; 1260 } else { 1261 if (ata_c->flags & AT_WAIT) { 1262 while ((ata_c->flags & AT_DONE) == 0) { 1263 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1264 } 1265 ret = ATACMD_COMPLETE; 1266 } else { 1267 ret = ATACMD_QUEUED; 1268 } 1269 } 1270 splx(s); 1271 return ret; 1272 } 1273 1274 static void 1275 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1276 { 1277 struct atac_softc *atac = chp->ch_atac; 1278 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1279 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1280 int drive = xfer->c_drive; 1281 struct ata_command *ata_c = xfer->c_cmd; 1282 1283 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1284 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1285 DEBUG_FUNCS); 1286 1287 if (wdc->select) 1288 wdc->select(chp,drive); 1289 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1290 WDSD_IBM | (drive << 4)); 1291 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1292 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1293 case WDCWAIT_OK: 1294 break; 1295 case WDCWAIT_TOUT: 1296 ata_c->flags |= AT_TIMEOU; 1297 __wdccommand_done(chp, xfer); 1298 return; 1299 case WDCWAIT_THR: 1300 return; 1301 } 1302 if (ata_c->flags & AT_POLL) { 1303 /* polled command, disable interrupts */ 1304 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1305 WDCTL_4BIT | WDCTL_IDS); 1306 } 1307 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1308 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1309 1310 if ((ata_c->flags & AT_POLL) == 0) { 1311 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1312 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1313 wdctimeout, chp); 1314 return; 1315 } 1316 /* 1317 * Polled command. Wait for drive ready or drq. Done in intr(). 1318 * Wait for at last 400ns for status bit to be valid. 1319 */ 1320 delay(10); /* 400ns delay */ 1321 __wdccommand_intr(chp, xfer, 0); 1322 } 1323 1324 static int 1325 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1326 { 1327 struct atac_softc *atac = chp->ch_atac; 1328 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1329 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1330 struct ata_command *ata_c = xfer->c_cmd; 1331 int bcount = ata_c->bcount; 1332 char *data = ata_c->data; 1333 int wflags; 1334 1335 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1336 /* both wait and poll, we can tsleep here */ 1337 wflags = AT_WAIT | AT_POLL; 1338 } else { 1339 wflags = AT_POLL; 1340 } 1341 1342 again: 1343 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1344 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1345 DEBUG_INTR); 1346 /* 1347 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1348 * Reselect again, it doesn't hurt for others commands, and the time 1349 * penalty for the extra regiter write is acceptable, 1350 * wdc_exec_command() isn't called often (mosly for autoconfig) 1351 */ 1352 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1353 WDSD_IBM | (xfer->c_drive << 4)); 1354 if ((ata_c->flags & AT_XFDONE) != 0) { 1355 /* 1356 * We have completed a data xfer. The drive should now be 1357 * in its initial state 1358 */ 1359 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1360 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1361 wflags) == WDCWAIT_TOUT) { 1362 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1363 return 0; /* IRQ was not for us */ 1364 ata_c->flags |= AT_TIMEOU; 1365 } 1366 goto out; 1367 } 1368 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1369 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1370 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1371 return 0; /* IRQ was not for us */ 1372 ata_c->flags |= AT_TIMEOU; 1373 goto out; 1374 } 1375 if (wdc->irqack) 1376 wdc->irqack(chp); 1377 if (ata_c->flags & AT_READ) { 1378 if ((chp->ch_status & WDCS_DRQ) == 0) { 1379 ata_c->flags |= AT_TIMEOU; 1380 goto out; 1381 } 1382 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1383 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1384 0, (u_int32_t*)data, bcount >> 2); 1385 data += bcount & 0xfffffffc; 1386 bcount = bcount & 0x03; 1387 } 1388 if (bcount > 0) 1389 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1390 /* at this point the drive should be in its initial state */ 1391 ata_c->flags |= AT_XFDONE; 1392 /* XXX should read status register here ? */ 1393 } else if (ata_c->flags & AT_WRITE) { 1394 if ((chp->ch_status & WDCS_DRQ) == 0) { 1395 ata_c->flags |= AT_TIMEOU; 1396 goto out; 1397 } 1398 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1399 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1400 0, (u_int32_t*)data, bcount >> 2); 1401 data += bcount & 0xfffffffc; 1402 bcount = bcount & 0x03; 1403 } 1404 if (bcount > 0) 1405 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1406 ata_c->flags |= AT_XFDONE; 1407 if ((ata_c->flags & AT_POLL) == 0) { 1408 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1409 callout_reset(&chp->ch_callout, 1410 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1411 return 1; 1412 } else { 1413 goto again; 1414 } 1415 } 1416 out: 1417 __wdccommand_done(chp, xfer); 1418 return 1; 1419 } 1420 1421 static void 1422 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1423 { 1424 struct atac_softc *atac = chp->ch_atac; 1425 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1426 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1427 struct ata_command *ata_c = xfer->c_cmd; 1428 1429 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1430 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1431 DEBUG_FUNCS); 1432 1433 1434 if (chp->ch_status & WDCS_DWF) 1435 ata_c->flags |= AT_DF; 1436 if (chp->ch_status & WDCS_ERR) { 1437 ata_c->flags |= AT_ERROR; 1438 ata_c->r_error = chp->ch_error; 1439 } 1440 if ((ata_c->flags & AT_READREG) != 0 && 1441 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1442 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1443 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1444 wdr->cmd_iohs[wd_sdh], 0); 1445 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1446 wdr->cmd_iohs[wd_seccnt], 0); 1447 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1448 wdr->cmd_iohs[wd_sector], 0); 1449 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1450 wdr->cmd_iohs[wd_cyl_lo], 0); 1451 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1452 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1453 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1454 wdr->cmd_iohs[wd_error], 0); 1455 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1456 wdr->cmd_iohs[wd_features], 0); 1457 } 1458 callout_stop(&chp->ch_callout); 1459 chp->ch_queue->active_xfer = NULL; 1460 if (ata_c->flags & AT_POLL) { 1461 /* enable interrupts */ 1462 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1463 WDCTL_4BIT); 1464 delay(10); /* some drives need a little delay here */ 1465 } 1466 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1467 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1468 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1469 wakeup(&chp->ch_queue->active_xfer); 1470 } else 1471 __wdccommand_done_end(chp, xfer); 1472 } 1473 1474 static void 1475 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1476 { 1477 struct ata_command *ata_c = xfer->c_cmd; 1478 1479 ata_c->flags |= AT_DONE; 1480 ata_free_xfer(chp, xfer); 1481 if (ata_c->flags & AT_WAIT) 1482 wakeup(ata_c); 1483 else if (ata_c->callback) 1484 ata_c->callback(ata_c->callback_arg); 1485 atastart(chp); 1486 return; 1487 } 1488 1489 static void 1490 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1491 int reason) 1492 { 1493 struct ata_command *ata_c = xfer->c_cmd; 1494 1495 switch (reason) { 1496 case KILL_GONE: 1497 ata_c->flags |= AT_GONE; 1498 break; 1499 case KILL_RESET: 1500 ata_c->flags |= AT_RESET; 1501 break; 1502 default: 1503 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1504 reason); 1505 panic("__wdccommand_kill_xfer"); 1506 } 1507 __wdccommand_done_end(chp, xfer); 1508 } 1509 1510 /* 1511 * Send a command. The drive should be ready. 1512 * Assumes interrupts are blocked. 1513 */ 1514 void 1515 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1516 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1517 u_int8_t features) 1518 { 1519 struct atac_softc *atac = chp->ch_atac; 1520 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1521 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1522 1523 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1524 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1525 chp->ch_channel, drive, command, cylin, head, sector, count, 1526 features), DEBUG_FUNCS); 1527 1528 if (wdc->select) 1529 wdc->select(chp,drive); 1530 1531 /* Select drive, head, and addressing mode. */ 1532 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1533 WDSD_IBM | (drive << 4) | head); 1534 /* Load parameters into the wd_features register. */ 1535 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1536 features); 1537 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1538 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1539 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1540 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1541 0, cylin >> 8); 1542 1543 /* Send command. */ 1544 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1545 return; 1546 } 1547 1548 /* 1549 * Send a 48-bit addressing command. The drive should be ready. 1550 * Assumes interrupts are blocked. 1551 */ 1552 void 1553 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1554 u_int64_t blkno, u_int16_t count) 1555 { 1556 struct atac_softc *atac = chp->ch_atac; 1557 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1558 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1559 1560 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1561 "count=%d\n", atac->atac_dev.dv_xname, 1562 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1563 DEBUG_FUNCS); 1564 1565 if (wdc->select) 1566 wdc->select(chp,drive); 1567 1568 /* Select drive, head, and addressing mode. */ 1569 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1570 (drive << 4) | WDSD_LBA); 1571 1572 /* previous */ 1573 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1574 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1575 0, count >> 8); 1576 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1577 0, blkno >> 24); 1578 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1579 0, blkno >> 32); 1580 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1581 0, blkno >> 40); 1582 1583 /* current */ 1584 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1585 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1586 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1587 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1588 0, blkno >> 8); 1589 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1590 0, blkno >> 16); 1591 1592 /* Send command. */ 1593 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1594 return; 1595 } 1596 1597 /* 1598 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1599 * tested by the caller. 1600 */ 1601 void 1602 wdccommandshort(struct ata_channel *chp, int drive, int command) 1603 { 1604 struct atac_softc *atac = chp->ch_atac; 1605 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1606 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1607 1608 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1609 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1610 DEBUG_FUNCS); 1611 1612 if (wdc->select) 1613 wdc->select(chp,drive); 1614 1615 /* Select drive. */ 1616 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1617 WDSD_IBM | (drive << 4)); 1618 1619 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1620 } 1621 1622 static void 1623 __wdcerror(struct ata_channel *chp, char *msg) 1624 { 1625 struct atac_softc *atac = chp->ch_atac; 1626 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1627 1628 if (xfer == NULL) 1629 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1630 msg); 1631 else 1632 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1633 chp->ch_channel, xfer->c_drive, msg); 1634 } 1635 1636 /* 1637 * the bit bucket 1638 */ 1639 void 1640 wdcbit_bucket(struct ata_channel *chp, int size) 1641 { 1642 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1643 1644 for (; size >= 2; size -= 2) 1645 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1646 if (size) 1647 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1648 } 1649 1650 void 1651 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1652 { 1653 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1654 1655 if (flags & DRIVE_NOSTREAM) { 1656 if (flags & DRIVE_CAP32) { 1657 bus_space_read_multi_4(wdr->data32iot, 1658 wdr->data32ioh, 0, buf, len >> 2); 1659 buf = (char *)buf + (len & ~3); 1660 len &= 3; 1661 } 1662 if (len) { 1663 bus_space_read_multi_2(wdr->cmd_iot, 1664 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1665 } 1666 } else { 1667 if (flags & DRIVE_CAP32) { 1668 bus_space_read_multi_stream_4(wdr->data32iot, 1669 wdr->data32ioh, 0, buf, len >> 2); 1670 buf = (char *)buf + (len & ~3); 1671 len &= 3; 1672 } 1673 if (len) { 1674 bus_space_read_multi_stream_2(wdr->cmd_iot, 1675 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1676 } 1677 } 1678 } 1679 1680 void 1681 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1682 { 1683 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1684 1685 if (flags & DRIVE_NOSTREAM) { 1686 if (flags & DRIVE_CAP32) { 1687 bus_space_write_multi_4(wdr->data32iot, 1688 wdr->data32ioh, 0, buf, len >> 2); 1689 buf = (char *)buf + (len & ~3); 1690 len &= 3; 1691 } 1692 if (len) { 1693 bus_space_write_multi_2(wdr->cmd_iot, 1694 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1695 } 1696 } else { 1697 if (flags & DRIVE_CAP32) { 1698 bus_space_write_multi_stream_4(wdr->data32iot, 1699 wdr->data32ioh, 0, buf, len >> 2); 1700 buf = (char *)buf + (len & ~3); 1701 len &= 3; 1702 } 1703 if (len) { 1704 bus_space_write_multi_stream_2(wdr->cmd_iot, 1705 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1706 } 1707 } 1708 } 1709
Indexes created Mon Sep 22 10:09:38 GMT 2025