wdc.c revision 1.214
1 /* $NetBSD: wdc.c,v 1.214 2004/10/25 22:42:09 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.214 2004/10/25 22:42:09 enami Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, /* wdc_ata_bio */ 129 NULL, /* wdc_reset_drive */ 130 wdc_reset_channel, 131 wdc_exec_command, 132 NULL, /* ata_get_params */ 133 NULL, /* wdc_ata_addref */ 134 NULL, /* wdc_ata_delref */ 135 NULL /* ata_kill_pending */ 136 }; 137 #endif 138 139 /* Flags to wdcreset(). */ 140 #define RESET_POLL 1 141 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 142 143 static int wdcprobe1(struct ata_channel *, int); 144 static int wdcreset(struct ata_channel *, int); 145 static void __wdcerror(struct ata_channel *, char *); 146 static int __wdcwait_reset(struct ata_channel *, int, int); 147 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 149 static void __wdccommand_kill_xfer(struct ata_channel *, 150 struct ata_xfer *, int); 151 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 153 static int __wdcwait(struct ata_channel *, int, int, int); 154 155 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 156 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef ATADEBUG 166 extern int atadebug_mask; /* init'ed in ata.c */ 167 int wdc_nxfer = 0; 168 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 169 #else 170 #define ATADEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * Initialize the "shadow register" handles for a standard wdc controller. 175 */ 176 void 177 wdc_init_shadow_regs(struct ata_channel *chp) 178 { 179 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 180 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 /* Test to see controller with at last one attached drive is there. 197 * Returns a bit for each possible drive found (0x01 for drive 0, 198 * 0x02 for drive 1). 199 * Logic: 200 * - If a status register is at 0xff, assume there is no drive here 201 * (ISA has pull-up resistors). Similarly if the status register has 202 * the value we last wrote to the bus (for IDE interfaces without pullups). 203 * If no drive at all -> return. 204 * - reset the controller, wait for it to complete (may take up to 31s !). 205 * If timeout -> return. 206 * - test ATA/ATAPI signatures. If at last one drive found -> return. 207 * - try an ATA command on the master. 208 */ 209 210 static void 211 wdc_drvprobe(struct ata_channel *chp) 212 { 213 struct ataparams params; 214 struct atac_softc *atac = chp->ch_atac; 215 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 216 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 217 u_int8_t st0 = 0, st1 = 0; 218 int i, error, s; 219 220 if (wdcprobe1(chp, 0) == 0) { 221 /* No drives, abort the attach here. */ 222 return; 223 } 224 225 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 226 for (i = 0; i < mstohz(3000); i++) { 227 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 228 if (wdc->select) 229 wdc->select(chp,0); 230 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 231 0, WDSD_IBM); 232 delay(10); /* 400ns delay */ 233 st0 = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_status], 0); 235 } 236 237 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 238 if (wdc->select) 239 wdc->select(chp,1); 240 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 241 0, WDSD_IBM | 0x10); 242 delay(10); /* 400ns delay */ 243 st1 = bus_space_read_1(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_status], 0); 245 } 246 247 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 248 == 0 || 249 (st0 & WDCS_DRDY)) && 250 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 251 == 0 || 252 (st1 & WDCS_DRDY))) 253 break; 254 tsleep(¶ms, PRIBIO, "atadrdy", 1); 255 } 256 s = splbio(); 257 if ((st0 & WDCS_DRDY) == 0) 258 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 259 if ((st1 & WDCS_DRDY) == 0) 260 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 261 splx(s); 262 263 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 264 atac->atac_dev.dv_xname, 265 chp->ch_channel, st0, st1), DEBUG_PROBE); 266 267 /* Wait a bit, some devices are weird just after a reset. */ 268 delay(5000); 269 270 for (i = 0; i < 2; i++) { 271 /* XXX This should be done by other code. */ 272 chp->ch_drive[i].chnl_softc = chp; 273 chp->ch_drive[i].drive = i; 274 275 /* 276 * Init error counter so that an error withing the first xfers 277 * will trigger a downgrade 278 */ 279 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 280 281 /* If controller can't do 16bit flag the drives as 32bit */ 282 if ((atac->atac_cap & 283 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 284 s = splbio(); 285 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 286 splx(s); 287 } 288 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 289 continue; 290 291 /* Shortcut in case we've been shutdown */ 292 if (chp->ch_flags & ATACH_SHUTDOWN) 293 return; 294 295 /* issue an identify, to try to detect ghosts */ 296 error = ata_get_params(&chp->ch_drive[i], 297 AT_WAIT | AT_POLL, ¶ms); 298 if (error != CMD_OK) { 299 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 300 301 /* Shortcut in case we've been shutdown */ 302 if (chp->ch_flags & ATACH_SHUTDOWN) 303 return; 304 305 error = ata_get_params(&chp->ch_drive[i], 306 AT_WAIT | AT_POLL, ¶ms); 307 } 308 if (error == CMD_OK) { 309 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 310 s = splbio(); 311 /* XXXJRT ch_ndrive */ 312 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 313 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 314 splx(s); 315 } else { 316 s = splbio(); 317 chp->ch_drive[i].drive_flags &= 318 ~(DRIVE_ATA | DRIVE_ATAPI); 319 splx(s); 320 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 321 atac->atac_dev.dv_xname, 322 chp->ch_channel, i, error), DEBUG_PROBE); 323 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 324 continue; 325 /* 326 * Pre-ATA drive ? 327 * Test registers writability (Error register not 328 * writable, but cyllo is), then try an ATA command. 329 */ 330 if (wdc->select) 331 wdc->select(chp,i); 332 bus_space_write_1(wdr->cmd_iot, 333 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 334 delay(10); /* 400ns delay */ 335 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 336 0, 0x58); 337 bus_space_write_1(wdr->cmd_iot, 338 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 339 if (bus_space_read_1(wdr->cmd_iot, 340 wdr->cmd_iohs[wd_error], 0) == 0x58 || 341 bus_space_read_1(wdr->cmd_iot, 342 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 343 ATADEBUG_PRINT(("%s:%d:%d: register " 344 "writability failed\n", 345 atac->atac_dev.dv_xname, 346 chp->ch_channel, i), DEBUG_PROBE); 347 s = splbio(); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 splx(s); 350 continue; 351 } 352 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 353 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 354 atac->atac_dev.dv_xname, 355 chp->ch_channel, i), DEBUG_PROBE); 356 s = splbio(); 357 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 358 splx(s); 359 continue; 360 } 361 bus_space_write_1(wdr->cmd_iot, 362 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 363 delay(10); /* 400ns delay */ 364 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 365 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 366 atac->atac_dev.dv_xname, 367 chp->ch_channel, i), DEBUG_PROBE); 368 s = splbio(); 369 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 370 splx(s); 371 } else { 372 s = splbio(); 373 /* XXXJRT ch_ndrive */ 374 chp->ch_drive[0].drive_flags &= 375 ~(DRIVE_ATA | DRIVE_ATAPI); 376 chp->ch_drive[1].drive_flags &= 377 ~(DRIVE_ATA | DRIVE_ATAPI); 378 splx(s); 379 } 380 } 381 } 382 } 383 384 int 385 wdcprobe(struct ata_channel *chp) 386 { 387 388 return (wdcprobe1(chp, 1)); 389 } 390 391 static int 392 wdcprobe1(struct ata_channel *chp, int poll) 393 { 394 struct atac_softc *atac = chp->ch_atac; 395 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 396 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 397 u_int8_t st0, st1, sc, sn, cl, ch; 398 u_int8_t ret_value = 0x03; 399 u_int8_t drive; 400 int s; 401 402 /* 403 * Sanity check to see if the wdc channel responds at all. 404 */ 405 406 s = splbio(); 407 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 408 409 if (wdc->select) 410 wdc->select(chp,0); 411 412 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 413 WDSD_IBM); 414 delay(10); /* 400ns delay */ 415 st0 = bus_space_read_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_status], 0); 417 418 if (wdc->select) 419 wdc->select(chp,1); 420 421 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 422 WDSD_IBM | 0x10); 423 delay(10); /* 400ns delay */ 424 st1 = bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_status], 0); 426 427 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 428 atac->atac_dev.dv_xname, 429 chp->ch_channel, st0, st1), DEBUG_PROBE); 430 431 if (st0 == 0xff || st0 == WDSD_IBM) 432 ret_value &= ~0x01; 433 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 434 ret_value &= ~0x02; 435 /* Register writability test, drive 0. */ 436 if (ret_value & 0x01) { 437 if (wdc->select) 438 wdc->select(chp,0); 439 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 440 0, WDSD_IBM); 441 bus_space_write_1(wdr->cmd_iot, 442 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 443 cl = bus_space_read_1(wdr->cmd_iot, 444 wdr->cmd_iohs[wd_cyl_lo], 0); 445 if (cl != 0x02) { 446 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 447 "got 0x%x != 0x02\n", 448 atac->atac_dev.dv_xname, 449 chp->ch_channel, cl), 450 DEBUG_PROBE); 451 ret_value &= ~0x01; 452 } 453 bus_space_write_1(wdr->cmd_iot, 454 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 455 cl = bus_space_read_1(wdr->cmd_iot, 456 wdr->cmd_iohs[wd_cyl_lo], 0); 457 if (cl != 0x01) { 458 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 459 "got 0x%x != 0x01\n", 460 atac->atac_dev.dv_xname, 461 chp->ch_channel, cl), 462 DEBUG_PROBE); 463 ret_value &= ~0x01; 464 } 465 bus_space_write_1(wdr->cmd_iot, 466 wdr->cmd_iohs[wd_sector], 0, 0x01); 467 cl = bus_space_read_1(wdr->cmd_iot, 468 wdr->cmd_iohs[wd_sector], 0); 469 if (cl != 0x01) { 470 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 471 "got 0x%x != 0x01\n", 472 atac->atac_dev.dv_xname, 473 chp->ch_channel, cl), 474 DEBUG_PROBE); 475 ret_value &= ~0x01; 476 } 477 bus_space_write_1(wdr->cmd_iot, 478 wdr->cmd_iohs[wd_sector], 0, 0x02); 479 cl = bus_space_read_1(wdr->cmd_iot, 480 wdr->cmd_iohs[wd_sector], 0); 481 if (cl != 0x02) { 482 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 483 "got 0x%x != 0x02\n", 484 atac->atac_dev.dv_xname, 485 chp->ch_channel, cl), 486 DEBUG_PROBE); 487 ret_value &= ~0x01; 488 } 489 cl = bus_space_read_1(wdr->cmd_iot, 490 wdr->cmd_iohs[wd_cyl_lo], 0); 491 if (cl != 0x01) { 492 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 493 "got 0x%x != 0x01\n", 494 atac->atac_dev.dv_xname, 495 chp->ch_channel, cl), 496 DEBUG_PROBE); 497 ret_value &= ~0x01; 498 } 499 } 500 /* Register writability test, drive 1. */ 501 if (ret_value & 0x02) { 502 if (wdc->select) 503 wdc->select(chp,1); 504 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 505 0, WDSD_IBM | 0x10); 506 bus_space_write_1(wdr->cmd_iot, 507 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 508 cl = bus_space_read_1(wdr->cmd_iot, 509 wdr->cmd_iohs[wd_cyl_lo], 0); 510 if (cl != 0x02) { 511 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 512 "got 0x%x != 0x02\n", 513 atac->atac_dev.dv_xname, 514 chp->ch_channel, cl), 515 DEBUG_PROBE); 516 ret_value &= ~0x02; 517 } 518 bus_space_write_1(wdr->cmd_iot, 519 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 520 cl = bus_space_read_1(wdr->cmd_iot, 521 wdr->cmd_iohs[wd_cyl_lo], 0); 522 if (cl != 0x01) { 523 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 524 "got 0x%x != 0x01\n", 525 atac->atac_dev.dv_xname, 526 chp->ch_channel, cl), 527 DEBUG_PROBE); 528 ret_value &= ~0x02; 529 } 530 bus_space_write_1(wdr->cmd_iot, 531 wdr->cmd_iohs[wd_sector], 0, 0x01); 532 cl = bus_space_read_1(wdr->cmd_iot, 533 wdr->cmd_iohs[wd_sector], 0); 534 if (cl != 0x01) { 535 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 536 "got 0x%x != 0x01\n", 537 atac->atac_dev.dv_xname, 538 chp->ch_channel, cl), 539 DEBUG_PROBE); 540 ret_value &= ~0x02; 541 } 542 bus_space_write_1(wdr->cmd_iot, 543 wdr->cmd_iohs[wd_sector], 0, 0x02); 544 cl = bus_space_read_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_sector], 0); 546 if (cl != 0x02) { 547 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 548 "got 0x%x != 0x02\n", 549 atac->atac_dev.dv_xname, 550 chp->ch_channel, cl), 551 DEBUG_PROBE); 552 ret_value &= ~0x02; 553 } 554 cl = bus_space_read_1(wdr->cmd_iot, 555 wdr->cmd_iohs[wd_cyl_lo], 0); 556 if (cl != 0x01) { 557 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 558 "got 0x%x != 0x01\n", 559 atac->atac_dev.dv_xname, 560 chp->ch_channel, cl), 561 DEBUG_PROBE); 562 ret_value &= ~0x02; 563 } 564 } 565 566 if (ret_value == 0) { 567 splx(s); 568 return 0; 569 } 570 } 571 572 573 #if 0 /* XXX this break some ATA or ATAPI devices */ 574 /* 575 * reset bus. Also send an ATAPI_RESET to devices, in case there are 576 * ATAPI device out there which don't react to the bus reset 577 */ 578 if (ret_value & 0x01) { 579 if (wdc->select) 580 wdc->select(chp,0); 581 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 582 0, WDSD_IBM); 583 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 584 ATAPI_SOFT_RESET); 585 } 586 if (ret_value & 0x02) { 587 if (wdc->select) 588 wdc->select(chp,0); 589 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 590 0, WDSD_IBM | 0x10); 591 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 592 ATAPI_SOFT_RESET); 593 } 594 595 delay(5000); 596 #endif 597 598 if (wdc->select) 599 wdc->select(chp,0); 600 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 601 delay(10); /* 400ns delay */ 602 /* assert SRST, wait for reset to complete */ 603 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 604 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 605 DELAY(1000); 606 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 607 WDCTL_IDS | WDCTL_4BIT); 608 DELAY(2000); 609 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 610 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 611 delay(10); /* 400ns delay */ 612 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 613 if (wdc->irqack != NULL) 614 wdc->irqack(chp); 615 splx(s); 616 617 ret_value = __wdcwait_reset(chp, ret_value, poll); 618 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 619 atac->atac_dev.dv_xname, chp->ch_channel, 620 ret_value), DEBUG_PROBE); 621 622 /* if reset failed, there's nothing here */ 623 if (ret_value == 0) 624 return 0; 625 626 /* 627 * Test presence of drives. First test register signatures looking 628 * for ATAPI devices. If it's not an ATAPI and reset said there may 629 * be something here assume it's ATA or OLD. Ghost will be killed 630 * later in attach routine. 631 */ 632 for (drive = 0; drive < 2; drive++) { 633 if ((ret_value & (0x01 << drive)) == 0) 634 continue; 635 if (wdc->select) 636 wdc->select(chp,drive); 637 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 638 WDSD_IBM | (drive << 4)); 639 delay(10); /* 400ns delay */ 640 /* Save registers contents */ 641 sc = bus_space_read_1(wdr->cmd_iot, 642 wdr->cmd_iohs[wd_seccnt], 0); 643 sn = bus_space_read_1(wdr->cmd_iot, 644 wdr->cmd_iohs[wd_sector], 0); 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 ch = bus_space_read_1(wdr->cmd_iot, 648 wdr->cmd_iohs[wd_cyl_hi], 0); 649 650 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 651 "cl=0x%x ch=0x%x\n", 652 atac->atac_dev.dv_xname, 653 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 654 /* 655 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 656 * we get wrong values here, so ignore it. 657 */ 658 s = splbio(); 659 if (cl == 0x14 && ch == 0xeb) { 660 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 661 } else { 662 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 663 if (wdc == NULL || 664 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 665 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 666 } 667 splx(s); 668 } 669 return (ret_value); 670 } 671 672 void 673 wdcattach(struct ata_channel *chp) 674 { 675 struct atac_softc *atac = chp->ch_atac; 676 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 677 678 /* 679 * Start out assuming 2 drives. This may change as we probe 680 * drives. 681 */ 682 chp->ch_ndrive = 2; 683 684 /* default data transfer methods */ 685 if (wdc->datain_pio == NULL) 686 wdc->datain_pio = wdc_datain_pio; 687 if (wdc->dataout_pio == NULL) 688 wdc->dataout_pio = wdc_dataout_pio; 689 690 /* initialise global data */ 691 if (atac->atac_bustype_ata == NULL) 692 atac->atac_bustype_ata = &wdc_ata_bustype; 693 if (atac->atac_probe == NULL) 694 atac->atac_probe = wdc_drvprobe; 695 #if NATAPIBUS > 0 696 if (atac->atac_atapibus_attach == NULL) 697 atac->atac_atapibus_attach = wdc_atapibus_attach; 698 #endif 699 700 ata_channel_attach(chp); 701 } 702 703 int 704 wdcactivate(struct device *self, enum devact act) 705 { 706 struct atac_softc *atac = (struct atac_softc *) self; 707 int s, i, error = 0; 708 709 s = splbio(); 710 switch (act) { 711 case DVACT_ACTIVATE: 712 error = EOPNOTSUPP; 713 break; 714 715 case DVACT_DEACTIVATE: 716 for (i = 0; i < atac->atac_nchannels; i++) { 717 error = 718 config_deactivate(atac->atac_channels[i]->atabus); 719 if (error) 720 break; 721 } 722 break; 723 } 724 splx(s); 725 return (error); 726 } 727 728 int 729 wdcdetach(struct device *self, int flags) 730 { 731 struct atac_softc *atac = (struct atac_softc *) self; 732 struct ata_channel *chp; 733 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 734 int i, error = 0; 735 736 for (i = 0; i < atac->atac_nchannels; i++) { 737 chp = atac->atac_channels[i]; 738 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 739 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 740 DEBUG_DETACH); 741 error = config_detach(chp->atabus, flags); 742 if (error) 743 break; 744 } 745 if (adapt->adapt_refcnt != 0) { 746 #ifdef DIAGNOSTIC 747 printf("wdcdetach: refcnt should be 0 here??\n"); 748 #endif 749 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 750 } 751 return (error); 752 } 753 754 /* restart an interrupted I/O */ 755 void 756 wdcrestart(void *v) 757 { 758 struct ata_channel *chp = v; 759 int s; 760 761 s = splbio(); 762 atastart(chp); 763 splx(s); 764 } 765 766 767 /* 768 * Interrupt routine for the controller. Acknowledge the interrupt, check for 769 * errors on the current operation, mark it done if necessary, and start the 770 * next request. Also check for a partially done transfer, and continue with 771 * the next chunk if so. 772 */ 773 int 774 wdcintr(void *arg) 775 { 776 struct ata_channel *chp = arg; 777 struct atac_softc *atac = chp->ch_atac; 778 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 779 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 780 struct ata_xfer *xfer; 781 int ret; 782 783 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 784 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 785 DEBUG_INTR); 786 return (0); 787 } 788 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 789 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 790 /* try to clear the pending interrupt anyway */ 791 (void)bus_space_read_1(wdr->cmd_iot, 792 wdr->cmd_iohs[wd_status], 0); 793 return (0); 794 } 795 796 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 797 xfer = chp->ch_queue->active_xfer; 798 #ifdef DIAGNOSTIC 799 if (xfer == NULL) 800 panic("wdcintr: no xfer"); 801 #endif 802 if (chp->ch_flags & ATACH_DMA_WAIT) { 803 wdc->dma_status = 804 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 805 xfer->c_drive, WDC_DMAEND_END); 806 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 807 /* IRQ not for us, not detected by DMA engine */ 808 return 0; 809 } 810 chp->ch_flags &= ~ATACH_DMA_WAIT; 811 } 812 chp->ch_flags &= ~ATACH_IRQ_WAIT; 813 ret = xfer->c_intr(chp, xfer, 1); 814 if (ret == 0) /* irq was not for us, still waiting for irq */ 815 chp->ch_flags |= ATACH_IRQ_WAIT; 816 return (ret); 817 } 818 819 /* Put all disk in RESET state */ 820 void 821 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 822 { 823 struct ata_channel *chp = drvp->chnl_softc; 824 struct atac_softc *atac = chp->ch_atac; 825 826 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 827 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 828 DEBUG_FUNCS); 829 830 ata_reset_channel(chp, flags); 831 } 832 833 void 834 wdc_reset_channel(struct ata_channel *chp, int flags) 835 { 836 TAILQ_HEAD(, ata_xfer) reset_xfer; 837 struct ata_xfer *xfer, *next_xfer; 838 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 839 840 TAILQ_INIT(&reset_xfer); 841 842 chp->ch_flags &= ~ATACH_IRQ_WAIT; 843 844 /* 845 * if the current command if on an ATAPI device, issue a 846 * ATAPI_SOFT_RESET 847 */ 848 xfer = chp->ch_queue->active_xfer; 849 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 850 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 851 if (flags & AT_WAIT) 852 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 853 else 854 delay(1000); 855 } 856 857 /* reset the channel */ 858 if (flags & AT_WAIT) 859 (void) wdcreset(chp, RESET_SLEEP); 860 else 861 (void) wdcreset(chp, RESET_POLL); 862 863 /* 864 * wait a bit after reset; in case the DMA engines needs some time 865 * to recover. 866 */ 867 if (flags & AT_WAIT) 868 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 869 else 870 delay(1000); 871 /* 872 * look for pending xfers. If we have a shared queue, we'll also reset 873 * the other channel if the current xfer is running on it. 874 * Then we'll dequeue only the xfers for this channel. 875 */ 876 if ((flags & AT_RST_NOCMD) == 0) { 877 /* 878 * move all xfers queued for this channel to the reset queue, 879 * and then process the current xfer and then the reset queue. 880 * We have to use a temporary queue because c_kill_xfer() 881 * may requeue commands. 882 */ 883 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 884 xfer != NULL; xfer = next_xfer) { 885 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 886 if (xfer->c_chp != chp) 887 continue; 888 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 889 xfer, c_xferchain); 890 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 891 } 892 xfer = chp->ch_queue->active_xfer; 893 if (xfer) { 894 if (xfer->c_chp != chp) 895 ata_reset_channel(xfer->c_chp, flags); 896 else { 897 callout_stop(&chp->ch_callout); 898 /* 899 * If we're waiting for DMA, stop the 900 * DMA engine 901 */ 902 if (chp->ch_flags & ATACH_DMA_WAIT) { 903 (*wdc->dma_finish)( 904 wdc->dma_arg, 905 chp->ch_channel, 906 xfer->c_drive, 907 WDC_DMAEND_ABRT_QUIET); 908 chp->ch_flags &= ~ATACH_DMA_WAIT; 909 } 910 chp->ch_queue->active_xfer = NULL; 911 if ((flags & AT_RST_EMERG) == 0) 912 xfer->c_kill_xfer( 913 chp, xfer, KILL_RESET); 914 } 915 } 916 917 for (xfer = TAILQ_FIRST(&reset_xfer); 918 xfer != NULL; xfer = next_xfer) { 919 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 920 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 921 if ((flags & AT_RST_EMERG) == 0) 922 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 923 } 924 } 925 } 926 927 static int 928 wdcreset(struct ata_channel *chp, int poll) 929 { 930 struct atac_softc *atac = chp->ch_atac; 931 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 932 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 933 int drv_mask1, drv_mask2; 934 int s = 0; 935 936 if (wdc->select) 937 wdc->select(chp,0); 938 if (poll != RESET_SLEEP) 939 s = splbio(); 940 /* master */ 941 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 942 delay(10); /* 400ns delay */ 943 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 944 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 945 delay(2000); 946 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 947 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 948 WDCTL_4BIT | WDCTL_IDS); 949 delay(10); /* 400ns delay */ 950 if (poll != RESET_SLEEP) { 951 if (wdc->irqack) 952 wdc->irqack(chp); 953 splx(s); 954 } 955 956 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 957 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 958 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 959 (poll == RESET_SLEEP) ? 0 : 1); 960 if (drv_mask2 != drv_mask1) { 961 printf("%s channel %d: reset failed for", 962 atac->atac_dev.dv_xname, chp->ch_channel); 963 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 964 printf(" drive 0"); 965 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 966 printf(" drive 1"); 967 printf("\n"); 968 } 969 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 970 return (drv_mask1 != drv_mask2) ? 1 : 0; 971 } 972 973 static int 974 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 975 { 976 struct atac_softc *atac = chp->ch_atac; 977 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 978 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 979 int timeout, nloop; 980 u_int8_t st0 = 0, st1 = 0; 981 #ifdef ATADEBUG 982 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 983 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 984 #endif 985 986 if (poll) 987 nloop = WDCNDELAY_RST; 988 else 989 nloop = WDC_RESET_WAIT * hz / 1000; 990 /* wait for BSY to deassert */ 991 for (timeout = 0; timeout < nloop; timeout++) { 992 if ((drv_mask & 0x01) != 0) { 993 if (wdc && wdc->select) 994 wdc->select(chp,0); 995 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 996 0, WDSD_IBM); /* master */ 997 delay(10); 998 st0 = bus_space_read_1(wdr->cmd_iot, 999 wdr->cmd_iohs[wd_status], 0); 1000 #ifdef ATADEBUG 1001 sc0 = bus_space_read_1(wdr->cmd_iot, 1002 wdr->cmd_iohs[wd_seccnt], 0); 1003 sn0 = bus_space_read_1(wdr->cmd_iot, 1004 wdr->cmd_iohs[wd_sector], 0); 1005 cl0 = bus_space_read_1(wdr->cmd_iot, 1006 wdr->cmd_iohs[wd_cyl_lo], 0); 1007 ch0 = bus_space_read_1(wdr->cmd_iot, 1008 wdr->cmd_iohs[wd_cyl_hi], 0); 1009 #endif 1010 } 1011 if ((drv_mask & 0x02) != 0) { 1012 if (wdc && wdc->select) 1013 wdc->select(chp,1); 1014 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1015 0, WDSD_IBM | 0x10); /* slave */ 1016 delay(10); 1017 st1 = bus_space_read_1(wdr->cmd_iot, 1018 wdr->cmd_iohs[wd_status], 0); 1019 #ifdef ATADEBUG 1020 sc1 = bus_space_read_1(wdr->cmd_iot, 1021 wdr->cmd_iohs[wd_seccnt], 0); 1022 sn1 = bus_space_read_1(wdr->cmd_iot, 1023 wdr->cmd_iohs[wd_sector], 0); 1024 cl1 = bus_space_read_1(wdr->cmd_iot, 1025 wdr->cmd_iohs[wd_cyl_lo], 0); 1026 ch1 = bus_space_read_1(wdr->cmd_iot, 1027 wdr->cmd_iohs[wd_cyl_hi], 0); 1028 #endif 1029 } 1030 1031 if ((drv_mask & 0x01) == 0) { 1032 /* no master */ 1033 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1034 /* No master, slave is ready, it's done */ 1035 goto end; 1036 } 1037 } else if ((drv_mask & 0x02) == 0) { 1038 /* no slave */ 1039 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1040 /* No slave, master is ready, it's done */ 1041 goto end; 1042 } 1043 } else { 1044 /* Wait for both master and slave to be ready */ 1045 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1046 goto end; 1047 } 1048 } 1049 if (poll) 1050 delay(WDCDELAY); 1051 else 1052 tsleep(&nloop, PRIBIO, "atarst", 1); 1053 } 1054 /* Reset timed out. Maybe it's because drv_mask was not right */ 1055 if (st0 & WDCS_BSY) 1056 drv_mask &= ~0x01; 1057 if (st1 & WDCS_BSY) 1058 drv_mask &= ~0x02; 1059 end: 1060 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1061 "cl=0x%x ch=0x%x\n", 1062 atac->atac_dev.dv_xname, 1063 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1064 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1065 "cl=0x%x ch=0x%x\n", 1066 atac->atac_dev.dv_xname, 1067 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1068 1069 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1070 atac->atac_dev.dv_xname, chp->ch_channel, 1071 st0, st1), DEBUG_PROBE); 1072 1073 return drv_mask; 1074 } 1075 1076 /* 1077 * Wait for a drive to be !BSY, and have mask in its status register. 1078 * return -1 for a timeout after "timeout" ms. 1079 */ 1080 static int 1081 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1082 { 1083 struct atac_softc *atac = chp->ch_atac; 1084 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1085 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1086 u_char status; 1087 int time = 0; 1088 1089 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1090 atac->atac_dev.dv_xname, 1091 chp->ch_channel), DEBUG_STATUS); 1092 chp->ch_error = 0; 1093 1094 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1095 1096 for (;;) { 1097 chp->ch_status = status = 1098 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1099 if ((status & (WDCS_BSY | mask)) == bits) 1100 break; 1101 if (++time > timeout) { 1102 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1103 "status %x error %x (mask 0x%x bits 0x%x)\n", 1104 time, status, 1105 bus_space_read_1(wdr->cmd_iot, 1106 wdr->cmd_iohs[wd_error], 0), mask, bits), 1107 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1108 return(WDCWAIT_TOUT); 1109 } 1110 delay(WDCDELAY); 1111 } 1112 #ifdef ATADEBUG 1113 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1114 printf("__wdcwait: did busy-wait, time=%d\n", time); 1115 #endif 1116 if (status & WDCS_ERR) 1117 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_error], 0); 1119 #ifdef WDCNDELAY_DEBUG 1120 /* After autoconfig, there should be no long delays. */ 1121 if (!cold && time > WDCNDELAY_DEBUG) { 1122 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1123 if (xfer == NULL) 1124 printf("%s channel %d: warning: busy-wait took %dus\n", 1125 atac->atac_dev.dv_xname, chp->ch_channel, 1126 WDCDELAY * time); 1127 else 1128 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1129 atac->atac_dev.dv_xname, chp->ch_channel, 1130 xfer->drive, 1131 WDCDELAY * time); 1132 } 1133 #endif 1134 return(WDCWAIT_OK); 1135 } 1136 1137 /* 1138 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1139 * thread if possible 1140 */ 1141 int 1142 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1143 { 1144 int error, i, timeout_hz = mstohz(timeout); 1145 1146 if (timeout_hz == 0 || 1147 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1148 error = __wdcwait(chp, mask, bits, timeout); 1149 else { 1150 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1151 if (error != 0) { 1152 if ((chp->ch_flags & ATACH_TH_RUN) || 1153 (flags & AT_WAIT)) { 1154 /* 1155 * we're running in the channel thread 1156 * or some userland thread context 1157 */ 1158 for (i = 0; i < timeout_hz; i++) { 1159 if (__wdcwait(chp, mask, bits, 1160 WDCDELAY_POLL) == 0) { 1161 error = 0; 1162 break; 1163 } 1164 tsleep(&chp, PRIBIO, "atapoll", 1); 1165 } 1166 } else { 1167 /* 1168 * we're probably in interrupt context, 1169 * ask the thread to come back here 1170 */ 1171 #ifdef DIAGNOSTIC 1172 if (chp->ch_queue->queue_freeze > 0) 1173 panic("wdcwait: queue_freeze"); 1174 #endif 1175 chp->ch_queue->queue_freeze++; 1176 wakeup(&chp->ch_thread); 1177 return(WDCWAIT_THR); 1178 } 1179 } 1180 } 1181 return (error); 1182 } 1183 1184 1185 /* 1186 * Busy-wait for DMA to complete 1187 */ 1188 int 1189 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1190 { 1191 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1192 int time; 1193 1194 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1195 wdc->dma_status = 1196 (*wdc->dma_finish)(wdc->dma_arg, 1197 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1198 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1199 return 0; 1200 delay(WDCDELAY); 1201 } 1202 /* timeout, force a DMA halt */ 1203 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1204 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1205 return 1; 1206 } 1207 1208 void 1209 wdctimeout(void *arg) 1210 { 1211 struct ata_channel *chp = (struct ata_channel *)arg; 1212 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1213 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1214 int s; 1215 1216 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1217 1218 s = splbio(); 1219 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1220 __wdcerror(chp, "lost interrupt"); 1221 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1222 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1223 xfer->c_bcount, 1224 xfer->c_skip); 1225 if (chp->ch_flags & ATACH_DMA_WAIT) { 1226 wdc->dma_status = 1227 (*wdc->dma_finish)(wdc->dma_arg, 1228 chp->ch_channel, xfer->c_drive, 1229 WDC_DMAEND_ABRT); 1230 chp->ch_flags &= ~ATACH_DMA_WAIT; 1231 } 1232 /* 1233 * Call the interrupt routine. If we just missed an interrupt, 1234 * it will do what's needed. Else, it will take the needed 1235 * action (reset the device). 1236 * Before that we need to reinstall the timeout callback, 1237 * in case it will miss another irq while in this transfer 1238 * We arbitray chose it to be 1s 1239 */ 1240 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1241 xfer->c_flags |= C_TIMEOU; 1242 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1243 xfer->c_intr(chp, xfer, 1); 1244 } else 1245 __wdcerror(chp, "missing untimeout"); 1246 splx(s); 1247 } 1248 1249 int 1250 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1251 { 1252 struct ata_channel *chp = drvp->chnl_softc; 1253 struct atac_softc *atac = chp->ch_atac; 1254 struct ata_xfer *xfer; 1255 int s, ret; 1256 1257 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1258 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1259 DEBUG_FUNCS); 1260 1261 /* set up an xfer and queue. Wait for completion */ 1262 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1263 ATAXF_NOSLEEP); 1264 if (xfer == NULL) { 1265 return ATACMD_TRY_AGAIN; 1266 } 1267 1268 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1269 ata_c->flags |= AT_POLL; 1270 if (ata_c->flags & AT_POLL) 1271 xfer->c_flags |= C_POLL; 1272 xfer->c_drive = drvp->drive; 1273 xfer->c_databuf = ata_c->data; 1274 xfer->c_bcount = ata_c->bcount; 1275 xfer->c_cmd = ata_c; 1276 xfer->c_start = __wdccommand_start; 1277 xfer->c_intr = __wdccommand_intr; 1278 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1279 1280 s = splbio(); 1281 ata_exec_xfer(chp, xfer); 1282 #ifdef DIAGNOSTIC 1283 if ((ata_c->flags & AT_POLL) != 0 && 1284 (ata_c->flags & AT_DONE) == 0) 1285 panic("wdc_exec_command: polled command not done"); 1286 #endif 1287 if (ata_c->flags & AT_DONE) { 1288 ret = ATACMD_COMPLETE; 1289 } else { 1290 if (ata_c->flags & AT_WAIT) { 1291 while ((ata_c->flags & AT_DONE) == 0) { 1292 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1293 } 1294 ret = ATACMD_COMPLETE; 1295 } else { 1296 ret = ATACMD_QUEUED; 1297 } 1298 } 1299 splx(s); 1300 return ret; 1301 } 1302 1303 static void 1304 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1305 { 1306 struct atac_softc *atac = chp->ch_atac; 1307 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1308 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1309 int drive = xfer->c_drive; 1310 struct ata_command *ata_c = xfer->c_cmd; 1311 1312 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1313 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1314 DEBUG_FUNCS); 1315 1316 if (wdc->select) 1317 wdc->select(chp,drive); 1318 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1319 WDSD_IBM | (drive << 4)); 1320 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1321 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1322 case WDCWAIT_OK: 1323 break; 1324 case WDCWAIT_TOUT: 1325 ata_c->flags |= AT_TIMEOU; 1326 __wdccommand_done(chp, xfer); 1327 return; 1328 case WDCWAIT_THR: 1329 return; 1330 } 1331 if (ata_c->flags & AT_POLL) { 1332 /* polled command, disable interrupts */ 1333 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1334 WDCTL_4BIT | WDCTL_IDS); 1335 } 1336 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1337 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1338 1339 if ((ata_c->flags & AT_POLL) == 0) { 1340 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1341 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1342 wdctimeout, chp); 1343 return; 1344 } 1345 /* 1346 * Polled command. Wait for drive ready or drq. Done in intr(). 1347 * Wait for at last 400ns for status bit to be valid. 1348 */ 1349 delay(10); /* 400ns delay */ 1350 __wdccommand_intr(chp, xfer, 0); 1351 } 1352 1353 static int 1354 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1355 { 1356 struct atac_softc *atac = chp->ch_atac; 1357 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1358 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1359 struct ata_command *ata_c = xfer->c_cmd; 1360 int bcount = ata_c->bcount; 1361 char *data = ata_c->data; 1362 int wflags; 1363 1364 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1365 /* both wait and poll, we can tsleep here */ 1366 wflags = AT_WAIT | AT_POLL; 1367 } else { 1368 wflags = AT_POLL; 1369 } 1370 1371 again: 1372 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1373 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1374 DEBUG_INTR); 1375 /* 1376 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1377 * Reselect again, it doesn't hurt for others commands, and the time 1378 * penalty for the extra regiter write is acceptable, 1379 * wdc_exec_command() isn't called often (mosly for autoconfig) 1380 */ 1381 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1382 WDSD_IBM | (xfer->c_drive << 4)); 1383 if ((ata_c->flags & AT_XFDONE) != 0) { 1384 /* 1385 * We have completed a data xfer. The drive should now be 1386 * in its initial state 1387 */ 1388 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1389 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1390 wflags) == WDCWAIT_TOUT) { 1391 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1392 return 0; /* IRQ was not for us */ 1393 ata_c->flags |= AT_TIMEOU; 1394 } 1395 goto out; 1396 } 1397 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1398 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1399 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1400 return 0; /* IRQ was not for us */ 1401 ata_c->flags |= AT_TIMEOU; 1402 goto out; 1403 } 1404 if (wdc->irqack) 1405 wdc->irqack(chp); 1406 if (ata_c->flags & AT_READ) { 1407 if ((chp->ch_status & WDCS_DRQ) == 0) { 1408 ata_c->flags |= AT_TIMEOU; 1409 goto out; 1410 } 1411 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1412 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1413 0, (u_int32_t*)data, bcount >> 2); 1414 data += bcount & 0xfffffffc; 1415 bcount = bcount & 0x03; 1416 } 1417 if (bcount > 0) 1418 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1419 /* at this point the drive should be in its initial state */ 1420 ata_c->flags |= AT_XFDONE; 1421 /* XXX should read status register here ? */ 1422 } else if (ata_c->flags & AT_WRITE) { 1423 if ((chp->ch_status & WDCS_DRQ) == 0) { 1424 ata_c->flags |= AT_TIMEOU; 1425 goto out; 1426 } 1427 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1428 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1429 0, (u_int32_t*)data, bcount >> 2); 1430 data += bcount & 0xfffffffc; 1431 bcount = bcount & 0x03; 1432 } 1433 if (bcount > 0) 1434 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1435 ata_c->flags |= AT_XFDONE; 1436 if ((ata_c->flags & AT_POLL) == 0) { 1437 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1438 callout_reset(&chp->ch_callout, 1439 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1440 return 1; 1441 } else { 1442 goto again; 1443 } 1444 } 1445 out: 1446 __wdccommand_done(chp, xfer); 1447 return 1; 1448 } 1449 1450 static void 1451 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1452 { 1453 struct atac_softc *atac = chp->ch_atac; 1454 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1455 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1456 struct ata_command *ata_c = xfer->c_cmd; 1457 1458 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1459 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1460 DEBUG_FUNCS); 1461 1462 1463 if (chp->ch_status & WDCS_DWF) 1464 ata_c->flags |= AT_DF; 1465 if (chp->ch_status & WDCS_ERR) { 1466 ata_c->flags |= AT_ERROR; 1467 ata_c->r_error = chp->ch_error; 1468 } 1469 if ((ata_c->flags & AT_READREG) != 0 && 1470 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1471 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1472 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1473 wdr->cmd_iohs[wd_sdh], 0); 1474 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1475 wdr->cmd_iohs[wd_seccnt], 0); 1476 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1477 wdr->cmd_iohs[wd_sector], 0); 1478 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1479 wdr->cmd_iohs[wd_cyl_lo], 0); 1480 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1481 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1482 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1483 wdr->cmd_iohs[wd_error], 0); 1484 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1485 wdr->cmd_iohs[wd_features], 0); 1486 } 1487 callout_stop(&chp->ch_callout); 1488 chp->ch_queue->active_xfer = NULL; 1489 if (ata_c->flags & AT_POLL) { 1490 /* enable interrupts */ 1491 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1492 WDCTL_4BIT); 1493 delay(10); /* some drives need a little delay here */ 1494 } 1495 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1496 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1497 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1498 wakeup(&chp->ch_queue->active_xfer); 1499 } else 1500 __wdccommand_done_end(chp, xfer); 1501 } 1502 1503 static void 1504 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1505 { 1506 struct ata_command *ata_c = xfer->c_cmd; 1507 1508 ata_c->flags |= AT_DONE; 1509 ata_free_xfer(chp, xfer); 1510 if (ata_c->flags & AT_WAIT) 1511 wakeup(ata_c); 1512 else if (ata_c->callback) 1513 ata_c->callback(ata_c->callback_arg); 1514 atastart(chp); 1515 return; 1516 } 1517 1518 static void 1519 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1520 int reason) 1521 { 1522 struct ata_command *ata_c = xfer->c_cmd; 1523 1524 switch (reason) { 1525 case KILL_GONE: 1526 ata_c->flags |= AT_GONE; 1527 break; 1528 case KILL_RESET: 1529 ata_c->flags |= AT_RESET; 1530 break; 1531 default: 1532 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1533 reason); 1534 panic("__wdccommand_kill_xfer"); 1535 } 1536 __wdccommand_done_end(chp, xfer); 1537 } 1538 1539 /* 1540 * Send a command. The drive should be ready. 1541 * Assumes interrupts are blocked. 1542 */ 1543 void 1544 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1545 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1546 u_int8_t features) 1547 { 1548 struct atac_softc *atac = chp->ch_atac; 1549 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1550 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1551 1552 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1553 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1554 chp->ch_channel, drive, command, cylin, head, sector, count, 1555 features), DEBUG_FUNCS); 1556 1557 if (wdc->select) 1558 wdc->select(chp,drive); 1559 1560 /* Select drive, head, and addressing mode. */ 1561 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1562 WDSD_IBM | (drive << 4) | head); 1563 /* Load parameters into the wd_features register. */ 1564 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1565 features); 1566 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1567 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1568 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1569 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1570 0, cylin >> 8); 1571 1572 /* Send command. */ 1573 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1574 return; 1575 } 1576 1577 /* 1578 * Send a 48-bit addressing command. The drive should be ready. 1579 * Assumes interrupts are blocked. 1580 */ 1581 void 1582 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1583 u_int64_t blkno, u_int16_t count) 1584 { 1585 struct atac_softc *atac = chp->ch_atac; 1586 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1587 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1588 1589 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1590 "count=%d\n", atac->atac_dev.dv_xname, 1591 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1592 DEBUG_FUNCS); 1593 1594 if (wdc->select) 1595 wdc->select(chp,drive); 1596 1597 /* Select drive, head, and addressing mode. */ 1598 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1599 (drive << 4) | WDSD_LBA); 1600 1601 /* previous */ 1602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1603 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1604 0, count >> 8); 1605 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1606 0, blkno >> 24); 1607 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1608 0, blkno >> 32); 1609 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1610 0, blkno >> 40); 1611 1612 /* current */ 1613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1614 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1615 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1616 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1617 0, blkno >> 8); 1618 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1619 0, blkno >> 16); 1620 1621 /* Send command. */ 1622 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1623 return; 1624 } 1625 1626 /* 1627 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1628 * tested by the caller. 1629 */ 1630 void 1631 wdccommandshort(struct ata_channel *chp, int drive, int command) 1632 { 1633 struct atac_softc *atac = chp->ch_atac; 1634 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1635 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1636 1637 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1638 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1639 DEBUG_FUNCS); 1640 1641 if (wdc->select) 1642 wdc->select(chp,drive); 1643 1644 /* Select drive. */ 1645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1646 WDSD_IBM | (drive << 4)); 1647 1648 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1649 } 1650 1651 static void 1652 __wdcerror(struct ata_channel *chp, char *msg) 1653 { 1654 struct atac_softc *atac = chp->ch_atac; 1655 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1656 1657 if (xfer == NULL) 1658 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1659 msg); 1660 else 1661 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1662 chp->ch_channel, xfer->c_drive, msg); 1663 } 1664 1665 /* 1666 * the bit bucket 1667 */ 1668 void 1669 wdcbit_bucket(struct ata_channel *chp, int size) 1670 { 1671 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1672 1673 for (; size >= 2; size -= 2) 1674 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1675 if (size) 1676 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1677 } 1678 1679 static void 1680 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1681 { 1682 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1683 1684 if (flags & DRIVE_NOSTREAM) { 1685 if (flags & DRIVE_CAP32) { 1686 bus_space_read_multi_4(wdr->data32iot, 1687 wdr->data32ioh, 0, buf, len >> 2); 1688 buf = (char *)buf + (len & ~3); 1689 len &= 3; 1690 } 1691 if (len) { 1692 bus_space_read_multi_2(wdr->cmd_iot, 1693 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1694 } 1695 } else { 1696 if (flags & DRIVE_CAP32) { 1697 bus_space_read_multi_stream_4(wdr->data32iot, 1698 wdr->data32ioh, 0, buf, len >> 2); 1699 buf = (char *)buf + (len & ~3); 1700 len &= 3; 1701 } 1702 if (len) { 1703 bus_space_read_multi_stream_2(wdr->cmd_iot, 1704 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1705 } 1706 } 1707 } 1708 1709 static void 1710 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1711 { 1712 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1713 1714 if (flags & DRIVE_NOSTREAM) { 1715 if (flags & DRIVE_CAP32) { 1716 bus_space_write_multi_4(wdr->data32iot, 1717 wdr->data32ioh, 0, buf, len >> 2); 1718 buf = (char *)buf + (len & ~3); 1719 len &= 3; 1720 } 1721 if (len) { 1722 bus_space_write_multi_2(wdr->cmd_iot, 1723 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1724 } 1725 } else { 1726 if (flags & DRIVE_CAP32) { 1727 bus_space_write_multi_stream_4(wdr->data32iot, 1728 wdr->data32ioh, 0, buf, len >> 2); 1729 buf = (char *)buf + (len & ~3); 1730 len &= 3; 1731 } 1732 if (len) { 1733 bus_space_write_multi_stream_2(wdr->cmd_iot, 1734 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1735 } 1736 } 1737 } 1738
Indexes created Thu Sep 25 16:09:42 GMT 2025