wdc.c revision 1.215
1 /* $NetBSD: wdc.c,v 1.215 2004/10/26 21:21:59 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.215 2004/10/26 21:21:59 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, /* wdc_ata_bio */ 129 NULL, /* wdc_reset_drive */ 130 wdc_reset_channel, 131 wdc_exec_command, 132 NULL, /* ata_get_params */ 133 NULL, /* wdc_ata_addref */ 134 NULL, /* wdc_ata_delref */ 135 NULL /* ata_kill_pending */ 136 }; 137 #endif 138 139 /* Flags to wdcreset(). */ 140 #define RESET_POLL 1 141 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 142 143 static int wdcprobe1(struct ata_channel *, int); 144 static int wdcreset(struct ata_channel *, int); 145 static void __wdcerror(struct ata_channel *, char *); 146 static int __wdcwait_reset(struct ata_channel *, int, int); 147 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 149 static void __wdccommand_kill_xfer(struct ata_channel *, 150 struct ata_xfer *, int); 151 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 153 static int __wdcwait(struct ata_channel *, int, int, int); 154 155 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 156 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef ATADEBUG 166 extern int atadebug_mask; /* init'ed in ata.c */ 167 int wdc_nxfer = 0; 168 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 169 #else 170 #define ATADEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * Initialize the "shadow register" handles for a standard wdc controller. 175 */ 176 void 177 wdc_init_shadow_regs(struct ata_channel *chp) 178 { 179 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 180 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 /* Test to see controller with at last one attached drive is there. 197 * Returns a bit for each possible drive found (0x01 for drive 0, 198 * 0x02 for drive 1). 199 * Logic: 200 * - If a status register is at 0xff, assume there is no drive here 201 * (ISA has pull-up resistors). Similarly if the status register has 202 * the value we last wrote to the bus (for IDE interfaces without pullups). 203 * If no drive at all -> return. 204 * - reset the controller, wait for it to complete (may take up to 31s !). 205 * If timeout -> return. 206 * - test ATA/ATAPI signatures. If at last one drive found -> return. 207 * - try an ATA command on the master. 208 */ 209 210 static void 211 wdc_drvprobe(struct ata_channel *chp) 212 { 213 struct ataparams params; 214 struct atac_softc *atac = chp->ch_atac; 215 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 216 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 217 u_int8_t st0 = 0, st1 = 0; 218 int i, error, s; 219 220 if (wdcprobe1(chp, 0) == 0) { 221 /* No drives, abort the attach here. */ 222 return; 223 } 224 225 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 226 for (i = 0; i < mstohz(3000); i++) { 227 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 228 if (wdc->select) 229 wdc->select(chp,0); 230 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 231 0, WDSD_IBM); 232 delay(10); /* 400ns delay */ 233 st0 = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_status], 0); 235 } 236 237 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 238 if (wdc->select) 239 wdc->select(chp,1); 240 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 241 0, WDSD_IBM | 0x10); 242 delay(10); /* 400ns delay */ 243 st1 = bus_space_read_1(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_status], 0); 245 } 246 247 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 248 == 0 || 249 (st0 & WDCS_DRDY)) && 250 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 251 == 0 || 252 (st1 & WDCS_DRDY))) 253 break; 254 tsleep(¶ms, PRIBIO, "atadrdy", 1); 255 } 256 s = splbio(); 257 if ((st0 & WDCS_DRDY) == 0) 258 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 259 if ((st1 & WDCS_DRDY) == 0) 260 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 261 splx(s); 262 263 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 264 atac->atac_dev.dv_xname, 265 chp->ch_channel, st0, st1), DEBUG_PROBE); 266 267 /* Wait a bit, some devices are weird just after a reset. */ 268 delay(5000); 269 270 for (i = 0; i < 2; i++) { 271 /* XXX This should be done by other code. */ 272 chp->ch_drive[i].chnl_softc = chp; 273 chp->ch_drive[i].drive = i; 274 275 /* 276 * Init error counter so that an error withing the first xfers 277 * will trigger a downgrade 278 */ 279 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 280 281 /* If controller can't do 16bit flag the drives as 32bit */ 282 if ((atac->atac_cap & 283 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 284 s = splbio(); 285 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 286 splx(s); 287 } 288 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 289 continue; 290 291 /* Shortcut in case we've been shutdown */ 292 if (chp->ch_flags & ATACH_SHUTDOWN) 293 return; 294 295 /* issue an identify, to try to detect ghosts */ 296 error = ata_get_params(&chp->ch_drive[i], AT_WAIT, ¶ms); 297 if (error != CMD_OK) { 298 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 299 300 /* Shortcut in case we've been shutdown */ 301 if (chp->ch_flags & ATACH_SHUTDOWN) 302 return; 303 304 error = ata_get_params(&chp->ch_drive[i], 305 AT_WAIT, ¶ms); 306 } 307 if (error == CMD_OK) { 308 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 309 s = splbio(); 310 /* XXXJRT ch_ndrive */ 311 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 312 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 313 splx(s); 314 } else { 315 s = splbio(); 316 chp->ch_drive[i].drive_flags &= 317 ~(DRIVE_ATA | DRIVE_ATAPI); 318 splx(s); 319 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 320 atac->atac_dev.dv_xname, 321 chp->ch_channel, i, error), DEBUG_PROBE); 322 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 323 continue; 324 /* 325 * Pre-ATA drive ? 326 * Test registers writability (Error register not 327 * writable, but cyllo is), then try an ATA command. 328 */ 329 if (wdc->select) 330 wdc->select(chp,i); 331 bus_space_write_1(wdr->cmd_iot, 332 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 333 delay(10); /* 400ns delay */ 334 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 335 0, 0x58); 336 bus_space_write_1(wdr->cmd_iot, 337 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 338 if (bus_space_read_1(wdr->cmd_iot, 339 wdr->cmd_iohs[wd_error], 0) == 0x58 || 340 bus_space_read_1(wdr->cmd_iot, 341 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 342 ATADEBUG_PRINT(("%s:%d:%d: register " 343 "writability failed\n", 344 atac->atac_dev.dv_xname, 345 chp->ch_channel, i), DEBUG_PROBE); 346 s = splbio(); 347 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 348 splx(s); 349 continue; 350 } 351 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 352 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 353 atac->atac_dev.dv_xname, 354 chp->ch_channel, i), DEBUG_PROBE); 355 s = splbio(); 356 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 357 splx(s); 358 continue; 359 } 360 bus_space_write_1(wdr->cmd_iot, 361 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 362 delay(10); /* 400ns delay */ 363 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 364 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 365 atac->atac_dev.dv_xname, 366 chp->ch_channel, i), DEBUG_PROBE); 367 s = splbio(); 368 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 369 splx(s); 370 } else { 371 s = splbio(); 372 /* XXXJRT ch_ndrive */ 373 chp->ch_drive[0].drive_flags &= 374 ~(DRIVE_ATA | DRIVE_ATAPI); 375 chp->ch_drive[1].drive_flags &= 376 ~(DRIVE_ATA | DRIVE_ATAPI); 377 splx(s); 378 } 379 } 380 } 381 } 382 383 int 384 wdcprobe(struct ata_channel *chp) 385 { 386 387 return (wdcprobe1(chp, 1)); 388 } 389 390 static int 391 wdcprobe1(struct ata_channel *chp, int poll) 392 { 393 struct atac_softc *atac = chp->ch_atac; 394 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 395 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 396 u_int8_t st0, st1, sc, sn, cl, ch; 397 u_int8_t ret_value = 0x03; 398 u_int8_t drive; 399 int s; 400 401 /* 402 * Sanity check to see if the wdc channel responds at all. 403 */ 404 405 s = splbio(); 406 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 407 408 if (wdc->select) 409 wdc->select(chp,0); 410 411 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 412 WDSD_IBM); 413 delay(10); /* 400ns delay */ 414 st0 = bus_space_read_1(wdr->cmd_iot, 415 wdr->cmd_iohs[wd_status], 0); 416 417 if (wdc->select) 418 wdc->select(chp,1); 419 420 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 421 WDSD_IBM | 0x10); 422 delay(10); /* 400ns delay */ 423 st1 = bus_space_read_1(wdr->cmd_iot, 424 wdr->cmd_iohs[wd_status], 0); 425 426 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 427 atac->atac_dev.dv_xname, 428 chp->ch_channel, st0, st1), DEBUG_PROBE); 429 430 if (st0 == 0xff || st0 == WDSD_IBM) 431 ret_value &= ~0x01; 432 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 433 ret_value &= ~0x02; 434 /* Register writability test, drive 0. */ 435 if (ret_value & 0x01) { 436 if (wdc->select) 437 wdc->select(chp,0); 438 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 439 0, WDSD_IBM); 440 bus_space_write_1(wdr->cmd_iot, 441 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 442 cl = bus_space_read_1(wdr->cmd_iot, 443 wdr->cmd_iohs[wd_cyl_lo], 0); 444 if (cl != 0x02) { 445 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 446 "got 0x%x != 0x02\n", 447 atac->atac_dev.dv_xname, 448 chp->ch_channel, cl), 449 DEBUG_PROBE); 450 ret_value &= ~0x01; 451 } 452 bus_space_write_1(wdr->cmd_iot, 453 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 454 cl = bus_space_read_1(wdr->cmd_iot, 455 wdr->cmd_iohs[wd_cyl_lo], 0); 456 if (cl != 0x01) { 457 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 458 "got 0x%x != 0x01\n", 459 atac->atac_dev.dv_xname, 460 chp->ch_channel, cl), 461 DEBUG_PROBE); 462 ret_value &= ~0x01; 463 } 464 bus_space_write_1(wdr->cmd_iot, 465 wdr->cmd_iohs[wd_sector], 0, 0x01); 466 cl = bus_space_read_1(wdr->cmd_iot, 467 wdr->cmd_iohs[wd_sector], 0); 468 if (cl != 0x01) { 469 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 470 "got 0x%x != 0x01\n", 471 atac->atac_dev.dv_xname, 472 chp->ch_channel, cl), 473 DEBUG_PROBE); 474 ret_value &= ~0x01; 475 } 476 bus_space_write_1(wdr->cmd_iot, 477 wdr->cmd_iohs[wd_sector], 0, 0x02); 478 cl = bus_space_read_1(wdr->cmd_iot, 479 wdr->cmd_iohs[wd_sector], 0); 480 if (cl != 0x02) { 481 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 482 "got 0x%x != 0x02\n", 483 atac->atac_dev.dv_xname, 484 chp->ch_channel, cl), 485 DEBUG_PROBE); 486 ret_value &= ~0x01; 487 } 488 cl = bus_space_read_1(wdr->cmd_iot, 489 wdr->cmd_iohs[wd_cyl_lo], 0); 490 if (cl != 0x01) { 491 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 492 "got 0x%x != 0x01\n", 493 atac->atac_dev.dv_xname, 494 chp->ch_channel, cl), 495 DEBUG_PROBE); 496 ret_value &= ~0x01; 497 } 498 } 499 /* Register writability test, drive 1. */ 500 if (ret_value & 0x02) { 501 if (wdc->select) 502 wdc->select(chp,1); 503 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 504 0, WDSD_IBM | 0x10); 505 bus_space_write_1(wdr->cmd_iot, 506 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 507 cl = bus_space_read_1(wdr->cmd_iot, 508 wdr->cmd_iohs[wd_cyl_lo], 0); 509 if (cl != 0x02) { 510 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 511 "got 0x%x != 0x02\n", 512 atac->atac_dev.dv_xname, 513 chp->ch_channel, cl), 514 DEBUG_PROBE); 515 ret_value &= ~0x02; 516 } 517 bus_space_write_1(wdr->cmd_iot, 518 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 519 cl = bus_space_read_1(wdr->cmd_iot, 520 wdr->cmd_iohs[wd_cyl_lo], 0); 521 if (cl != 0x01) { 522 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 523 "got 0x%x != 0x01\n", 524 atac->atac_dev.dv_xname, 525 chp->ch_channel, cl), 526 DEBUG_PROBE); 527 ret_value &= ~0x02; 528 } 529 bus_space_write_1(wdr->cmd_iot, 530 wdr->cmd_iohs[wd_sector], 0, 0x01); 531 cl = bus_space_read_1(wdr->cmd_iot, 532 wdr->cmd_iohs[wd_sector], 0); 533 if (cl != 0x01) { 534 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 535 "got 0x%x != 0x01\n", 536 atac->atac_dev.dv_xname, 537 chp->ch_channel, cl), 538 DEBUG_PROBE); 539 ret_value &= ~0x02; 540 } 541 bus_space_write_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_sector], 0, 0x02); 543 cl = bus_space_read_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_sector], 0); 545 if (cl != 0x02) { 546 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 547 "got 0x%x != 0x02\n", 548 atac->atac_dev.dv_xname, 549 chp->ch_channel, cl), 550 DEBUG_PROBE); 551 ret_value &= ~0x02; 552 } 553 cl = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_cyl_lo], 0); 555 if (cl != 0x01) { 556 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 557 "got 0x%x != 0x01\n", 558 atac->atac_dev.dv_xname, 559 chp->ch_channel, cl), 560 DEBUG_PROBE); 561 ret_value &= ~0x02; 562 } 563 } 564 565 if (ret_value == 0) { 566 splx(s); 567 return 0; 568 } 569 } 570 571 572 #if 0 /* XXX this break some ATA or ATAPI devices */ 573 /* 574 * reset bus. Also send an ATAPI_RESET to devices, in case there are 575 * ATAPI device out there which don't react to the bus reset 576 */ 577 if (ret_value & 0x01) { 578 if (wdc->select) 579 wdc->select(chp,0); 580 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 581 0, WDSD_IBM); 582 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 583 ATAPI_SOFT_RESET); 584 } 585 if (ret_value & 0x02) { 586 if (wdc->select) 587 wdc->select(chp,0); 588 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 589 0, WDSD_IBM | 0x10); 590 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 591 ATAPI_SOFT_RESET); 592 } 593 594 delay(5000); 595 #endif 596 597 if (wdc->select) 598 wdc->select(chp,0); 599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 600 delay(10); /* 400ns delay */ 601 /* assert SRST, wait for reset to complete */ 602 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 603 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 604 DELAY(1000); 605 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 606 WDCTL_IDS | WDCTL_4BIT); 607 DELAY(2000); 608 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 609 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 610 delay(10); /* 400ns delay */ 611 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 612 if (wdc->irqack != NULL) 613 wdc->irqack(chp); 614 splx(s); 615 616 ret_value = __wdcwait_reset(chp, ret_value, poll); 617 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 618 atac->atac_dev.dv_xname, chp->ch_channel, 619 ret_value), DEBUG_PROBE); 620 621 /* if reset failed, there's nothing here */ 622 if (ret_value == 0) 623 return 0; 624 625 /* 626 * Test presence of drives. First test register signatures looking 627 * for ATAPI devices. If it's not an ATAPI and reset said there may 628 * be something here assume it's ATA or OLD. Ghost will be killed 629 * later in attach routine. 630 */ 631 for (drive = 0; drive < 2; drive++) { 632 if ((ret_value & (0x01 << drive)) == 0) 633 continue; 634 if (wdc->select) 635 wdc->select(chp,drive); 636 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 637 WDSD_IBM | (drive << 4)); 638 delay(10); /* 400ns delay */ 639 /* Save registers contents */ 640 sc = bus_space_read_1(wdr->cmd_iot, 641 wdr->cmd_iohs[wd_seccnt], 0); 642 sn = bus_space_read_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_sector], 0); 644 cl = bus_space_read_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_cyl_lo], 0); 646 ch = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_cyl_hi], 0); 648 649 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 650 "cl=0x%x ch=0x%x\n", 651 atac->atac_dev.dv_xname, 652 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 653 /* 654 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 655 * we get wrong values here, so ignore it. 656 */ 657 s = splbio(); 658 if (cl == 0x14 && ch == 0xeb) { 659 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 660 } else { 661 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 662 if (wdc == NULL || 663 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 664 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 665 } 666 splx(s); 667 } 668 return (ret_value); 669 } 670 671 void 672 wdcattach(struct ata_channel *chp) 673 { 674 struct atac_softc *atac = chp->ch_atac; 675 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 676 677 /* 678 * Start out assuming 2 drives. This may change as we probe 679 * drives. 680 */ 681 chp->ch_ndrive = 2; 682 683 /* default data transfer methods */ 684 if (wdc->datain_pio == NULL) 685 wdc->datain_pio = wdc_datain_pio; 686 if (wdc->dataout_pio == NULL) 687 wdc->dataout_pio = wdc_dataout_pio; 688 689 /* initialise global data */ 690 if (atac->atac_bustype_ata == NULL) 691 atac->atac_bustype_ata = &wdc_ata_bustype; 692 if (atac->atac_probe == NULL) 693 atac->atac_probe = wdc_drvprobe; 694 #if NATAPIBUS > 0 695 if (atac->atac_atapibus_attach == NULL) 696 atac->atac_atapibus_attach = wdc_atapibus_attach; 697 #endif 698 699 ata_channel_attach(chp); 700 } 701 702 int 703 wdcactivate(struct device *self, enum devact act) 704 { 705 struct atac_softc *atac = (struct atac_softc *) self; 706 int s, i, error = 0; 707 708 s = splbio(); 709 switch (act) { 710 case DVACT_ACTIVATE: 711 error = EOPNOTSUPP; 712 break; 713 714 case DVACT_DEACTIVATE: 715 for (i = 0; i < atac->atac_nchannels; i++) { 716 error = 717 config_deactivate(atac->atac_channels[i]->atabus); 718 if (error) 719 break; 720 } 721 break; 722 } 723 splx(s); 724 return (error); 725 } 726 727 int 728 wdcdetach(struct device *self, int flags) 729 { 730 struct atac_softc *atac = (struct atac_softc *) self; 731 struct ata_channel *chp; 732 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 733 int i, error = 0; 734 735 for (i = 0; i < atac->atac_nchannels; i++) { 736 chp = atac->atac_channels[i]; 737 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 738 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 739 DEBUG_DETACH); 740 error = config_detach(chp->atabus, flags); 741 if (error) 742 break; 743 } 744 if (adapt->adapt_refcnt != 0) { 745 #ifdef DIAGNOSTIC 746 printf("wdcdetach: refcnt should be 0 here??\n"); 747 #endif 748 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 749 } 750 return (error); 751 } 752 753 /* restart an interrupted I/O */ 754 void 755 wdcrestart(void *v) 756 { 757 struct ata_channel *chp = v; 758 int s; 759 760 s = splbio(); 761 atastart(chp); 762 splx(s); 763 } 764 765 766 /* 767 * Interrupt routine for the controller. Acknowledge the interrupt, check for 768 * errors on the current operation, mark it done if necessary, and start the 769 * next request. Also check for a partially done transfer, and continue with 770 * the next chunk if so. 771 */ 772 int 773 wdcintr(void *arg) 774 { 775 struct ata_channel *chp = arg; 776 struct atac_softc *atac = chp->ch_atac; 777 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 778 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 779 struct ata_xfer *xfer; 780 int ret; 781 782 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 783 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 784 DEBUG_INTR); 785 return (0); 786 } 787 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 788 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 789 /* try to clear the pending interrupt anyway */ 790 (void)bus_space_read_1(wdr->cmd_iot, 791 wdr->cmd_iohs[wd_status], 0); 792 return (0); 793 } 794 795 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 796 xfer = chp->ch_queue->active_xfer; 797 #ifdef DIAGNOSTIC 798 if (xfer == NULL) 799 panic("wdcintr: no xfer"); 800 #endif 801 if (chp->ch_flags & ATACH_DMA_WAIT) { 802 wdc->dma_status = 803 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 804 xfer->c_drive, WDC_DMAEND_END); 805 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 806 /* IRQ not for us, not detected by DMA engine */ 807 return 0; 808 } 809 chp->ch_flags &= ~ATACH_DMA_WAIT; 810 } 811 chp->ch_flags &= ~ATACH_IRQ_WAIT; 812 ret = xfer->c_intr(chp, xfer, 1); 813 if (ret == 0) /* irq was not for us, still waiting for irq */ 814 chp->ch_flags |= ATACH_IRQ_WAIT; 815 return (ret); 816 } 817 818 /* Put all disk in RESET state */ 819 void 820 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 821 { 822 struct ata_channel *chp = drvp->chnl_softc; 823 struct atac_softc *atac = chp->ch_atac; 824 825 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 826 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 827 DEBUG_FUNCS); 828 829 ata_reset_channel(chp, flags); 830 } 831 832 void 833 wdc_reset_channel(struct ata_channel *chp, int flags) 834 { 835 TAILQ_HEAD(, ata_xfer) reset_xfer; 836 struct ata_xfer *xfer, *next_xfer; 837 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 838 839 TAILQ_INIT(&reset_xfer); 840 841 chp->ch_flags &= ~ATACH_IRQ_WAIT; 842 843 /* 844 * if the current command if on an ATAPI device, issue a 845 * ATAPI_SOFT_RESET 846 */ 847 xfer = chp->ch_queue->active_xfer; 848 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 849 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 850 if (flags & AT_WAIT) 851 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 852 else 853 delay(1000); 854 } 855 856 /* reset the channel */ 857 if (flags & AT_WAIT) 858 (void) wdcreset(chp, RESET_SLEEP); 859 else 860 (void) wdcreset(chp, RESET_POLL); 861 862 /* 863 * wait a bit after reset; in case the DMA engines needs some time 864 * to recover. 865 */ 866 if (flags & AT_WAIT) 867 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 868 else 869 delay(1000); 870 /* 871 * look for pending xfers. If we have a shared queue, we'll also reset 872 * the other channel if the current xfer is running on it. 873 * Then we'll dequeue only the xfers for this channel. 874 */ 875 if ((flags & AT_RST_NOCMD) == 0) { 876 /* 877 * move all xfers queued for this channel to the reset queue, 878 * and then process the current xfer and then the reset queue. 879 * We have to use a temporary queue because c_kill_xfer() 880 * may requeue commands. 881 */ 882 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 883 xfer != NULL; xfer = next_xfer) { 884 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 885 if (xfer->c_chp != chp) 886 continue; 887 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 888 xfer, c_xferchain); 889 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 890 } 891 xfer = chp->ch_queue->active_xfer; 892 if (xfer) { 893 if (xfer->c_chp != chp) 894 ata_reset_channel(xfer->c_chp, flags); 895 else { 896 callout_stop(&chp->ch_callout); 897 /* 898 * If we're waiting for DMA, stop the 899 * DMA engine 900 */ 901 if (chp->ch_flags & ATACH_DMA_WAIT) { 902 (*wdc->dma_finish)( 903 wdc->dma_arg, 904 chp->ch_channel, 905 xfer->c_drive, 906 WDC_DMAEND_ABRT_QUIET); 907 chp->ch_flags &= ~ATACH_DMA_WAIT; 908 } 909 chp->ch_queue->active_xfer = NULL; 910 if ((flags & AT_RST_EMERG) == 0) 911 xfer->c_kill_xfer( 912 chp, xfer, KILL_RESET); 913 } 914 } 915 916 for (xfer = TAILQ_FIRST(&reset_xfer); 917 xfer != NULL; xfer = next_xfer) { 918 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 919 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 920 if ((flags & AT_RST_EMERG) == 0) 921 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 922 } 923 } 924 } 925 926 static int 927 wdcreset(struct ata_channel *chp, int poll) 928 { 929 struct atac_softc *atac = chp->ch_atac; 930 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 931 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 932 int drv_mask1, drv_mask2; 933 int s = 0; 934 935 if (wdc->select) 936 wdc->select(chp,0); 937 if (poll != RESET_SLEEP) 938 s = splbio(); 939 /* master */ 940 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 941 delay(10); /* 400ns delay */ 942 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 943 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 944 delay(2000); 945 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 946 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 947 WDCTL_4BIT | WDCTL_IDS); 948 delay(10); /* 400ns delay */ 949 if (poll != RESET_SLEEP) { 950 if (wdc->irqack) 951 wdc->irqack(chp); 952 splx(s); 953 } 954 955 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 956 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 957 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 958 (poll == RESET_SLEEP) ? 0 : 1); 959 if (drv_mask2 != drv_mask1) { 960 printf("%s channel %d: reset failed for", 961 atac->atac_dev.dv_xname, chp->ch_channel); 962 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 963 printf(" drive 0"); 964 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 965 printf(" drive 1"); 966 printf("\n"); 967 } 968 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 969 return (drv_mask1 != drv_mask2) ? 1 : 0; 970 } 971 972 static int 973 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 974 { 975 struct atac_softc *atac = chp->ch_atac; 976 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 977 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 978 int timeout, nloop; 979 u_int8_t st0 = 0, st1 = 0; 980 #ifdef ATADEBUG 981 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 982 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 983 #endif 984 985 if (poll) 986 nloop = WDCNDELAY_RST; 987 else 988 nloop = WDC_RESET_WAIT * hz / 1000; 989 /* wait for BSY to deassert */ 990 for (timeout = 0; timeout < nloop; timeout++) { 991 if ((drv_mask & 0x01) != 0) { 992 if (wdc && wdc->select) 993 wdc->select(chp,0); 994 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 995 0, WDSD_IBM); /* master */ 996 delay(10); 997 st0 = bus_space_read_1(wdr->cmd_iot, 998 wdr->cmd_iohs[wd_status], 0); 999 #ifdef ATADEBUG 1000 sc0 = bus_space_read_1(wdr->cmd_iot, 1001 wdr->cmd_iohs[wd_seccnt], 0); 1002 sn0 = bus_space_read_1(wdr->cmd_iot, 1003 wdr->cmd_iohs[wd_sector], 0); 1004 cl0 = bus_space_read_1(wdr->cmd_iot, 1005 wdr->cmd_iohs[wd_cyl_lo], 0); 1006 ch0 = bus_space_read_1(wdr->cmd_iot, 1007 wdr->cmd_iohs[wd_cyl_hi], 0); 1008 #endif 1009 } 1010 if ((drv_mask & 0x02) != 0) { 1011 if (wdc && wdc->select) 1012 wdc->select(chp,1); 1013 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1014 0, WDSD_IBM | 0x10); /* slave */ 1015 delay(10); 1016 st1 = bus_space_read_1(wdr->cmd_iot, 1017 wdr->cmd_iohs[wd_status], 0); 1018 #ifdef ATADEBUG 1019 sc1 = bus_space_read_1(wdr->cmd_iot, 1020 wdr->cmd_iohs[wd_seccnt], 0); 1021 sn1 = bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_sector], 0); 1023 cl1 = bus_space_read_1(wdr->cmd_iot, 1024 wdr->cmd_iohs[wd_cyl_lo], 0); 1025 ch1 = bus_space_read_1(wdr->cmd_iot, 1026 wdr->cmd_iohs[wd_cyl_hi], 0); 1027 #endif 1028 } 1029 1030 if ((drv_mask & 0x01) == 0) { 1031 /* no master */ 1032 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1033 /* No master, slave is ready, it's done */ 1034 goto end; 1035 } 1036 } else if ((drv_mask & 0x02) == 0) { 1037 /* no slave */ 1038 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1039 /* No slave, master is ready, it's done */ 1040 goto end; 1041 } 1042 } else { 1043 /* Wait for both master and slave to be ready */ 1044 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1045 goto end; 1046 } 1047 } 1048 if (poll) 1049 delay(WDCDELAY); 1050 else 1051 tsleep(&nloop, PRIBIO, "atarst", 1); 1052 } 1053 /* Reset timed out. Maybe it's because drv_mask was not right */ 1054 if (st0 & WDCS_BSY) 1055 drv_mask &= ~0x01; 1056 if (st1 & WDCS_BSY) 1057 drv_mask &= ~0x02; 1058 end: 1059 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1060 "cl=0x%x ch=0x%x\n", 1061 atac->atac_dev.dv_xname, 1062 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1063 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1064 "cl=0x%x ch=0x%x\n", 1065 atac->atac_dev.dv_xname, 1066 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1067 1068 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1069 atac->atac_dev.dv_xname, chp->ch_channel, 1070 st0, st1), DEBUG_PROBE); 1071 1072 return drv_mask; 1073 } 1074 1075 /* 1076 * Wait for a drive to be !BSY, and have mask in its status register. 1077 * return -1 for a timeout after "timeout" ms. 1078 */ 1079 static int 1080 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1081 { 1082 struct atac_softc *atac = chp->ch_atac; 1083 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1084 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1085 u_char status; 1086 int time = 0; 1087 1088 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1089 atac->atac_dev.dv_xname, 1090 chp->ch_channel), DEBUG_STATUS); 1091 chp->ch_error = 0; 1092 1093 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1094 1095 for (;;) { 1096 chp->ch_status = status = 1097 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1098 if ((status & (WDCS_BSY | mask)) == bits) 1099 break; 1100 if (++time > timeout) { 1101 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1102 "status %x error %x (mask 0x%x bits 0x%x)\n", 1103 time, status, 1104 bus_space_read_1(wdr->cmd_iot, 1105 wdr->cmd_iohs[wd_error], 0), mask, bits), 1106 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1107 return(WDCWAIT_TOUT); 1108 } 1109 delay(WDCDELAY); 1110 } 1111 #ifdef ATADEBUG 1112 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1113 printf("__wdcwait: did busy-wait, time=%d\n", time); 1114 #endif 1115 if (status & WDCS_ERR) 1116 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_error], 0); 1118 #ifdef WDCNDELAY_DEBUG 1119 /* After autoconfig, there should be no long delays. */ 1120 if (!cold && time > WDCNDELAY_DEBUG) { 1121 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1122 if (xfer == NULL) 1123 printf("%s channel %d: warning: busy-wait took %dus\n", 1124 atac->atac_dev.dv_xname, chp->ch_channel, 1125 WDCDELAY * time); 1126 else 1127 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1128 atac->atac_dev.dv_xname, chp->ch_channel, 1129 xfer->drive, 1130 WDCDELAY * time); 1131 } 1132 #endif 1133 return(WDCWAIT_OK); 1134 } 1135 1136 /* 1137 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1138 * thread if possible 1139 */ 1140 int 1141 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1142 { 1143 int error, i, timeout_hz = mstohz(timeout); 1144 1145 if (timeout_hz == 0 || 1146 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1147 error = __wdcwait(chp, mask, bits, timeout); 1148 else { 1149 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1150 if (error != 0) { 1151 if ((chp->ch_flags & ATACH_TH_RUN) || 1152 (flags & AT_WAIT)) { 1153 /* 1154 * we're running in the channel thread 1155 * or some userland thread context 1156 */ 1157 for (i = 0; i < timeout_hz; i++) { 1158 if (__wdcwait(chp, mask, bits, 1159 WDCDELAY_POLL) == 0) { 1160 error = 0; 1161 break; 1162 } 1163 tsleep(&chp, PRIBIO, "atapoll", 1); 1164 } 1165 } else { 1166 /* 1167 * we're probably in interrupt context, 1168 * ask the thread to come back here 1169 */ 1170 #ifdef DIAGNOSTIC 1171 if (chp->ch_queue->queue_freeze > 0) 1172 panic("wdcwait: queue_freeze"); 1173 #endif 1174 chp->ch_queue->queue_freeze++; 1175 wakeup(&chp->ch_thread); 1176 return(WDCWAIT_THR); 1177 } 1178 } 1179 } 1180 return (error); 1181 } 1182 1183 1184 /* 1185 * Busy-wait for DMA to complete 1186 */ 1187 int 1188 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1189 { 1190 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1191 int time; 1192 1193 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1194 wdc->dma_status = 1195 (*wdc->dma_finish)(wdc->dma_arg, 1196 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1197 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1198 return 0; 1199 delay(WDCDELAY); 1200 } 1201 /* timeout, force a DMA halt */ 1202 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1203 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1204 return 1; 1205 } 1206 1207 void 1208 wdctimeout(void *arg) 1209 { 1210 struct ata_channel *chp = (struct ata_channel *)arg; 1211 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1212 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1213 int s; 1214 1215 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1216 1217 s = splbio(); 1218 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1219 __wdcerror(chp, "lost interrupt"); 1220 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1221 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1222 xfer->c_bcount, 1223 xfer->c_skip); 1224 if (chp->ch_flags & ATACH_DMA_WAIT) { 1225 wdc->dma_status = 1226 (*wdc->dma_finish)(wdc->dma_arg, 1227 chp->ch_channel, xfer->c_drive, 1228 WDC_DMAEND_ABRT); 1229 chp->ch_flags &= ~ATACH_DMA_WAIT; 1230 } 1231 /* 1232 * Call the interrupt routine. If we just missed an interrupt, 1233 * it will do what's needed. Else, it will take the needed 1234 * action (reset the device). 1235 * Before that we need to reinstall the timeout callback, 1236 * in case it will miss another irq while in this transfer 1237 * We arbitray chose it to be 1s 1238 */ 1239 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1240 xfer->c_flags |= C_TIMEOU; 1241 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1242 xfer->c_intr(chp, xfer, 1); 1243 } else 1244 __wdcerror(chp, "missing untimeout"); 1245 splx(s); 1246 } 1247 1248 int 1249 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1250 { 1251 struct ata_channel *chp = drvp->chnl_softc; 1252 struct atac_softc *atac = chp->ch_atac; 1253 struct ata_xfer *xfer; 1254 int s, ret; 1255 1256 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1257 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1258 DEBUG_FUNCS); 1259 1260 /* set up an xfer and queue. Wait for completion */ 1261 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1262 ATAXF_NOSLEEP); 1263 if (xfer == NULL) { 1264 return ATACMD_TRY_AGAIN; 1265 } 1266 1267 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1268 ata_c->flags |= AT_POLL; 1269 if (ata_c->flags & AT_POLL) 1270 xfer->c_flags |= C_POLL; 1271 xfer->c_drive = drvp->drive; 1272 xfer->c_databuf = ata_c->data; 1273 xfer->c_bcount = ata_c->bcount; 1274 xfer->c_cmd = ata_c; 1275 xfer->c_start = __wdccommand_start; 1276 xfer->c_intr = __wdccommand_intr; 1277 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1278 1279 s = splbio(); 1280 ata_exec_xfer(chp, xfer); 1281 #ifdef DIAGNOSTIC 1282 if ((ata_c->flags & AT_POLL) != 0 && 1283 (ata_c->flags & AT_DONE) == 0) 1284 panic("wdc_exec_command: polled command not done"); 1285 #endif 1286 if (ata_c->flags & AT_DONE) { 1287 ret = ATACMD_COMPLETE; 1288 } else { 1289 if (ata_c->flags & AT_WAIT) { 1290 while ((ata_c->flags & AT_DONE) == 0) { 1291 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1292 } 1293 ret = ATACMD_COMPLETE; 1294 } else { 1295 ret = ATACMD_QUEUED; 1296 } 1297 } 1298 splx(s); 1299 return ret; 1300 } 1301 1302 static void 1303 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1304 { 1305 struct atac_softc *atac = chp->ch_atac; 1306 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1307 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1308 int drive = xfer->c_drive; 1309 struct ata_command *ata_c = xfer->c_cmd; 1310 1311 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1312 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1313 DEBUG_FUNCS); 1314 1315 if (wdc->select) 1316 wdc->select(chp,drive); 1317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1318 WDSD_IBM | (drive << 4)); 1319 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1320 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1321 case WDCWAIT_OK: 1322 break; 1323 case WDCWAIT_TOUT: 1324 ata_c->flags |= AT_TIMEOU; 1325 __wdccommand_done(chp, xfer); 1326 return; 1327 case WDCWAIT_THR: 1328 return; 1329 } 1330 if (ata_c->flags & AT_POLL) { 1331 /* polled command, disable interrupts */ 1332 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1333 WDCTL_4BIT | WDCTL_IDS); 1334 } 1335 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1336 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1337 1338 if ((ata_c->flags & AT_POLL) == 0) { 1339 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1340 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1341 wdctimeout, chp); 1342 return; 1343 } 1344 /* 1345 * Polled command. Wait for drive ready or drq. Done in intr(). 1346 * Wait for at last 400ns for status bit to be valid. 1347 */ 1348 delay(10); /* 400ns delay */ 1349 __wdccommand_intr(chp, xfer, 0); 1350 } 1351 1352 static int 1353 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1354 { 1355 struct atac_softc *atac = chp->ch_atac; 1356 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1357 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1358 struct ata_command *ata_c = xfer->c_cmd; 1359 int bcount = ata_c->bcount; 1360 char *data = ata_c->data; 1361 int wflags; 1362 1363 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1364 /* both wait and poll, we can tsleep here */ 1365 wflags = AT_WAIT | AT_POLL; 1366 } else { 1367 wflags = AT_POLL; 1368 } 1369 1370 again: 1371 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1372 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1373 DEBUG_INTR); 1374 /* 1375 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1376 * Reselect again, it doesn't hurt for others commands, and the time 1377 * penalty for the extra regiter write is acceptable, 1378 * wdc_exec_command() isn't called often (mosly for autoconfig) 1379 */ 1380 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1381 WDSD_IBM | (xfer->c_drive << 4)); 1382 if ((ata_c->flags & AT_XFDONE) != 0) { 1383 /* 1384 * We have completed a data xfer. The drive should now be 1385 * in its initial state 1386 */ 1387 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1388 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1389 wflags) == WDCWAIT_TOUT) { 1390 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1391 return 0; /* IRQ was not for us */ 1392 ata_c->flags |= AT_TIMEOU; 1393 } 1394 goto out; 1395 } 1396 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1397 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1398 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1399 return 0; /* IRQ was not for us */ 1400 ata_c->flags |= AT_TIMEOU; 1401 goto out; 1402 } 1403 if (wdc->irqack) 1404 wdc->irqack(chp); 1405 if (ata_c->flags & AT_READ) { 1406 if ((chp->ch_status & WDCS_DRQ) == 0) { 1407 ata_c->flags |= AT_TIMEOU; 1408 goto out; 1409 } 1410 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1411 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1412 0, (u_int32_t*)data, bcount >> 2); 1413 data += bcount & 0xfffffffc; 1414 bcount = bcount & 0x03; 1415 } 1416 if (bcount > 0) 1417 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1418 /* at this point the drive should be in its initial state */ 1419 ata_c->flags |= AT_XFDONE; 1420 /* XXX should read status register here ? */ 1421 } else if (ata_c->flags & AT_WRITE) { 1422 if ((chp->ch_status & WDCS_DRQ) == 0) { 1423 ata_c->flags |= AT_TIMEOU; 1424 goto out; 1425 } 1426 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1427 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1428 0, (u_int32_t*)data, bcount >> 2); 1429 data += bcount & 0xfffffffc; 1430 bcount = bcount & 0x03; 1431 } 1432 if (bcount > 0) 1433 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1434 ata_c->flags |= AT_XFDONE; 1435 if ((ata_c->flags & AT_POLL) == 0) { 1436 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1437 callout_reset(&chp->ch_callout, 1438 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1439 return 1; 1440 } else { 1441 goto again; 1442 } 1443 } 1444 out: 1445 __wdccommand_done(chp, xfer); 1446 return 1; 1447 } 1448 1449 static void 1450 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1451 { 1452 struct atac_softc *atac = chp->ch_atac; 1453 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1454 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1455 struct ata_command *ata_c = xfer->c_cmd; 1456 1457 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1458 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1459 DEBUG_FUNCS); 1460 1461 1462 if (chp->ch_status & WDCS_DWF) 1463 ata_c->flags |= AT_DF; 1464 if (chp->ch_status & WDCS_ERR) { 1465 ata_c->flags |= AT_ERROR; 1466 ata_c->r_error = chp->ch_error; 1467 } 1468 if ((ata_c->flags & AT_READREG) != 0 && 1469 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1470 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1471 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1472 wdr->cmd_iohs[wd_sdh], 0); 1473 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1474 wdr->cmd_iohs[wd_seccnt], 0); 1475 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1476 wdr->cmd_iohs[wd_sector], 0); 1477 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1478 wdr->cmd_iohs[wd_cyl_lo], 0); 1479 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1480 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1481 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1482 wdr->cmd_iohs[wd_error], 0); 1483 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1484 wdr->cmd_iohs[wd_features], 0); 1485 } 1486 callout_stop(&chp->ch_callout); 1487 chp->ch_queue->active_xfer = NULL; 1488 if (ata_c->flags & AT_POLL) { 1489 /* enable interrupts */ 1490 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1491 WDCTL_4BIT); 1492 delay(10); /* some drives need a little delay here */ 1493 } 1494 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1495 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1496 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1497 wakeup(&chp->ch_queue->active_xfer); 1498 } else 1499 __wdccommand_done_end(chp, xfer); 1500 } 1501 1502 static void 1503 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1504 { 1505 struct ata_command *ata_c = xfer->c_cmd; 1506 1507 ata_c->flags |= AT_DONE; 1508 ata_free_xfer(chp, xfer); 1509 if (ata_c->flags & AT_WAIT) 1510 wakeup(ata_c); 1511 else if (ata_c->callback) 1512 ata_c->callback(ata_c->callback_arg); 1513 atastart(chp); 1514 return; 1515 } 1516 1517 static void 1518 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1519 int reason) 1520 { 1521 struct ata_command *ata_c = xfer->c_cmd; 1522 1523 switch (reason) { 1524 case KILL_GONE: 1525 ata_c->flags |= AT_GONE; 1526 break; 1527 case KILL_RESET: 1528 ata_c->flags |= AT_RESET; 1529 break; 1530 default: 1531 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1532 reason); 1533 panic("__wdccommand_kill_xfer"); 1534 } 1535 __wdccommand_done_end(chp, xfer); 1536 } 1537 1538 /* 1539 * Send a command. The drive should be ready. 1540 * Assumes interrupts are blocked. 1541 */ 1542 void 1543 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1544 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1545 u_int8_t features) 1546 { 1547 struct atac_softc *atac = chp->ch_atac; 1548 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1549 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1550 1551 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1552 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1553 chp->ch_channel, drive, command, cylin, head, sector, count, 1554 features), DEBUG_FUNCS); 1555 1556 if (wdc->select) 1557 wdc->select(chp,drive); 1558 1559 /* Select drive, head, and addressing mode. */ 1560 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1561 WDSD_IBM | (drive << 4) | head); 1562 /* Load parameters into the wd_features register. */ 1563 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1564 features); 1565 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1566 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1567 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1568 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1569 0, cylin >> 8); 1570 1571 /* Send command. */ 1572 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1573 return; 1574 } 1575 1576 /* 1577 * Send a 48-bit addressing command. The drive should be ready. 1578 * Assumes interrupts are blocked. 1579 */ 1580 void 1581 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1582 u_int64_t blkno, u_int16_t count) 1583 { 1584 struct atac_softc *atac = chp->ch_atac; 1585 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1586 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1587 1588 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1589 "count=%d\n", atac->atac_dev.dv_xname, 1590 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1591 DEBUG_FUNCS); 1592 1593 if (wdc->select) 1594 wdc->select(chp,drive); 1595 1596 /* Select drive, head, and addressing mode. */ 1597 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1598 (drive << 4) | WDSD_LBA); 1599 1600 /* previous */ 1601 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1603 0, count >> 8); 1604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1605 0, blkno >> 24); 1606 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1607 0, blkno >> 32); 1608 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1609 0, blkno >> 40); 1610 1611 /* current */ 1612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 0); 1613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1614 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, blkno); 1615 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1616 0, blkno >> 8); 1617 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1618 0, blkno >> 16); 1619 1620 /* Send command. */ 1621 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1622 return; 1623 } 1624 1625 /* 1626 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1627 * tested by the caller. 1628 */ 1629 void 1630 wdccommandshort(struct ata_channel *chp, int drive, int command) 1631 { 1632 struct atac_softc *atac = chp->ch_atac; 1633 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1634 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1635 1636 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1637 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1638 DEBUG_FUNCS); 1639 1640 if (wdc->select) 1641 wdc->select(chp,drive); 1642 1643 /* Select drive. */ 1644 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1645 WDSD_IBM | (drive << 4)); 1646 1647 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1648 } 1649 1650 static void 1651 __wdcerror(struct ata_channel *chp, char *msg) 1652 { 1653 struct atac_softc *atac = chp->ch_atac; 1654 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1655 1656 if (xfer == NULL) 1657 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1658 msg); 1659 else 1660 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1661 chp->ch_channel, xfer->c_drive, msg); 1662 } 1663 1664 /* 1665 * the bit bucket 1666 */ 1667 void 1668 wdcbit_bucket(struct ata_channel *chp, int size) 1669 { 1670 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1671 1672 for (; size >= 2; size -= 2) 1673 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1674 if (size) 1675 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1676 } 1677 1678 static void 1679 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1680 { 1681 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1682 1683 if (flags & DRIVE_NOSTREAM) { 1684 if (flags & DRIVE_CAP32) { 1685 bus_space_read_multi_4(wdr->data32iot, 1686 wdr->data32ioh, 0, buf, len >> 2); 1687 buf = (char *)buf + (len & ~3); 1688 len &= 3; 1689 } 1690 if (len) { 1691 bus_space_read_multi_2(wdr->cmd_iot, 1692 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1693 } 1694 } else { 1695 if (flags & DRIVE_CAP32) { 1696 bus_space_read_multi_stream_4(wdr->data32iot, 1697 wdr->data32ioh, 0, buf, len >> 2); 1698 buf = (char *)buf + (len & ~3); 1699 len &= 3; 1700 } 1701 if (len) { 1702 bus_space_read_multi_stream_2(wdr->cmd_iot, 1703 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1704 } 1705 } 1706 } 1707 1708 static void 1709 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1710 { 1711 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1712 1713 if (flags & DRIVE_NOSTREAM) { 1714 if (flags & DRIVE_CAP32) { 1715 bus_space_write_multi_4(wdr->data32iot, 1716 wdr->data32ioh, 0, buf, len >> 2); 1717 buf = (char *)buf + (len & ~3); 1718 len &= 3; 1719 } 1720 if (len) { 1721 bus_space_write_multi_2(wdr->cmd_iot, 1722 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1723 } 1724 } else { 1725 if (flags & DRIVE_CAP32) { 1726 bus_space_write_multi_stream_4(wdr->data32iot, 1727 wdr->data32ioh, 0, buf, len >> 2); 1728 buf = (char *)buf + (len & ~3); 1729 len &= 3; 1730 } 1731 if (len) { 1732 bus_space_write_multi_stream_2(wdr->cmd_iot, 1733 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1734 } 1735 } 1736 } 1737
Indexes created Thu Sep 25 16:09:42 GMT 2025