wdc.c revision 1.221
1 /* $NetBSD: wdc.c,v 1.221 2005/03/28 22:08:51 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.221 2005/03/28 22:08:51 fvdl Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, /* wdc_ata_bio */ 129 NULL, /* wdc_reset_drive */ 130 wdc_reset_channel, 131 wdc_exec_command, 132 NULL, /* ata_get_params */ 133 NULL, /* wdc_ata_addref */ 134 NULL, /* wdc_ata_delref */ 135 NULL /* ata_kill_pending */ 136 }; 137 #endif 138 139 /* Flags to wdcreset(). */ 140 #define RESET_POLL 1 141 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 142 143 static int wdcprobe1(struct ata_channel *, int); 144 static int wdcreset(struct ata_channel *, int); 145 static void __wdcerror(struct ata_channel *, char *); 146 static int __wdcwait_reset(struct ata_channel *, int, int); 147 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 149 static void __wdccommand_kill_xfer(struct ata_channel *, 150 struct ata_xfer *, int); 151 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 153 static int __wdcwait(struct ata_channel *, int, int, int); 154 155 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 156 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef ATADEBUG 166 extern int atadebug_mask; /* init'ed in ata.c */ 167 int wdc_nxfer = 0; 168 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 169 #else 170 #define ATADEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * Initialize the "shadow register" handles for a standard wdc controller. 175 */ 176 void 177 wdc_init_shadow_regs(struct ata_channel *chp) 178 { 179 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 180 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 /* Test to see controller with at last one attached drive is there. 197 * Returns a bit for each possible drive found (0x01 for drive 0, 198 * 0x02 for drive 1). 199 * Logic: 200 * - If a status register is at 0xff, assume there is no drive here 201 * (ISA has pull-up resistors). Similarly if the status register has 202 * the value we last wrote to the bus (for IDE interfaces without pullups). 203 * If no drive at all -> return. 204 * - reset the controller, wait for it to complete (may take up to 31s !). 205 * If timeout -> return. 206 * - test ATA/ATAPI signatures. If at last one drive found -> return. 207 * - try an ATA command on the master. 208 */ 209 210 static void 211 wdc_drvprobe(struct ata_channel *chp) 212 { 213 struct ataparams params; 214 struct atac_softc *atac = chp->ch_atac; 215 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 216 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 217 u_int8_t st0 = 0, st1 = 0; 218 int i, error, s; 219 220 if (wdcprobe1(chp, 0) == 0) { 221 /* No drives, abort the attach here. */ 222 return; 223 } 224 225 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 226 for (i = 0; i < mstohz(3000); i++) { 227 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 228 if (wdc->select) 229 wdc->select(chp,0); 230 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 231 0, WDSD_IBM); 232 delay(10); /* 400ns delay */ 233 st0 = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_status], 0); 235 } 236 237 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 238 if (wdc->select) 239 wdc->select(chp,1); 240 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 241 0, WDSD_IBM | 0x10); 242 delay(10); /* 400ns delay */ 243 st1 = bus_space_read_1(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_status], 0); 245 } 246 247 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 248 == 0 || 249 (st0 & WDCS_DRDY)) && 250 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 251 == 0 || 252 (st1 & WDCS_DRDY))) 253 break; 254 tsleep(¶ms, PRIBIO, "atadrdy", 1); 255 } 256 s = splbio(); 257 if ((st0 & WDCS_DRDY) == 0) 258 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 259 if ((st1 & WDCS_DRDY) == 0) 260 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 261 splx(s); 262 263 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 264 atac->atac_dev.dv_xname, 265 chp->ch_channel, st0, st1), DEBUG_PROBE); 266 267 /* Wait a bit, some devices are weird just after a reset. */ 268 delay(5000); 269 270 for (i = 0; i < 2; i++) { 271 /* XXX This should be done by other code. */ 272 chp->ch_drive[i].chnl_softc = chp; 273 chp->ch_drive[i].drive = i; 274 275 /* 276 * Init error counter so that an error withing the first xfers 277 * will trigger a downgrade 278 */ 279 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 280 281 /* If controller can't do 16bit flag the drives as 32bit */ 282 if ((atac->atac_cap & 283 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 284 s = splbio(); 285 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 286 splx(s); 287 } 288 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 289 continue; 290 291 /* Shortcut in case we've been shutdown */ 292 if (chp->ch_flags & ATACH_SHUTDOWN) 293 return; 294 295 /* 296 * Issue an identify, to try to detect ghosts. 297 * Note that we can't use interrupts here, because if there 298 * is no devices, we will get a command aborted without 299 * interrupts. 300 */ 301 error = ata_get_params(&chp->ch_drive[i], 302 AT_WAIT | AT_POLL, ¶ms); 303 if (error != CMD_OK) { 304 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 305 306 /* Shortcut in case we've been shutdown */ 307 if (chp->ch_flags & ATACH_SHUTDOWN) 308 return; 309 310 error = ata_get_params(&chp->ch_drive[i], 311 AT_WAIT | AT_POLL, ¶ms); 312 } 313 if (error == CMD_OK) { 314 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 315 s = splbio(); 316 /* XXXJRT ch_ndrive */ 317 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 318 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 319 splx(s); 320 } else { 321 s = splbio(); 322 chp->ch_drive[i].drive_flags &= 323 ~(DRIVE_ATA | DRIVE_ATAPI); 324 splx(s); 325 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 326 atac->atac_dev.dv_xname, 327 chp->ch_channel, i, error), DEBUG_PROBE); 328 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 329 continue; 330 /* 331 * Pre-ATA drive ? 332 * Test registers writability (Error register not 333 * writable, but cyllo is), then try an ATA command. 334 */ 335 if (wdc->select) 336 wdc->select(chp,i); 337 bus_space_write_1(wdr->cmd_iot, 338 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 339 delay(10); /* 400ns delay */ 340 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 341 0, 0x58); 342 bus_space_write_1(wdr->cmd_iot, 343 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 344 if (bus_space_read_1(wdr->cmd_iot, 345 wdr->cmd_iohs[wd_error], 0) == 0x58 || 346 bus_space_read_1(wdr->cmd_iot, 347 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 348 ATADEBUG_PRINT(("%s:%d:%d: register " 349 "writability failed\n", 350 atac->atac_dev.dv_xname, 351 chp->ch_channel, i), DEBUG_PROBE); 352 s = splbio(); 353 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 354 splx(s); 355 continue; 356 } 357 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 358 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 359 atac->atac_dev.dv_xname, 360 chp->ch_channel, i), DEBUG_PROBE); 361 s = splbio(); 362 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 363 splx(s); 364 continue; 365 } 366 bus_space_write_1(wdr->cmd_iot, 367 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 368 delay(10); /* 400ns delay */ 369 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 370 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 371 atac->atac_dev.dv_xname, 372 chp->ch_channel, i), DEBUG_PROBE); 373 s = splbio(); 374 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 375 splx(s); 376 } else { 377 s = splbio(); 378 /* XXXJRT ch_ndrive */ 379 chp->ch_drive[0].drive_flags &= 380 ~(DRIVE_ATA | DRIVE_ATAPI); 381 chp->ch_drive[1].drive_flags &= 382 ~(DRIVE_ATA | DRIVE_ATAPI); 383 splx(s); 384 } 385 } 386 } 387 } 388 389 int 390 wdcprobe(struct ata_channel *chp) 391 { 392 393 return (wdcprobe1(chp, 1)); 394 } 395 396 static int 397 wdcprobe1(struct ata_channel *chp, int poll) 398 { 399 struct atac_softc *atac = chp->ch_atac; 400 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 401 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 402 u_int8_t st0, st1, sc, sn, cl, ch; 403 u_int8_t ret_value = 0x03; 404 u_int8_t drive; 405 int s; 406 407 /* 408 * Sanity check to see if the wdc channel responds at all. 409 */ 410 411 s = splbio(); 412 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 413 414 if (wdc->select) 415 wdc->select(chp,0); 416 417 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 418 WDSD_IBM); 419 delay(10); /* 400ns delay */ 420 st0 = bus_space_read_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_status], 0); 422 423 if (wdc->select) 424 wdc->select(chp,1); 425 426 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 427 WDSD_IBM | 0x10); 428 delay(10); /* 400ns delay */ 429 st1 = bus_space_read_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_status], 0); 431 432 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 433 atac->atac_dev.dv_xname, 434 chp->ch_channel, st0, st1), DEBUG_PROBE); 435 436 if (st0 == 0xff || st0 == WDSD_IBM) 437 ret_value &= ~0x01; 438 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 439 ret_value &= ~0x02; 440 /* Register writability test, drive 0. */ 441 if (ret_value & 0x01) { 442 if (wdc->select) 443 wdc->select(chp,0); 444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 445 0, WDSD_IBM); 446 bus_space_write_1(wdr->cmd_iot, 447 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 448 cl = bus_space_read_1(wdr->cmd_iot, 449 wdr->cmd_iohs[wd_cyl_lo], 0); 450 if (cl != 0x02) { 451 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 452 "got 0x%x != 0x02\n", 453 atac->atac_dev.dv_xname, 454 chp->ch_channel, cl), 455 DEBUG_PROBE); 456 ret_value &= ~0x01; 457 } 458 bus_space_write_1(wdr->cmd_iot, 459 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 460 cl = bus_space_read_1(wdr->cmd_iot, 461 wdr->cmd_iohs[wd_cyl_lo], 0); 462 if (cl != 0x01) { 463 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 464 "got 0x%x != 0x01\n", 465 atac->atac_dev.dv_xname, 466 chp->ch_channel, cl), 467 DEBUG_PROBE); 468 ret_value &= ~0x01; 469 } 470 bus_space_write_1(wdr->cmd_iot, 471 wdr->cmd_iohs[wd_sector], 0, 0x01); 472 cl = bus_space_read_1(wdr->cmd_iot, 473 wdr->cmd_iohs[wd_sector], 0); 474 if (cl != 0x01) { 475 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 476 "got 0x%x != 0x01\n", 477 atac->atac_dev.dv_xname, 478 chp->ch_channel, cl), 479 DEBUG_PROBE); 480 ret_value &= ~0x01; 481 } 482 bus_space_write_1(wdr->cmd_iot, 483 wdr->cmd_iohs[wd_sector], 0, 0x02); 484 cl = bus_space_read_1(wdr->cmd_iot, 485 wdr->cmd_iohs[wd_sector], 0); 486 if (cl != 0x02) { 487 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 488 "got 0x%x != 0x02\n", 489 atac->atac_dev.dv_xname, 490 chp->ch_channel, cl), 491 DEBUG_PROBE); 492 ret_value &= ~0x01; 493 } 494 cl = bus_space_read_1(wdr->cmd_iot, 495 wdr->cmd_iohs[wd_cyl_lo], 0); 496 if (cl != 0x01) { 497 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 498 "got 0x%x != 0x01\n", 499 atac->atac_dev.dv_xname, 500 chp->ch_channel, cl), 501 DEBUG_PROBE); 502 ret_value &= ~0x01; 503 } 504 } 505 /* Register writability test, drive 1. */ 506 if (ret_value & 0x02) { 507 if (wdc->select) 508 wdc->select(chp,1); 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 bus_space_write_1(wdr->cmd_iot, 512 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 513 cl = bus_space_read_1(wdr->cmd_iot, 514 wdr->cmd_iohs[wd_cyl_lo], 0); 515 if (cl != 0x02) { 516 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 517 "got 0x%x != 0x02\n", 518 atac->atac_dev.dv_xname, 519 chp->ch_channel, cl), 520 DEBUG_PROBE); 521 ret_value &= ~0x02; 522 } 523 bus_space_write_1(wdr->cmd_iot, 524 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 525 cl = bus_space_read_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_cyl_lo], 0); 527 if (cl != 0x01) { 528 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 529 "got 0x%x != 0x01\n", 530 atac->atac_dev.dv_xname, 531 chp->ch_channel, cl), 532 DEBUG_PROBE); 533 ret_value &= ~0x02; 534 } 535 bus_space_write_1(wdr->cmd_iot, 536 wdr->cmd_iohs[wd_sector], 0, 0x01); 537 cl = bus_space_read_1(wdr->cmd_iot, 538 wdr->cmd_iohs[wd_sector], 0); 539 if (cl != 0x01) { 540 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 541 "got 0x%x != 0x01\n", 542 atac->atac_dev.dv_xname, 543 chp->ch_channel, cl), 544 DEBUG_PROBE); 545 ret_value &= ~0x02; 546 } 547 bus_space_write_1(wdr->cmd_iot, 548 wdr->cmd_iohs[wd_sector], 0, 0x02); 549 cl = bus_space_read_1(wdr->cmd_iot, 550 wdr->cmd_iohs[wd_sector], 0); 551 if (cl != 0x02) { 552 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 553 "got 0x%x != 0x02\n", 554 atac->atac_dev.dv_xname, 555 chp->ch_channel, cl), 556 DEBUG_PROBE); 557 ret_value &= ~0x02; 558 } 559 cl = bus_space_read_1(wdr->cmd_iot, 560 wdr->cmd_iohs[wd_cyl_lo], 0); 561 if (cl != 0x01) { 562 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 563 "got 0x%x != 0x01\n", 564 atac->atac_dev.dv_xname, 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x02; 568 } 569 } 570 571 if (ret_value == 0) { 572 splx(s); 573 return 0; 574 } 575 } 576 577 578 #if 0 /* XXX this break some ATA or ATAPI devices */ 579 /* 580 * reset bus. Also send an ATAPI_RESET to devices, in case there are 581 * ATAPI device out there which don't react to the bus reset 582 */ 583 if (ret_value & 0x01) { 584 if (wdc->select) 585 wdc->select(chp,0); 586 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 587 0, WDSD_IBM); 588 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 589 ATAPI_SOFT_RESET); 590 } 591 if (ret_value & 0x02) { 592 if (wdc->select) 593 wdc->select(chp,0); 594 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 595 0, WDSD_IBM | 0x10); 596 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 597 ATAPI_SOFT_RESET); 598 } 599 600 delay(5000); 601 #endif 602 603 if (wdc->select) 604 wdc->select(chp,0); 605 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 606 delay(10); /* 400ns delay */ 607 /* assert SRST, wait for reset to complete */ 608 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 609 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 610 DELAY(1000); 611 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 612 WDCTL_IDS | WDCTL_4BIT); 613 DELAY(2000); 614 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 615 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 616 delay(10); /* 400ns delay */ 617 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 618 if (wdc->irqack != NULL) 619 wdc->irqack(chp); 620 splx(s); 621 622 ret_value = __wdcwait_reset(chp, ret_value, poll); 623 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 624 atac->atac_dev.dv_xname, chp->ch_channel, 625 ret_value), DEBUG_PROBE); 626 627 /* if reset failed, there's nothing here */ 628 if (ret_value == 0) 629 return 0; 630 631 /* 632 * Test presence of drives. First test register signatures looking 633 * for ATAPI devices. If it's not an ATAPI and reset said there may 634 * be something here assume it's ATA or OLD. Ghost will be killed 635 * later in attach routine. 636 */ 637 for (drive = 0; drive < 2; drive++) { 638 if ((ret_value & (0x01 << drive)) == 0) 639 continue; 640 if (wdc->select) 641 wdc->select(chp,drive); 642 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 643 WDSD_IBM | (drive << 4)); 644 delay(10); /* 400ns delay */ 645 /* Save registers contents */ 646 sc = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_seccnt], 0); 648 sn = bus_space_read_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0); 650 cl = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_cyl_lo], 0); 652 ch = bus_space_read_1(wdr->cmd_iot, 653 wdr->cmd_iohs[wd_cyl_hi], 0); 654 655 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 656 "cl=0x%x ch=0x%x\n", 657 atac->atac_dev.dv_xname, 658 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 659 /* 660 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 661 * we get wrong values here, so ignore it. 662 */ 663 s = splbio(); 664 if (cl == 0x14 && ch == 0xeb) { 665 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 666 } else { 667 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 668 if (wdc == NULL || 669 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 670 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 671 } 672 splx(s); 673 } 674 return (ret_value); 675 } 676 677 void 678 wdcattach(struct ata_channel *chp) 679 { 680 struct atac_softc *atac = chp->ch_atac; 681 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 682 683 /* 684 * Start out assuming 2 drives. This may change as we probe 685 * drives. 686 */ 687 chp->ch_ndrive = 2; 688 689 /* default data transfer methods */ 690 if (wdc->datain_pio == NULL) 691 wdc->datain_pio = wdc_datain_pio; 692 if (wdc->dataout_pio == NULL) 693 wdc->dataout_pio = wdc_dataout_pio; 694 695 /* initialise global data */ 696 if (atac->atac_bustype_ata == NULL) 697 atac->atac_bustype_ata = &wdc_ata_bustype; 698 if (atac->atac_probe == NULL) 699 atac->atac_probe = wdc_drvprobe; 700 #if NATAPIBUS > 0 701 if (atac->atac_atapibus_attach == NULL) 702 atac->atac_atapibus_attach = wdc_atapibus_attach; 703 #endif 704 705 ata_channel_attach(chp); 706 } 707 708 int 709 wdcactivate(struct device *self, enum devact act) 710 { 711 struct atac_softc *atac = (struct atac_softc *) self; 712 int s, i, error = 0; 713 714 s = splbio(); 715 switch (act) { 716 case DVACT_ACTIVATE: 717 error = EOPNOTSUPP; 718 break; 719 720 case DVACT_DEACTIVATE: 721 for (i = 0; i < atac->atac_nchannels; i++) { 722 error = 723 config_deactivate(atac->atac_channels[i]->atabus); 724 if (error) 725 break; 726 } 727 break; 728 } 729 splx(s); 730 return (error); 731 } 732 733 int 734 wdcdetach(struct device *self, int flags) 735 { 736 struct atac_softc *atac = (struct atac_softc *) self; 737 struct ata_channel *chp; 738 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 739 int i, error = 0; 740 741 for (i = 0; i < atac->atac_nchannels; i++) { 742 chp = atac->atac_channels[i]; 743 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 744 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 745 DEBUG_DETACH); 746 error = config_detach(chp->atabus, flags); 747 if (error) 748 break; 749 } 750 if (adapt->adapt_refcnt != 0) { 751 #ifdef DIAGNOSTIC 752 printf("wdcdetach: refcnt should be 0 here??\n"); 753 #endif 754 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 755 } 756 return (error); 757 } 758 759 /* restart an interrupted I/O */ 760 void 761 wdcrestart(void *v) 762 { 763 struct ata_channel *chp = v; 764 int s; 765 766 s = splbio(); 767 atastart(chp); 768 splx(s); 769 } 770 771 772 /* 773 * Interrupt routine for the controller. Acknowledge the interrupt, check for 774 * errors on the current operation, mark it done if necessary, and start the 775 * next request. Also check for a partially done transfer, and continue with 776 * the next chunk if so. 777 */ 778 int 779 wdcintr(void *arg) 780 { 781 struct ata_channel *chp = arg; 782 struct atac_softc *atac = chp->ch_atac; 783 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 784 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 785 struct ata_xfer *xfer; 786 int ret; 787 788 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 789 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 790 DEBUG_INTR); 791 return (0); 792 } 793 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 794 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 795 /* try to clear the pending interrupt anyway */ 796 (void)bus_space_read_1(wdr->cmd_iot, 797 wdr->cmd_iohs[wd_status], 0); 798 return (0); 799 } 800 801 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 802 xfer = chp->ch_queue->active_xfer; 803 #ifdef DIAGNOSTIC 804 if (xfer == NULL) 805 panic("wdcintr: no xfer"); 806 #endif 807 if (chp->ch_flags & ATACH_DMA_WAIT) { 808 wdc->dma_status = 809 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 810 xfer->c_drive, WDC_DMAEND_END); 811 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 812 /* IRQ not for us, not detected by DMA engine */ 813 return 0; 814 } 815 chp->ch_flags &= ~ATACH_DMA_WAIT; 816 } 817 chp->ch_flags &= ~ATACH_IRQ_WAIT; 818 ret = xfer->c_intr(chp, xfer, 1); 819 if (ret == 0) /* irq was not for us, still waiting for irq */ 820 chp->ch_flags |= ATACH_IRQ_WAIT; 821 return (ret); 822 } 823 824 /* Put all disk in RESET state */ 825 void 826 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 827 { 828 struct ata_channel *chp = drvp->chnl_softc; 829 struct atac_softc *atac = chp->ch_atac; 830 831 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 832 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 833 DEBUG_FUNCS); 834 835 ata_reset_channel(chp, flags); 836 } 837 838 void 839 wdc_reset_channel(struct ata_channel *chp, int flags) 840 { 841 TAILQ_HEAD(, ata_xfer) reset_xfer; 842 struct ata_xfer *xfer, *next_xfer; 843 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 844 845 TAILQ_INIT(&reset_xfer); 846 847 chp->ch_flags &= ~ATACH_IRQ_WAIT; 848 849 /* 850 * if the current command if on an ATAPI device, issue a 851 * ATAPI_SOFT_RESET 852 */ 853 xfer = chp->ch_queue->active_xfer; 854 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 855 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 856 if (flags & AT_WAIT) 857 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 858 else 859 delay(1000); 860 } 861 862 /* reset the channel */ 863 if (flags & AT_WAIT) 864 (void) wdcreset(chp, RESET_SLEEP); 865 else 866 (void) wdcreset(chp, RESET_POLL); 867 868 /* 869 * wait a bit after reset; in case the DMA engines needs some time 870 * to recover. 871 */ 872 if (flags & AT_WAIT) 873 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 874 else 875 delay(1000); 876 /* 877 * look for pending xfers. If we have a shared queue, we'll also reset 878 * the other channel if the current xfer is running on it. 879 * Then we'll dequeue only the xfers for this channel. 880 */ 881 if ((flags & AT_RST_NOCMD) == 0) { 882 /* 883 * move all xfers queued for this channel to the reset queue, 884 * and then process the current xfer and then the reset queue. 885 * We have to use a temporary queue because c_kill_xfer() 886 * may requeue commands. 887 */ 888 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 889 xfer != NULL; xfer = next_xfer) { 890 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 891 if (xfer->c_chp != chp) 892 continue; 893 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 894 xfer, c_xferchain); 895 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 896 } 897 xfer = chp->ch_queue->active_xfer; 898 if (xfer) { 899 if (xfer->c_chp != chp) 900 ata_reset_channel(xfer->c_chp, flags); 901 else { 902 callout_stop(&chp->ch_callout); 903 /* 904 * If we're waiting for DMA, stop the 905 * DMA engine 906 */ 907 if (chp->ch_flags & ATACH_DMA_WAIT) { 908 (*wdc->dma_finish)( 909 wdc->dma_arg, 910 chp->ch_channel, 911 xfer->c_drive, 912 WDC_DMAEND_ABRT_QUIET); 913 chp->ch_flags &= ~ATACH_DMA_WAIT; 914 } 915 chp->ch_queue->active_xfer = NULL; 916 if ((flags & AT_RST_EMERG) == 0) 917 xfer->c_kill_xfer( 918 chp, xfer, KILL_RESET); 919 } 920 } 921 922 for (xfer = TAILQ_FIRST(&reset_xfer); 923 xfer != NULL; xfer = next_xfer) { 924 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 925 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 926 if ((flags & AT_RST_EMERG) == 0) 927 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 928 } 929 } 930 } 931 932 static int 933 wdcreset(struct ata_channel *chp, int poll) 934 { 935 struct atac_softc *atac = chp->ch_atac; 936 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 937 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 938 int drv_mask1, drv_mask2; 939 int s = 0; 940 941 if (wdc->select) 942 wdc->select(chp,0); 943 if (poll != RESET_SLEEP) 944 s = splbio(); 945 /* master */ 946 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 947 delay(10); /* 400ns delay */ 948 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 949 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 950 delay(2000); 951 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 952 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 953 WDCTL_4BIT | WDCTL_IDS); 954 delay(10); /* 400ns delay */ 955 if (poll != RESET_SLEEP) { 956 if (wdc->irqack) 957 wdc->irqack(chp); 958 splx(s); 959 } 960 961 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 962 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 963 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 964 (poll == RESET_SLEEP) ? 0 : 1); 965 if (drv_mask2 != drv_mask1) { 966 printf("%s channel %d: reset failed for", 967 atac->atac_dev.dv_xname, chp->ch_channel); 968 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 969 printf(" drive 0"); 970 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 971 printf(" drive 1"); 972 printf("\n"); 973 } 974 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 975 return (drv_mask1 != drv_mask2) ? 1 : 0; 976 } 977 978 static int 979 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 980 { 981 struct atac_softc *atac = chp->ch_atac; 982 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 983 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 984 int timeout, nloop; 985 u_int8_t st0 = 0, st1 = 0; 986 #ifdef ATADEBUG 987 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 988 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 989 #endif 990 991 if (poll) 992 nloop = WDCNDELAY_RST; 993 else 994 nloop = WDC_RESET_WAIT * hz / 1000; 995 /* wait for BSY to deassert */ 996 for (timeout = 0; timeout < nloop; timeout++) { 997 if ((drv_mask & 0x01) != 0) { 998 if (wdc && wdc->select) 999 wdc->select(chp,0); 1000 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1001 0, WDSD_IBM); /* master */ 1002 delay(10); 1003 st0 = bus_space_read_1(wdr->cmd_iot, 1004 wdr->cmd_iohs[wd_status], 0); 1005 #ifdef ATADEBUG 1006 sc0 = bus_space_read_1(wdr->cmd_iot, 1007 wdr->cmd_iohs[wd_seccnt], 0); 1008 sn0 = bus_space_read_1(wdr->cmd_iot, 1009 wdr->cmd_iohs[wd_sector], 0); 1010 cl0 = bus_space_read_1(wdr->cmd_iot, 1011 wdr->cmd_iohs[wd_cyl_lo], 0); 1012 ch0 = bus_space_read_1(wdr->cmd_iot, 1013 wdr->cmd_iohs[wd_cyl_hi], 0); 1014 #endif 1015 } 1016 if ((drv_mask & 0x02) != 0) { 1017 if (wdc && wdc->select) 1018 wdc->select(chp,1); 1019 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1020 0, WDSD_IBM | 0x10); /* slave */ 1021 delay(10); 1022 st1 = bus_space_read_1(wdr->cmd_iot, 1023 wdr->cmd_iohs[wd_status], 0); 1024 #ifdef ATADEBUG 1025 sc1 = bus_space_read_1(wdr->cmd_iot, 1026 wdr->cmd_iohs[wd_seccnt], 0); 1027 sn1 = bus_space_read_1(wdr->cmd_iot, 1028 wdr->cmd_iohs[wd_sector], 0); 1029 cl1 = bus_space_read_1(wdr->cmd_iot, 1030 wdr->cmd_iohs[wd_cyl_lo], 0); 1031 ch1 = bus_space_read_1(wdr->cmd_iot, 1032 wdr->cmd_iohs[wd_cyl_hi], 0); 1033 #endif 1034 } 1035 1036 if ((drv_mask & 0x01) == 0) { 1037 /* no master */ 1038 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1039 /* No master, slave is ready, it's done */ 1040 goto end; 1041 } 1042 } else if ((drv_mask & 0x02) == 0) { 1043 /* no slave */ 1044 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1045 /* No slave, master is ready, it's done */ 1046 goto end; 1047 } 1048 } else { 1049 /* Wait for both master and slave to be ready */ 1050 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1051 goto end; 1052 } 1053 } 1054 if (poll) 1055 delay(WDCDELAY); 1056 else 1057 tsleep(&nloop, PRIBIO, "atarst", 1); 1058 } 1059 /* Reset timed out. Maybe it's because drv_mask was not right */ 1060 if (st0 & WDCS_BSY) 1061 drv_mask &= ~0x01; 1062 if (st1 & WDCS_BSY) 1063 drv_mask &= ~0x02; 1064 end: 1065 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1066 "cl=0x%x ch=0x%x\n", 1067 atac->atac_dev.dv_xname, 1068 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1069 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1070 "cl=0x%x ch=0x%x\n", 1071 atac->atac_dev.dv_xname, 1072 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1073 1074 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1075 atac->atac_dev.dv_xname, chp->ch_channel, 1076 st0, st1), DEBUG_PROBE); 1077 1078 return drv_mask; 1079 } 1080 1081 /* 1082 * Wait for a drive to be !BSY, and have mask in its status register. 1083 * return -1 for a timeout after "timeout" ms. 1084 */ 1085 static int 1086 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1087 { 1088 struct atac_softc *atac = chp->ch_atac; 1089 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1090 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1091 u_char status; 1092 int time = 0; 1093 1094 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1095 atac->atac_dev.dv_xname, 1096 chp->ch_channel), DEBUG_STATUS); 1097 chp->ch_error = 0; 1098 1099 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1100 1101 for (;;) { 1102 chp->ch_status = status = 1103 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1104 if ((status & (WDCS_BSY | mask)) == bits) 1105 break; 1106 if (++time > timeout) { 1107 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1108 "status %x error %x (mask 0x%x bits 0x%x)\n", 1109 time, status, 1110 bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_error], 0), mask, bits), 1112 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1113 return(WDCWAIT_TOUT); 1114 } 1115 delay(WDCDELAY); 1116 } 1117 #ifdef ATADEBUG 1118 if (time > 0 && (atadebug_mask & DEBUG_DELAY)) 1119 printf("__wdcwait: did busy-wait, time=%d\n", time); 1120 #endif 1121 if (status & WDCS_ERR) 1122 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_error], 0); 1124 #ifdef WDCNDELAY_DEBUG 1125 /* After autoconfig, there should be no long delays. */ 1126 if (!cold && time > WDCNDELAY_DEBUG) { 1127 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1128 if (xfer == NULL) 1129 printf("%s channel %d: warning: busy-wait took %dus\n", 1130 atac->atac_dev.dv_xname, chp->ch_channel, 1131 WDCDELAY * time); 1132 else 1133 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1134 atac->atac_dev.dv_xname, chp->ch_channel, 1135 xfer->drive, 1136 WDCDELAY * time); 1137 } 1138 #endif 1139 return(WDCWAIT_OK); 1140 } 1141 1142 /* 1143 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1144 * thread if possible 1145 */ 1146 int 1147 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1148 { 1149 int error, i, timeout_hz = mstohz(timeout); 1150 1151 if (timeout_hz == 0 || 1152 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1153 error = __wdcwait(chp, mask, bits, timeout); 1154 else { 1155 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1156 if (error != 0) { 1157 if ((chp->ch_flags & ATACH_TH_RUN) || 1158 (flags & AT_WAIT)) { 1159 /* 1160 * we're running in the channel thread 1161 * or some userland thread context 1162 */ 1163 for (i = 0; i < timeout_hz; i++) { 1164 if (__wdcwait(chp, mask, bits, 1165 WDCDELAY_POLL) == 0) { 1166 error = 0; 1167 break; 1168 } 1169 tsleep(&chp, PRIBIO, "atapoll", 1); 1170 } 1171 } else { 1172 /* 1173 * we're probably in interrupt context, 1174 * ask the thread to come back here 1175 */ 1176 #ifdef DIAGNOSTIC 1177 if (chp->ch_queue->queue_freeze > 0) 1178 panic("wdcwait: queue_freeze"); 1179 #endif 1180 chp->ch_queue->queue_freeze++; 1181 wakeup(&chp->ch_thread); 1182 return(WDCWAIT_THR); 1183 } 1184 } 1185 } 1186 return (error); 1187 } 1188 1189 1190 /* 1191 * Busy-wait for DMA to complete 1192 */ 1193 int 1194 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1195 { 1196 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1197 int time; 1198 1199 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1200 wdc->dma_status = 1201 (*wdc->dma_finish)(wdc->dma_arg, 1202 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1203 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1204 return 0; 1205 delay(WDCDELAY); 1206 } 1207 /* timeout, force a DMA halt */ 1208 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1209 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1210 return 1; 1211 } 1212 1213 void 1214 wdctimeout(void *arg) 1215 { 1216 struct ata_channel *chp = (struct ata_channel *)arg; 1217 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1218 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1219 int s; 1220 1221 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1222 1223 s = splbio(); 1224 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1225 __wdcerror(chp, "lost interrupt"); 1226 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1227 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1228 xfer->c_bcount, 1229 xfer->c_skip); 1230 if (chp->ch_flags & ATACH_DMA_WAIT) { 1231 wdc->dma_status = 1232 (*wdc->dma_finish)(wdc->dma_arg, 1233 chp->ch_channel, xfer->c_drive, 1234 WDC_DMAEND_ABRT); 1235 chp->ch_flags &= ~ATACH_DMA_WAIT; 1236 } 1237 /* 1238 * Call the interrupt routine. If we just missed an interrupt, 1239 * it will do what's needed. Else, it will take the needed 1240 * action (reset the device). 1241 * Before that we need to reinstall the timeout callback, 1242 * in case it will miss another irq while in this transfer 1243 * We arbitray chose it to be 1s 1244 */ 1245 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1246 xfer->c_flags |= C_TIMEOU; 1247 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1248 xfer->c_intr(chp, xfer, 1); 1249 } else 1250 __wdcerror(chp, "missing untimeout"); 1251 splx(s); 1252 } 1253 1254 int 1255 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1256 { 1257 struct ata_channel *chp = drvp->chnl_softc; 1258 struct atac_softc *atac = chp->ch_atac; 1259 struct ata_xfer *xfer; 1260 int s, ret; 1261 1262 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1263 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1264 DEBUG_FUNCS); 1265 1266 /* set up an xfer and queue. Wait for completion */ 1267 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1268 ATAXF_NOSLEEP); 1269 if (xfer == NULL) { 1270 return ATACMD_TRY_AGAIN; 1271 } 1272 1273 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1274 ata_c->flags |= AT_POLL; 1275 if (ata_c->flags & AT_POLL) 1276 xfer->c_flags |= C_POLL; 1277 if (ata_c->flags & AT_WAIT) 1278 xfer->c_flags |= C_WAIT; 1279 xfer->c_drive = drvp->drive; 1280 xfer->c_databuf = ata_c->data; 1281 xfer->c_bcount = ata_c->bcount; 1282 xfer->c_cmd = ata_c; 1283 xfer->c_start = __wdccommand_start; 1284 xfer->c_intr = __wdccommand_intr; 1285 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1286 1287 s = splbio(); 1288 ata_exec_xfer(chp, xfer); 1289 #ifdef DIAGNOSTIC 1290 if ((ata_c->flags & AT_POLL) != 0 && 1291 (ata_c->flags & AT_DONE) == 0) 1292 panic("wdc_exec_command: polled command not done"); 1293 #endif 1294 if (ata_c->flags & AT_DONE) { 1295 ret = ATACMD_COMPLETE; 1296 } else { 1297 if (ata_c->flags & AT_WAIT) { 1298 while ((ata_c->flags & AT_DONE) == 0) { 1299 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1300 } 1301 ret = ATACMD_COMPLETE; 1302 } else { 1303 ret = ATACMD_QUEUED; 1304 } 1305 } 1306 splx(s); 1307 return ret; 1308 } 1309 1310 static void 1311 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1312 { 1313 struct atac_softc *atac = chp->ch_atac; 1314 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1315 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1316 int drive = xfer->c_drive; 1317 struct ata_command *ata_c = xfer->c_cmd; 1318 1319 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1320 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1321 DEBUG_FUNCS); 1322 1323 if (wdc->select) 1324 wdc->select(chp,drive); 1325 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1326 WDSD_IBM | (drive << 4)); 1327 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1328 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1329 case WDCWAIT_OK: 1330 break; 1331 case WDCWAIT_TOUT: 1332 ata_c->flags |= AT_TIMEOU; 1333 __wdccommand_done(chp, xfer); 1334 return; 1335 case WDCWAIT_THR: 1336 return; 1337 } 1338 if (ata_c->flags & AT_POLL) { 1339 /* polled command, disable interrupts */ 1340 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1341 WDCTL_4BIT | WDCTL_IDS); 1342 } 1343 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1344 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1345 1346 if ((ata_c->flags & AT_POLL) == 0) { 1347 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1348 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1349 wdctimeout, chp); 1350 return; 1351 } 1352 /* 1353 * Polled command. Wait for drive ready or drq. Done in intr(). 1354 * Wait for at last 400ns for status bit to be valid. 1355 */ 1356 delay(10); /* 400ns delay */ 1357 __wdccommand_intr(chp, xfer, 0); 1358 } 1359 1360 static int 1361 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1362 { 1363 struct atac_softc *atac = chp->ch_atac; 1364 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1365 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1366 struct ata_command *ata_c = xfer->c_cmd; 1367 int bcount = ata_c->bcount; 1368 char *data = ata_c->data; 1369 int wflags; 1370 1371 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1372 /* both wait and poll, we can tsleep here */ 1373 wflags = AT_WAIT | AT_POLL; 1374 } else { 1375 wflags = AT_POLL; 1376 } 1377 1378 again: 1379 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1380 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1381 DEBUG_INTR); 1382 /* 1383 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1384 * Reselect again, it doesn't hurt for others commands, and the time 1385 * penalty for the extra regiter write is acceptable, 1386 * wdc_exec_command() isn't called often (mosly for autoconfig) 1387 */ 1388 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1389 WDSD_IBM | (xfer->c_drive << 4)); 1390 if ((ata_c->flags & AT_XFDONE) != 0) { 1391 /* 1392 * We have completed a data xfer. The drive should now be 1393 * in its initial state 1394 */ 1395 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1396 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1397 wflags) == WDCWAIT_TOUT) { 1398 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1399 return 0; /* IRQ was not for us */ 1400 ata_c->flags |= AT_TIMEOU; 1401 } 1402 goto out; 1403 } 1404 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1405 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1406 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1407 return 0; /* IRQ was not for us */ 1408 ata_c->flags |= AT_TIMEOU; 1409 goto out; 1410 } 1411 if (wdc->irqack) 1412 wdc->irqack(chp); 1413 if (ata_c->flags & AT_READ) { 1414 if ((chp->ch_status & WDCS_DRQ) == 0) { 1415 ata_c->flags |= AT_TIMEOU; 1416 goto out; 1417 } 1418 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1419 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1420 0, (u_int32_t*)data, bcount >> 2); 1421 data += bcount & 0xfffffffc; 1422 bcount = bcount & 0x03; 1423 } 1424 if (bcount > 0) 1425 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1426 /* at this point the drive should be in its initial state */ 1427 ata_c->flags |= AT_XFDONE; 1428 /* XXX should read status register here ? */ 1429 } else if (ata_c->flags & AT_WRITE) { 1430 if ((chp->ch_status & WDCS_DRQ) == 0) { 1431 ata_c->flags |= AT_TIMEOU; 1432 goto out; 1433 } 1434 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1435 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1436 0, (u_int32_t*)data, bcount >> 2); 1437 data += bcount & 0xfffffffc; 1438 bcount = bcount & 0x03; 1439 } 1440 if (bcount > 0) 1441 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1442 ata_c->flags |= AT_XFDONE; 1443 if ((ata_c->flags & AT_POLL) == 0) { 1444 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1445 callout_reset(&chp->ch_callout, 1446 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1447 return 1; 1448 } else { 1449 goto again; 1450 } 1451 } 1452 out: 1453 __wdccommand_done(chp, xfer); 1454 return 1; 1455 } 1456 1457 static void 1458 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1459 { 1460 struct atac_softc *atac = chp->ch_atac; 1461 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1462 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1463 struct ata_command *ata_c = xfer->c_cmd; 1464 1465 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1466 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1467 DEBUG_FUNCS); 1468 1469 1470 if (chp->ch_status & WDCS_DWF) 1471 ata_c->flags |= AT_DF; 1472 if (chp->ch_status & WDCS_ERR) { 1473 ata_c->flags |= AT_ERROR; 1474 ata_c->r_error = chp->ch_error; 1475 } 1476 if ((ata_c->flags & AT_READREG) != 0 && 1477 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1478 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1479 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1480 wdr->cmd_iohs[wd_sdh], 0); 1481 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1482 wdr->cmd_iohs[wd_seccnt], 0); 1483 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1484 wdr->cmd_iohs[wd_sector], 0); 1485 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1486 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1487 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1488 wdr->cmd_iohs[wd_cyl_lo], 0); 1489 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1490 wdr->cmd_iohs[wd_error], 0); 1491 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1492 wdr->cmd_iohs[wd_features], 0); 1493 } 1494 callout_stop(&chp->ch_callout); 1495 chp->ch_queue->active_xfer = NULL; 1496 if (ata_c->flags & AT_POLL) { 1497 /* enable interrupts */ 1498 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1499 WDCTL_4BIT); 1500 delay(10); /* some drives need a little delay here */ 1501 } 1502 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1503 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1504 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1505 wakeup(&chp->ch_queue->active_xfer); 1506 } else 1507 __wdccommand_done_end(chp, xfer); 1508 } 1509 1510 static void 1511 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1512 { 1513 struct ata_command *ata_c = xfer->c_cmd; 1514 1515 ata_c->flags |= AT_DONE; 1516 ata_free_xfer(chp, xfer); 1517 if (ata_c->flags & AT_WAIT) 1518 wakeup(ata_c); 1519 else if (ata_c->callback) 1520 ata_c->callback(ata_c->callback_arg); 1521 atastart(chp); 1522 return; 1523 } 1524 1525 static void 1526 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1527 int reason) 1528 { 1529 struct ata_command *ata_c = xfer->c_cmd; 1530 1531 switch (reason) { 1532 case KILL_GONE: 1533 ata_c->flags |= AT_GONE; 1534 break; 1535 case KILL_RESET: 1536 ata_c->flags |= AT_RESET; 1537 break; 1538 default: 1539 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1540 reason); 1541 panic("__wdccommand_kill_xfer"); 1542 } 1543 __wdccommand_done_end(chp, xfer); 1544 } 1545 1546 /* 1547 * Send a command. The drive should be ready. 1548 * Assumes interrupts are blocked. 1549 */ 1550 void 1551 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1552 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1553 u_int8_t features) 1554 { 1555 struct atac_softc *atac = chp->ch_atac; 1556 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1557 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1558 1559 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1560 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1561 chp->ch_channel, drive, command, cylin, head, sector, count, 1562 features), DEBUG_FUNCS); 1563 1564 if (wdc->select) 1565 wdc->select(chp,drive); 1566 1567 /* Select drive, head, and addressing mode. */ 1568 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1569 WDSD_IBM | (drive << 4) | head); 1570 /* Load parameters into the wd_features register. */ 1571 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1572 features); 1573 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1574 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1575 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1576 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1577 0, cylin >> 8); 1578 1579 /* Send command. */ 1580 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1581 return; 1582 } 1583 1584 /* 1585 * Send a 48-bit addressing command. The drive should be ready. 1586 * Assumes interrupts are blocked. 1587 */ 1588 void 1589 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1590 u_int64_t blkno, u_int16_t count) 1591 { 1592 struct atac_softc *atac = chp->ch_atac; 1593 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1594 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1595 1596 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1597 "count=%d\n", atac->atac_dev.dv_xname, 1598 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1599 DEBUG_FUNCS); 1600 1601 if (wdc->select) 1602 wdc->select(chp,drive); 1603 1604 /* Select drive, head, and addressing mode. */ 1605 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1606 (drive << 4) | WDSD_LBA); 1607 1608 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1609 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1610 0); 1611 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1612 0, count); 1613 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1614 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1615 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1616 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1617 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1618 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1619 } else { 1620 /* previous */ 1621 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1622 0); 1623 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1624 0, count >> 8); 1625 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1626 0, blkno >> 24); 1627 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1628 0, blkno >> 32); 1629 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1630 0, blkno >> 40); 1631 1632 /* current */ 1633 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1634 0); 1635 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1636 count); 1637 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1638 blkno); 1639 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1640 0, blkno >> 8); 1641 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1642 0, blkno >> 16); 1643 } 1644 1645 /* Send command. */ 1646 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1647 return; 1648 } 1649 1650 /* 1651 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1652 * tested by the caller. 1653 */ 1654 void 1655 wdccommandshort(struct ata_channel *chp, int drive, int command) 1656 { 1657 struct atac_softc *atac = chp->ch_atac; 1658 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1659 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1660 1661 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1662 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1663 DEBUG_FUNCS); 1664 1665 if (wdc->select) 1666 wdc->select(chp,drive); 1667 1668 /* Select drive. */ 1669 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1670 WDSD_IBM | (drive << 4)); 1671 1672 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1673 } 1674 1675 static void 1676 __wdcerror(struct ata_channel *chp, char *msg) 1677 { 1678 struct atac_softc *atac = chp->ch_atac; 1679 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1680 1681 if (xfer == NULL) 1682 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1683 msg); 1684 else 1685 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1686 chp->ch_channel, xfer->c_drive, msg); 1687 } 1688 1689 /* 1690 * the bit bucket 1691 */ 1692 void 1693 wdcbit_bucket(struct ata_channel *chp, int size) 1694 { 1695 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1696 1697 for (; size >= 2; size -= 2) 1698 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1699 if (size) 1700 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1701 } 1702 1703 static void 1704 wdc_datain_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1705 { 1706 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1707 1708 if (flags & DRIVE_NOSTREAM) { 1709 if (flags & DRIVE_CAP32) { 1710 bus_space_read_multi_4(wdr->data32iot, 1711 wdr->data32ioh, 0, buf, len >> 2); 1712 buf = (char *)buf + (len & ~3); 1713 len &= 3; 1714 } 1715 if (len) { 1716 bus_space_read_multi_2(wdr->cmd_iot, 1717 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1718 } 1719 } else { 1720 if (flags & DRIVE_CAP32) { 1721 bus_space_read_multi_stream_4(wdr->data32iot, 1722 wdr->data32ioh, 0, buf, len >> 2); 1723 buf = (char *)buf + (len & ~3); 1724 len &= 3; 1725 } 1726 if (len) { 1727 bus_space_read_multi_stream_2(wdr->cmd_iot, 1728 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1729 } 1730 } 1731 } 1732 1733 static void 1734 wdc_dataout_pio(struct ata_channel *chp, int flags, void *buf, size_t len) 1735 { 1736 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1737 1738 if (flags & DRIVE_NOSTREAM) { 1739 if (flags & DRIVE_CAP32) { 1740 bus_space_write_multi_4(wdr->data32iot, 1741 wdr->data32ioh, 0, buf, len >> 2); 1742 buf = (char *)buf + (len & ~3); 1743 len &= 3; 1744 } 1745 if (len) { 1746 bus_space_write_multi_2(wdr->cmd_iot, 1747 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1748 } 1749 } else { 1750 if (flags & DRIVE_CAP32) { 1751 bus_space_write_multi_stream_4(wdr->data32iot, 1752 wdr->data32ioh, 0, buf, len >> 2); 1753 buf = (char *)buf + (len & ~3); 1754 len &= 3; 1755 } 1756 if (len) { 1757 bus_space_write_multi_stream_2(wdr->cmd_iot, 1758 wdr->cmd_iohs[wd_data], 0, buf, len >> 1); 1759 } 1760 } 1761 } 1762
Indexes created Mon Sep 22 13:09:51 GMT 2025