wdc.c revision 1.223
1 /* $NetBSD: wdc.c,v 1.223 2005/06/16 20:15:04 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.223 2005/06/16 20:15:04 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 #if NWD > 0 123 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 124 #else 125 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 126 const struct ata_bustype wdc_ata_bustype = { 127 SCSIPI_BUSTYPE_ATA, 128 NULL, /* wdc_ata_bio */ 129 NULL, /* wdc_reset_drive */ 130 wdc_reset_channel, 131 wdc_exec_command, 132 NULL, /* ata_get_params */ 133 NULL, /* wdc_ata_addref */ 134 NULL, /* wdc_ata_delref */ 135 NULL /* ata_kill_pending */ 136 }; 137 #endif 138 139 /* Flags to wdcreset(). */ 140 #define RESET_POLL 1 141 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 142 143 static int wdcprobe1(struct ata_channel *, int); 144 static int wdcreset(struct ata_channel *, int); 145 static void __wdcerror(struct ata_channel *, const char *); 146 static int __wdcwait_reset(struct ata_channel *, int, int); 147 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 148 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 149 static void __wdccommand_kill_xfer(struct ata_channel *, 150 struct ata_xfer *, int); 151 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 153 static int __wdcwait(struct ata_channel *, int, int, int); 154 155 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 156 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef ATADEBUG 166 extern int atadebug_mask; /* init'ed in ata.c */ 167 int wdc_nxfer = 0; 168 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 169 #else 170 #define ATADEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * Initialize the "shadow register" handles for a standard wdc controller. 175 */ 176 void 177 wdc_init_shadow_regs(struct ata_channel *chp) 178 { 179 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 180 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 /* Test to see controller with at last one attached drive is there. 197 * Returns a bit for each possible drive found (0x01 for drive 0, 198 * 0x02 for drive 1). 199 * Logic: 200 * - If a status register is at 0xff, assume there is no drive here 201 * (ISA has pull-up resistors). Similarly if the status register has 202 * the value we last wrote to the bus (for IDE interfaces without pullups). 203 * If no drive at all -> return. 204 * - reset the controller, wait for it to complete (may take up to 31s !). 205 * If timeout -> return. 206 * - test ATA/ATAPI signatures. If at last one drive found -> return. 207 * - try an ATA command on the master. 208 */ 209 210 static void 211 wdc_drvprobe(struct ata_channel *chp) 212 { 213 struct ataparams params; 214 struct atac_softc *atac = chp->ch_atac; 215 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 216 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 217 u_int8_t st0 = 0, st1 = 0; 218 int i, error, s; 219 220 if (wdcprobe1(chp, 0) == 0) { 221 /* No drives, abort the attach here. */ 222 return; 223 } 224 225 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 226 for (i = 0; i < mstohz(3000); i++) { 227 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 228 if (wdc->select) 229 wdc->select(chp,0); 230 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 231 0, WDSD_IBM); 232 delay(10); /* 400ns delay */ 233 st0 = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_status], 0); 235 } 236 237 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 238 if (wdc->select) 239 wdc->select(chp,1); 240 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 241 0, WDSD_IBM | 0x10); 242 delay(10); /* 400ns delay */ 243 st1 = bus_space_read_1(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_status], 0); 245 } 246 247 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 248 == 0 || 249 (st0 & WDCS_DRDY)) && 250 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 251 == 0 || 252 (st1 & WDCS_DRDY))) 253 break; 254 tsleep(¶ms, PRIBIO, "atadrdy", 1); 255 } 256 s = splbio(); 257 if ((st0 & WDCS_DRDY) == 0) 258 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 259 if ((st1 & WDCS_DRDY) == 0) 260 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 261 splx(s); 262 263 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 264 atac->atac_dev.dv_xname, 265 chp->ch_channel, st0, st1), DEBUG_PROBE); 266 267 /* Wait a bit, some devices are weird just after a reset. */ 268 delay(5000); 269 270 for (i = 0; i < 2; i++) { 271 /* XXX This should be done by other code. */ 272 chp->ch_drive[i].chnl_softc = chp; 273 chp->ch_drive[i].drive = i; 274 275 /* 276 * Init error counter so that an error withing the first xfers 277 * will trigger a downgrade 278 */ 279 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 280 281 /* If controller can't do 16bit flag the drives as 32bit */ 282 if ((atac->atac_cap & 283 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 284 s = splbio(); 285 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 286 splx(s); 287 } 288 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 289 continue; 290 291 /* Shortcut in case we've been shutdown */ 292 if (chp->ch_flags & ATACH_SHUTDOWN) 293 return; 294 295 /* 296 * Issue an identify, to try to detect ghosts. 297 * Note that we can't use interrupts here, because if there 298 * is no devices, we will get a command aborted without 299 * interrupts. 300 */ 301 error = ata_get_params(&chp->ch_drive[i], 302 AT_WAIT | AT_POLL, ¶ms); 303 if (error != CMD_OK) { 304 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 305 306 /* Shortcut in case we've been shutdown */ 307 if (chp->ch_flags & ATACH_SHUTDOWN) 308 return; 309 310 error = ata_get_params(&chp->ch_drive[i], 311 AT_WAIT | AT_POLL, ¶ms); 312 } 313 if (error == CMD_OK) { 314 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 315 s = splbio(); 316 /* XXXJRT ch_ndrive */ 317 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 318 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 319 splx(s); 320 } else { 321 s = splbio(); 322 chp->ch_drive[i].drive_flags &= 323 ~(DRIVE_ATA | DRIVE_ATAPI); 324 splx(s); 325 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 326 atac->atac_dev.dv_xname, 327 chp->ch_channel, i, error), DEBUG_PROBE); 328 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 329 continue; 330 /* 331 * Pre-ATA drive ? 332 * Test registers writability (Error register not 333 * writable, but cyllo is), then try an ATA command. 334 */ 335 if (wdc->select) 336 wdc->select(chp,i); 337 bus_space_write_1(wdr->cmd_iot, 338 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 339 delay(10); /* 400ns delay */ 340 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 341 0, 0x58); 342 bus_space_write_1(wdr->cmd_iot, 343 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 344 if (bus_space_read_1(wdr->cmd_iot, 345 wdr->cmd_iohs[wd_error], 0) == 0x58 || 346 bus_space_read_1(wdr->cmd_iot, 347 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 348 ATADEBUG_PRINT(("%s:%d:%d: register " 349 "writability failed\n", 350 atac->atac_dev.dv_xname, 351 chp->ch_channel, i), DEBUG_PROBE); 352 s = splbio(); 353 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 354 splx(s); 355 continue; 356 } 357 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 358 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 359 atac->atac_dev.dv_xname, 360 chp->ch_channel, i), DEBUG_PROBE); 361 s = splbio(); 362 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 363 splx(s); 364 continue; 365 } 366 bus_space_write_1(wdr->cmd_iot, 367 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 368 delay(10); /* 400ns delay */ 369 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 370 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 371 atac->atac_dev.dv_xname, 372 chp->ch_channel, i), DEBUG_PROBE); 373 s = splbio(); 374 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 375 splx(s); 376 } else { 377 s = splbio(); 378 /* XXXJRT ch_ndrive */ 379 chp->ch_drive[0].drive_flags &= 380 ~(DRIVE_ATA | DRIVE_ATAPI); 381 chp->ch_drive[1].drive_flags &= 382 ~(DRIVE_ATA | DRIVE_ATAPI); 383 splx(s); 384 } 385 } 386 } 387 } 388 389 int 390 wdcprobe(struct ata_channel *chp) 391 { 392 393 return (wdcprobe1(chp, 1)); 394 } 395 396 static int 397 wdcprobe1(struct ata_channel *chp, int poll) 398 { 399 struct atac_softc *atac = chp->ch_atac; 400 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 401 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 402 u_int8_t st0, st1, sc, sn, cl, ch; 403 u_int8_t ret_value = 0x03; 404 u_int8_t drive; 405 int s; 406 407 /* 408 * Sanity check to see if the wdc channel responds at all. 409 */ 410 411 s = splbio(); 412 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 413 414 if (wdc->select) 415 wdc->select(chp,0); 416 417 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 418 WDSD_IBM); 419 delay(10); /* 400ns delay */ 420 st0 = bus_space_read_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_status], 0); 422 423 if (wdc->select) 424 wdc->select(chp,1); 425 426 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 427 WDSD_IBM | 0x10); 428 delay(10); /* 400ns delay */ 429 st1 = bus_space_read_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_status], 0); 431 432 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 433 atac->atac_dev.dv_xname, 434 chp->ch_channel, st0, st1), DEBUG_PROBE); 435 436 if (st0 == 0xff || st0 == WDSD_IBM) 437 ret_value &= ~0x01; 438 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 439 ret_value &= ~0x02; 440 /* Register writability test, drive 0. */ 441 if (ret_value & 0x01) { 442 if (wdc->select) 443 wdc->select(chp,0); 444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 445 0, WDSD_IBM); 446 bus_space_write_1(wdr->cmd_iot, 447 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 448 cl = bus_space_read_1(wdr->cmd_iot, 449 wdr->cmd_iohs[wd_cyl_lo], 0); 450 if (cl != 0x02) { 451 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 452 "got 0x%x != 0x02\n", 453 atac->atac_dev.dv_xname, 454 chp->ch_channel, cl), 455 DEBUG_PROBE); 456 ret_value &= ~0x01; 457 } 458 bus_space_write_1(wdr->cmd_iot, 459 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 460 cl = bus_space_read_1(wdr->cmd_iot, 461 wdr->cmd_iohs[wd_cyl_lo], 0); 462 if (cl != 0x01) { 463 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 464 "got 0x%x != 0x01\n", 465 atac->atac_dev.dv_xname, 466 chp->ch_channel, cl), 467 DEBUG_PROBE); 468 ret_value &= ~0x01; 469 } 470 bus_space_write_1(wdr->cmd_iot, 471 wdr->cmd_iohs[wd_sector], 0, 0x01); 472 cl = bus_space_read_1(wdr->cmd_iot, 473 wdr->cmd_iohs[wd_sector], 0); 474 if (cl != 0x01) { 475 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 476 "got 0x%x != 0x01\n", 477 atac->atac_dev.dv_xname, 478 chp->ch_channel, cl), 479 DEBUG_PROBE); 480 ret_value &= ~0x01; 481 } 482 bus_space_write_1(wdr->cmd_iot, 483 wdr->cmd_iohs[wd_sector], 0, 0x02); 484 cl = bus_space_read_1(wdr->cmd_iot, 485 wdr->cmd_iohs[wd_sector], 0); 486 if (cl != 0x02) { 487 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 488 "got 0x%x != 0x02\n", 489 atac->atac_dev.dv_xname, 490 chp->ch_channel, cl), 491 DEBUG_PROBE); 492 ret_value &= ~0x01; 493 } 494 cl = bus_space_read_1(wdr->cmd_iot, 495 wdr->cmd_iohs[wd_cyl_lo], 0); 496 if (cl != 0x01) { 497 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 498 "got 0x%x != 0x01\n", 499 atac->atac_dev.dv_xname, 500 chp->ch_channel, cl), 501 DEBUG_PROBE); 502 ret_value &= ~0x01; 503 } 504 } 505 /* Register writability test, drive 1. */ 506 if (ret_value & 0x02) { 507 if (wdc->select) 508 wdc->select(chp,1); 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 bus_space_write_1(wdr->cmd_iot, 512 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 513 cl = bus_space_read_1(wdr->cmd_iot, 514 wdr->cmd_iohs[wd_cyl_lo], 0); 515 if (cl != 0x02) { 516 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 517 "got 0x%x != 0x02\n", 518 atac->atac_dev.dv_xname, 519 chp->ch_channel, cl), 520 DEBUG_PROBE); 521 ret_value &= ~0x02; 522 } 523 bus_space_write_1(wdr->cmd_iot, 524 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 525 cl = bus_space_read_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_cyl_lo], 0); 527 if (cl != 0x01) { 528 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 529 "got 0x%x != 0x01\n", 530 atac->atac_dev.dv_xname, 531 chp->ch_channel, cl), 532 DEBUG_PROBE); 533 ret_value &= ~0x02; 534 } 535 bus_space_write_1(wdr->cmd_iot, 536 wdr->cmd_iohs[wd_sector], 0, 0x01); 537 cl = bus_space_read_1(wdr->cmd_iot, 538 wdr->cmd_iohs[wd_sector], 0); 539 if (cl != 0x01) { 540 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 541 "got 0x%x != 0x01\n", 542 atac->atac_dev.dv_xname, 543 chp->ch_channel, cl), 544 DEBUG_PROBE); 545 ret_value &= ~0x02; 546 } 547 bus_space_write_1(wdr->cmd_iot, 548 wdr->cmd_iohs[wd_sector], 0, 0x02); 549 cl = bus_space_read_1(wdr->cmd_iot, 550 wdr->cmd_iohs[wd_sector], 0); 551 if (cl != 0x02) { 552 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 553 "got 0x%x != 0x02\n", 554 atac->atac_dev.dv_xname, 555 chp->ch_channel, cl), 556 DEBUG_PROBE); 557 ret_value &= ~0x02; 558 } 559 cl = bus_space_read_1(wdr->cmd_iot, 560 wdr->cmd_iohs[wd_cyl_lo], 0); 561 if (cl != 0x01) { 562 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 563 "got 0x%x != 0x01\n", 564 atac->atac_dev.dv_xname, 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x02; 568 } 569 } 570 571 if (ret_value == 0) { 572 splx(s); 573 return 0; 574 } 575 } 576 577 578 #if 0 /* XXX this break some ATA or ATAPI devices */ 579 /* 580 * reset bus. Also send an ATAPI_RESET to devices, in case there are 581 * ATAPI device out there which don't react to the bus reset 582 */ 583 if (ret_value & 0x01) { 584 if (wdc->select) 585 wdc->select(chp,0); 586 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 587 0, WDSD_IBM); 588 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 589 ATAPI_SOFT_RESET); 590 } 591 if (ret_value & 0x02) { 592 if (wdc->select) 593 wdc->select(chp,0); 594 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 595 0, WDSD_IBM | 0x10); 596 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 597 ATAPI_SOFT_RESET); 598 } 599 600 delay(5000); 601 #endif 602 603 if (wdc->select) 604 wdc->select(chp,0); 605 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 606 delay(10); /* 400ns delay */ 607 /* assert SRST, wait for reset to complete */ 608 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 609 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 610 DELAY(1000); 611 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 612 WDCTL_IDS | WDCTL_4BIT); 613 DELAY(2000); 614 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 615 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 616 delay(10); /* 400ns delay */ 617 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 618 if (wdc->irqack != NULL) 619 wdc->irqack(chp); 620 splx(s); 621 622 ret_value = __wdcwait_reset(chp, ret_value, poll); 623 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 624 atac->atac_dev.dv_xname, chp->ch_channel, 625 ret_value), DEBUG_PROBE); 626 627 /* if reset failed, there's nothing here */ 628 if (ret_value == 0) 629 return 0; 630 631 /* 632 * Test presence of drives. First test register signatures looking 633 * for ATAPI devices. If it's not an ATAPI and reset said there may 634 * be something here assume it's ATA or OLD. Ghost will be killed 635 * later in attach routine. 636 */ 637 for (drive = 0; drive < 2; drive++) { 638 if ((ret_value & (0x01 << drive)) == 0) 639 continue; 640 if (wdc->select) 641 wdc->select(chp,drive); 642 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 643 WDSD_IBM | (drive << 4)); 644 delay(10); /* 400ns delay */ 645 /* Save registers contents */ 646 sc = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_seccnt], 0); 648 sn = bus_space_read_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0); 650 cl = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_cyl_lo], 0); 652 ch = bus_space_read_1(wdr->cmd_iot, 653 wdr->cmd_iohs[wd_cyl_hi], 0); 654 655 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 656 "cl=0x%x ch=0x%x\n", 657 atac->atac_dev.dv_xname, 658 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 659 /* 660 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 661 * we get wrong values here, so ignore it. 662 */ 663 s = splbio(); 664 if (cl == 0x14 && ch == 0xeb) { 665 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 666 } else { 667 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 668 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 669 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 670 } 671 splx(s); 672 } 673 return (ret_value); 674 } 675 676 void 677 wdcattach(struct ata_channel *chp) 678 { 679 struct atac_softc *atac = chp->ch_atac; 680 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 681 682 /* 683 * Start out assuming 2 drives. This may change as we probe 684 * drives. 685 */ 686 chp->ch_ndrive = 2; 687 688 /* default data transfer methods */ 689 if (wdc->datain_pio == NULL) 690 wdc->datain_pio = wdc_datain_pio; 691 if (wdc->dataout_pio == NULL) 692 wdc->dataout_pio = wdc_dataout_pio; 693 694 /* initialise global data */ 695 if (atac->atac_bustype_ata == NULL) 696 atac->atac_bustype_ata = &wdc_ata_bustype; 697 if (atac->atac_probe == NULL) 698 atac->atac_probe = wdc_drvprobe; 699 #if NATAPIBUS > 0 700 if (atac->atac_atapibus_attach == NULL) 701 atac->atac_atapibus_attach = wdc_atapibus_attach; 702 #endif 703 704 ata_channel_attach(chp); 705 } 706 707 int 708 wdcactivate(struct device *self, enum devact act) 709 { 710 struct atac_softc *atac = (struct atac_softc *) self; 711 int s, i, error = 0; 712 713 s = splbio(); 714 switch (act) { 715 case DVACT_ACTIVATE: 716 error = EOPNOTSUPP; 717 break; 718 719 case DVACT_DEACTIVATE: 720 for (i = 0; i < atac->atac_nchannels; i++) { 721 error = 722 config_deactivate(atac->atac_channels[i]->atabus); 723 if (error) 724 break; 725 } 726 break; 727 } 728 splx(s); 729 return (error); 730 } 731 732 int 733 wdcdetach(struct device *self, int flags) 734 { 735 struct atac_softc *atac = (struct atac_softc *) self; 736 struct ata_channel *chp; 737 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 738 int i, error = 0; 739 740 for (i = 0; i < atac->atac_nchannels; i++) { 741 chp = atac->atac_channels[i]; 742 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 743 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 744 DEBUG_DETACH); 745 error = config_detach(chp->atabus, flags); 746 if (error) 747 break; 748 } 749 if (adapt->adapt_refcnt != 0) { 750 #ifdef DIAGNOSTIC 751 printf("wdcdetach: refcnt should be 0 here??\n"); 752 #endif 753 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 754 } 755 return (error); 756 } 757 758 /* restart an interrupted I/O */ 759 void 760 wdcrestart(void *v) 761 { 762 struct ata_channel *chp = v; 763 int s; 764 765 s = splbio(); 766 atastart(chp); 767 splx(s); 768 } 769 770 771 /* 772 * Interrupt routine for the controller. Acknowledge the interrupt, check for 773 * errors on the current operation, mark it done if necessary, and start the 774 * next request. Also check for a partially done transfer, and continue with 775 * the next chunk if so. 776 */ 777 int 778 wdcintr(void *arg) 779 { 780 struct ata_channel *chp = arg; 781 struct atac_softc *atac = chp->ch_atac; 782 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 783 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 784 struct ata_xfer *xfer; 785 int ret; 786 787 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 788 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 789 DEBUG_INTR); 790 return (0); 791 } 792 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 793 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 794 /* try to clear the pending interrupt anyway */ 795 (void)bus_space_read_1(wdr->cmd_iot, 796 wdr->cmd_iohs[wd_status], 0); 797 return (0); 798 } 799 800 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 801 xfer = chp->ch_queue->active_xfer; 802 #ifdef DIAGNOSTIC 803 if (xfer == NULL) 804 panic("wdcintr: no xfer"); 805 #endif 806 if (chp->ch_flags & ATACH_DMA_WAIT) { 807 wdc->dma_status = 808 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 809 xfer->c_drive, WDC_DMAEND_END); 810 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 811 /* IRQ not for us, not detected by DMA engine */ 812 return 0; 813 } 814 chp->ch_flags &= ~ATACH_DMA_WAIT; 815 } 816 chp->ch_flags &= ~ATACH_IRQ_WAIT; 817 ret = xfer->c_intr(chp, xfer, 1); 818 if (ret == 0) /* irq was not for us, still waiting for irq */ 819 chp->ch_flags |= ATACH_IRQ_WAIT; 820 return (ret); 821 } 822 823 /* Put all disk in RESET state */ 824 void 825 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 826 { 827 struct ata_channel *chp = drvp->chnl_softc; 828 struct atac_softc *atac = chp->ch_atac; 829 830 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 831 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 832 DEBUG_FUNCS); 833 834 ata_reset_channel(chp, flags); 835 } 836 837 void 838 wdc_reset_channel(struct ata_channel *chp, int flags) 839 { 840 TAILQ_HEAD(, ata_xfer) reset_xfer; 841 struct ata_xfer *xfer, *next_xfer; 842 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 843 844 TAILQ_INIT(&reset_xfer); 845 846 chp->ch_flags &= ~ATACH_IRQ_WAIT; 847 848 /* 849 * if the current command if on an ATAPI device, issue a 850 * ATAPI_SOFT_RESET 851 */ 852 xfer = chp->ch_queue->active_xfer; 853 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 854 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 855 if (flags & AT_WAIT) 856 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 857 else 858 delay(1000); 859 } 860 861 /* reset the channel */ 862 if (flags & AT_WAIT) 863 (void) wdcreset(chp, RESET_SLEEP); 864 else 865 (void) wdcreset(chp, RESET_POLL); 866 867 /* 868 * wait a bit after reset; in case the DMA engines needs some time 869 * to recover. 870 */ 871 if (flags & AT_WAIT) 872 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 873 else 874 delay(1000); 875 /* 876 * look for pending xfers. If we have a shared queue, we'll also reset 877 * the other channel if the current xfer is running on it. 878 * Then we'll dequeue only the xfers for this channel. 879 */ 880 if ((flags & AT_RST_NOCMD) == 0) { 881 /* 882 * move all xfers queued for this channel to the reset queue, 883 * and then process the current xfer and then the reset queue. 884 * We have to use a temporary queue because c_kill_xfer() 885 * may requeue commands. 886 */ 887 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 888 xfer != NULL; xfer = next_xfer) { 889 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 890 if (xfer->c_chp != chp) 891 continue; 892 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 893 xfer, c_xferchain); 894 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 895 } 896 xfer = chp->ch_queue->active_xfer; 897 if (xfer) { 898 if (xfer->c_chp != chp) 899 ata_reset_channel(xfer->c_chp, flags); 900 else { 901 callout_stop(&chp->ch_callout); 902 /* 903 * If we're waiting for DMA, stop the 904 * DMA engine 905 */ 906 if (chp->ch_flags & ATACH_DMA_WAIT) { 907 (*wdc->dma_finish)( 908 wdc->dma_arg, 909 chp->ch_channel, 910 xfer->c_drive, 911 WDC_DMAEND_ABRT_QUIET); 912 chp->ch_flags &= ~ATACH_DMA_WAIT; 913 } 914 chp->ch_queue->active_xfer = NULL; 915 if ((flags & AT_RST_EMERG) == 0) 916 xfer->c_kill_xfer( 917 chp, xfer, KILL_RESET); 918 } 919 } 920 921 for (xfer = TAILQ_FIRST(&reset_xfer); 922 xfer != NULL; xfer = next_xfer) { 923 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 924 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 925 if ((flags & AT_RST_EMERG) == 0) 926 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 927 } 928 } 929 } 930 931 static int 932 wdcreset(struct ata_channel *chp, int poll) 933 { 934 struct atac_softc *atac = chp->ch_atac; 935 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 936 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 937 int drv_mask1, drv_mask2; 938 int s = 0; 939 940 if (wdc->select) 941 wdc->select(chp,0); 942 if (poll != RESET_SLEEP) 943 s = splbio(); 944 /* master */ 945 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 946 delay(10); /* 400ns delay */ 947 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 948 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 949 delay(2000); 950 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 951 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 952 WDCTL_4BIT | WDCTL_IDS); 953 delay(10); /* 400ns delay */ 954 if (poll != RESET_SLEEP) { 955 if (wdc->irqack) 956 wdc->irqack(chp); 957 splx(s); 958 } 959 960 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 961 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 962 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 963 (poll == RESET_SLEEP) ? 0 : 1); 964 if (drv_mask2 != drv_mask1) { 965 printf("%s channel %d: reset failed for", 966 atac->atac_dev.dv_xname, chp->ch_channel); 967 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 968 printf(" drive 0"); 969 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 970 printf(" drive 1"); 971 printf("\n"); 972 } 973 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 974 return (drv_mask1 != drv_mask2) ? 1 : 0; 975 } 976 977 static int 978 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 979 { 980 struct atac_softc *atac = chp->ch_atac; 981 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 982 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 983 int timeout, nloop; 984 u_int8_t st0 = 0, st1 = 0; 985 #ifdef ATADEBUG 986 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 987 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 988 #endif 989 990 if (poll) 991 nloop = WDCNDELAY_RST; 992 else 993 nloop = WDC_RESET_WAIT * hz / 1000; 994 /* wait for BSY to deassert */ 995 for (timeout = 0; timeout < nloop; timeout++) { 996 if ((drv_mask & 0x01) != 0) { 997 if (wdc && wdc->select) 998 wdc->select(chp,0); 999 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1000 0, WDSD_IBM); /* master */ 1001 delay(10); 1002 st0 = bus_space_read_1(wdr->cmd_iot, 1003 wdr->cmd_iohs[wd_status], 0); 1004 #ifdef ATADEBUG 1005 sc0 = bus_space_read_1(wdr->cmd_iot, 1006 wdr->cmd_iohs[wd_seccnt], 0); 1007 sn0 = bus_space_read_1(wdr->cmd_iot, 1008 wdr->cmd_iohs[wd_sector], 0); 1009 cl0 = bus_space_read_1(wdr->cmd_iot, 1010 wdr->cmd_iohs[wd_cyl_lo], 0); 1011 ch0 = bus_space_read_1(wdr->cmd_iot, 1012 wdr->cmd_iohs[wd_cyl_hi], 0); 1013 #endif 1014 } 1015 if ((drv_mask & 0x02) != 0) { 1016 if (wdc && wdc->select) 1017 wdc->select(chp,1); 1018 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1019 0, WDSD_IBM | 0x10); /* slave */ 1020 delay(10); 1021 st1 = bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_status], 0); 1023 #ifdef ATADEBUG 1024 sc1 = bus_space_read_1(wdr->cmd_iot, 1025 wdr->cmd_iohs[wd_seccnt], 0); 1026 sn1 = bus_space_read_1(wdr->cmd_iot, 1027 wdr->cmd_iohs[wd_sector], 0); 1028 cl1 = bus_space_read_1(wdr->cmd_iot, 1029 wdr->cmd_iohs[wd_cyl_lo], 0); 1030 ch1 = bus_space_read_1(wdr->cmd_iot, 1031 wdr->cmd_iohs[wd_cyl_hi], 0); 1032 #endif 1033 } 1034 1035 if ((drv_mask & 0x01) == 0) { 1036 /* no master */ 1037 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1038 /* No master, slave is ready, it's done */ 1039 goto end; 1040 } 1041 } else if ((drv_mask & 0x02) == 0) { 1042 /* no slave */ 1043 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1044 /* No slave, master is ready, it's done */ 1045 goto end; 1046 } 1047 } else { 1048 /* Wait for both master and slave to be ready */ 1049 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1050 goto end; 1051 } 1052 } 1053 if (poll) 1054 delay(WDCDELAY); 1055 else 1056 tsleep(&nloop, PRIBIO, "atarst", 1); 1057 } 1058 /* Reset timed out. Maybe it's because drv_mask was not right */ 1059 if (st0 & WDCS_BSY) 1060 drv_mask &= ~0x01; 1061 if (st1 & WDCS_BSY) 1062 drv_mask &= ~0x02; 1063 end: 1064 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1065 "cl=0x%x ch=0x%x\n", 1066 atac->atac_dev.dv_xname, 1067 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1068 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1069 "cl=0x%x ch=0x%x\n", 1070 atac->atac_dev.dv_xname, 1071 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1072 1073 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1074 atac->atac_dev.dv_xname, chp->ch_channel, 1075 st0, st1), DEBUG_PROBE); 1076 1077 return drv_mask; 1078 } 1079 1080 /* 1081 * Wait for a drive to be !BSY, and have mask in its status register. 1082 * return -1 for a timeout after "timeout" ms. 1083 */ 1084 static int 1085 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1086 { 1087 struct atac_softc *atac = chp->ch_atac; 1088 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1089 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1090 u_char status; 1091 int xtime = 0; 1092 1093 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1094 atac->atac_dev.dv_xname, 1095 chp->ch_channel), DEBUG_STATUS); 1096 chp->ch_error = 0; 1097 1098 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1099 1100 for (;;) { 1101 chp->ch_status = status = 1102 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1103 if ((status & (WDCS_BSY | mask)) == bits) 1104 break; 1105 if (++xtime > timeout) { 1106 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1107 "status %x error %x (mask 0x%x bits 0x%x)\n", 1108 xtime, status, 1109 bus_space_read_1(wdr->cmd_iot, 1110 wdr->cmd_iohs[wd_error], 0), mask, bits), 1111 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1112 return(WDCWAIT_TOUT); 1113 } 1114 delay(WDCDELAY); 1115 } 1116 #ifdef ATADEBUG 1117 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1118 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1119 #endif 1120 if (status & WDCS_ERR) 1121 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_error], 0); 1123 #ifdef WDCNDELAY_DEBUG 1124 /* After autoconfig, there should be no long delays. */ 1125 if (!cold && xtime > WDCNDELAY_DEBUG) { 1126 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1127 if (xfer == NULL) 1128 printf("%s channel %d: warning: busy-wait took %dus\n", 1129 atac->atac_dev.dv_xname, chp->ch_channel, 1130 WDCDELAY * xtime); 1131 else 1132 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1133 atac->atac_dev.dv_xname, chp->ch_channel, 1134 xfer->drive, 1135 WDCDELAY * xtime); 1136 } 1137 #endif 1138 return(WDCWAIT_OK); 1139 } 1140 1141 /* 1142 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1143 * thread if possible 1144 */ 1145 int 1146 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1147 { 1148 int error, i, timeout_hz = mstohz(timeout); 1149 1150 if (timeout_hz == 0 || 1151 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1152 error = __wdcwait(chp, mask, bits, timeout); 1153 else { 1154 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1155 if (error != 0) { 1156 if ((chp->ch_flags & ATACH_TH_RUN) || 1157 (flags & AT_WAIT)) { 1158 /* 1159 * we're running in the channel thread 1160 * or some userland thread context 1161 */ 1162 for (i = 0; i < timeout_hz; i++) { 1163 if (__wdcwait(chp, mask, bits, 1164 WDCDELAY_POLL) == 0) { 1165 error = 0; 1166 break; 1167 } 1168 tsleep(&chp, PRIBIO, "atapoll", 1); 1169 } 1170 } else { 1171 /* 1172 * we're probably in interrupt context, 1173 * ask the thread to come back here 1174 */ 1175 #ifdef DIAGNOSTIC 1176 if (chp->ch_queue->queue_freeze > 0) 1177 panic("wdcwait: queue_freeze"); 1178 #endif 1179 chp->ch_queue->queue_freeze++; 1180 wakeup(&chp->ch_thread); 1181 return(WDCWAIT_THR); 1182 } 1183 } 1184 } 1185 return (error); 1186 } 1187 1188 1189 /* 1190 * Busy-wait for DMA to complete 1191 */ 1192 int 1193 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1194 { 1195 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1196 int xtime; 1197 1198 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1199 wdc->dma_status = 1200 (*wdc->dma_finish)(wdc->dma_arg, 1201 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1202 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1203 return 0; 1204 delay(WDCDELAY); 1205 } 1206 /* timeout, force a DMA halt */ 1207 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1208 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1209 return 1; 1210 } 1211 1212 void 1213 wdctimeout(void *arg) 1214 { 1215 struct ata_channel *chp = (struct ata_channel *)arg; 1216 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1217 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1218 int s; 1219 1220 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1221 1222 s = splbio(); 1223 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1224 __wdcerror(chp, "lost interrupt"); 1225 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1226 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1227 xfer->c_bcount, 1228 xfer->c_skip); 1229 if (chp->ch_flags & ATACH_DMA_WAIT) { 1230 wdc->dma_status = 1231 (*wdc->dma_finish)(wdc->dma_arg, 1232 chp->ch_channel, xfer->c_drive, 1233 WDC_DMAEND_ABRT); 1234 chp->ch_flags &= ~ATACH_DMA_WAIT; 1235 } 1236 /* 1237 * Call the interrupt routine. If we just missed an interrupt, 1238 * it will do what's needed. Else, it will take the needed 1239 * action (reset the device). 1240 * Before that we need to reinstall the timeout callback, 1241 * in case it will miss another irq while in this transfer 1242 * We arbitray chose it to be 1s 1243 */ 1244 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1245 xfer->c_flags |= C_TIMEOU; 1246 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1247 xfer->c_intr(chp, xfer, 1); 1248 } else 1249 __wdcerror(chp, "missing untimeout"); 1250 splx(s); 1251 } 1252 1253 int 1254 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1255 { 1256 struct ata_channel *chp = drvp->chnl_softc; 1257 struct atac_softc *atac = chp->ch_atac; 1258 struct ata_xfer *xfer; 1259 int s, ret; 1260 1261 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1262 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1263 DEBUG_FUNCS); 1264 1265 /* set up an xfer and queue. Wait for completion */ 1266 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1267 ATAXF_NOSLEEP); 1268 if (xfer == NULL) { 1269 return ATACMD_TRY_AGAIN; 1270 } 1271 1272 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1273 ata_c->flags |= AT_POLL; 1274 if (ata_c->flags & AT_POLL) 1275 xfer->c_flags |= C_POLL; 1276 if (ata_c->flags & AT_WAIT) 1277 xfer->c_flags |= C_WAIT; 1278 xfer->c_drive = drvp->drive; 1279 xfer->c_databuf = ata_c->data; 1280 xfer->c_bcount = ata_c->bcount; 1281 xfer->c_cmd = ata_c; 1282 xfer->c_start = __wdccommand_start; 1283 xfer->c_intr = __wdccommand_intr; 1284 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1285 1286 s = splbio(); 1287 ata_exec_xfer(chp, xfer); 1288 #ifdef DIAGNOSTIC 1289 if ((ata_c->flags & AT_POLL) != 0 && 1290 (ata_c->flags & AT_DONE) == 0) 1291 panic("wdc_exec_command: polled command not done"); 1292 #endif 1293 if (ata_c->flags & AT_DONE) { 1294 ret = ATACMD_COMPLETE; 1295 } else { 1296 if (ata_c->flags & AT_WAIT) { 1297 while ((ata_c->flags & AT_DONE) == 0) { 1298 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1299 } 1300 ret = ATACMD_COMPLETE; 1301 } else { 1302 ret = ATACMD_QUEUED; 1303 } 1304 } 1305 splx(s); 1306 return ret; 1307 } 1308 1309 static void 1310 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1311 { 1312 struct atac_softc *atac = chp->ch_atac; 1313 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1314 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1315 int drive = xfer->c_drive; 1316 struct ata_command *ata_c = xfer->c_cmd; 1317 1318 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1319 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1320 DEBUG_FUNCS); 1321 1322 if (wdc->select) 1323 wdc->select(chp,drive); 1324 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1325 WDSD_IBM | (drive << 4)); 1326 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1327 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1328 case WDCWAIT_OK: 1329 break; 1330 case WDCWAIT_TOUT: 1331 ata_c->flags |= AT_TIMEOU; 1332 __wdccommand_done(chp, xfer); 1333 return; 1334 case WDCWAIT_THR: 1335 return; 1336 } 1337 if (ata_c->flags & AT_POLL) { 1338 /* polled command, disable interrupts */ 1339 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1340 WDCTL_4BIT | WDCTL_IDS); 1341 } 1342 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1343 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1344 1345 if ((ata_c->flags & AT_POLL) == 0) { 1346 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1347 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1348 wdctimeout, chp); 1349 return; 1350 } 1351 /* 1352 * Polled command. Wait for drive ready or drq. Done in intr(). 1353 * Wait for at last 400ns for status bit to be valid. 1354 */ 1355 delay(10); /* 400ns delay */ 1356 __wdccommand_intr(chp, xfer, 0); 1357 } 1358 1359 static int 1360 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1361 { 1362 struct atac_softc *atac = chp->ch_atac; 1363 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1364 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1365 struct ata_command *ata_c = xfer->c_cmd; 1366 int bcount = ata_c->bcount; 1367 char *data = ata_c->data; 1368 int wflags; 1369 1370 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1371 /* both wait and poll, we can tsleep here */ 1372 wflags = AT_WAIT | AT_POLL; 1373 } else { 1374 wflags = AT_POLL; 1375 } 1376 1377 again: 1378 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1379 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1380 DEBUG_INTR); 1381 /* 1382 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1383 * Reselect again, it doesn't hurt for others commands, and the time 1384 * penalty for the extra regiter write is acceptable, 1385 * wdc_exec_command() isn't called often (mosly for autoconfig) 1386 */ 1387 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1388 WDSD_IBM | (xfer->c_drive << 4)); 1389 if ((ata_c->flags & AT_XFDONE) != 0) { 1390 /* 1391 * We have completed a data xfer. The drive should now be 1392 * in its initial state 1393 */ 1394 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1395 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1396 wflags) == WDCWAIT_TOUT) { 1397 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1398 return 0; /* IRQ was not for us */ 1399 ata_c->flags |= AT_TIMEOU; 1400 } 1401 goto out; 1402 } 1403 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1404 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1405 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1406 return 0; /* IRQ was not for us */ 1407 ata_c->flags |= AT_TIMEOU; 1408 goto out; 1409 } 1410 if (wdc->irqack) 1411 wdc->irqack(chp); 1412 if (ata_c->flags & AT_READ) { 1413 if ((chp->ch_status & WDCS_DRQ) == 0) { 1414 ata_c->flags |= AT_TIMEOU; 1415 goto out; 1416 } 1417 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1418 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1419 0, (u_int32_t*)data, bcount >> 2); 1420 data += bcount & 0xfffffffc; 1421 bcount = bcount & 0x03; 1422 } 1423 if (bcount > 0) 1424 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1425 /* at this point the drive should be in its initial state */ 1426 ata_c->flags |= AT_XFDONE; 1427 /* XXX should read status register here ? */ 1428 } else if (ata_c->flags & AT_WRITE) { 1429 if ((chp->ch_status & WDCS_DRQ) == 0) { 1430 ata_c->flags |= AT_TIMEOU; 1431 goto out; 1432 } 1433 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1434 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1435 0, (u_int32_t*)data, bcount >> 2); 1436 data += bcount & 0xfffffffc; 1437 bcount = bcount & 0x03; 1438 } 1439 if (bcount > 0) 1440 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1441 ata_c->flags |= AT_XFDONE; 1442 if ((ata_c->flags & AT_POLL) == 0) { 1443 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1444 callout_reset(&chp->ch_callout, 1445 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1446 return 1; 1447 } else { 1448 goto again; 1449 } 1450 } 1451 out: 1452 __wdccommand_done(chp, xfer); 1453 return 1; 1454 } 1455 1456 static void 1457 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1458 { 1459 struct atac_softc *atac = chp->ch_atac; 1460 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1461 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1462 struct ata_command *ata_c = xfer->c_cmd; 1463 1464 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1465 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1466 DEBUG_FUNCS); 1467 1468 1469 if (chp->ch_status & WDCS_DWF) 1470 ata_c->flags |= AT_DF; 1471 if (chp->ch_status & WDCS_ERR) { 1472 ata_c->flags |= AT_ERROR; 1473 ata_c->r_error = chp->ch_error; 1474 } 1475 if ((ata_c->flags & AT_READREG) != 0 && 1476 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1477 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1478 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1479 wdr->cmd_iohs[wd_sdh], 0); 1480 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1481 wdr->cmd_iohs[wd_seccnt], 0); 1482 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1483 wdr->cmd_iohs[wd_sector], 0); 1484 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1485 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1486 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1487 wdr->cmd_iohs[wd_cyl_lo], 0); 1488 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1489 wdr->cmd_iohs[wd_error], 0); 1490 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1491 wdr->cmd_iohs[wd_features], 0); 1492 } 1493 callout_stop(&chp->ch_callout); 1494 chp->ch_queue->active_xfer = NULL; 1495 if (ata_c->flags & AT_POLL) { 1496 /* enable interrupts */ 1497 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1498 WDCTL_4BIT); 1499 delay(10); /* some drives need a little delay here */ 1500 } 1501 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1502 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1503 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1504 wakeup(&chp->ch_queue->active_xfer); 1505 } else 1506 __wdccommand_done_end(chp, xfer); 1507 } 1508 1509 static void 1510 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1511 { 1512 struct ata_command *ata_c = xfer->c_cmd; 1513 1514 ata_c->flags |= AT_DONE; 1515 ata_free_xfer(chp, xfer); 1516 if (ata_c->flags & AT_WAIT) 1517 wakeup(ata_c); 1518 else if (ata_c->callback) 1519 ata_c->callback(ata_c->callback_arg); 1520 atastart(chp); 1521 return; 1522 } 1523 1524 static void 1525 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1526 int reason) 1527 { 1528 struct ata_command *ata_c = xfer->c_cmd; 1529 1530 switch (reason) { 1531 case KILL_GONE: 1532 ata_c->flags |= AT_GONE; 1533 break; 1534 case KILL_RESET: 1535 ata_c->flags |= AT_RESET; 1536 break; 1537 default: 1538 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1539 reason); 1540 panic("__wdccommand_kill_xfer"); 1541 } 1542 __wdccommand_done_end(chp, xfer); 1543 } 1544 1545 /* 1546 * Send a command. The drive should be ready. 1547 * Assumes interrupts are blocked. 1548 */ 1549 void 1550 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1551 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1552 u_int8_t features) 1553 { 1554 struct atac_softc *atac = chp->ch_atac; 1555 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1556 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1557 1558 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1559 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1560 chp->ch_channel, drive, command, cylin, head, sector, count, 1561 features), DEBUG_FUNCS); 1562 1563 if (wdc->select) 1564 wdc->select(chp,drive); 1565 1566 /* Select drive, head, and addressing mode. */ 1567 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1568 WDSD_IBM | (drive << 4) | head); 1569 /* Load parameters into the wd_features register. */ 1570 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1571 features); 1572 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1573 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1574 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1575 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1576 0, cylin >> 8); 1577 1578 /* Send command. */ 1579 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1580 return; 1581 } 1582 1583 /* 1584 * Send a 48-bit addressing command. The drive should be ready. 1585 * Assumes interrupts are blocked. 1586 */ 1587 void 1588 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1589 u_int64_t blkno, u_int16_t count) 1590 { 1591 struct atac_softc *atac = chp->ch_atac; 1592 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1593 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1594 1595 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1596 "count=%d\n", atac->atac_dev.dv_xname, 1597 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1598 DEBUG_FUNCS); 1599 1600 if (wdc->select) 1601 wdc->select(chp,drive); 1602 1603 /* Select drive, head, and addressing mode. */ 1604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1605 (drive << 4) | WDSD_LBA); 1606 1607 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1608 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1609 0); 1610 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1611 0, count); 1612 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1613 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1614 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1615 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1616 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1617 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1618 } else { 1619 /* previous */ 1620 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1621 0); 1622 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1623 0, count >> 8); 1624 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1625 0, blkno >> 24); 1626 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1627 0, blkno >> 32); 1628 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1629 0, blkno >> 40); 1630 1631 /* current */ 1632 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1633 0); 1634 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1635 count); 1636 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1637 blkno); 1638 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1639 0, blkno >> 8); 1640 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1641 0, blkno >> 16); 1642 } 1643 1644 /* Send command. */ 1645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1646 return; 1647 } 1648 1649 /* 1650 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1651 * tested by the caller. 1652 */ 1653 void 1654 wdccommandshort(struct ata_channel *chp, int drive, int command) 1655 { 1656 struct atac_softc *atac = chp->ch_atac; 1657 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1658 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1659 1660 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1661 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1662 DEBUG_FUNCS); 1663 1664 if (wdc->select) 1665 wdc->select(chp,drive); 1666 1667 /* Select drive. */ 1668 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1669 WDSD_IBM | (drive << 4)); 1670 1671 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1672 } 1673 1674 static void 1675 __wdcerror(struct ata_channel *chp, const char *msg) 1676 { 1677 struct atac_softc *atac = chp->ch_atac; 1678 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1679 1680 if (xfer == NULL) 1681 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1682 msg); 1683 else 1684 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1685 chp->ch_channel, xfer->c_drive, msg); 1686 } 1687 1688 /* 1689 * the bit bucket 1690 */ 1691 void 1692 wdcbit_bucket(struct ata_channel *chp, int size) 1693 { 1694 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1695 1696 for (; size >= 2; size -= 2) 1697 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1698 if (size) 1699 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1700 } 1701 1702 static void 1703 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1704 { 1705 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1706 1707 if (flags & DRIVE_NOSTREAM) { 1708 if (flags & DRIVE_CAP32) { 1709 bus_space_read_multi_4(wdr->data32iot, 1710 wdr->data32ioh, 0, bf, len >> 2); 1711 bf = (char *)bf + (len & ~3); 1712 len &= 3; 1713 } 1714 if (len) { 1715 bus_space_read_multi_2(wdr->cmd_iot, 1716 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1717 } 1718 } else { 1719 if (flags & DRIVE_CAP32) { 1720 bus_space_read_multi_stream_4(wdr->data32iot, 1721 wdr->data32ioh, 0, bf, len >> 2); 1722 bf = (char *)bf + (len & ~3); 1723 len &= 3; 1724 } 1725 if (len) { 1726 bus_space_read_multi_stream_2(wdr->cmd_iot, 1727 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1728 } 1729 } 1730 } 1731 1732 static void 1733 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1734 { 1735 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1736 1737 if (flags & DRIVE_NOSTREAM) { 1738 if (flags & DRIVE_CAP32) { 1739 bus_space_write_multi_4(wdr->data32iot, 1740 wdr->data32ioh, 0, bf, len >> 2); 1741 bf = (char *)bf + (len & ~3); 1742 len &= 3; 1743 } 1744 if (len) { 1745 bus_space_write_multi_2(wdr->cmd_iot, 1746 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1747 } 1748 } else { 1749 if (flags & DRIVE_CAP32) { 1750 bus_space_write_multi_stream_4(wdr->data32iot, 1751 wdr->data32ioh, 0, bf, len >> 2); 1752 bf = (char *)bf + (len & ~3); 1753 len &= 3; 1754 } 1755 if (len) { 1756 bus_space_write_multi_stream_2(wdr->cmd_iot, 1757 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1758 } 1759 } 1760 } 1761
Indexes created Fri Sep 26 08:10:20 GMT 2025