wdc.c revision 1.225
1 /* $NetBSD: wdc.c,v 1.225 2005/08/06 22:07:24 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.225 2005/08/06 22:07:24 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 /* 123 * timeout when waiting for BSY to deassert when probing. 124 * set to 5s. From the standards this could be up to 31, but we can't 125 * wait that much at boot time, and 5s seems to be enouth. 126 */ 127 #define WDC_PROBE_WAIT 5 128 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, /* wdc_ata_bio */ 137 NULL, /* wdc_reset_drive */ 138 wdc_reset_channel, 139 wdc_exec_command, 140 NULL, /* ata_get_params */ 141 NULL, /* wdc_ata_addref */ 142 NULL, /* wdc_ata_delref */ 143 NULL /* ata_kill_pending */ 144 }; 145 #endif 146 147 /* Flags to wdcreset(). */ 148 #define RESET_POLL 1 149 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 150 151 static int wdcprobe1(struct ata_channel *, int); 152 static int wdcreset(struct ata_channel *, int); 153 static void __wdcerror(struct ata_channel *, const char *); 154 static int __wdcwait_reset(struct ata_channel *, int, int); 155 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 156 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 157 static void __wdccommand_kill_xfer(struct ata_channel *, 158 struct ata_xfer *, int); 159 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 160 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 161 static int __wdcwait(struct ata_channel *, int, int, int); 162 163 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 164 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 165 166 #define DEBUG_INTR 0x01 167 #define DEBUG_XFERS 0x02 168 #define DEBUG_STATUS 0x04 169 #define DEBUG_FUNCS 0x08 170 #define DEBUG_PROBE 0x10 171 #define DEBUG_DETACH 0x20 172 #define DEBUG_DELAY 0x40 173 #ifdef ATADEBUG 174 extern int atadebug_mask; /* init'ed in ata.c */ 175 int wdc_nxfer = 0; 176 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 177 #else 178 #define ATADEBUG_PRINT(args, level) 179 #endif 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct ata_channel *chp) 186 { 187 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 188 189 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 190 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 191 } 192 193 /* 194 * Allocate a wdc_regs array, based on the number of channels. 195 */ 196 void 197 wdc_allocate_regs(struct wdc_softc *wdc) 198 { 199 200 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 201 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 202 } 203 204 /* Test to see controller with at last one attached drive is there. 205 * Returns a bit for each possible drive found (0x01 for drive 0, 206 * 0x02 for drive 1). 207 * Logic: 208 * - If a status register is at 0xff, assume there is no drive here 209 * (ISA has pull-up resistors). Similarly if the status register has 210 * the value we last wrote to the bus (for IDE interfaces without pullups). 211 * If no drive at all -> return. 212 * - reset the controller, wait for it to complete (may take up to 31s !). 213 * If timeout -> return. 214 * - test ATA/ATAPI signatures. If at last one drive found -> return. 215 * - try an ATA command on the master. 216 */ 217 218 static void 219 wdc_drvprobe(struct ata_channel *chp) 220 { 221 struct ataparams params; 222 struct atac_softc *atac = chp->ch_atac; 223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 225 u_int8_t st0 = 0, st1 = 0; 226 int i, error, s; 227 228 if (wdcprobe1(chp, 0) == 0) { 229 /* No drives, abort the attach here. */ 230 return; 231 } 232 233 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 234 for (i = 0; i < mstohz(3000); i++) { 235 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 236 if (wdc->select) 237 wdc->select(chp,0); 238 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 239 0, WDSD_IBM); 240 delay(10); /* 400ns delay */ 241 st0 = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_status], 0); 243 } 244 245 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 246 if (wdc->select) 247 wdc->select(chp,1); 248 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 249 0, WDSD_IBM | 0x10); 250 delay(10); /* 400ns delay */ 251 st1 = bus_space_read_1(wdr->cmd_iot, 252 wdr->cmd_iohs[wd_status], 0); 253 } 254 255 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 256 == 0 || 257 (st0 & WDCS_DRDY)) && 258 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 259 == 0 || 260 (st1 & WDCS_DRDY))) 261 break; 262 tsleep(¶ms, PRIBIO, "atadrdy", 1); 263 } 264 s = splbio(); 265 if ((st0 & WDCS_DRDY) == 0) 266 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 267 if ((st1 & WDCS_DRDY) == 0) 268 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 269 splx(s); 270 271 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 272 atac->atac_dev.dv_xname, 273 chp->ch_channel, st0, st1), DEBUG_PROBE); 274 275 /* Wait a bit, some devices are weird just after a reset. */ 276 delay(5000); 277 278 for (i = 0; i < 2; i++) { 279 /* XXX This should be done by other code. */ 280 chp->ch_drive[i].chnl_softc = chp; 281 chp->ch_drive[i].drive = i; 282 283 /* 284 * Init error counter so that an error withing the first xfers 285 * will trigger a downgrade 286 */ 287 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 288 289 /* If controller can't do 16bit flag the drives as 32bit */ 290 if ((atac->atac_cap & 291 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 292 s = splbio(); 293 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 294 splx(s); 295 } 296 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 297 continue; 298 299 /* Shortcut in case we've been shutdown */ 300 if (chp->ch_flags & ATACH_SHUTDOWN) 301 return; 302 303 /* 304 * Issue an identify, to try to detect ghosts. 305 * Note that we can't use interrupts here, because if there 306 * is no devices, we will get a command aborted without 307 * interrupts. 308 */ 309 error = ata_get_params(&chp->ch_drive[i], 310 AT_WAIT | AT_POLL, ¶ms); 311 if (error != CMD_OK) { 312 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 313 314 /* Shortcut in case we've been shutdown */ 315 if (chp->ch_flags & ATACH_SHUTDOWN) 316 return; 317 318 error = ata_get_params(&chp->ch_drive[i], 319 AT_WAIT | AT_POLL, ¶ms); 320 } 321 if (error == CMD_OK) { 322 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 323 s = splbio(); 324 /* XXXJRT ch_ndrive */ 325 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 326 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 327 splx(s); 328 } else { 329 s = splbio(); 330 chp->ch_drive[i].drive_flags &= 331 ~(DRIVE_ATA | DRIVE_ATAPI); 332 splx(s); 333 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 atac->atac_dev.dv_xname, 335 chp->ch_channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 if (wdc->select) 344 wdc->select(chp,i); 345 bus_space_write_1(wdr->cmd_iot, 346 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 347 delay(10); /* 400ns delay */ 348 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 349 0, 0x58); 350 bus_space_write_1(wdr->cmd_iot, 351 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 352 if (bus_space_read_1(wdr->cmd_iot, 353 wdr->cmd_iohs[wd_error], 0) == 0x58 || 354 bus_space_read_1(wdr->cmd_iot, 355 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 356 ATADEBUG_PRINT(("%s:%d:%d: register " 357 "writability failed\n", 358 atac->atac_dev.dv_xname, 359 chp->ch_channel, i), DEBUG_PROBE); 360 s = splbio(); 361 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 362 splx(s); 363 continue; 364 } 365 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 366 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 367 atac->atac_dev.dv_xname, 368 chp->ch_channel, i), DEBUG_PROBE); 369 s = splbio(); 370 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 371 splx(s); 372 continue; 373 } 374 bus_space_write_1(wdr->cmd_iot, 375 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 376 delay(10); /* 400ns delay */ 377 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 378 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 379 atac->atac_dev.dv_xname, 380 chp->ch_channel, i), DEBUG_PROBE); 381 s = splbio(); 382 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 383 splx(s); 384 } else { 385 s = splbio(); 386 /* XXXJRT ch_ndrive */ 387 chp->ch_drive[0].drive_flags &= 388 ~(DRIVE_ATA | DRIVE_ATAPI); 389 chp->ch_drive[1].drive_flags &= 390 ~(DRIVE_ATA | DRIVE_ATAPI); 391 splx(s); 392 } 393 } 394 } 395 } 396 397 int 398 wdcprobe(struct ata_channel *chp) 399 { 400 401 return (wdcprobe1(chp, 1)); 402 } 403 404 static int 405 wdcprobe1(struct ata_channel *chp, int poll) 406 { 407 struct atac_softc *atac = chp->ch_atac; 408 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 409 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 410 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 411 u_int8_t ret_value = 0x03; 412 u_int8_t drive; 413 int s; 414 int wdc_probe_count = 415 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 416 417 /* 418 * Sanity check to see if the wdc channel responds at all. 419 */ 420 421 s = splbio(); 422 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 423 while (wdc_probe_count-- > 0) { 424 if (wdc->select) 425 wdc->select(chp,0); 426 427 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 428 0, WDSD_IBM); 429 delay(10); /* 400ns delay */ 430 st0 = bus_space_read_1(wdr->cmd_iot, 431 wdr->cmd_iohs[wd_status], 0); 432 433 if (wdc->select) 434 wdc->select(chp,1); 435 436 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 437 0, WDSD_IBM | 0x10); 438 delay(10); /* 400ns delay */ 439 st1 = bus_space_read_1(wdr->cmd_iot, 440 wdr->cmd_iohs[wd_status], 0); 441 if ((st0 & WDCS_BSY) == 0) 442 break; 443 } 444 445 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 446 atac->atac_dev.dv_xname, 447 chp->ch_channel, st0, st1), DEBUG_PROBE); 448 449 if (st0 == 0xff || st0 == WDSD_IBM) 450 ret_value &= ~0x01; 451 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 452 ret_value &= ~0x02; 453 /* Register writability test, drive 0. */ 454 if (ret_value & 0x01) { 455 if (wdc->select) 456 wdc->select(chp,0); 457 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 458 0, WDSD_IBM); 459 bus_space_write_1(wdr->cmd_iot, 460 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 461 cl = bus_space_read_1(wdr->cmd_iot, 462 wdr->cmd_iohs[wd_cyl_lo], 0); 463 if (cl != 0x02) { 464 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 465 "got 0x%x != 0x02\n", 466 atac->atac_dev.dv_xname, 467 chp->ch_channel, cl), 468 DEBUG_PROBE); 469 ret_value &= ~0x01; 470 } 471 bus_space_write_1(wdr->cmd_iot, 472 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 473 cl = bus_space_read_1(wdr->cmd_iot, 474 wdr->cmd_iohs[wd_cyl_lo], 0); 475 if (cl != 0x01) { 476 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 477 "got 0x%x != 0x01\n", 478 atac->atac_dev.dv_xname, 479 chp->ch_channel, cl), 480 DEBUG_PROBE); 481 ret_value &= ~0x01; 482 } 483 bus_space_write_1(wdr->cmd_iot, 484 wdr->cmd_iohs[wd_sector], 0, 0x01); 485 cl = bus_space_read_1(wdr->cmd_iot, 486 wdr->cmd_iohs[wd_sector], 0); 487 if (cl != 0x01) { 488 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 489 "got 0x%x != 0x01\n", 490 atac->atac_dev.dv_xname, 491 chp->ch_channel, cl), 492 DEBUG_PROBE); 493 ret_value &= ~0x01; 494 } 495 bus_space_write_1(wdr->cmd_iot, 496 wdr->cmd_iohs[wd_sector], 0, 0x02); 497 cl = bus_space_read_1(wdr->cmd_iot, 498 wdr->cmd_iohs[wd_sector], 0); 499 if (cl != 0x02) { 500 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 501 "got 0x%x != 0x02\n", 502 atac->atac_dev.dv_xname, 503 chp->ch_channel, cl), 504 DEBUG_PROBE); 505 ret_value &= ~0x01; 506 } 507 cl = bus_space_read_1(wdr->cmd_iot, 508 wdr->cmd_iohs[wd_cyl_lo], 0); 509 if (cl != 0x01) { 510 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 511 "got 0x%x != 0x01\n", 512 atac->atac_dev.dv_xname, 513 chp->ch_channel, cl), 514 DEBUG_PROBE); 515 ret_value &= ~0x01; 516 } 517 } 518 /* Register writability test, drive 1. */ 519 if (ret_value & 0x02) { 520 if (wdc->select) 521 wdc->select(chp,1); 522 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 523 0, WDSD_IBM | 0x10); 524 bus_space_write_1(wdr->cmd_iot, 525 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 526 cl = bus_space_read_1(wdr->cmd_iot, 527 wdr->cmd_iohs[wd_cyl_lo], 0); 528 if (cl != 0x02) { 529 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 530 "got 0x%x != 0x02\n", 531 atac->atac_dev.dv_xname, 532 chp->ch_channel, cl), 533 DEBUG_PROBE); 534 ret_value &= ~0x02; 535 } 536 bus_space_write_1(wdr->cmd_iot, 537 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 538 cl = bus_space_read_1(wdr->cmd_iot, 539 wdr->cmd_iohs[wd_cyl_lo], 0); 540 if (cl != 0x01) { 541 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 542 "got 0x%x != 0x01\n", 543 atac->atac_dev.dv_xname, 544 chp->ch_channel, cl), 545 DEBUG_PROBE); 546 ret_value &= ~0x02; 547 } 548 bus_space_write_1(wdr->cmd_iot, 549 wdr->cmd_iohs[wd_sector], 0, 0x01); 550 cl = bus_space_read_1(wdr->cmd_iot, 551 wdr->cmd_iohs[wd_sector], 0); 552 if (cl != 0x01) { 553 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 554 "got 0x%x != 0x01\n", 555 atac->atac_dev.dv_xname, 556 chp->ch_channel, cl), 557 DEBUG_PROBE); 558 ret_value &= ~0x02; 559 } 560 bus_space_write_1(wdr->cmd_iot, 561 wdr->cmd_iohs[wd_sector], 0, 0x02); 562 cl = bus_space_read_1(wdr->cmd_iot, 563 wdr->cmd_iohs[wd_sector], 0); 564 if (cl != 0x02) { 565 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 566 "got 0x%x != 0x02\n", 567 atac->atac_dev.dv_xname, 568 chp->ch_channel, cl), 569 DEBUG_PROBE); 570 ret_value &= ~0x02; 571 } 572 cl = bus_space_read_1(wdr->cmd_iot, 573 wdr->cmd_iohs[wd_cyl_lo], 0); 574 if (cl != 0x01) { 575 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 576 "got 0x%x != 0x01\n", 577 atac->atac_dev.dv_xname, 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x02; 581 } 582 } 583 584 if (ret_value == 0) { 585 splx(s); 586 return 0; 587 } 588 } 589 590 591 #if 0 /* XXX this break some ATA or ATAPI devices */ 592 /* 593 * reset bus. Also send an ATAPI_RESET to devices, in case there are 594 * ATAPI device out there which don't react to the bus reset 595 */ 596 if (ret_value & 0x01) { 597 if (wdc->select) 598 wdc->select(chp,0); 599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 600 0, WDSD_IBM); 601 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 602 ATAPI_SOFT_RESET); 603 } 604 if (ret_value & 0x02) { 605 if (wdc->select) 606 wdc->select(chp,0); 607 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 608 0, WDSD_IBM | 0x10); 609 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 610 ATAPI_SOFT_RESET); 611 } 612 613 delay(5000); 614 #endif 615 616 wdc->reset(chp, RESET_POLL); 617 DELAY(2000); 618 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 619 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 620 splx(s); 621 622 ret_value = __wdcwait_reset(chp, ret_value, poll); 623 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 624 atac->atac_dev.dv_xname, chp->ch_channel, 625 ret_value), DEBUG_PROBE); 626 627 /* if reset failed, there's nothing here */ 628 if (ret_value == 0) 629 return 0; 630 631 /* 632 * Test presence of drives. First test register signatures looking 633 * for ATAPI devices. If it's not an ATAPI and reset said there may 634 * be something here assume it's ATA or OLD. Ghost will be killed 635 * later in attach routine. 636 */ 637 for (drive = 0; drive < 2; drive++) { 638 if ((ret_value & (0x01 << drive)) == 0) 639 continue; 640 if (wdc->select) 641 wdc->select(chp,drive); 642 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 643 WDSD_IBM | (drive << 4)); 644 delay(10); /* 400ns delay */ 645 /* Save registers contents */ 646 sc = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_seccnt], 0); 648 sn = bus_space_read_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0); 650 cl = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_cyl_lo], 0); 652 ch = bus_space_read_1(wdr->cmd_iot, 653 wdr->cmd_iohs[wd_cyl_hi], 0); 654 655 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 656 "cl=0x%x ch=0x%x\n", 657 atac->atac_dev.dv_xname, 658 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 659 /* 660 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 661 * we get wrong values here, so ignore it. 662 */ 663 s = splbio(); 664 if (cl == 0x14 && ch == 0xeb) { 665 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 666 } else { 667 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 668 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 669 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 670 } 671 splx(s); 672 } 673 return (ret_value); 674 } 675 676 void 677 wdcattach(struct ata_channel *chp) 678 { 679 struct atac_softc *atac = chp->ch_atac; 680 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 681 682 /* 683 * Start out assuming 2 drives. This may change as we probe 684 * drives. 685 */ 686 chp->ch_ndrive = 2; 687 688 /* default data transfer methods */ 689 if (wdc->datain_pio == NULL) 690 wdc->datain_pio = wdc_datain_pio; 691 if (wdc->dataout_pio == NULL) 692 wdc->dataout_pio = wdc_dataout_pio; 693 /* default reset method */ 694 if (wdc->reset == NULL) 695 wdc->reset = wdc_do_reset; 696 697 /* initialise global data */ 698 if (atac->atac_bustype_ata == NULL) 699 atac->atac_bustype_ata = &wdc_ata_bustype; 700 if (atac->atac_probe == NULL) 701 atac->atac_probe = wdc_drvprobe; 702 #if NATAPIBUS > 0 703 if (atac->atac_atapibus_attach == NULL) 704 atac->atac_atapibus_attach = wdc_atapibus_attach; 705 #endif 706 707 ata_channel_attach(chp); 708 } 709 710 int 711 wdcactivate(struct device *self, enum devact act) 712 { 713 struct atac_softc *atac = (struct atac_softc *) self; 714 int s, i, error = 0; 715 716 s = splbio(); 717 switch (act) { 718 case DVACT_ACTIVATE: 719 error = EOPNOTSUPP; 720 break; 721 722 case DVACT_DEACTIVATE: 723 for (i = 0; i < atac->atac_nchannels; i++) { 724 error = 725 config_deactivate(atac->atac_channels[i]->atabus); 726 if (error) 727 break; 728 } 729 break; 730 } 731 splx(s); 732 return (error); 733 } 734 735 int 736 wdcdetach(struct device *self, int flags) 737 { 738 struct atac_softc *atac = (struct atac_softc *) self; 739 struct ata_channel *chp; 740 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 741 int i, error = 0; 742 743 for (i = 0; i < atac->atac_nchannels; i++) { 744 chp = atac->atac_channels[i]; 745 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 746 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 747 DEBUG_DETACH); 748 error = config_detach(chp->atabus, flags); 749 if (error) 750 break; 751 } 752 if (adapt->adapt_refcnt != 0) { 753 #ifdef DIAGNOSTIC 754 printf("wdcdetach: refcnt should be 0 here??\n"); 755 #endif 756 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 757 } 758 return (error); 759 } 760 761 /* restart an interrupted I/O */ 762 void 763 wdcrestart(void *v) 764 { 765 struct ata_channel *chp = v; 766 int s; 767 768 s = splbio(); 769 atastart(chp); 770 splx(s); 771 } 772 773 774 /* 775 * Interrupt routine for the controller. Acknowledge the interrupt, check for 776 * errors on the current operation, mark it done if necessary, and start the 777 * next request. Also check for a partially done transfer, and continue with 778 * the next chunk if so. 779 */ 780 int 781 wdcintr(void *arg) 782 { 783 struct ata_channel *chp = arg; 784 struct atac_softc *atac = chp->ch_atac; 785 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 786 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 787 struct ata_xfer *xfer; 788 int ret; 789 790 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 791 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 792 DEBUG_INTR); 793 return (0); 794 } 795 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 796 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 797 /* try to clear the pending interrupt anyway */ 798 (void)bus_space_read_1(wdr->cmd_iot, 799 wdr->cmd_iohs[wd_status], 0); 800 return (0); 801 } 802 803 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 804 xfer = chp->ch_queue->active_xfer; 805 #ifdef DIAGNOSTIC 806 if (xfer == NULL) 807 panic("wdcintr: no xfer"); 808 #endif 809 if (chp->ch_flags & ATACH_DMA_WAIT) { 810 wdc->dma_status = 811 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 812 xfer->c_drive, WDC_DMAEND_END); 813 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 814 /* IRQ not for us, not detected by DMA engine */ 815 return 0; 816 } 817 chp->ch_flags &= ~ATACH_DMA_WAIT; 818 } 819 chp->ch_flags &= ~ATACH_IRQ_WAIT; 820 ret = xfer->c_intr(chp, xfer, 1); 821 if (ret == 0) /* irq was not for us, still waiting for irq */ 822 chp->ch_flags |= ATACH_IRQ_WAIT; 823 return (ret); 824 } 825 826 /* Put all disk in RESET state */ 827 void 828 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 829 { 830 struct ata_channel *chp = drvp->chnl_softc; 831 struct atac_softc *atac = chp->ch_atac; 832 833 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 834 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 835 DEBUG_FUNCS); 836 837 ata_reset_channel(chp, flags); 838 } 839 840 void 841 wdc_reset_channel(struct ata_channel *chp, int flags) 842 { 843 TAILQ_HEAD(, ata_xfer) reset_xfer; 844 struct ata_xfer *xfer, *next_xfer; 845 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 846 847 TAILQ_INIT(&reset_xfer); 848 849 chp->ch_flags &= ~ATACH_IRQ_WAIT; 850 851 /* 852 * if the current command if on an ATAPI device, issue a 853 * ATAPI_SOFT_RESET 854 */ 855 xfer = chp->ch_queue->active_xfer; 856 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 857 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 858 if (flags & AT_WAIT) 859 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 860 else 861 delay(1000); 862 } 863 864 /* reset the channel */ 865 if (flags & AT_WAIT) 866 (void) wdcreset(chp, RESET_SLEEP); 867 else 868 (void) wdcreset(chp, RESET_POLL); 869 870 /* 871 * wait a bit after reset; in case the DMA engines needs some time 872 * to recover. 873 */ 874 if (flags & AT_WAIT) 875 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 876 else 877 delay(1000); 878 /* 879 * look for pending xfers. If we have a shared queue, we'll also reset 880 * the other channel if the current xfer is running on it. 881 * Then we'll dequeue only the xfers for this channel. 882 */ 883 if ((flags & AT_RST_NOCMD) == 0) { 884 /* 885 * move all xfers queued for this channel to the reset queue, 886 * and then process the current xfer and then the reset queue. 887 * We have to use a temporary queue because c_kill_xfer() 888 * may requeue commands. 889 */ 890 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 891 xfer != NULL; xfer = next_xfer) { 892 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 893 if (xfer->c_chp != chp) 894 continue; 895 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 896 xfer, c_xferchain); 897 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 898 } 899 xfer = chp->ch_queue->active_xfer; 900 if (xfer) { 901 if (xfer->c_chp != chp) 902 ata_reset_channel(xfer->c_chp, flags); 903 else { 904 callout_stop(&chp->ch_callout); 905 /* 906 * If we're waiting for DMA, stop the 907 * DMA engine 908 */ 909 if (chp->ch_flags & ATACH_DMA_WAIT) { 910 (*wdc->dma_finish)( 911 wdc->dma_arg, 912 chp->ch_channel, 913 xfer->c_drive, 914 WDC_DMAEND_ABRT_QUIET); 915 chp->ch_flags &= ~ATACH_DMA_WAIT; 916 } 917 chp->ch_queue->active_xfer = NULL; 918 if ((flags & AT_RST_EMERG) == 0) 919 xfer->c_kill_xfer( 920 chp, xfer, KILL_RESET); 921 } 922 } 923 924 for (xfer = TAILQ_FIRST(&reset_xfer); 925 xfer != NULL; xfer = next_xfer) { 926 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 927 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 928 if ((flags & AT_RST_EMERG) == 0) 929 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 930 } 931 } 932 } 933 934 static int 935 wdcreset(struct ata_channel *chp, int poll) 936 { 937 struct atac_softc *atac = chp->ch_atac; 938 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 939 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 940 int drv_mask1, drv_mask2; 941 942 wdc->reset(chp, poll); 943 944 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 945 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 946 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 947 (poll == RESET_SLEEP) ? 0 : 1); 948 if (drv_mask2 != drv_mask1) { 949 printf("%s channel %d: reset failed for", 950 atac->atac_dev.dv_xname, chp->ch_channel); 951 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 952 printf(" drive 0"); 953 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 954 printf(" drive 1"); 955 printf("\n"); 956 } 957 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 958 return (drv_mask1 != drv_mask2) ? 1 : 0; 959 } 960 961 void 962 wdc_do_reset(struct ata_channel *chp, int poll) 963 { 964 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 965 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 966 int s = 0; 967 968 if (poll != RESET_SLEEP) 969 s = splbio(); 970 if (wdc->select) 971 wdc->select(chp,0); 972 /* master */ 973 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 974 delay(10); /* 400ns delay */ 975 /* assert SRST, wait for reset to complete */ 976 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 977 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 978 delay(2000); 979 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 980 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 981 WDCTL_4BIT | WDCTL_IDS); 982 delay(10); /* 400ns delay */ 983 if (poll != RESET_SLEEP) { 984 if (wdc->irqack) 985 wdc->irqack(chp); 986 splx(s); 987 } 988 } 989 990 static int 991 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 992 { 993 struct atac_softc *atac = chp->ch_atac; 994 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 995 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 996 int timeout, nloop; 997 u_int8_t st0 = 0, st1 = 0; 998 #ifdef ATADEBUG 999 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1000 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1001 #endif 1002 1003 if (poll) 1004 nloop = WDCNDELAY_RST; 1005 else 1006 nloop = WDC_RESET_WAIT * hz / 1000; 1007 /* wait for BSY to deassert */ 1008 for (timeout = 0; timeout < nloop; timeout++) { 1009 if ((drv_mask & 0x01) != 0) { 1010 if (wdc && wdc->select) 1011 wdc->select(chp,0); 1012 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1013 0, WDSD_IBM); /* master */ 1014 delay(10); 1015 st0 = bus_space_read_1(wdr->cmd_iot, 1016 wdr->cmd_iohs[wd_status], 0); 1017 #ifdef ATADEBUG 1018 sc0 = bus_space_read_1(wdr->cmd_iot, 1019 wdr->cmd_iohs[wd_seccnt], 0); 1020 sn0 = bus_space_read_1(wdr->cmd_iot, 1021 wdr->cmd_iohs[wd_sector], 0); 1022 cl0 = bus_space_read_1(wdr->cmd_iot, 1023 wdr->cmd_iohs[wd_cyl_lo], 0); 1024 ch0 = bus_space_read_1(wdr->cmd_iot, 1025 wdr->cmd_iohs[wd_cyl_hi], 0); 1026 #endif 1027 } 1028 if ((drv_mask & 0x02) != 0) { 1029 if (wdc && wdc->select) 1030 wdc->select(chp,1); 1031 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1032 0, WDSD_IBM | 0x10); /* slave */ 1033 delay(10); 1034 st1 = bus_space_read_1(wdr->cmd_iot, 1035 wdr->cmd_iohs[wd_status], 0); 1036 #ifdef ATADEBUG 1037 sc1 = bus_space_read_1(wdr->cmd_iot, 1038 wdr->cmd_iohs[wd_seccnt], 0); 1039 sn1 = bus_space_read_1(wdr->cmd_iot, 1040 wdr->cmd_iohs[wd_sector], 0); 1041 cl1 = bus_space_read_1(wdr->cmd_iot, 1042 wdr->cmd_iohs[wd_cyl_lo], 0); 1043 ch1 = bus_space_read_1(wdr->cmd_iot, 1044 wdr->cmd_iohs[wd_cyl_hi], 0); 1045 #endif 1046 } 1047 1048 if ((drv_mask & 0x01) == 0) { 1049 /* no master */ 1050 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1051 /* No master, slave is ready, it's done */ 1052 goto end; 1053 } 1054 } else if ((drv_mask & 0x02) == 0) { 1055 /* no slave */ 1056 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1057 /* No slave, master is ready, it's done */ 1058 goto end; 1059 } 1060 } else { 1061 /* Wait for both master and slave to be ready */ 1062 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1063 goto end; 1064 } 1065 } 1066 if (poll) 1067 delay(WDCDELAY); 1068 else 1069 tsleep(&nloop, PRIBIO, "atarst", 1); 1070 } 1071 /* Reset timed out. Maybe it's because drv_mask was not right */ 1072 if (st0 & WDCS_BSY) 1073 drv_mask &= ~0x01; 1074 if (st1 & WDCS_BSY) 1075 drv_mask &= ~0x02; 1076 end: 1077 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1078 "cl=0x%x ch=0x%x\n", 1079 atac->atac_dev.dv_xname, 1080 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1081 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1082 "cl=0x%x ch=0x%x\n", 1083 atac->atac_dev.dv_xname, 1084 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1085 1086 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1087 atac->atac_dev.dv_xname, chp->ch_channel, 1088 st0, st1), DEBUG_PROBE); 1089 1090 return drv_mask; 1091 } 1092 1093 /* 1094 * Wait for a drive to be !BSY, and have mask in its status register. 1095 * return -1 for a timeout after "timeout" ms. 1096 */ 1097 static int 1098 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1099 { 1100 struct atac_softc *atac = chp->ch_atac; 1101 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1102 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1103 u_char status; 1104 int xtime = 0; 1105 1106 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1107 atac->atac_dev.dv_xname, 1108 chp->ch_channel), DEBUG_STATUS); 1109 chp->ch_error = 0; 1110 1111 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1112 1113 for (;;) { 1114 chp->ch_status = status = 1115 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1116 if ((status & (WDCS_BSY | mask)) == bits) 1117 break; 1118 if (++xtime > timeout) { 1119 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1120 "status %x error %x (mask 0x%x bits 0x%x)\n", 1121 xtime, status, 1122 bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_error], 0), mask, bits), 1124 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1125 return(WDCWAIT_TOUT); 1126 } 1127 delay(WDCDELAY); 1128 } 1129 #ifdef ATADEBUG 1130 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1131 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1132 #endif 1133 if (status & WDCS_ERR) 1134 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_error], 0); 1136 #ifdef WDCNDELAY_DEBUG 1137 /* After autoconfig, there should be no long delays. */ 1138 if (!cold && xtime > WDCNDELAY_DEBUG) { 1139 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1140 if (xfer == NULL) 1141 printf("%s channel %d: warning: busy-wait took %dus\n", 1142 atac->atac_dev.dv_xname, chp->ch_channel, 1143 WDCDELAY * xtime); 1144 else 1145 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1146 atac->atac_dev.dv_xname, chp->ch_channel, 1147 xfer->drive, 1148 WDCDELAY * xtime); 1149 } 1150 #endif 1151 return(WDCWAIT_OK); 1152 } 1153 1154 /* 1155 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1156 * thread if possible 1157 */ 1158 int 1159 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1160 { 1161 int error, i, timeout_hz = mstohz(timeout); 1162 1163 if (timeout_hz == 0 || 1164 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1165 error = __wdcwait(chp, mask, bits, timeout); 1166 else { 1167 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1168 if (error != 0) { 1169 if ((chp->ch_flags & ATACH_TH_RUN) || 1170 (flags & AT_WAIT)) { 1171 /* 1172 * we're running in the channel thread 1173 * or some userland thread context 1174 */ 1175 for (i = 0; i < timeout_hz; i++) { 1176 if (__wdcwait(chp, mask, bits, 1177 WDCDELAY_POLL) == 0) { 1178 error = 0; 1179 break; 1180 } 1181 tsleep(&chp, PRIBIO, "atapoll", 1); 1182 } 1183 } else { 1184 /* 1185 * we're probably in interrupt context, 1186 * ask the thread to come back here 1187 */ 1188 #ifdef DIAGNOSTIC 1189 if (chp->ch_queue->queue_freeze > 0) 1190 panic("wdcwait: queue_freeze"); 1191 #endif 1192 chp->ch_queue->queue_freeze++; 1193 wakeup(&chp->ch_thread); 1194 return(WDCWAIT_THR); 1195 } 1196 } 1197 } 1198 return (error); 1199 } 1200 1201 1202 /* 1203 * Busy-wait for DMA to complete 1204 */ 1205 int 1206 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1207 { 1208 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1209 int xtime; 1210 1211 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1212 wdc->dma_status = 1213 (*wdc->dma_finish)(wdc->dma_arg, 1214 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1215 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1216 return 0; 1217 delay(WDCDELAY); 1218 } 1219 /* timeout, force a DMA halt */ 1220 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1221 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1222 return 1; 1223 } 1224 1225 void 1226 wdctimeout(void *arg) 1227 { 1228 struct ata_channel *chp = (struct ata_channel *)arg; 1229 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1230 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1231 int s; 1232 1233 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1234 1235 s = splbio(); 1236 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1237 __wdcerror(chp, "lost interrupt"); 1238 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1239 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1240 xfer->c_bcount, 1241 xfer->c_skip); 1242 if (chp->ch_flags & ATACH_DMA_WAIT) { 1243 wdc->dma_status = 1244 (*wdc->dma_finish)(wdc->dma_arg, 1245 chp->ch_channel, xfer->c_drive, 1246 WDC_DMAEND_ABRT); 1247 chp->ch_flags &= ~ATACH_DMA_WAIT; 1248 } 1249 /* 1250 * Call the interrupt routine. If we just missed an interrupt, 1251 * it will do what's needed. Else, it will take the needed 1252 * action (reset the device). 1253 * Before that we need to reinstall the timeout callback, 1254 * in case it will miss another irq while in this transfer 1255 * We arbitray chose it to be 1s 1256 */ 1257 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1258 xfer->c_flags |= C_TIMEOU; 1259 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1260 xfer->c_intr(chp, xfer, 1); 1261 } else 1262 __wdcerror(chp, "missing untimeout"); 1263 splx(s); 1264 } 1265 1266 int 1267 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1268 { 1269 struct ata_channel *chp = drvp->chnl_softc; 1270 struct atac_softc *atac = chp->ch_atac; 1271 struct ata_xfer *xfer; 1272 int s, ret; 1273 1274 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1275 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1276 DEBUG_FUNCS); 1277 1278 /* set up an xfer and queue. Wait for completion */ 1279 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1280 ATAXF_NOSLEEP); 1281 if (xfer == NULL) { 1282 return ATACMD_TRY_AGAIN; 1283 } 1284 1285 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1286 ata_c->flags |= AT_POLL; 1287 if (ata_c->flags & AT_POLL) 1288 xfer->c_flags |= C_POLL; 1289 if (ata_c->flags & AT_WAIT) 1290 xfer->c_flags |= C_WAIT; 1291 xfer->c_drive = drvp->drive; 1292 xfer->c_databuf = ata_c->data; 1293 xfer->c_bcount = ata_c->bcount; 1294 xfer->c_cmd = ata_c; 1295 xfer->c_start = __wdccommand_start; 1296 xfer->c_intr = __wdccommand_intr; 1297 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1298 1299 s = splbio(); 1300 ata_exec_xfer(chp, xfer); 1301 #ifdef DIAGNOSTIC 1302 if ((ata_c->flags & AT_POLL) != 0 && 1303 (ata_c->flags & AT_DONE) == 0) 1304 panic("wdc_exec_command: polled command not done"); 1305 #endif 1306 if (ata_c->flags & AT_DONE) { 1307 ret = ATACMD_COMPLETE; 1308 } else { 1309 if (ata_c->flags & AT_WAIT) { 1310 while ((ata_c->flags & AT_DONE) == 0) { 1311 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1312 } 1313 ret = ATACMD_COMPLETE; 1314 } else { 1315 ret = ATACMD_QUEUED; 1316 } 1317 } 1318 splx(s); 1319 return ret; 1320 } 1321 1322 static void 1323 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1324 { 1325 struct atac_softc *atac = chp->ch_atac; 1326 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1327 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1328 int drive = xfer->c_drive; 1329 struct ata_command *ata_c = xfer->c_cmd; 1330 1331 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1332 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1333 DEBUG_FUNCS); 1334 1335 if (wdc->select) 1336 wdc->select(chp,drive); 1337 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1338 WDSD_IBM | (drive << 4)); 1339 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1340 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1341 case WDCWAIT_OK: 1342 break; 1343 case WDCWAIT_TOUT: 1344 ata_c->flags |= AT_TIMEOU; 1345 __wdccommand_done(chp, xfer); 1346 return; 1347 case WDCWAIT_THR: 1348 return; 1349 } 1350 if (ata_c->flags & AT_POLL) { 1351 /* polled command, disable interrupts */ 1352 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1353 WDCTL_4BIT | WDCTL_IDS); 1354 } 1355 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1356 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1357 1358 if ((ata_c->flags & AT_POLL) == 0) { 1359 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1360 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1361 wdctimeout, chp); 1362 return; 1363 } 1364 /* 1365 * Polled command. Wait for drive ready or drq. Done in intr(). 1366 * Wait for at last 400ns for status bit to be valid. 1367 */ 1368 delay(10); /* 400ns delay */ 1369 __wdccommand_intr(chp, xfer, 0); 1370 } 1371 1372 static int 1373 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1374 { 1375 struct atac_softc *atac = chp->ch_atac; 1376 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1377 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1378 struct ata_command *ata_c = xfer->c_cmd; 1379 int bcount = ata_c->bcount; 1380 char *data = ata_c->data; 1381 int wflags; 1382 1383 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1384 /* both wait and poll, we can tsleep here */ 1385 wflags = AT_WAIT | AT_POLL; 1386 } else { 1387 wflags = AT_POLL; 1388 } 1389 1390 again: 1391 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1392 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1393 DEBUG_INTR); 1394 /* 1395 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1396 * Reselect again, it doesn't hurt for others commands, and the time 1397 * penalty for the extra regiter write is acceptable, 1398 * wdc_exec_command() isn't called often (mosly for autoconfig) 1399 */ 1400 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1401 WDSD_IBM | (xfer->c_drive << 4)); 1402 if ((ata_c->flags & AT_XFDONE) != 0) { 1403 /* 1404 * We have completed a data xfer. The drive should now be 1405 * in its initial state 1406 */ 1407 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1408 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1409 wflags) == WDCWAIT_TOUT) { 1410 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1411 return 0; /* IRQ was not for us */ 1412 ata_c->flags |= AT_TIMEOU; 1413 } 1414 goto out; 1415 } 1416 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1417 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1418 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1419 return 0; /* IRQ was not for us */ 1420 ata_c->flags |= AT_TIMEOU; 1421 goto out; 1422 } 1423 if (wdc->irqack) 1424 wdc->irqack(chp); 1425 if (ata_c->flags & AT_READ) { 1426 if ((chp->ch_status & WDCS_DRQ) == 0) { 1427 ata_c->flags |= AT_TIMEOU; 1428 goto out; 1429 } 1430 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1431 bus_space_read_multi_4(wdr->data32iot, wdr->data32ioh, 1432 0, (u_int32_t*)data, bcount >> 2); 1433 data += bcount & 0xfffffffc; 1434 bcount = bcount & 0x03; 1435 } 1436 if (bcount > 0) 1437 wdc->datain_pio(chp, DRIVE_NOSTREAM, data, bcount); 1438 /* at this point the drive should be in its initial state */ 1439 ata_c->flags |= AT_XFDONE; 1440 /* XXX should read status register here ? */ 1441 } else if (ata_c->flags & AT_WRITE) { 1442 if ((chp->ch_status & WDCS_DRQ) == 0) { 1443 ata_c->flags |= AT_TIMEOU; 1444 goto out; 1445 } 1446 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1447 bus_space_write_multi_4(wdr->data32iot, wdr->data32ioh, 1448 0, (u_int32_t*)data, bcount >> 2); 1449 data += bcount & 0xfffffffc; 1450 bcount = bcount & 0x03; 1451 } 1452 if (bcount > 0) 1453 wdc->dataout_pio(chp, DRIVE_NOSTREAM, data, bcount); 1454 ata_c->flags |= AT_XFDONE; 1455 if ((ata_c->flags & AT_POLL) == 0) { 1456 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1457 callout_reset(&chp->ch_callout, 1458 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1459 return 1; 1460 } else { 1461 goto again; 1462 } 1463 } 1464 out: 1465 __wdccommand_done(chp, xfer); 1466 return 1; 1467 } 1468 1469 static void 1470 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1471 { 1472 struct atac_softc *atac = chp->ch_atac; 1473 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1474 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1475 struct ata_command *ata_c = xfer->c_cmd; 1476 1477 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1478 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1479 DEBUG_FUNCS); 1480 1481 1482 if (chp->ch_status & WDCS_DWF) 1483 ata_c->flags |= AT_DF; 1484 if (chp->ch_status & WDCS_ERR) { 1485 ata_c->flags |= AT_ERROR; 1486 ata_c->r_error = chp->ch_error; 1487 } 1488 if ((ata_c->flags & AT_READREG) != 0 && 1489 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1490 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1491 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1492 wdr->cmd_iohs[wd_sdh], 0); 1493 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1494 wdr->cmd_iohs[wd_seccnt], 0); 1495 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1496 wdr->cmd_iohs[wd_sector], 0); 1497 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1498 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1499 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1500 wdr->cmd_iohs[wd_cyl_lo], 0); 1501 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1502 wdr->cmd_iohs[wd_error], 0); 1503 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1504 wdr->cmd_iohs[wd_features], 0); 1505 } 1506 callout_stop(&chp->ch_callout); 1507 chp->ch_queue->active_xfer = NULL; 1508 if (ata_c->flags & AT_POLL) { 1509 /* enable interrupts */ 1510 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1511 WDCTL_4BIT); 1512 delay(10); /* some drives need a little delay here */ 1513 } 1514 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1515 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1516 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1517 wakeup(&chp->ch_queue->active_xfer); 1518 } else 1519 __wdccommand_done_end(chp, xfer); 1520 } 1521 1522 static void 1523 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1524 { 1525 struct ata_command *ata_c = xfer->c_cmd; 1526 1527 ata_c->flags |= AT_DONE; 1528 ata_free_xfer(chp, xfer); 1529 if (ata_c->flags & AT_WAIT) 1530 wakeup(ata_c); 1531 else if (ata_c->callback) 1532 ata_c->callback(ata_c->callback_arg); 1533 atastart(chp); 1534 return; 1535 } 1536 1537 static void 1538 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1539 int reason) 1540 { 1541 struct ata_command *ata_c = xfer->c_cmd; 1542 1543 switch (reason) { 1544 case KILL_GONE: 1545 ata_c->flags |= AT_GONE; 1546 break; 1547 case KILL_RESET: 1548 ata_c->flags |= AT_RESET; 1549 break; 1550 default: 1551 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1552 reason); 1553 panic("__wdccommand_kill_xfer"); 1554 } 1555 __wdccommand_done_end(chp, xfer); 1556 } 1557 1558 /* 1559 * Send a command. The drive should be ready. 1560 * Assumes interrupts are blocked. 1561 */ 1562 void 1563 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1564 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1565 u_int8_t features) 1566 { 1567 struct atac_softc *atac = chp->ch_atac; 1568 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1569 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1570 1571 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1572 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1573 chp->ch_channel, drive, command, cylin, head, sector, count, 1574 features), DEBUG_FUNCS); 1575 1576 if (wdc->select) 1577 wdc->select(chp,drive); 1578 1579 /* Select drive, head, and addressing mode. */ 1580 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1581 WDSD_IBM | (drive << 4) | head); 1582 /* Load parameters into the wd_features register. */ 1583 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1584 features); 1585 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1586 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1587 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1588 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1589 0, cylin >> 8); 1590 1591 /* Send command. */ 1592 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1593 return; 1594 } 1595 1596 /* 1597 * Send a 48-bit addressing command. The drive should be ready. 1598 * Assumes interrupts are blocked. 1599 */ 1600 void 1601 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1602 u_int64_t blkno, u_int16_t count) 1603 { 1604 struct atac_softc *atac = chp->ch_atac; 1605 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1606 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1607 1608 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1609 "count=%d\n", atac->atac_dev.dv_xname, 1610 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1611 DEBUG_FUNCS); 1612 1613 if (wdc->select) 1614 wdc->select(chp,drive); 1615 1616 /* Select drive, head, and addressing mode. */ 1617 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1618 (drive << 4) | WDSD_LBA); 1619 1620 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1621 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1622 0); 1623 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1624 0, count); 1625 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1626 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1627 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1628 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1629 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1630 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1631 } else { 1632 /* previous */ 1633 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1634 0); 1635 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1636 0, count >> 8); 1637 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1638 0, blkno >> 24); 1639 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1640 0, blkno >> 32); 1641 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1642 0, blkno >> 40); 1643 1644 /* current */ 1645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1646 0); 1647 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1648 count); 1649 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1650 blkno); 1651 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1652 0, blkno >> 8); 1653 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1654 0, blkno >> 16); 1655 } 1656 1657 /* Send command. */ 1658 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1659 return; 1660 } 1661 1662 /* 1663 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1664 * tested by the caller. 1665 */ 1666 void 1667 wdccommandshort(struct ata_channel *chp, int drive, int command) 1668 { 1669 struct atac_softc *atac = chp->ch_atac; 1670 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1671 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1672 1673 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1674 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1675 DEBUG_FUNCS); 1676 1677 if (wdc->select) 1678 wdc->select(chp,drive); 1679 1680 /* Select drive. */ 1681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1682 WDSD_IBM | (drive << 4)); 1683 1684 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1685 } 1686 1687 static void 1688 __wdcerror(struct ata_channel *chp, const char *msg) 1689 { 1690 struct atac_softc *atac = chp->ch_atac; 1691 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1692 1693 if (xfer == NULL) 1694 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1695 msg); 1696 else 1697 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1698 chp->ch_channel, xfer->c_drive, msg); 1699 } 1700 1701 /* 1702 * the bit bucket 1703 */ 1704 void 1705 wdcbit_bucket(struct ata_channel *chp, int size) 1706 { 1707 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1708 1709 for (; size >= 2; size -= 2) 1710 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1711 if (size) 1712 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1713 } 1714 1715 static void 1716 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1717 { 1718 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1719 1720 if (flags & DRIVE_NOSTREAM) { 1721 if (flags & DRIVE_CAP32) { 1722 bus_space_read_multi_4(wdr->data32iot, 1723 wdr->data32ioh, 0, bf, len >> 2); 1724 bf = (char *)bf + (len & ~3); 1725 len &= 3; 1726 } 1727 if (len) { 1728 bus_space_read_multi_2(wdr->cmd_iot, 1729 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1730 } 1731 } else { 1732 if (flags & DRIVE_CAP32) { 1733 bus_space_read_multi_stream_4(wdr->data32iot, 1734 wdr->data32ioh, 0, bf, len >> 2); 1735 bf = (char *)bf + (len & ~3); 1736 len &= 3; 1737 } 1738 if (len) { 1739 bus_space_read_multi_stream_2(wdr->cmd_iot, 1740 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1741 } 1742 } 1743 } 1744 1745 static void 1746 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1747 { 1748 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1749 1750 if (flags & DRIVE_NOSTREAM) { 1751 if (flags & DRIVE_CAP32) { 1752 bus_space_write_multi_4(wdr->data32iot, 1753 wdr->data32ioh, 0, bf, len >> 2); 1754 bf = (char *)bf + (len & ~3); 1755 len &= 3; 1756 } 1757 if (len) { 1758 bus_space_write_multi_2(wdr->cmd_iot, 1759 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1760 } 1761 } else { 1762 if (flags & DRIVE_CAP32) { 1763 bus_space_write_multi_stream_4(wdr->data32iot, 1764 wdr->data32ioh, 0, bf, len >> 2); 1765 bf = (char *)bf + (len & ~3); 1766 len &= 3; 1767 } 1768 if (len) { 1769 bus_space_write_multi_stream_2(wdr->cmd_iot, 1770 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1771 } 1772 } 1773 } 1774
Indexes created Tue Sep 23 14:10:03 GMT 2025