wdc.c revision 1.227
1 /* $NetBSD: wdc.c,v 1.227 2005/08/10 11:16:53 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.227 2005/08/10 11:16:53 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 /* 123 * timeout when waiting for BSY to deassert when probing. 124 * set to 5s. From the standards this could be up to 31, but we can't 125 * wait that much at boot time, and 5s seems to be enouth. 126 */ 127 #define WDC_PROBE_WAIT 5 128 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, /* wdc_ata_bio */ 137 NULL, /* wdc_reset_drive */ 138 wdc_reset_channel, 139 wdc_exec_command, 140 NULL, /* ata_get_params */ 141 NULL, /* wdc_ata_addref */ 142 NULL, /* wdc_ata_delref */ 143 NULL /* ata_kill_pending */ 144 }; 145 #endif 146 147 /* Flags to wdcreset(). */ 148 #define RESET_POLL 1 149 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 150 151 static int wdcprobe1(struct ata_channel *, int); 152 static int wdcreset(struct ata_channel *, int); 153 static void __wdcerror(struct ata_channel *, const char *); 154 static int __wdcwait_reset(struct ata_channel *, int, int); 155 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 156 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 157 static void __wdccommand_kill_xfer(struct ata_channel *, 158 struct ata_xfer *, int); 159 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 160 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 161 static int __wdcwait(struct ata_channel *, int, int, int); 162 163 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 164 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 165 166 #define DEBUG_INTR 0x01 167 #define DEBUG_XFERS 0x02 168 #define DEBUG_STATUS 0x04 169 #define DEBUG_FUNCS 0x08 170 #define DEBUG_PROBE 0x10 171 #define DEBUG_DETACH 0x20 172 #define DEBUG_DELAY 0x40 173 #ifdef ATADEBUG 174 extern int atadebug_mask; /* init'ed in ata.c */ 175 int wdc_nxfer = 0; 176 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 177 #else 178 #define ATADEBUG_PRINT(args, level) 179 #endif 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct ata_channel *chp) 186 { 187 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 188 189 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 190 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 191 } 192 193 /* 194 * Allocate a wdc_regs array, based on the number of channels. 195 */ 196 void 197 wdc_allocate_regs(struct wdc_softc *wdc) 198 { 199 200 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 201 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 202 } 203 204 /* Test to see controller with at last one attached drive is there. 205 * Returns a bit for each possible drive found (0x01 for drive 0, 206 * 0x02 for drive 1). 207 * Logic: 208 * - If a status register is at 0xff, assume there is no drive here 209 * (ISA has pull-up resistors). Similarly if the status register has 210 * the value we last wrote to the bus (for IDE interfaces without pullups). 211 * If no drive at all -> return. 212 * - reset the controller, wait for it to complete (may take up to 31s !). 213 * If timeout -> return. 214 * - test ATA/ATAPI signatures. If at last one drive found -> return. 215 * - try an ATA command on the master. 216 */ 217 218 static void 219 wdc_drvprobe(struct ata_channel *chp) 220 { 221 struct ataparams params; 222 struct atac_softc *atac = chp->ch_atac; 223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 225 u_int8_t st0 = 0, st1 = 0; 226 int i, error, s; 227 228 if (wdcprobe1(chp, 0) == 0) { 229 /* No drives, abort the attach here. */ 230 return; 231 } 232 233 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 234 for (i = 0; i < mstohz(3000); i++) { 235 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 236 if (wdc->select) 237 wdc->select(chp,0); 238 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 239 0, WDSD_IBM); 240 delay(10); /* 400ns delay */ 241 st0 = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_status], 0); 243 } 244 245 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 246 if (wdc->select) 247 wdc->select(chp,1); 248 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 249 0, WDSD_IBM | 0x10); 250 delay(10); /* 400ns delay */ 251 st1 = bus_space_read_1(wdr->cmd_iot, 252 wdr->cmd_iohs[wd_status], 0); 253 } 254 255 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 256 == 0 || 257 (st0 & WDCS_DRDY)) && 258 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 259 == 0 || 260 (st1 & WDCS_DRDY))) 261 break; 262 tsleep(¶ms, PRIBIO, "atadrdy", 1); 263 } 264 s = splbio(); 265 if ((st0 & WDCS_DRDY) == 0) 266 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 267 if ((st1 & WDCS_DRDY) == 0) 268 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 269 splx(s); 270 271 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 272 atac->atac_dev.dv_xname, 273 chp->ch_channel, st0, st1), DEBUG_PROBE); 274 275 /* Wait a bit, some devices are weird just after a reset. */ 276 delay(5000); 277 278 for (i = 0; i < 2; i++) { 279 /* XXX This should be done by other code. */ 280 chp->ch_drive[i].chnl_softc = chp; 281 chp->ch_drive[i].drive = i; 282 283 /* 284 * Init error counter so that an error withing the first xfers 285 * will trigger a downgrade 286 */ 287 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 288 289 /* If controller can't do 16bit flag the drives as 32bit */ 290 if ((atac->atac_cap & 291 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 292 s = splbio(); 293 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 294 splx(s); 295 } 296 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 297 continue; 298 299 /* Shortcut in case we've been shutdown */ 300 if (chp->ch_flags & ATACH_SHUTDOWN) 301 return; 302 303 /* 304 * Issue an identify, to try to detect ghosts. 305 * Note that we can't use interrupts here, because if there 306 * is no devices, we will get a command aborted without 307 * interrupts. 308 */ 309 error = ata_get_params(&chp->ch_drive[i], 310 AT_WAIT | AT_POLL, ¶ms); 311 if (error != CMD_OK) { 312 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 313 314 /* Shortcut in case we've been shutdown */ 315 if (chp->ch_flags & ATACH_SHUTDOWN) 316 return; 317 318 error = ata_get_params(&chp->ch_drive[i], 319 AT_WAIT | AT_POLL, ¶ms); 320 } 321 if (error == CMD_OK) { 322 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 323 s = splbio(); 324 /* XXXJRT ch_ndrive */ 325 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 326 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 327 splx(s); 328 } else { 329 s = splbio(); 330 chp->ch_drive[i].drive_flags &= 331 ~(DRIVE_ATA | DRIVE_ATAPI); 332 splx(s); 333 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 atac->atac_dev.dv_xname, 335 chp->ch_channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 if (wdc->select) 344 wdc->select(chp,i); 345 bus_space_write_1(wdr->cmd_iot, 346 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 347 delay(10); /* 400ns delay */ 348 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 349 0, 0x58); 350 bus_space_write_1(wdr->cmd_iot, 351 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 352 if (bus_space_read_1(wdr->cmd_iot, 353 wdr->cmd_iohs[wd_error], 0) == 0x58 || 354 bus_space_read_1(wdr->cmd_iot, 355 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 356 ATADEBUG_PRINT(("%s:%d:%d: register " 357 "writability failed\n", 358 atac->atac_dev.dv_xname, 359 chp->ch_channel, i), DEBUG_PROBE); 360 s = splbio(); 361 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 362 splx(s); 363 continue; 364 } 365 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 366 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 367 atac->atac_dev.dv_xname, 368 chp->ch_channel, i), DEBUG_PROBE); 369 s = splbio(); 370 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 371 splx(s); 372 continue; 373 } 374 bus_space_write_1(wdr->cmd_iot, 375 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 376 delay(10); /* 400ns delay */ 377 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 378 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 379 atac->atac_dev.dv_xname, 380 chp->ch_channel, i), DEBUG_PROBE); 381 s = splbio(); 382 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 383 splx(s); 384 } else { 385 s = splbio(); 386 /* XXXJRT ch_ndrive */ 387 chp->ch_drive[0].drive_flags &= 388 ~(DRIVE_ATA | DRIVE_ATAPI); 389 chp->ch_drive[1].drive_flags &= 390 ~(DRIVE_ATA | DRIVE_ATAPI); 391 splx(s); 392 } 393 } 394 } 395 } 396 397 int 398 wdcprobe(struct ata_channel *chp) 399 { 400 /* default reset method */ 401 if (wdc->reset == NULL) 402 wdc->reset = wdc_do_reset; 403 404 return (wdcprobe1(chp, 1)); 405 } 406 407 static int 408 wdcprobe1(struct ata_channel *chp, int poll) 409 { 410 struct atac_softc *atac = chp->ch_atac; 411 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 412 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 413 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 414 u_int8_t ret_value = 0x03; 415 u_int8_t drive; 416 int s; 417 int wdc_probe_count = 418 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 419 420 /* 421 * Sanity check to see if the wdc channel responds at all. 422 */ 423 424 s = splbio(); 425 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 426 while (wdc_probe_count-- > 0) { 427 if (wdc->select) 428 wdc->select(chp,0); 429 430 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 431 0, WDSD_IBM); 432 delay(10); /* 400ns delay */ 433 st0 = bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_status], 0); 435 436 if (wdc->select) 437 wdc->select(chp,1); 438 439 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 440 0, WDSD_IBM | 0x10); 441 delay(10); /* 400ns delay */ 442 st1 = bus_space_read_1(wdr->cmd_iot, 443 wdr->cmd_iohs[wd_status], 0); 444 if ((st0 & WDCS_BSY) == 0) 445 break; 446 } 447 448 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 449 atac->atac_dev.dv_xname, 450 chp->ch_channel, st0, st1), DEBUG_PROBE); 451 452 if (st0 == 0xff || st0 == WDSD_IBM) 453 ret_value &= ~0x01; 454 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 455 ret_value &= ~0x02; 456 /* Register writability test, drive 0. */ 457 if (ret_value & 0x01) { 458 if (wdc->select) 459 wdc->select(chp,0); 460 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 461 0, WDSD_IBM); 462 bus_space_write_1(wdr->cmd_iot, 463 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 464 cl = bus_space_read_1(wdr->cmd_iot, 465 wdr->cmd_iohs[wd_cyl_lo], 0); 466 if (cl != 0x02) { 467 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 468 "got 0x%x != 0x02\n", 469 atac->atac_dev.dv_xname, 470 chp->ch_channel, cl), 471 DEBUG_PROBE); 472 ret_value &= ~0x01; 473 } 474 bus_space_write_1(wdr->cmd_iot, 475 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 476 cl = bus_space_read_1(wdr->cmd_iot, 477 wdr->cmd_iohs[wd_cyl_lo], 0); 478 if (cl != 0x01) { 479 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 480 "got 0x%x != 0x01\n", 481 atac->atac_dev.dv_xname, 482 chp->ch_channel, cl), 483 DEBUG_PROBE); 484 ret_value &= ~0x01; 485 } 486 bus_space_write_1(wdr->cmd_iot, 487 wdr->cmd_iohs[wd_sector], 0, 0x01); 488 cl = bus_space_read_1(wdr->cmd_iot, 489 wdr->cmd_iohs[wd_sector], 0); 490 if (cl != 0x01) { 491 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 492 "got 0x%x != 0x01\n", 493 atac->atac_dev.dv_xname, 494 chp->ch_channel, cl), 495 DEBUG_PROBE); 496 ret_value &= ~0x01; 497 } 498 bus_space_write_1(wdr->cmd_iot, 499 wdr->cmd_iohs[wd_sector], 0, 0x02); 500 cl = bus_space_read_1(wdr->cmd_iot, 501 wdr->cmd_iohs[wd_sector], 0); 502 if (cl != 0x02) { 503 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 504 "got 0x%x != 0x02\n", 505 atac->atac_dev.dv_xname, 506 chp->ch_channel, cl), 507 DEBUG_PROBE); 508 ret_value &= ~0x01; 509 } 510 cl = bus_space_read_1(wdr->cmd_iot, 511 wdr->cmd_iohs[wd_cyl_lo], 0); 512 if (cl != 0x01) { 513 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 514 "got 0x%x != 0x01\n", 515 atac->atac_dev.dv_xname, 516 chp->ch_channel, cl), 517 DEBUG_PROBE); 518 ret_value &= ~0x01; 519 } 520 } 521 /* Register writability test, drive 1. */ 522 if (ret_value & 0x02) { 523 if (wdc->select) 524 wdc->select(chp,1); 525 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 526 0, WDSD_IBM | 0x10); 527 bus_space_write_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 529 cl = bus_space_read_1(wdr->cmd_iot, 530 wdr->cmd_iohs[wd_cyl_lo], 0); 531 if (cl != 0x02) { 532 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 533 "got 0x%x != 0x02\n", 534 atac->atac_dev.dv_xname, 535 chp->ch_channel, cl), 536 DEBUG_PROBE); 537 ret_value &= ~0x02; 538 } 539 bus_space_write_1(wdr->cmd_iot, 540 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 541 cl = bus_space_read_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_cyl_lo], 0); 543 if (cl != 0x01) { 544 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 545 "got 0x%x != 0x01\n", 546 atac->atac_dev.dv_xname, 547 chp->ch_channel, cl), 548 DEBUG_PROBE); 549 ret_value &= ~0x02; 550 } 551 bus_space_write_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_sector], 0, 0x01); 553 cl = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_sector], 0); 555 if (cl != 0x01) { 556 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 557 "got 0x%x != 0x01\n", 558 atac->atac_dev.dv_xname, 559 chp->ch_channel, cl), 560 DEBUG_PROBE); 561 ret_value &= ~0x02; 562 } 563 bus_space_write_1(wdr->cmd_iot, 564 wdr->cmd_iohs[wd_sector], 0, 0x02); 565 cl = bus_space_read_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_sector], 0); 567 if (cl != 0x02) { 568 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 569 "got 0x%x != 0x02\n", 570 atac->atac_dev.dv_xname, 571 chp->ch_channel, cl), 572 DEBUG_PROBE); 573 ret_value &= ~0x02; 574 } 575 cl = bus_space_read_1(wdr->cmd_iot, 576 wdr->cmd_iohs[wd_cyl_lo], 0); 577 if (cl != 0x01) { 578 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 579 "got 0x%x != 0x01\n", 580 atac->atac_dev.dv_xname, 581 chp->ch_channel, cl), 582 DEBUG_PROBE); 583 ret_value &= ~0x02; 584 } 585 } 586 587 if (ret_value == 0) { 588 splx(s); 589 return 0; 590 } 591 } 592 593 594 #if 0 /* XXX this break some ATA or ATAPI devices */ 595 /* 596 * reset bus. Also send an ATAPI_RESET to devices, in case there are 597 * ATAPI device out there which don't react to the bus reset 598 */ 599 if (ret_value & 0x01) { 600 if (wdc->select) 601 wdc->select(chp,0); 602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 603 0, WDSD_IBM); 604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 605 ATAPI_SOFT_RESET); 606 } 607 if (ret_value & 0x02) { 608 if (wdc->select) 609 wdc->select(chp,0); 610 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 611 0, WDSD_IBM | 0x10); 612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 613 ATAPI_SOFT_RESET); 614 } 615 616 delay(5000); 617 #endif 618 619 wdc->reset(chp, RESET_POLL); 620 DELAY(2000); 621 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 622 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 623 splx(s); 624 625 ret_value = __wdcwait_reset(chp, ret_value, poll); 626 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 627 atac->atac_dev.dv_xname, chp->ch_channel, 628 ret_value), DEBUG_PROBE); 629 630 /* if reset failed, there's nothing here */ 631 if (ret_value == 0) 632 return 0; 633 634 /* 635 * Test presence of drives. First test register signatures looking 636 * for ATAPI devices. If it's not an ATAPI and reset said there may 637 * be something here assume it's ATA or OLD. Ghost will be killed 638 * later in attach routine. 639 */ 640 for (drive = 0; drive < 2; drive++) { 641 if ((ret_value & (0x01 << drive)) == 0) 642 continue; 643 if (wdc->select) 644 wdc->select(chp,drive); 645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 646 WDSD_IBM | (drive << 4)); 647 delay(10); /* 400ns delay */ 648 /* Save registers contents */ 649 sc = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_seccnt], 0); 651 sn = bus_space_read_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_sector], 0); 653 cl = bus_space_read_1(wdr->cmd_iot, 654 wdr->cmd_iohs[wd_cyl_lo], 0); 655 ch = bus_space_read_1(wdr->cmd_iot, 656 wdr->cmd_iohs[wd_cyl_hi], 0); 657 658 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 659 "cl=0x%x ch=0x%x\n", 660 atac->atac_dev.dv_xname, 661 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 662 /* 663 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 664 * we get wrong values here, so ignore it. 665 */ 666 s = splbio(); 667 if (cl == 0x14 && ch == 0xeb) { 668 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 669 } else { 670 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 671 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 672 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 673 } 674 splx(s); 675 } 676 return (ret_value); 677 } 678 679 void 680 wdcattach(struct ata_channel *chp) 681 { 682 struct atac_softc *atac = chp->ch_atac; 683 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 684 685 /* 686 * Start out assuming 2 drives. This may change as we probe 687 * drives. 688 */ 689 chp->ch_ndrive = 2; 690 691 /* default data transfer methods */ 692 if (wdc->datain_pio == NULL) 693 wdc->datain_pio = wdc_datain_pio; 694 if (wdc->dataout_pio == NULL) 695 wdc->dataout_pio = wdc_dataout_pio; 696 /* default reset method */ 697 if (wdc->reset == NULL) 698 wdc->reset = wdc_do_reset; 699 700 /* initialise global data */ 701 if (atac->atac_bustype_ata == NULL) 702 atac->atac_bustype_ata = &wdc_ata_bustype; 703 if (atac->atac_probe == NULL) 704 atac->atac_probe = wdc_drvprobe; 705 #if NATAPIBUS > 0 706 if (atac->atac_atapibus_attach == NULL) 707 atac->atac_atapibus_attach = wdc_atapibus_attach; 708 #endif 709 710 ata_channel_attach(chp); 711 } 712 713 int 714 wdcactivate(struct device *self, enum devact act) 715 { 716 struct atac_softc *atac = (struct atac_softc *) self; 717 int s, i, error = 0; 718 719 s = splbio(); 720 switch (act) { 721 case DVACT_ACTIVATE: 722 error = EOPNOTSUPP; 723 break; 724 725 case DVACT_DEACTIVATE: 726 for (i = 0; i < atac->atac_nchannels; i++) { 727 error = 728 config_deactivate(atac->atac_channels[i]->atabus); 729 if (error) 730 break; 731 } 732 break; 733 } 734 splx(s); 735 return (error); 736 } 737 738 int 739 wdcdetach(struct device *self, int flags) 740 { 741 struct atac_softc *atac = (struct atac_softc *) self; 742 struct ata_channel *chp; 743 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 744 int i, error = 0; 745 746 for (i = 0; i < atac->atac_nchannels; i++) { 747 chp = atac->atac_channels[i]; 748 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 749 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 750 DEBUG_DETACH); 751 error = config_detach(chp->atabus, flags); 752 if (error) 753 break; 754 } 755 if (adapt->adapt_refcnt != 0) { 756 #ifdef DIAGNOSTIC 757 printf("wdcdetach: refcnt should be 0 here??\n"); 758 #endif 759 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 760 } 761 return (error); 762 } 763 764 /* restart an interrupted I/O */ 765 void 766 wdcrestart(void *v) 767 { 768 struct ata_channel *chp = v; 769 int s; 770 771 s = splbio(); 772 atastart(chp); 773 splx(s); 774 } 775 776 777 /* 778 * Interrupt routine for the controller. Acknowledge the interrupt, check for 779 * errors on the current operation, mark it done if necessary, and start the 780 * next request. Also check for a partially done transfer, and continue with 781 * the next chunk if so. 782 */ 783 int 784 wdcintr(void *arg) 785 { 786 struct ata_channel *chp = arg; 787 struct atac_softc *atac = chp->ch_atac; 788 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 789 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 790 struct ata_xfer *xfer; 791 int ret; 792 793 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 794 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 795 DEBUG_INTR); 796 return (0); 797 } 798 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 799 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 800 /* try to clear the pending interrupt anyway */ 801 (void)bus_space_read_1(wdr->cmd_iot, 802 wdr->cmd_iohs[wd_status], 0); 803 return (0); 804 } 805 806 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 807 xfer = chp->ch_queue->active_xfer; 808 #ifdef DIAGNOSTIC 809 if (xfer == NULL) 810 panic("wdcintr: no xfer"); 811 #endif 812 if (chp->ch_flags & ATACH_DMA_WAIT) { 813 wdc->dma_status = 814 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 815 xfer->c_drive, WDC_DMAEND_END); 816 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 817 /* IRQ not for us, not detected by DMA engine */ 818 return 0; 819 } 820 chp->ch_flags &= ~ATACH_DMA_WAIT; 821 } 822 chp->ch_flags &= ~ATACH_IRQ_WAIT; 823 ret = xfer->c_intr(chp, xfer, 1); 824 if (ret == 0) /* irq was not for us, still waiting for irq */ 825 chp->ch_flags |= ATACH_IRQ_WAIT; 826 return (ret); 827 } 828 829 /* Put all disk in RESET state */ 830 void 831 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 832 { 833 struct ata_channel *chp = drvp->chnl_softc; 834 struct atac_softc *atac = chp->ch_atac; 835 836 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 837 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 838 DEBUG_FUNCS); 839 840 ata_reset_channel(chp, flags); 841 } 842 843 void 844 wdc_reset_channel(struct ata_channel *chp, int flags) 845 { 846 TAILQ_HEAD(, ata_xfer) reset_xfer; 847 struct ata_xfer *xfer, *next_xfer; 848 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 849 850 TAILQ_INIT(&reset_xfer); 851 852 chp->ch_flags &= ~ATACH_IRQ_WAIT; 853 854 /* 855 * if the current command if on an ATAPI device, issue a 856 * ATAPI_SOFT_RESET 857 */ 858 xfer = chp->ch_queue->active_xfer; 859 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 860 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 861 if (flags & AT_WAIT) 862 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 863 else 864 delay(1000); 865 } 866 867 /* reset the channel */ 868 if (flags & AT_WAIT) 869 (void) wdcreset(chp, RESET_SLEEP); 870 else 871 (void) wdcreset(chp, RESET_POLL); 872 873 /* 874 * wait a bit after reset; in case the DMA engines needs some time 875 * to recover. 876 */ 877 if (flags & AT_WAIT) 878 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 879 else 880 delay(1000); 881 /* 882 * look for pending xfers. If we have a shared queue, we'll also reset 883 * the other channel if the current xfer is running on it. 884 * Then we'll dequeue only the xfers for this channel. 885 */ 886 if ((flags & AT_RST_NOCMD) == 0) { 887 /* 888 * move all xfers queued for this channel to the reset queue, 889 * and then process the current xfer and then the reset queue. 890 * We have to use a temporary queue because c_kill_xfer() 891 * may requeue commands. 892 */ 893 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 894 xfer != NULL; xfer = next_xfer) { 895 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 896 if (xfer->c_chp != chp) 897 continue; 898 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 899 xfer, c_xferchain); 900 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 901 } 902 xfer = chp->ch_queue->active_xfer; 903 if (xfer) { 904 if (xfer->c_chp != chp) 905 ata_reset_channel(xfer->c_chp, flags); 906 else { 907 callout_stop(&chp->ch_callout); 908 /* 909 * If we're waiting for DMA, stop the 910 * DMA engine 911 */ 912 if (chp->ch_flags & ATACH_DMA_WAIT) { 913 (*wdc->dma_finish)( 914 wdc->dma_arg, 915 chp->ch_channel, 916 xfer->c_drive, 917 WDC_DMAEND_ABRT_QUIET); 918 chp->ch_flags &= ~ATACH_DMA_WAIT; 919 } 920 chp->ch_queue->active_xfer = NULL; 921 if ((flags & AT_RST_EMERG) == 0) 922 xfer->c_kill_xfer( 923 chp, xfer, KILL_RESET); 924 } 925 } 926 927 for (xfer = TAILQ_FIRST(&reset_xfer); 928 xfer != NULL; xfer = next_xfer) { 929 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 930 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 931 if ((flags & AT_RST_EMERG) == 0) 932 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 933 } 934 } 935 } 936 937 static int 938 wdcreset(struct ata_channel *chp, int poll) 939 { 940 struct atac_softc *atac = chp->ch_atac; 941 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 942 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 943 int drv_mask1, drv_mask2; 944 945 wdc->reset(chp, poll); 946 947 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 948 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 949 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 950 (poll == RESET_SLEEP) ? 0 : 1); 951 if (drv_mask2 != drv_mask1) { 952 printf("%s channel %d: reset failed for", 953 atac->atac_dev.dv_xname, chp->ch_channel); 954 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 955 printf(" drive 0"); 956 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 957 printf(" drive 1"); 958 printf("\n"); 959 } 960 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 961 return (drv_mask1 != drv_mask2) ? 1 : 0; 962 } 963 964 void 965 wdc_do_reset(struct ata_channel *chp, int poll) 966 { 967 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 968 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 969 int s = 0; 970 971 if (poll != RESET_SLEEP) 972 s = splbio(); 973 if (wdc->select) 974 wdc->select(chp,0); 975 /* master */ 976 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 977 delay(10); /* 400ns delay */ 978 /* assert SRST, wait for reset to complete */ 979 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 980 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 981 delay(2000); 982 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 983 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 984 WDCTL_4BIT | WDCTL_IDS); 985 delay(10); /* 400ns delay */ 986 if (poll != RESET_SLEEP) { 987 if (wdc->irqack) 988 wdc->irqack(chp); 989 splx(s); 990 } 991 } 992 993 static int 994 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 995 { 996 struct atac_softc *atac = chp->ch_atac; 997 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 998 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 999 int timeout, nloop; 1000 u_int8_t st0 = 0, st1 = 0; 1001 #ifdef ATADEBUG 1002 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1003 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1004 #endif 1005 1006 if (poll) 1007 nloop = WDCNDELAY_RST; 1008 else 1009 nloop = WDC_RESET_WAIT * hz / 1000; 1010 /* wait for BSY to deassert */ 1011 for (timeout = 0; timeout < nloop; timeout++) { 1012 if ((drv_mask & 0x01) != 0) { 1013 if (wdc && wdc->select) 1014 wdc->select(chp,0); 1015 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1016 0, WDSD_IBM); /* master */ 1017 delay(10); 1018 st0 = bus_space_read_1(wdr->cmd_iot, 1019 wdr->cmd_iohs[wd_status], 0); 1020 #ifdef ATADEBUG 1021 sc0 = bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_seccnt], 0); 1023 sn0 = bus_space_read_1(wdr->cmd_iot, 1024 wdr->cmd_iohs[wd_sector], 0); 1025 cl0 = bus_space_read_1(wdr->cmd_iot, 1026 wdr->cmd_iohs[wd_cyl_lo], 0); 1027 ch0 = bus_space_read_1(wdr->cmd_iot, 1028 wdr->cmd_iohs[wd_cyl_hi], 0); 1029 #endif 1030 } 1031 if ((drv_mask & 0x02) != 0) { 1032 if (wdc && wdc->select) 1033 wdc->select(chp,1); 1034 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1035 0, WDSD_IBM | 0x10); /* slave */ 1036 delay(10); 1037 st1 = bus_space_read_1(wdr->cmd_iot, 1038 wdr->cmd_iohs[wd_status], 0); 1039 #ifdef ATADEBUG 1040 sc1 = bus_space_read_1(wdr->cmd_iot, 1041 wdr->cmd_iohs[wd_seccnt], 0); 1042 sn1 = bus_space_read_1(wdr->cmd_iot, 1043 wdr->cmd_iohs[wd_sector], 0); 1044 cl1 = bus_space_read_1(wdr->cmd_iot, 1045 wdr->cmd_iohs[wd_cyl_lo], 0); 1046 ch1 = bus_space_read_1(wdr->cmd_iot, 1047 wdr->cmd_iohs[wd_cyl_hi], 0); 1048 #endif 1049 } 1050 1051 if ((drv_mask & 0x01) == 0) { 1052 /* no master */ 1053 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1054 /* No master, slave is ready, it's done */ 1055 goto end; 1056 } 1057 } else if ((drv_mask & 0x02) == 0) { 1058 /* no slave */ 1059 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1060 /* No slave, master is ready, it's done */ 1061 goto end; 1062 } 1063 } else { 1064 /* Wait for both master and slave to be ready */ 1065 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1066 goto end; 1067 } 1068 } 1069 if (poll) 1070 delay(WDCDELAY); 1071 else 1072 tsleep(&nloop, PRIBIO, "atarst", 1); 1073 } 1074 /* Reset timed out. Maybe it's because drv_mask was not right */ 1075 if (st0 & WDCS_BSY) 1076 drv_mask &= ~0x01; 1077 if (st1 & WDCS_BSY) 1078 drv_mask &= ~0x02; 1079 end: 1080 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1081 "cl=0x%x ch=0x%x\n", 1082 atac->atac_dev.dv_xname, 1083 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1084 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1085 "cl=0x%x ch=0x%x\n", 1086 atac->atac_dev.dv_xname, 1087 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1088 1089 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1090 atac->atac_dev.dv_xname, chp->ch_channel, 1091 st0, st1), DEBUG_PROBE); 1092 1093 return drv_mask; 1094 } 1095 1096 /* 1097 * Wait for a drive to be !BSY, and have mask in its status register. 1098 * return -1 for a timeout after "timeout" ms. 1099 */ 1100 static int 1101 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1102 { 1103 struct atac_softc *atac = chp->ch_atac; 1104 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1105 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1106 u_char status; 1107 int xtime = 0; 1108 1109 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1110 atac->atac_dev.dv_xname, 1111 chp->ch_channel), DEBUG_STATUS); 1112 chp->ch_error = 0; 1113 1114 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1115 1116 for (;;) { 1117 chp->ch_status = status = 1118 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1119 if ((status & (WDCS_BSY | mask)) == bits) 1120 break; 1121 if (++xtime > timeout) { 1122 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1123 "status %x error %x (mask 0x%x bits 0x%x)\n", 1124 xtime, status, 1125 bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_error], 0), mask, bits), 1127 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1128 return(WDCWAIT_TOUT); 1129 } 1130 delay(WDCDELAY); 1131 } 1132 #ifdef ATADEBUG 1133 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1134 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1135 #endif 1136 if (status & WDCS_ERR) 1137 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_error], 0); 1139 #ifdef WDCNDELAY_DEBUG 1140 /* After autoconfig, there should be no long delays. */ 1141 if (!cold && xtime > WDCNDELAY_DEBUG) { 1142 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1143 if (xfer == NULL) 1144 printf("%s channel %d: warning: busy-wait took %dus\n", 1145 atac->atac_dev.dv_xname, chp->ch_channel, 1146 WDCDELAY * xtime); 1147 else 1148 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1149 atac->atac_dev.dv_xname, chp->ch_channel, 1150 xfer->drive, 1151 WDCDELAY * xtime); 1152 } 1153 #endif 1154 return(WDCWAIT_OK); 1155 } 1156 1157 /* 1158 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1159 * thread if possible 1160 */ 1161 int 1162 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1163 { 1164 int error, i, timeout_hz = mstohz(timeout); 1165 1166 if (timeout_hz == 0 || 1167 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1168 error = __wdcwait(chp, mask, bits, timeout); 1169 else { 1170 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1171 if (error != 0) { 1172 if ((chp->ch_flags & ATACH_TH_RUN) || 1173 (flags & AT_WAIT)) { 1174 /* 1175 * we're running in the channel thread 1176 * or some userland thread context 1177 */ 1178 for (i = 0; i < timeout_hz; i++) { 1179 if (__wdcwait(chp, mask, bits, 1180 WDCDELAY_POLL) == 0) { 1181 error = 0; 1182 break; 1183 } 1184 tsleep(&chp, PRIBIO, "atapoll", 1); 1185 } 1186 } else { 1187 /* 1188 * we're probably in interrupt context, 1189 * ask the thread to come back here 1190 */ 1191 #ifdef DIAGNOSTIC 1192 if (chp->ch_queue->queue_freeze > 0) 1193 panic("wdcwait: queue_freeze"); 1194 #endif 1195 chp->ch_queue->queue_freeze++; 1196 wakeup(&chp->ch_thread); 1197 return(WDCWAIT_THR); 1198 } 1199 } 1200 } 1201 return (error); 1202 } 1203 1204 1205 /* 1206 * Busy-wait for DMA to complete 1207 */ 1208 int 1209 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1210 { 1211 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1212 int xtime; 1213 1214 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1215 wdc->dma_status = 1216 (*wdc->dma_finish)(wdc->dma_arg, 1217 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1218 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1219 return 0; 1220 delay(WDCDELAY); 1221 } 1222 /* timeout, force a DMA halt */ 1223 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1224 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1225 return 1; 1226 } 1227 1228 void 1229 wdctimeout(void *arg) 1230 { 1231 struct ata_channel *chp = (struct ata_channel *)arg; 1232 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1233 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1234 int s; 1235 1236 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1237 1238 s = splbio(); 1239 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1240 __wdcerror(chp, "lost interrupt"); 1241 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1242 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1243 xfer->c_bcount, 1244 xfer->c_skip); 1245 if (chp->ch_flags & ATACH_DMA_WAIT) { 1246 wdc->dma_status = 1247 (*wdc->dma_finish)(wdc->dma_arg, 1248 chp->ch_channel, xfer->c_drive, 1249 WDC_DMAEND_ABRT); 1250 chp->ch_flags &= ~ATACH_DMA_WAIT; 1251 } 1252 /* 1253 * Call the interrupt routine. If we just missed an interrupt, 1254 * it will do what's needed. Else, it will take the needed 1255 * action (reset the device). 1256 * Before that we need to reinstall the timeout callback, 1257 * in case it will miss another irq while in this transfer 1258 * We arbitray chose it to be 1s 1259 */ 1260 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1261 xfer->c_flags |= C_TIMEOU; 1262 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1263 xfer->c_intr(chp, xfer, 1); 1264 } else 1265 __wdcerror(chp, "missing untimeout"); 1266 splx(s); 1267 } 1268 1269 int 1270 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1271 { 1272 struct ata_channel *chp = drvp->chnl_softc; 1273 struct atac_softc *atac = chp->ch_atac; 1274 struct ata_xfer *xfer; 1275 int s, ret; 1276 1277 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1278 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1279 DEBUG_FUNCS); 1280 1281 /* set up an xfer and queue. Wait for completion */ 1282 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1283 ATAXF_NOSLEEP); 1284 if (xfer == NULL) { 1285 return ATACMD_TRY_AGAIN; 1286 } 1287 1288 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1289 ata_c->flags |= AT_POLL; 1290 if (ata_c->flags & AT_POLL) 1291 xfer->c_flags |= C_POLL; 1292 if (ata_c->flags & AT_WAIT) 1293 xfer->c_flags |= C_WAIT; 1294 xfer->c_drive = drvp->drive; 1295 xfer->c_databuf = ata_c->data; 1296 xfer->c_bcount = ata_c->bcount; 1297 xfer->c_cmd = ata_c; 1298 xfer->c_start = __wdccommand_start; 1299 xfer->c_intr = __wdccommand_intr; 1300 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1301 1302 s = splbio(); 1303 ata_exec_xfer(chp, xfer); 1304 #ifdef DIAGNOSTIC 1305 if ((ata_c->flags & AT_POLL) != 0 && 1306 (ata_c->flags & AT_DONE) == 0) 1307 panic("wdc_exec_command: polled command not done"); 1308 #endif 1309 if (ata_c->flags & AT_DONE) { 1310 ret = ATACMD_COMPLETE; 1311 } else { 1312 if (ata_c->flags & AT_WAIT) { 1313 while ((ata_c->flags & AT_DONE) == 0) { 1314 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1315 } 1316 ret = ATACMD_COMPLETE; 1317 } else { 1318 ret = ATACMD_QUEUED; 1319 } 1320 } 1321 splx(s); 1322 return ret; 1323 } 1324 1325 static void 1326 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1327 { 1328 struct atac_softc *atac = chp->ch_atac; 1329 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1330 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1331 int drive = xfer->c_drive; 1332 struct ata_command *ata_c = xfer->c_cmd; 1333 1334 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1335 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1336 DEBUG_FUNCS); 1337 1338 if (wdc->select) 1339 wdc->select(chp,drive); 1340 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1341 WDSD_IBM | (drive << 4)); 1342 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1343 ata_c->r_st_bmask, ata_c->timeout, ata_c->flags)) { 1344 case WDCWAIT_OK: 1345 break; 1346 case WDCWAIT_TOUT: 1347 ata_c->flags |= AT_TIMEOU; 1348 __wdccommand_done(chp, xfer); 1349 return; 1350 case WDCWAIT_THR: 1351 return; 1352 } 1353 if (ata_c->flags & AT_POLL) { 1354 /* polled command, disable interrupts */ 1355 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1356 WDCTL_4BIT | WDCTL_IDS); 1357 } 1358 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1359 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1360 1361 if ((ata_c->flags & AT_POLL) == 0) { 1362 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1363 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1364 wdctimeout, chp); 1365 return; 1366 } 1367 /* 1368 * Polled command. Wait for drive ready or drq. Done in intr(). 1369 * Wait for at last 400ns for status bit to be valid. 1370 */ 1371 delay(10); /* 400ns delay */ 1372 __wdccommand_intr(chp, xfer, 0); 1373 } 1374 1375 static int 1376 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1377 { 1378 struct atac_softc *atac = chp->ch_atac; 1379 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1380 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1381 struct ata_command *ata_c = xfer->c_cmd; 1382 int bcount = ata_c->bcount; 1383 char *data = ata_c->data; 1384 int wflags; 1385 int drive_flags; 1386 1387 if (ata_c->r_command == WDCC_IDENTIFY || 1388 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1389 /* 1390 * The IDENTIFY data has been designed as an array of 1391 * u_int16_t, so we can byteswap it on the fly. 1392 * Historically it's what we have always done so keeping it 1393 * here ensure binary backward compatibility. 1394 */ 1395 drive_flags = DRIVE_NOSTREAM; 1396 } else { 1397 /* 1398 * Other data structure are opaque and should be transfered 1399 * as is. 1400 */ 1401 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1402 } 1403 1404 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1405 /* both wait and poll, we can tsleep here */ 1406 wflags = AT_WAIT | AT_POLL; 1407 } else { 1408 wflags = AT_POLL; 1409 } 1410 1411 again: 1412 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1413 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1414 DEBUG_INTR); 1415 /* 1416 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1417 * Reselect again, it doesn't hurt for others commands, and the time 1418 * penalty for the extra regiter write is acceptable, 1419 * wdc_exec_command() isn't called often (mosly for autoconfig) 1420 */ 1421 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1422 WDSD_IBM | (xfer->c_drive << 4)); 1423 if ((ata_c->flags & AT_XFDONE) != 0) { 1424 /* 1425 * We have completed a data xfer. The drive should now be 1426 * in its initial state 1427 */ 1428 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1429 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1430 wflags) == WDCWAIT_TOUT) { 1431 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1432 return 0; /* IRQ was not for us */ 1433 ata_c->flags |= AT_TIMEOU; 1434 } 1435 goto out; 1436 } 1437 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1438 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1439 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1440 return 0; /* IRQ was not for us */ 1441 ata_c->flags |= AT_TIMEOU; 1442 goto out; 1443 } 1444 if (wdc->irqack) 1445 wdc->irqack(chp); 1446 if (ata_c->flags & AT_READ) { 1447 if ((chp->ch_status & WDCS_DRQ) == 0) { 1448 ata_c->flags |= AT_TIMEOU; 1449 goto out; 1450 } 1451 wdc->datain_pio(chp, drive_flags, data, bcount); 1452 /* at this point the drive should be in its initial state */ 1453 ata_c->flags |= AT_XFDONE; 1454 /* XXX should read status register here ? */ 1455 } else if (ata_c->flags & AT_WRITE) { 1456 if ((chp->ch_status & WDCS_DRQ) == 0) { 1457 ata_c->flags |= AT_TIMEOU; 1458 goto out; 1459 } 1460 wdc->dataout_pio(chp, drive_flags, data, bcount); 1461 ata_c->flags |= AT_XFDONE; 1462 if ((ata_c->flags & AT_POLL) == 0) { 1463 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1464 callout_reset(&chp->ch_callout, 1465 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1466 return 1; 1467 } else { 1468 goto again; 1469 } 1470 } 1471 out: 1472 __wdccommand_done(chp, xfer); 1473 return 1; 1474 } 1475 1476 static void 1477 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1478 { 1479 struct atac_softc *atac = chp->ch_atac; 1480 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1481 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1482 struct ata_command *ata_c = xfer->c_cmd; 1483 1484 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1485 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1486 DEBUG_FUNCS); 1487 1488 1489 if (chp->ch_status & WDCS_DWF) 1490 ata_c->flags |= AT_DF; 1491 if (chp->ch_status & WDCS_ERR) { 1492 ata_c->flags |= AT_ERROR; 1493 ata_c->r_error = chp->ch_error; 1494 } 1495 if ((ata_c->flags & AT_READREG) != 0 && 1496 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1497 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1498 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1499 wdr->cmd_iohs[wd_sdh], 0); 1500 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1501 wdr->cmd_iohs[wd_seccnt], 0); 1502 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1503 wdr->cmd_iohs[wd_sector], 0); 1504 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1505 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1506 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1507 wdr->cmd_iohs[wd_cyl_lo], 0); 1508 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1509 wdr->cmd_iohs[wd_error], 0); 1510 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1511 wdr->cmd_iohs[wd_features], 0); 1512 } 1513 callout_stop(&chp->ch_callout); 1514 chp->ch_queue->active_xfer = NULL; 1515 if (ata_c->flags & AT_POLL) { 1516 /* enable interrupts */ 1517 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1518 WDCTL_4BIT); 1519 delay(10); /* some drives need a little delay here */ 1520 } 1521 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1522 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1523 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1524 wakeup(&chp->ch_queue->active_xfer); 1525 } else 1526 __wdccommand_done_end(chp, xfer); 1527 } 1528 1529 static void 1530 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1531 { 1532 struct ata_command *ata_c = xfer->c_cmd; 1533 1534 ata_c->flags |= AT_DONE; 1535 ata_free_xfer(chp, xfer); 1536 if (ata_c->flags & AT_WAIT) 1537 wakeup(ata_c); 1538 else if (ata_c->callback) 1539 ata_c->callback(ata_c->callback_arg); 1540 atastart(chp); 1541 return; 1542 } 1543 1544 static void 1545 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1546 int reason) 1547 { 1548 struct ata_command *ata_c = xfer->c_cmd; 1549 1550 switch (reason) { 1551 case KILL_GONE: 1552 ata_c->flags |= AT_GONE; 1553 break; 1554 case KILL_RESET: 1555 ata_c->flags |= AT_RESET; 1556 break; 1557 default: 1558 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1559 reason); 1560 panic("__wdccommand_kill_xfer"); 1561 } 1562 __wdccommand_done_end(chp, xfer); 1563 } 1564 1565 /* 1566 * Send a command. The drive should be ready. 1567 * Assumes interrupts are blocked. 1568 */ 1569 void 1570 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1571 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1572 u_int8_t features) 1573 { 1574 struct atac_softc *atac = chp->ch_atac; 1575 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1576 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1577 1578 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1579 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1580 chp->ch_channel, drive, command, cylin, head, sector, count, 1581 features), DEBUG_FUNCS); 1582 1583 if (wdc->select) 1584 wdc->select(chp,drive); 1585 1586 /* Select drive, head, and addressing mode. */ 1587 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1588 WDSD_IBM | (drive << 4) | head); 1589 /* Load parameters into the wd_features register. */ 1590 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1591 features); 1592 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1593 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1594 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1596 0, cylin >> 8); 1597 1598 /* Send command. */ 1599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1600 return; 1601 } 1602 1603 /* 1604 * Send a 48-bit addressing command. The drive should be ready. 1605 * Assumes interrupts are blocked. 1606 */ 1607 void 1608 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1609 u_int64_t blkno, u_int16_t count) 1610 { 1611 struct atac_softc *atac = chp->ch_atac; 1612 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1613 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1614 1615 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1616 "count=%d\n", atac->atac_dev.dv_xname, 1617 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1618 DEBUG_FUNCS); 1619 1620 if (wdc->select) 1621 wdc->select(chp,drive); 1622 1623 /* Select drive, head, and addressing mode. */ 1624 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1625 (drive << 4) | WDSD_LBA); 1626 1627 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1628 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1629 0); 1630 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1631 0, count); 1632 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1633 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1634 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1635 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1636 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1637 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1638 } else { 1639 /* previous */ 1640 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1641 0); 1642 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1643 0, count >> 8); 1644 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1645 0, blkno >> 24); 1646 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1647 0, blkno >> 32); 1648 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1649 0, blkno >> 40); 1650 1651 /* current */ 1652 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1653 0); 1654 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1655 count); 1656 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1657 blkno); 1658 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1659 0, blkno >> 8); 1660 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1661 0, blkno >> 16); 1662 } 1663 1664 /* Send command. */ 1665 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1666 return; 1667 } 1668 1669 /* 1670 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1671 * tested by the caller. 1672 */ 1673 void 1674 wdccommandshort(struct ata_channel *chp, int drive, int command) 1675 { 1676 struct atac_softc *atac = chp->ch_atac; 1677 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1678 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1679 1680 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1681 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1682 DEBUG_FUNCS); 1683 1684 if (wdc->select) 1685 wdc->select(chp,drive); 1686 1687 /* Select drive. */ 1688 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1689 WDSD_IBM | (drive << 4)); 1690 1691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1692 } 1693 1694 static void 1695 __wdcerror(struct ata_channel *chp, const char *msg) 1696 { 1697 struct atac_softc *atac = chp->ch_atac; 1698 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1699 1700 if (xfer == NULL) 1701 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1702 msg); 1703 else 1704 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1705 chp->ch_channel, xfer->c_drive, msg); 1706 } 1707 1708 /* 1709 * the bit bucket 1710 */ 1711 void 1712 wdcbit_bucket(struct ata_channel *chp, int size) 1713 { 1714 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1715 1716 for (; size >= 2; size -= 2) 1717 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1718 if (size) 1719 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1720 } 1721 1722 static void 1723 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1724 { 1725 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1726 1727 if (flags & DRIVE_NOSTREAM) { 1728 if (flags & DRIVE_CAP32) { 1729 bus_space_read_multi_4(wdr->data32iot, 1730 wdr->data32ioh, 0, bf, len >> 2); 1731 bf = (char *)bf + (len & ~3); 1732 len &= 3; 1733 } 1734 if (len) { 1735 bus_space_read_multi_2(wdr->cmd_iot, 1736 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1737 } 1738 } else { 1739 if (flags & DRIVE_CAP32) { 1740 bus_space_read_multi_stream_4(wdr->data32iot, 1741 wdr->data32ioh, 0, bf, len >> 2); 1742 bf = (char *)bf + (len & ~3); 1743 len &= 3; 1744 } 1745 if (len) { 1746 bus_space_read_multi_stream_2(wdr->cmd_iot, 1747 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1748 } 1749 } 1750 } 1751 1752 static void 1753 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1754 { 1755 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1756 1757 if (flags & DRIVE_NOSTREAM) { 1758 if (flags & DRIVE_CAP32) { 1759 bus_space_write_multi_4(wdr->data32iot, 1760 wdr->data32ioh, 0, bf, len >> 2); 1761 bf = (char *)bf + (len & ~3); 1762 len &= 3; 1763 } 1764 if (len) { 1765 bus_space_write_multi_2(wdr->cmd_iot, 1766 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1767 } 1768 } else { 1769 if (flags & DRIVE_CAP32) { 1770 bus_space_write_multi_stream_4(wdr->data32iot, 1771 wdr->data32ioh, 0, bf, len >> 2); 1772 bf = (char *)bf + (len & ~3); 1773 len &= 3; 1774 } 1775 if (len) { 1776 bus_space_write_multi_stream_2(wdr->cmd_iot, 1777 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1778 } 1779 } 1780 } 1781
Indexes created Fri Sep 26 20:09:58 GMT 2025