wdc.c revision 1.230
1 /* $NetBSD: wdc.c,v 1.230 2005/08/29 19:30:07 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.230 2005/08/29 19:30:07 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 /* 123 * timeout when waiting for BSY to deassert when probing. 124 * set to 5s. From the standards this could be up to 31, but we can't 125 * wait that much at boot time, and 5s seems to be enouth. 126 */ 127 #define WDC_PROBE_WAIT 5 128 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, /* wdc_ata_bio */ 137 NULL, /* wdc_reset_drive */ 138 wdc_reset_channel, 139 wdc_exec_command, 140 NULL, /* ata_get_params */ 141 NULL, /* wdc_ata_addref */ 142 NULL, /* wdc_ata_delref */ 143 NULL /* ata_kill_pending */ 144 }; 145 #endif 146 147 /* Flags to wdcreset(). */ 148 #define RESET_POLL 1 149 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 150 151 static int wdcprobe1(struct ata_channel *, int); 152 static int wdcreset(struct ata_channel *, int); 153 static void __wdcerror(struct ata_channel *, const char *); 154 static int __wdcwait_reset(struct ata_channel *, int, int); 155 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 156 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 157 static void __wdccommand_kill_xfer(struct ata_channel *, 158 struct ata_xfer *, int); 159 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 160 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 161 static int __wdcwait(struct ata_channel *, int, int, int); 162 163 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 164 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 165 166 #define DEBUG_INTR 0x01 167 #define DEBUG_XFERS 0x02 168 #define DEBUG_STATUS 0x04 169 #define DEBUG_FUNCS 0x08 170 #define DEBUG_PROBE 0x10 171 #define DEBUG_DETACH 0x20 172 #define DEBUG_DELAY 0x40 173 #ifdef ATADEBUG 174 extern int atadebug_mask; /* init'ed in ata.c */ 175 int wdc_nxfer = 0; 176 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 177 #else 178 #define ATADEBUG_PRINT(args, level) 179 #endif 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct ata_channel *chp) 186 { 187 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 188 189 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 190 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 191 } 192 193 /* 194 * Allocate a wdc_regs array, based on the number of channels. 195 */ 196 void 197 wdc_allocate_regs(struct wdc_softc *wdc) 198 { 199 200 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 201 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 202 } 203 204 /* Test to see controller with at last one attached drive is there. 205 * Returns a bit for each possible drive found (0x01 for drive 0, 206 * 0x02 for drive 1). 207 * Logic: 208 * - If a status register is at 0xff, assume there is no drive here 209 * (ISA has pull-up resistors). Similarly if the status register has 210 * the value we last wrote to the bus (for IDE interfaces without pullups). 211 * If no drive at all -> return. 212 * - reset the controller, wait for it to complete (may take up to 31s !). 213 * If timeout -> return. 214 * - test ATA/ATAPI signatures. If at last one drive found -> return. 215 * - try an ATA command on the master. 216 */ 217 218 static void 219 wdc_drvprobe(struct ata_channel *chp) 220 { 221 struct ataparams params; 222 struct atac_softc *atac = chp->ch_atac; 223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 225 u_int8_t st0 = 0, st1 = 0; 226 int i, error, s; 227 228 if (wdcprobe1(chp, 0) == 0) { 229 /* No drives, abort the attach here. */ 230 return; 231 } 232 233 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 234 for (i = 0; i < mstohz(3000); i++) { 235 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 236 if (wdc->select) 237 wdc->select(chp,0); 238 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 239 0, WDSD_IBM); 240 delay(10); /* 400ns delay */ 241 st0 = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_status], 0); 243 } 244 245 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 246 if (wdc->select) 247 wdc->select(chp,1); 248 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 249 0, WDSD_IBM | 0x10); 250 delay(10); /* 400ns delay */ 251 st1 = bus_space_read_1(wdr->cmd_iot, 252 wdr->cmd_iohs[wd_status], 0); 253 } 254 255 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 256 == 0 || 257 (st0 & WDCS_DRDY)) && 258 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 259 == 0 || 260 (st1 & WDCS_DRDY))) 261 break; 262 tsleep(¶ms, PRIBIO, "atadrdy", 1); 263 } 264 s = splbio(); 265 if ((st0 & WDCS_DRDY) == 0) 266 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 267 if ((st1 & WDCS_DRDY) == 0) 268 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 269 splx(s); 270 271 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 272 atac->atac_dev.dv_xname, 273 chp->ch_channel, st0, st1), DEBUG_PROBE); 274 275 /* Wait a bit, some devices are weird just after a reset. */ 276 delay(5000); 277 278 for (i = 0; i < 2; i++) { 279 /* XXX This should be done by other code. */ 280 chp->ch_drive[i].chnl_softc = chp; 281 chp->ch_drive[i].drive = i; 282 283 /* 284 * Init error counter so that an error withing the first xfers 285 * will trigger a downgrade 286 */ 287 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 288 289 /* If controller can't do 16bit flag the drives as 32bit */ 290 if ((atac->atac_cap & 291 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 292 s = splbio(); 293 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 294 splx(s); 295 } 296 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 297 continue; 298 299 /* Shortcut in case we've been shutdown */ 300 if (chp->ch_flags & ATACH_SHUTDOWN) 301 return; 302 303 /* 304 * Issue an identify, to try to detect ghosts. 305 * Note that we can't use interrupts here, because if there 306 * is no devices, we will get a command aborted without 307 * interrupts. 308 */ 309 error = ata_get_params(&chp->ch_drive[i], 310 AT_WAIT | AT_POLL, ¶ms); 311 if (error != CMD_OK) { 312 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 313 314 /* Shortcut in case we've been shutdown */ 315 if (chp->ch_flags & ATACH_SHUTDOWN) 316 return; 317 318 error = ata_get_params(&chp->ch_drive[i], 319 AT_WAIT | AT_POLL, ¶ms); 320 } 321 if (error == CMD_OK) { 322 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 323 s = splbio(); 324 /* XXXJRT ch_ndrive */ 325 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 326 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 327 splx(s); 328 } else { 329 s = splbio(); 330 chp->ch_drive[i].drive_flags &= 331 ~(DRIVE_ATA | DRIVE_ATAPI); 332 splx(s); 333 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 atac->atac_dev.dv_xname, 335 chp->ch_channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 if (wdc->select) 344 wdc->select(chp,i); 345 bus_space_write_1(wdr->cmd_iot, 346 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 347 delay(10); /* 400ns delay */ 348 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 349 0, 0x58); 350 bus_space_write_1(wdr->cmd_iot, 351 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 352 if (bus_space_read_1(wdr->cmd_iot, 353 wdr->cmd_iohs[wd_error], 0) == 0x58 || 354 bus_space_read_1(wdr->cmd_iot, 355 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 356 ATADEBUG_PRINT(("%s:%d:%d: register " 357 "writability failed\n", 358 atac->atac_dev.dv_xname, 359 chp->ch_channel, i), DEBUG_PROBE); 360 s = splbio(); 361 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 362 splx(s); 363 continue; 364 } 365 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 366 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 367 atac->atac_dev.dv_xname, 368 chp->ch_channel, i), DEBUG_PROBE); 369 s = splbio(); 370 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 371 splx(s); 372 continue; 373 } 374 bus_space_write_1(wdr->cmd_iot, 375 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 376 delay(10); /* 400ns delay */ 377 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 378 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 379 atac->atac_dev.dv_xname, 380 chp->ch_channel, i), DEBUG_PROBE); 381 s = splbio(); 382 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 383 splx(s); 384 } else { 385 s = splbio(); 386 /* XXXJRT ch_ndrive */ 387 chp->ch_drive[0].drive_flags &= 388 ~(DRIVE_ATA | DRIVE_ATAPI); 389 chp->ch_drive[1].drive_flags &= 390 ~(DRIVE_ATA | DRIVE_ATAPI); 391 splx(s); 392 } 393 } 394 } 395 } 396 397 int 398 wdcprobe(struct ata_channel *chp) 399 { 400 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 401 /* default reset method */ 402 if (wdc->reset == NULL) 403 wdc->reset = wdc_do_reset; 404 405 return (wdcprobe1(chp, 1)); 406 } 407 408 static int 409 wdcprobe1(struct ata_channel *chp, int poll) 410 { 411 struct atac_softc *atac = chp->ch_atac; 412 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 413 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 414 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 415 u_int8_t ret_value = 0x03; 416 u_int8_t drive; 417 int s; 418 int wdc_probe_count = 419 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 420 421 /* 422 * Sanity check to see if the wdc channel responds at all. 423 */ 424 425 s = splbio(); 426 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 427 while (wdc_probe_count-- > 0) { 428 if (wdc->select) 429 wdc->select(chp,0); 430 431 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 432 0, WDSD_IBM); 433 delay(10); /* 400ns delay */ 434 st0 = bus_space_read_1(wdr->cmd_iot, 435 wdr->cmd_iohs[wd_status], 0); 436 437 if (wdc->select) 438 wdc->select(chp,1); 439 440 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 441 0, WDSD_IBM | 0x10); 442 delay(10); /* 400ns delay */ 443 st1 = bus_space_read_1(wdr->cmd_iot, 444 wdr->cmd_iohs[wd_status], 0); 445 if ((st0 & WDCS_BSY) == 0) 446 break; 447 } 448 449 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 450 atac->atac_dev.dv_xname, 451 chp->ch_channel, st0, st1), DEBUG_PROBE); 452 453 if (st0 == 0xff || st0 == WDSD_IBM) 454 ret_value &= ~0x01; 455 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 456 ret_value &= ~0x02; 457 /* Register writability test, drive 0. */ 458 if (ret_value & 0x01) { 459 if (wdc->select) 460 wdc->select(chp,0); 461 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 462 0, WDSD_IBM); 463 bus_space_write_1(wdr->cmd_iot, 464 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 465 cl = bus_space_read_1(wdr->cmd_iot, 466 wdr->cmd_iohs[wd_cyl_lo], 0); 467 if (cl != 0x02) { 468 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 469 "got 0x%x != 0x02\n", 470 atac->atac_dev.dv_xname, 471 chp->ch_channel, cl), 472 DEBUG_PROBE); 473 ret_value &= ~0x01; 474 } 475 bus_space_write_1(wdr->cmd_iot, 476 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 477 cl = bus_space_read_1(wdr->cmd_iot, 478 wdr->cmd_iohs[wd_cyl_lo], 0); 479 if (cl != 0x01) { 480 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 481 "got 0x%x != 0x01\n", 482 atac->atac_dev.dv_xname, 483 chp->ch_channel, cl), 484 DEBUG_PROBE); 485 ret_value &= ~0x01; 486 } 487 bus_space_write_1(wdr->cmd_iot, 488 wdr->cmd_iohs[wd_sector], 0, 0x01); 489 cl = bus_space_read_1(wdr->cmd_iot, 490 wdr->cmd_iohs[wd_sector], 0); 491 if (cl != 0x01) { 492 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 493 "got 0x%x != 0x01\n", 494 atac->atac_dev.dv_xname, 495 chp->ch_channel, cl), 496 DEBUG_PROBE); 497 ret_value &= ~0x01; 498 } 499 bus_space_write_1(wdr->cmd_iot, 500 wdr->cmd_iohs[wd_sector], 0, 0x02); 501 cl = bus_space_read_1(wdr->cmd_iot, 502 wdr->cmd_iohs[wd_sector], 0); 503 if (cl != 0x02) { 504 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 505 "got 0x%x != 0x02\n", 506 atac->atac_dev.dv_xname, 507 chp->ch_channel, cl), 508 DEBUG_PROBE); 509 ret_value &= ~0x01; 510 } 511 cl = bus_space_read_1(wdr->cmd_iot, 512 wdr->cmd_iohs[wd_cyl_lo], 0); 513 if (cl != 0x01) { 514 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 515 "got 0x%x != 0x01\n", 516 atac->atac_dev.dv_xname, 517 chp->ch_channel, cl), 518 DEBUG_PROBE); 519 ret_value &= ~0x01; 520 } 521 } 522 /* Register writability test, drive 1. */ 523 if (ret_value & 0x02) { 524 if (wdc->select) 525 wdc->select(chp,1); 526 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 527 0, WDSD_IBM | 0x10); 528 bus_space_write_1(wdr->cmd_iot, 529 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 530 cl = bus_space_read_1(wdr->cmd_iot, 531 wdr->cmd_iohs[wd_cyl_lo], 0); 532 if (cl != 0x02) { 533 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 534 "got 0x%x != 0x02\n", 535 atac->atac_dev.dv_xname, 536 chp->ch_channel, cl), 537 DEBUG_PROBE); 538 ret_value &= ~0x02; 539 } 540 bus_space_write_1(wdr->cmd_iot, 541 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 542 cl = bus_space_read_1(wdr->cmd_iot, 543 wdr->cmd_iohs[wd_cyl_lo], 0); 544 if (cl != 0x01) { 545 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 546 "got 0x%x != 0x01\n", 547 atac->atac_dev.dv_xname, 548 chp->ch_channel, cl), 549 DEBUG_PROBE); 550 ret_value &= ~0x02; 551 } 552 bus_space_write_1(wdr->cmd_iot, 553 wdr->cmd_iohs[wd_sector], 0, 0x01); 554 cl = bus_space_read_1(wdr->cmd_iot, 555 wdr->cmd_iohs[wd_sector], 0); 556 if (cl != 0x01) { 557 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 558 "got 0x%x != 0x01\n", 559 atac->atac_dev.dv_xname, 560 chp->ch_channel, cl), 561 DEBUG_PROBE); 562 ret_value &= ~0x02; 563 } 564 bus_space_write_1(wdr->cmd_iot, 565 wdr->cmd_iohs[wd_sector], 0, 0x02); 566 cl = bus_space_read_1(wdr->cmd_iot, 567 wdr->cmd_iohs[wd_sector], 0); 568 if (cl != 0x02) { 569 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 570 "got 0x%x != 0x02\n", 571 atac->atac_dev.dv_xname, 572 chp->ch_channel, cl), 573 DEBUG_PROBE); 574 ret_value &= ~0x02; 575 } 576 cl = bus_space_read_1(wdr->cmd_iot, 577 wdr->cmd_iohs[wd_cyl_lo], 0); 578 if (cl != 0x01) { 579 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 580 "got 0x%x != 0x01\n", 581 atac->atac_dev.dv_xname, 582 chp->ch_channel, cl), 583 DEBUG_PROBE); 584 ret_value &= ~0x02; 585 } 586 } 587 588 if (ret_value == 0) { 589 splx(s); 590 return 0; 591 } 592 } 593 594 595 #if 0 /* XXX this break some ATA or ATAPI devices */ 596 /* 597 * reset bus. Also send an ATAPI_RESET to devices, in case there are 598 * ATAPI device out there which don't react to the bus reset 599 */ 600 if (ret_value & 0x01) { 601 if (wdc->select) 602 wdc->select(chp,0); 603 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 604 0, WDSD_IBM); 605 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 606 ATAPI_SOFT_RESET); 607 } 608 if (ret_value & 0x02) { 609 if (wdc->select) 610 wdc->select(chp,0); 611 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 612 0, WDSD_IBM | 0x10); 613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 614 ATAPI_SOFT_RESET); 615 } 616 617 delay(5000); 618 #endif 619 620 wdc->reset(chp, RESET_POLL); 621 DELAY(2000); 622 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 623 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 624 splx(s); 625 626 ret_value = __wdcwait_reset(chp, ret_value, poll); 627 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 628 atac->atac_dev.dv_xname, chp->ch_channel, 629 ret_value), DEBUG_PROBE); 630 631 /* if reset failed, there's nothing here */ 632 if (ret_value == 0) 633 return 0; 634 635 /* 636 * Test presence of drives. First test register signatures looking 637 * for ATAPI devices. If it's not an ATAPI and reset said there may 638 * be something here assume it's ATA or OLD. Ghost will be killed 639 * later in attach routine. 640 */ 641 for (drive = 0; drive < 2; drive++) { 642 if ((ret_value & (0x01 << drive)) == 0) 643 continue; 644 if (wdc->select) 645 wdc->select(chp,drive); 646 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 647 WDSD_IBM | (drive << 4)); 648 delay(10); /* 400ns delay */ 649 /* Save registers contents */ 650 sc = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_seccnt], 0); 652 sn = bus_space_read_1(wdr->cmd_iot, 653 wdr->cmd_iohs[wd_sector], 0); 654 cl = bus_space_read_1(wdr->cmd_iot, 655 wdr->cmd_iohs[wd_cyl_lo], 0); 656 ch = bus_space_read_1(wdr->cmd_iot, 657 wdr->cmd_iohs[wd_cyl_hi], 0); 658 659 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 660 "cl=0x%x ch=0x%x\n", 661 atac->atac_dev.dv_xname, 662 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 663 /* 664 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 665 * we get wrong values here, so ignore it. 666 */ 667 s = splbio(); 668 if (cl == 0x14 && ch == 0xeb) { 669 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 670 } else { 671 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 672 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 673 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 674 } 675 splx(s); 676 } 677 return (ret_value); 678 } 679 680 void 681 wdcattach(struct ata_channel *chp) 682 { 683 struct atac_softc *atac = chp->ch_atac; 684 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 685 686 /* 687 * Start out assuming 2 drives. This may change as we probe 688 * drives. 689 */ 690 chp->ch_ndrive = 2; 691 692 /* default data transfer methods */ 693 if (wdc->datain_pio == NULL) 694 wdc->datain_pio = wdc_datain_pio; 695 if (wdc->dataout_pio == NULL) 696 wdc->dataout_pio = wdc_dataout_pio; 697 /* default reset method */ 698 if (wdc->reset == NULL) 699 wdc->reset = wdc_do_reset; 700 701 /* initialise global data */ 702 if (atac->atac_bustype_ata == NULL) 703 atac->atac_bustype_ata = &wdc_ata_bustype; 704 if (atac->atac_probe == NULL) 705 atac->atac_probe = wdc_drvprobe; 706 #if NATAPIBUS > 0 707 if (atac->atac_atapibus_attach == NULL) 708 atac->atac_atapibus_attach = wdc_atapibus_attach; 709 #endif 710 711 ata_channel_attach(chp); 712 } 713 714 int 715 wdcactivate(struct device *self, enum devact act) 716 { 717 struct atac_softc *atac = (struct atac_softc *) self; 718 int s, i, error = 0; 719 720 s = splbio(); 721 switch (act) { 722 case DVACT_ACTIVATE: 723 error = EOPNOTSUPP; 724 break; 725 726 case DVACT_DEACTIVATE: 727 for (i = 0; i < atac->atac_nchannels; i++) { 728 error = 729 config_deactivate(atac->atac_channels[i]->atabus); 730 if (error) 731 break; 732 } 733 break; 734 } 735 splx(s); 736 return (error); 737 } 738 739 int 740 wdcdetach(struct device *self, int flags) 741 { 742 struct atac_softc *atac = (struct atac_softc *) self; 743 struct ata_channel *chp; 744 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 745 int i, error = 0; 746 747 for (i = 0; i < atac->atac_nchannels; i++) { 748 chp = atac->atac_channels[i]; 749 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 750 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 751 DEBUG_DETACH); 752 error = config_detach(chp->atabus, flags); 753 if (error) 754 break; 755 } 756 if (adapt->adapt_refcnt != 0) { 757 #ifdef DIAGNOSTIC 758 printf("wdcdetach: refcnt should be 0 here??\n"); 759 #endif 760 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 761 } 762 return (error); 763 } 764 765 /* restart an interrupted I/O */ 766 void 767 wdcrestart(void *v) 768 { 769 struct ata_channel *chp = v; 770 int s; 771 772 s = splbio(); 773 atastart(chp); 774 splx(s); 775 } 776 777 778 /* 779 * Interrupt routine for the controller. Acknowledge the interrupt, check for 780 * errors on the current operation, mark it done if necessary, and start the 781 * next request. Also check for a partially done transfer, and continue with 782 * the next chunk if so. 783 */ 784 int 785 wdcintr(void *arg) 786 { 787 struct ata_channel *chp = arg; 788 struct atac_softc *atac = chp->ch_atac; 789 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 790 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 791 struct ata_xfer *xfer; 792 int ret; 793 794 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 795 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 796 DEBUG_INTR); 797 return (0); 798 } 799 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 800 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 801 /* try to clear the pending interrupt anyway */ 802 (void)bus_space_read_1(wdr->cmd_iot, 803 wdr->cmd_iohs[wd_status], 0); 804 return (0); 805 } 806 807 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 808 xfer = chp->ch_queue->active_xfer; 809 #ifdef DIAGNOSTIC 810 if (xfer == NULL) 811 panic("wdcintr: no xfer"); 812 #endif 813 if (chp->ch_flags & ATACH_DMA_WAIT) { 814 wdc->dma_status = 815 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 816 xfer->c_drive, WDC_DMAEND_END); 817 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 818 /* IRQ not for us, not detected by DMA engine */ 819 return 0; 820 } 821 chp->ch_flags &= ~ATACH_DMA_WAIT; 822 } 823 chp->ch_flags &= ~ATACH_IRQ_WAIT; 824 ret = xfer->c_intr(chp, xfer, 1); 825 if (ret == 0) /* irq was not for us, still waiting for irq */ 826 chp->ch_flags |= ATACH_IRQ_WAIT; 827 return (ret); 828 } 829 830 /* Put all disk in RESET state */ 831 void 832 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 833 { 834 struct ata_channel *chp = drvp->chnl_softc; 835 struct atac_softc *atac = chp->ch_atac; 836 837 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 838 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 839 DEBUG_FUNCS); 840 841 ata_reset_channel(chp, flags); 842 } 843 844 void 845 wdc_reset_channel(struct ata_channel *chp, int flags) 846 { 847 TAILQ_HEAD(, ata_xfer) reset_xfer; 848 struct ata_xfer *xfer, *next_xfer; 849 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 850 851 TAILQ_INIT(&reset_xfer); 852 853 chp->ch_flags &= ~ATACH_IRQ_WAIT; 854 855 /* 856 * if the current command if on an ATAPI device, issue a 857 * ATAPI_SOFT_RESET 858 */ 859 xfer = chp->ch_queue->active_xfer; 860 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 861 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 862 if (flags & AT_WAIT) 863 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 864 else 865 delay(1000); 866 } 867 868 /* reset the channel */ 869 if (flags & AT_WAIT) 870 (void) wdcreset(chp, RESET_SLEEP); 871 else 872 (void) wdcreset(chp, RESET_POLL); 873 874 /* 875 * wait a bit after reset; in case the DMA engines needs some time 876 * to recover. 877 */ 878 if (flags & AT_WAIT) 879 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 880 else 881 delay(1000); 882 /* 883 * look for pending xfers. If we have a shared queue, we'll also reset 884 * the other channel if the current xfer is running on it. 885 * Then we'll dequeue only the xfers for this channel. 886 */ 887 if ((flags & AT_RST_NOCMD) == 0) { 888 /* 889 * move all xfers queued for this channel to the reset queue, 890 * and then process the current xfer and then the reset queue. 891 * We have to use a temporary queue because c_kill_xfer() 892 * may requeue commands. 893 */ 894 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 895 xfer != NULL; xfer = next_xfer) { 896 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 897 if (xfer->c_chp != chp) 898 continue; 899 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 900 xfer, c_xferchain); 901 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 902 } 903 xfer = chp->ch_queue->active_xfer; 904 if (xfer) { 905 if (xfer->c_chp != chp) 906 ata_reset_channel(xfer->c_chp, flags); 907 else { 908 callout_stop(&chp->ch_callout); 909 /* 910 * If we're waiting for DMA, stop the 911 * DMA engine 912 */ 913 if (chp->ch_flags & ATACH_DMA_WAIT) { 914 (*wdc->dma_finish)( 915 wdc->dma_arg, 916 chp->ch_channel, 917 xfer->c_drive, 918 WDC_DMAEND_ABRT_QUIET); 919 chp->ch_flags &= ~ATACH_DMA_WAIT; 920 } 921 chp->ch_queue->active_xfer = NULL; 922 if ((flags & AT_RST_EMERG) == 0) 923 xfer->c_kill_xfer( 924 chp, xfer, KILL_RESET); 925 } 926 } 927 928 for (xfer = TAILQ_FIRST(&reset_xfer); 929 xfer != NULL; xfer = next_xfer) { 930 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 931 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 932 if ((flags & AT_RST_EMERG) == 0) 933 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 934 } 935 } 936 } 937 938 static int 939 wdcreset(struct ata_channel *chp, int poll) 940 { 941 struct atac_softc *atac = chp->ch_atac; 942 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 943 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 944 int drv_mask1, drv_mask2; 945 946 wdc->reset(chp, poll); 947 948 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 949 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 950 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 951 (poll == RESET_SLEEP) ? 0 : 1); 952 if (drv_mask2 != drv_mask1) { 953 printf("%s channel %d: reset failed for", 954 atac->atac_dev.dv_xname, chp->ch_channel); 955 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 956 printf(" drive 0"); 957 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 958 printf(" drive 1"); 959 printf("\n"); 960 } 961 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 962 return (drv_mask1 != drv_mask2) ? 1 : 0; 963 } 964 965 void 966 wdc_do_reset(struct ata_channel *chp, int poll) 967 { 968 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 969 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 970 int s = 0; 971 972 if (poll != RESET_SLEEP) 973 s = splbio(); 974 if (wdc->select) 975 wdc->select(chp,0); 976 /* master */ 977 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 978 delay(10); /* 400ns delay */ 979 /* assert SRST, wait for reset to complete */ 980 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 981 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 982 delay(2000); 983 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 984 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 985 WDCTL_4BIT | WDCTL_IDS); 986 delay(10); /* 400ns delay */ 987 if (poll != RESET_SLEEP) { 988 if (wdc->irqack) 989 wdc->irqack(chp); 990 splx(s); 991 } 992 } 993 994 static int 995 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 996 { 997 struct atac_softc *atac = chp->ch_atac; 998 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 999 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1000 int timeout, nloop; 1001 u_int8_t st0 = 0, st1 = 0; 1002 #ifdef ATADEBUG 1003 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1004 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1005 #endif 1006 1007 if (poll) 1008 nloop = WDCNDELAY_RST; 1009 else 1010 nloop = WDC_RESET_WAIT * hz / 1000; 1011 /* wait for BSY to deassert */ 1012 for (timeout = 0; timeout < nloop; timeout++) { 1013 if ((drv_mask & 0x01) != 0) { 1014 if (wdc && wdc->select) 1015 wdc->select(chp,0); 1016 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1017 0, WDSD_IBM); /* master */ 1018 delay(10); 1019 st0 = bus_space_read_1(wdr->cmd_iot, 1020 wdr->cmd_iohs[wd_status], 0); 1021 #ifdef ATADEBUG 1022 sc0 = bus_space_read_1(wdr->cmd_iot, 1023 wdr->cmd_iohs[wd_seccnt], 0); 1024 sn0 = bus_space_read_1(wdr->cmd_iot, 1025 wdr->cmd_iohs[wd_sector], 0); 1026 cl0 = bus_space_read_1(wdr->cmd_iot, 1027 wdr->cmd_iohs[wd_cyl_lo], 0); 1028 ch0 = bus_space_read_1(wdr->cmd_iot, 1029 wdr->cmd_iohs[wd_cyl_hi], 0); 1030 #endif 1031 } 1032 if ((drv_mask & 0x02) != 0) { 1033 if (wdc && wdc->select) 1034 wdc->select(chp,1); 1035 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1036 0, WDSD_IBM | 0x10); /* slave */ 1037 delay(10); 1038 st1 = bus_space_read_1(wdr->cmd_iot, 1039 wdr->cmd_iohs[wd_status], 0); 1040 #ifdef ATADEBUG 1041 sc1 = bus_space_read_1(wdr->cmd_iot, 1042 wdr->cmd_iohs[wd_seccnt], 0); 1043 sn1 = bus_space_read_1(wdr->cmd_iot, 1044 wdr->cmd_iohs[wd_sector], 0); 1045 cl1 = bus_space_read_1(wdr->cmd_iot, 1046 wdr->cmd_iohs[wd_cyl_lo], 0); 1047 ch1 = bus_space_read_1(wdr->cmd_iot, 1048 wdr->cmd_iohs[wd_cyl_hi], 0); 1049 #endif 1050 } 1051 1052 if ((drv_mask & 0x01) == 0) { 1053 /* no master */ 1054 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1055 /* No master, slave is ready, it's done */ 1056 goto end; 1057 } 1058 } else if ((drv_mask & 0x02) == 0) { 1059 /* no slave */ 1060 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1061 /* No slave, master is ready, it's done */ 1062 goto end; 1063 } 1064 } else { 1065 /* Wait for both master and slave to be ready */ 1066 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1067 goto end; 1068 } 1069 } 1070 if (poll) 1071 delay(WDCDELAY); 1072 else 1073 tsleep(&nloop, PRIBIO, "atarst", 1); 1074 } 1075 /* Reset timed out. Maybe it's because drv_mask was not right */ 1076 if (st0 & WDCS_BSY) 1077 drv_mask &= ~0x01; 1078 if (st1 & WDCS_BSY) 1079 drv_mask &= ~0x02; 1080 end: 1081 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1082 "cl=0x%x ch=0x%x\n", 1083 atac->atac_dev.dv_xname, 1084 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1085 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1086 "cl=0x%x ch=0x%x\n", 1087 atac->atac_dev.dv_xname, 1088 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1089 1090 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1091 atac->atac_dev.dv_xname, chp->ch_channel, 1092 st0, st1), DEBUG_PROBE); 1093 1094 return drv_mask; 1095 } 1096 1097 /* 1098 * Wait for a drive to be !BSY, and have mask in its status register. 1099 * return -1 for a timeout after "timeout" ms. 1100 */ 1101 static int 1102 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1103 { 1104 struct atac_softc *atac = chp->ch_atac; 1105 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1106 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1107 u_char status; 1108 int xtime = 0; 1109 1110 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1111 atac->atac_dev.dv_xname, 1112 chp->ch_channel), DEBUG_STATUS); 1113 chp->ch_error = 0; 1114 1115 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1116 1117 for (;;) { 1118 chp->ch_status = status = 1119 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1120 if ((status & (WDCS_BSY | mask)) == bits) 1121 break; 1122 if (++xtime > timeout) { 1123 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1124 "status %x error %x (mask 0x%x bits 0x%x)\n", 1125 xtime, status, 1126 bus_space_read_1(wdr->cmd_iot, 1127 wdr->cmd_iohs[wd_error], 0), mask, bits), 1128 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1129 return(WDCWAIT_TOUT); 1130 } 1131 delay(WDCDELAY); 1132 } 1133 #ifdef ATADEBUG 1134 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1135 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1136 #endif 1137 if (status & WDCS_ERR) 1138 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_error], 0); 1140 #ifdef WDCNDELAY_DEBUG 1141 /* After autoconfig, there should be no long delays. */ 1142 if (!cold && xtime > WDCNDELAY_DEBUG) { 1143 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1144 if (xfer == NULL) 1145 printf("%s channel %d: warning: busy-wait took %dus\n", 1146 atac->atac_dev.dv_xname, chp->ch_channel, 1147 WDCDELAY * xtime); 1148 else 1149 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1150 atac->atac_dev.dv_xname, chp->ch_channel, 1151 xfer->drive, 1152 WDCDELAY * xtime); 1153 } 1154 #endif 1155 return(WDCWAIT_OK); 1156 } 1157 1158 /* 1159 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1160 * thread if possible 1161 */ 1162 int 1163 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1164 { 1165 int error, i, timeout_hz = mstohz(timeout); 1166 1167 if (timeout_hz == 0 || 1168 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1169 error = __wdcwait(chp, mask, bits, timeout); 1170 else { 1171 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1172 if (error != 0) { 1173 if ((chp->ch_flags & ATACH_TH_RUN) || 1174 (flags & AT_WAIT)) { 1175 /* 1176 * we're running in the channel thread 1177 * or some userland thread context 1178 */ 1179 for (i = 0; i < timeout_hz; i++) { 1180 if (__wdcwait(chp, mask, bits, 1181 WDCDELAY_POLL) == 0) { 1182 error = 0; 1183 break; 1184 } 1185 tsleep(&chp, PRIBIO, "atapoll", 1); 1186 } 1187 } else { 1188 /* 1189 * we're probably in interrupt context, 1190 * ask the thread to come back here 1191 */ 1192 #ifdef DIAGNOSTIC 1193 if (chp->ch_queue->queue_freeze > 0) 1194 panic("wdcwait: queue_freeze"); 1195 #endif 1196 chp->ch_queue->queue_freeze++; 1197 wakeup(&chp->ch_thread); 1198 return(WDCWAIT_THR); 1199 } 1200 } 1201 } 1202 return (error); 1203 } 1204 1205 1206 /* 1207 * Busy-wait for DMA to complete 1208 */ 1209 int 1210 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1211 { 1212 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1213 int xtime; 1214 1215 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1216 wdc->dma_status = 1217 (*wdc->dma_finish)(wdc->dma_arg, 1218 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1219 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1220 return 0; 1221 delay(WDCDELAY); 1222 } 1223 /* timeout, force a DMA halt */ 1224 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1225 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1226 return 1; 1227 } 1228 1229 void 1230 wdctimeout(void *arg) 1231 { 1232 struct ata_channel *chp = (struct ata_channel *)arg; 1233 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1234 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1235 int s; 1236 1237 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1238 1239 s = splbio(); 1240 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1241 __wdcerror(chp, "lost interrupt"); 1242 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1243 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1244 xfer->c_bcount, 1245 xfer->c_skip); 1246 if (chp->ch_flags & ATACH_DMA_WAIT) { 1247 wdc->dma_status = 1248 (*wdc->dma_finish)(wdc->dma_arg, 1249 chp->ch_channel, xfer->c_drive, 1250 WDC_DMAEND_ABRT); 1251 chp->ch_flags &= ~ATACH_DMA_WAIT; 1252 } 1253 /* 1254 * Call the interrupt routine. If we just missed an interrupt, 1255 * it will do what's needed. Else, it will take the needed 1256 * action (reset the device). 1257 * Before that we need to reinstall the timeout callback, 1258 * in case it will miss another irq while in this transfer 1259 * We arbitray chose it to be 1s 1260 */ 1261 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1262 xfer->c_flags |= C_TIMEOU; 1263 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1264 xfer->c_intr(chp, xfer, 1); 1265 } else 1266 __wdcerror(chp, "missing untimeout"); 1267 splx(s); 1268 } 1269 1270 int 1271 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1272 { 1273 struct ata_channel *chp = drvp->chnl_softc; 1274 struct atac_softc *atac = chp->ch_atac; 1275 struct ata_xfer *xfer; 1276 int s, ret; 1277 1278 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1279 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1280 DEBUG_FUNCS); 1281 1282 /* set up an xfer and queue. Wait for completion */ 1283 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1284 ATAXF_NOSLEEP); 1285 if (xfer == NULL) { 1286 return ATACMD_TRY_AGAIN; 1287 } 1288 1289 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1290 ata_c->flags |= AT_POLL; 1291 if (ata_c->flags & AT_POLL) 1292 xfer->c_flags |= C_POLL; 1293 if (ata_c->flags & AT_WAIT) 1294 xfer->c_flags |= C_WAIT; 1295 xfer->c_drive = drvp->drive; 1296 xfer->c_databuf = ata_c->data; 1297 xfer->c_bcount = ata_c->bcount; 1298 xfer->c_cmd = ata_c; 1299 xfer->c_start = __wdccommand_start; 1300 xfer->c_intr = __wdccommand_intr; 1301 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1302 1303 s = splbio(); 1304 ata_exec_xfer(chp, xfer); 1305 #ifdef DIAGNOSTIC 1306 if ((ata_c->flags & AT_POLL) != 0 && 1307 (ata_c->flags & AT_DONE) == 0) 1308 panic("wdc_exec_command: polled command not done"); 1309 #endif 1310 if (ata_c->flags & AT_DONE) { 1311 ret = ATACMD_COMPLETE; 1312 } else { 1313 if (ata_c->flags & AT_WAIT) { 1314 while ((ata_c->flags & AT_DONE) == 0) { 1315 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1316 } 1317 ret = ATACMD_COMPLETE; 1318 } else { 1319 ret = ATACMD_QUEUED; 1320 } 1321 } 1322 splx(s); 1323 return ret; 1324 } 1325 1326 static void 1327 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1328 { 1329 struct atac_softc *atac = chp->ch_atac; 1330 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1331 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1332 int drive = xfer->c_drive; 1333 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1334 struct ata_command *ata_c = xfer->c_cmd; 1335 1336 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1337 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1338 DEBUG_FUNCS); 1339 1340 if (wdc->select) 1341 wdc->select(chp,drive); 1342 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1343 WDSD_IBM | (drive << 4)); 1344 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1345 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1346 case WDCWAIT_OK: 1347 break; 1348 case WDCWAIT_TOUT: 1349 ata_c->flags |= AT_TIMEOU; 1350 __wdccommand_done(chp, xfer); 1351 return; 1352 case WDCWAIT_THR: 1353 return; 1354 } 1355 if (ata_c->flags & AT_POLL) { 1356 /* polled command, disable interrupts */ 1357 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1358 WDCTL_4BIT | WDCTL_IDS); 1359 } 1360 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1361 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1362 1363 if ((ata_c->flags & AT_POLL) == 0) { 1364 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1365 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1366 wdctimeout, chp); 1367 return; 1368 } 1369 /* 1370 * Polled command. Wait for drive ready or drq. Done in intr(). 1371 * Wait for at last 400ns for status bit to be valid. 1372 */ 1373 delay(10); /* 400ns delay */ 1374 __wdccommand_intr(chp, xfer, 0); 1375 } 1376 1377 static int 1378 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1379 { 1380 struct atac_softc *atac = chp->ch_atac; 1381 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1382 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1383 struct ata_command *ata_c = xfer->c_cmd; 1384 int bcount = ata_c->bcount; 1385 char *data = ata_c->data; 1386 int wflags; 1387 int drive_flags; 1388 1389 if (ata_c->r_command == WDCC_IDENTIFY || 1390 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1391 /* 1392 * The IDENTIFY data has been designed as an array of 1393 * u_int16_t, so we can byteswap it on the fly. 1394 * Historically it's what we have always done so keeping it 1395 * here ensure binary backward compatibility. 1396 */ 1397 drive_flags = DRIVE_NOSTREAM | 1398 chp->ch_drive[xfer->c_drive].drive_flags; 1399 } else { 1400 /* 1401 * Other data structure are opaque and should be transfered 1402 * as is. 1403 */ 1404 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1405 } 1406 1407 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1408 /* both wait and poll, we can tsleep here */ 1409 wflags = AT_WAIT | AT_POLL; 1410 } else { 1411 wflags = AT_POLL; 1412 } 1413 1414 again: 1415 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1416 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1417 DEBUG_INTR); 1418 /* 1419 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1420 * Reselect again, it doesn't hurt for others commands, and the time 1421 * penalty for the extra regiter write is acceptable, 1422 * wdc_exec_command() isn't called often (mosly for autoconfig) 1423 */ 1424 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1425 WDSD_IBM | (xfer->c_drive << 4)); 1426 if ((ata_c->flags & AT_XFDONE) != 0) { 1427 /* 1428 * We have completed a data xfer. The drive should now be 1429 * in its initial state 1430 */ 1431 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1432 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1433 wflags) == WDCWAIT_TOUT) { 1434 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1435 return 0; /* IRQ was not for us */ 1436 ata_c->flags |= AT_TIMEOU; 1437 } 1438 goto out; 1439 } 1440 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1441 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1442 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1443 return 0; /* IRQ was not for us */ 1444 ata_c->flags |= AT_TIMEOU; 1445 goto out; 1446 } 1447 if (wdc->irqack) 1448 wdc->irqack(chp); 1449 if (ata_c->flags & AT_READ) { 1450 if ((chp->ch_status & WDCS_DRQ) == 0) { 1451 ata_c->flags |= AT_TIMEOU; 1452 goto out; 1453 } 1454 wdc->datain_pio(chp, drive_flags, data, bcount); 1455 /* at this point the drive should be in its initial state */ 1456 ata_c->flags |= AT_XFDONE; 1457 /* XXX should read status register here ? */ 1458 } else if (ata_c->flags & AT_WRITE) { 1459 if ((chp->ch_status & WDCS_DRQ) == 0) { 1460 ata_c->flags |= AT_TIMEOU; 1461 goto out; 1462 } 1463 wdc->dataout_pio(chp, drive_flags, data, bcount); 1464 ata_c->flags |= AT_XFDONE; 1465 if ((ata_c->flags & AT_POLL) == 0) { 1466 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1467 callout_reset(&chp->ch_callout, 1468 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1469 return 1; 1470 } else { 1471 goto again; 1472 } 1473 } 1474 out: 1475 __wdccommand_done(chp, xfer); 1476 return 1; 1477 } 1478 1479 static void 1480 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1481 { 1482 struct atac_softc *atac = chp->ch_atac; 1483 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1484 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1485 struct ata_command *ata_c = xfer->c_cmd; 1486 1487 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1488 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1489 DEBUG_FUNCS); 1490 1491 1492 if (chp->ch_status & WDCS_DWF) 1493 ata_c->flags |= AT_DF; 1494 if (chp->ch_status & WDCS_ERR) { 1495 ata_c->flags |= AT_ERROR; 1496 ata_c->r_error = chp->ch_error; 1497 } 1498 if ((ata_c->flags & AT_READREG) != 0 && 1499 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1500 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1501 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1502 wdr->cmd_iohs[wd_sdh], 0); 1503 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1504 wdr->cmd_iohs[wd_seccnt], 0); 1505 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1506 wdr->cmd_iohs[wd_sector], 0); 1507 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1508 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1509 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1510 wdr->cmd_iohs[wd_cyl_lo], 0); 1511 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1512 wdr->cmd_iohs[wd_error], 0); 1513 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1514 wdr->cmd_iohs[wd_features], 0); 1515 } 1516 callout_stop(&chp->ch_callout); 1517 chp->ch_queue->active_xfer = NULL; 1518 if (ata_c->flags & AT_POLL) { 1519 /* enable interrupts */ 1520 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1521 WDCTL_4BIT); 1522 delay(10); /* some drives need a little delay here */ 1523 } 1524 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1525 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1526 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1527 wakeup(&chp->ch_queue->active_xfer); 1528 } else 1529 __wdccommand_done_end(chp, xfer); 1530 } 1531 1532 static void 1533 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1534 { 1535 struct ata_command *ata_c = xfer->c_cmd; 1536 1537 ata_c->flags |= AT_DONE; 1538 ata_free_xfer(chp, xfer); 1539 if (ata_c->flags & AT_WAIT) 1540 wakeup(ata_c); 1541 else if (ata_c->callback) 1542 ata_c->callback(ata_c->callback_arg); 1543 atastart(chp); 1544 return; 1545 } 1546 1547 static void 1548 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1549 int reason) 1550 { 1551 struct ata_command *ata_c = xfer->c_cmd; 1552 1553 switch (reason) { 1554 case KILL_GONE: 1555 ata_c->flags |= AT_GONE; 1556 break; 1557 case KILL_RESET: 1558 ata_c->flags |= AT_RESET; 1559 break; 1560 default: 1561 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1562 reason); 1563 panic("__wdccommand_kill_xfer"); 1564 } 1565 __wdccommand_done_end(chp, xfer); 1566 } 1567 1568 /* 1569 * Send a command. The drive should be ready. 1570 * Assumes interrupts are blocked. 1571 */ 1572 void 1573 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1574 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1575 u_int8_t features) 1576 { 1577 struct atac_softc *atac = chp->ch_atac; 1578 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1579 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1580 1581 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1582 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1583 chp->ch_channel, drive, command, cylin, head, sector, count, 1584 features), DEBUG_FUNCS); 1585 1586 if (wdc->select) 1587 wdc->select(chp,drive); 1588 1589 /* Select drive, head, and addressing mode. */ 1590 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1591 WDSD_IBM | (drive << 4) | head); 1592 /* Load parameters into the wd_features register. */ 1593 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1594 features); 1595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1596 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1597 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1598 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1599 0, cylin >> 8); 1600 1601 /* Send command. */ 1602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1603 return; 1604 } 1605 1606 /* 1607 * Send a 48-bit addressing command. The drive should be ready. 1608 * Assumes interrupts are blocked. 1609 */ 1610 void 1611 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1612 u_int64_t blkno, u_int16_t count) 1613 { 1614 struct atac_softc *atac = chp->ch_atac; 1615 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1616 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1617 1618 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1619 "count=%d\n", atac->atac_dev.dv_xname, 1620 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1621 DEBUG_FUNCS); 1622 1623 if (wdc->select) 1624 wdc->select(chp,drive); 1625 1626 /* Select drive, head, and addressing mode. */ 1627 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1628 (drive << 4) | WDSD_LBA); 1629 1630 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1631 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1632 0); 1633 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1634 0, count); 1635 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1636 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1637 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1638 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1639 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1640 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1641 } else { 1642 /* previous */ 1643 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1644 0); 1645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1646 0, count >> 8); 1647 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1648 0, blkno >> 24); 1649 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1650 0, blkno >> 32); 1651 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1652 0, blkno >> 40); 1653 1654 /* current */ 1655 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1656 0); 1657 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1658 count); 1659 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1660 blkno); 1661 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1662 0, blkno >> 8); 1663 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1664 0, blkno >> 16); 1665 } 1666 1667 /* Send command. */ 1668 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1669 return; 1670 } 1671 1672 /* 1673 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1674 * tested by the caller. 1675 */ 1676 void 1677 wdccommandshort(struct ata_channel *chp, int drive, int command) 1678 { 1679 struct atac_softc *atac = chp->ch_atac; 1680 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1681 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1682 1683 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1684 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1685 DEBUG_FUNCS); 1686 1687 if (wdc->select) 1688 wdc->select(chp,drive); 1689 1690 /* Select drive. */ 1691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1692 WDSD_IBM | (drive << 4)); 1693 1694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1695 } 1696 1697 static void 1698 __wdcerror(struct ata_channel *chp, const char *msg) 1699 { 1700 struct atac_softc *atac = chp->ch_atac; 1701 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1702 1703 if (xfer == NULL) 1704 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1705 msg); 1706 else 1707 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1708 chp->ch_channel, xfer->c_drive, msg); 1709 } 1710 1711 /* 1712 * the bit bucket 1713 */ 1714 void 1715 wdcbit_bucket(struct ata_channel *chp, int size) 1716 { 1717 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1718 1719 for (; size >= 2; size -= 2) 1720 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1721 if (size) 1722 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1723 } 1724 1725 static void 1726 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1727 { 1728 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1729 1730 if (flags & DRIVE_NOSTREAM) { 1731 if (flags & DRIVE_CAP32) { 1732 bus_space_read_multi_4(wdr->data32iot, 1733 wdr->data32ioh, 0, bf, len >> 2); 1734 bf = (char *)bf + (len & ~3); 1735 len &= 3; 1736 } 1737 if (len) { 1738 bus_space_read_multi_2(wdr->cmd_iot, 1739 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1740 } 1741 } else { 1742 if (flags & DRIVE_CAP32) { 1743 bus_space_read_multi_stream_4(wdr->data32iot, 1744 wdr->data32ioh, 0, bf, len >> 2); 1745 bf = (char *)bf + (len & ~3); 1746 len &= 3; 1747 } 1748 if (len) { 1749 bus_space_read_multi_stream_2(wdr->cmd_iot, 1750 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1751 } 1752 } 1753 } 1754 1755 static void 1756 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1757 { 1758 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1759 1760 if (flags & DRIVE_NOSTREAM) { 1761 if (flags & DRIVE_CAP32) { 1762 bus_space_write_multi_4(wdr->data32iot, 1763 wdr->data32ioh, 0, bf, len >> 2); 1764 bf = (char *)bf + (len & ~3); 1765 len &= 3; 1766 } 1767 if (len) { 1768 bus_space_write_multi_2(wdr->cmd_iot, 1769 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1770 } 1771 } else { 1772 if (flags & DRIVE_CAP32) { 1773 bus_space_write_multi_stream_4(wdr->data32iot, 1774 wdr->data32ioh, 0, bf, len >> 2); 1775 bf = (char *)bf + (len & ~3); 1776 len &= 3; 1777 } 1778 if (len) { 1779 bus_space_write_multi_stream_2(wdr->cmd_iot, 1780 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1781 } 1782 } 1783 } 1784
Indexes created Mon Sep 22 21:09:42 GMT 2025