wdc.c revision 1.232
1 /* $NetBSD: wdc.c,v 1.232 2006/01/16 20:30:19 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.232 2006/01/16 20:30:19 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 /* 123 * timeout when waiting for BSY to deassert when probing. 124 * set to 5s. From the standards this could be up to 31, but we can't 125 * wait that much at boot time, and 5s seems to be enouth. 126 */ 127 #define WDC_PROBE_WAIT 5 128 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, /* wdc_ata_bio */ 137 NULL, /* wdc_reset_drive */ 138 wdc_reset_channel, 139 wdc_exec_command, 140 NULL, /* ata_get_params */ 141 NULL, /* wdc_ata_addref */ 142 NULL, /* wdc_ata_delref */ 143 NULL /* ata_kill_pending */ 144 }; 145 #endif 146 147 /* Flags to wdcreset(). */ 148 #define RESET_POLL 1 149 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 150 151 static int wdcprobe1(struct ata_channel *, int); 152 static int wdcreset(struct ata_channel *, int); 153 static void __wdcerror(struct ata_channel *, const char *); 154 static int __wdcwait_reset(struct ata_channel *, int, int); 155 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 156 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 157 static void __wdccommand_kill_xfer(struct ata_channel *, 158 struct ata_xfer *, int); 159 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 160 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 161 static int __wdcwait(struct ata_channel *, int, int, int); 162 163 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 164 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 165 166 #define DEBUG_INTR 0x01 167 #define DEBUG_XFERS 0x02 168 #define DEBUG_STATUS 0x04 169 #define DEBUG_FUNCS 0x08 170 #define DEBUG_PROBE 0x10 171 #define DEBUG_DETACH 0x20 172 #define DEBUG_DELAY 0x40 173 #ifdef ATADEBUG 174 extern int atadebug_mask; /* init'ed in ata.c */ 175 int wdc_nxfer = 0; 176 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 177 #else 178 #define ATADEBUG_PRINT(args, level) 179 #endif 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct ata_channel *chp) 186 { 187 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 188 189 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 190 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 191 } 192 193 /* 194 * Allocate a wdc_regs array, based on the number of channels. 195 */ 196 void 197 wdc_allocate_regs(struct wdc_softc *wdc) 198 { 199 200 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 201 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 202 } 203 204 /* Test to see controller with at last one attached drive is there. 205 * Returns a bit for each possible drive found (0x01 for drive 0, 206 * 0x02 for drive 1). 207 * Logic: 208 * - If a status register is at 0xff, assume there is no drive here 209 * (ISA has pull-up resistors). Similarly if the status register has 210 * the value we last wrote to the bus (for IDE interfaces without pullups). 211 * If no drive at all -> return. 212 * - reset the controller, wait for it to complete (may take up to 31s !). 213 * If timeout -> return. 214 * - test ATA/ATAPI signatures. If at last one drive found -> return. 215 * - try an ATA command on the master. 216 */ 217 218 static void 219 wdc_drvprobe(struct ata_channel *chp) 220 { 221 struct ataparams params; 222 struct atac_softc *atac = chp->ch_atac; 223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 225 u_int8_t st0 = 0, st1 = 0; 226 int i, j, error, s; 227 228 if (wdcprobe1(chp, 0) == 0) { 229 /* No drives, abort the attach here. */ 230 return; 231 } 232 233 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 234 for (i = 0; i < mstohz(3000); i++) { 235 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 236 if (wdc->select) 237 wdc->select(chp,0); 238 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 239 0, WDSD_IBM); 240 delay(10); /* 400ns delay */ 241 st0 = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_status], 0); 243 } 244 245 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 246 if (wdc->select) 247 wdc->select(chp,1); 248 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 249 0, WDSD_IBM | 0x10); 250 delay(10); /* 400ns delay */ 251 st1 = bus_space_read_1(wdr->cmd_iot, 252 wdr->cmd_iohs[wd_status], 0); 253 } 254 255 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 256 == 0 || 257 (st0 & WDCS_DRDY)) && 258 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 259 == 0 || 260 (st1 & WDCS_DRDY))) 261 break; 262 tsleep(¶ms, PRIBIO, "atadrdy", 1); 263 } 264 s = splbio(); 265 if ((st0 & WDCS_DRDY) == 0) 266 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 267 if ((st1 & WDCS_DRDY) == 0) 268 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 269 splx(s); 270 271 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 272 atac->atac_dev.dv_xname, 273 chp->ch_channel, st0, st1), DEBUG_PROBE); 274 275 /* Wait a bit, some devices are weird just after a reset. */ 276 delay(5000); 277 278 for (i = 0; i < chp->ch_ndrive; i++) { 279 /* XXX This should be done by other code. */ 280 chp->ch_drive[i].chnl_softc = chp; 281 chp->ch_drive[i].drive = i; 282 283 /* 284 * Init error counter so that an error withing the first xfers 285 * will trigger a downgrade 286 */ 287 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 288 289 /* If controller can't do 16bit flag the drives as 32bit */ 290 if ((atac->atac_cap & 291 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 292 s = splbio(); 293 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 294 splx(s); 295 } 296 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 297 continue; 298 299 /* Shortcut in case we've been shutdown */ 300 if (chp->ch_flags & ATACH_SHUTDOWN) 301 return; 302 303 /* 304 * Issue an identify, to try to detect ghosts. 305 * Note that we can't use interrupts here, because if there 306 * is no devices, we will get a command aborted without 307 * interrupts. 308 */ 309 error = ata_get_params(&chp->ch_drive[i], 310 AT_WAIT | AT_POLL, ¶ms); 311 if (error != CMD_OK) { 312 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 313 314 /* Shortcut in case we've been shutdown */ 315 if (chp->ch_flags & ATACH_SHUTDOWN) 316 return; 317 318 error = ata_get_params(&chp->ch_drive[i], 319 AT_WAIT | AT_POLL, ¶ms); 320 } 321 if (error == CMD_OK) { 322 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 323 s = splbio(); 324 for (j = 0; j < chp->ch_ndrive; j++) 325 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 326 splx(s); 327 } else { 328 s = splbio(); 329 chp->ch_drive[i].drive_flags &= 330 ~(DRIVE_ATA | DRIVE_ATAPI); 331 splx(s); 332 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 333 atac->atac_dev.dv_xname, 334 chp->ch_channel, i, error), DEBUG_PROBE); 335 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 336 continue; 337 /* 338 * Pre-ATA drive ? 339 * Test registers writability (Error register not 340 * writable, but cyllo is), then try an ATA command. 341 */ 342 if (wdc->select) 343 wdc->select(chp,i); 344 bus_space_write_1(wdr->cmd_iot, 345 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 346 delay(10); /* 400ns delay */ 347 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 348 0, 0x58); 349 bus_space_write_1(wdr->cmd_iot, 350 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 351 if (bus_space_read_1(wdr->cmd_iot, 352 wdr->cmd_iohs[wd_error], 0) == 0x58 || 353 bus_space_read_1(wdr->cmd_iot, 354 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 355 ATADEBUG_PRINT(("%s:%d:%d: register " 356 "writability failed\n", 357 atac->atac_dev.dv_xname, 358 chp->ch_channel, i), DEBUG_PROBE); 359 s = splbio(); 360 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 361 splx(s); 362 continue; 363 } 364 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 365 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 366 atac->atac_dev.dv_xname, 367 chp->ch_channel, i), DEBUG_PROBE); 368 s = splbio(); 369 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 370 splx(s); 371 continue; 372 } 373 bus_space_write_1(wdr->cmd_iot, 374 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 375 delay(10); /* 400ns delay */ 376 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 377 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 378 atac->atac_dev.dv_xname, 379 chp->ch_channel, i), DEBUG_PROBE); 380 s = splbio(); 381 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 382 splx(s); 383 } else { 384 s = splbio(); 385 for (j = 0; j < chp->ch_ndrive; j++) 386 chp->ch_drive[j].drive_flags &= 387 ~(DRIVE_ATA | DRIVE_ATAPI); 388 splx(s); 389 } 390 } 391 } 392 } 393 394 int 395 wdcprobe(struct ata_channel *chp) 396 { 397 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 398 /* default reset method */ 399 if (wdc->reset == NULL) 400 wdc->reset = wdc_do_reset; 401 402 return (wdcprobe1(chp, 1)); 403 } 404 405 static int 406 wdcprobe1(struct ata_channel *chp, int poll) 407 { 408 struct atac_softc *atac = chp->ch_atac; 409 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 410 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 411 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 412 u_int8_t ret_value = 0x03; 413 u_int8_t drive; 414 int s; 415 int wdc_probe_count = 416 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 417 418 /* 419 * Sanity check to see if the wdc channel responds at all. 420 */ 421 422 s = splbio(); 423 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 424 while (wdc_probe_count-- > 0) { 425 if (wdc->select) 426 wdc->select(chp,0); 427 428 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 429 0, WDSD_IBM); 430 delay(10); /* 400ns delay */ 431 st0 = bus_space_read_1(wdr->cmd_iot, 432 wdr->cmd_iohs[wd_status], 0); 433 434 if (wdc->select) 435 wdc->select(chp,1); 436 437 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 438 0, WDSD_IBM | 0x10); 439 delay(10); /* 400ns delay */ 440 st1 = bus_space_read_1(wdr->cmd_iot, 441 wdr->cmd_iohs[wd_status], 0); 442 if ((st0 & WDCS_BSY) == 0) 443 break; 444 } 445 446 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 447 atac->atac_dev.dv_xname, 448 chp->ch_channel, st0, st1), DEBUG_PROBE); 449 450 if (st0 == 0xff || st0 == WDSD_IBM) 451 ret_value &= ~0x01; 452 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 453 ret_value &= ~0x02; 454 /* Register writability test, drive 0. */ 455 if (ret_value & 0x01) { 456 if (wdc->select) 457 wdc->select(chp,0); 458 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 459 0, WDSD_IBM); 460 bus_space_write_1(wdr->cmd_iot, 461 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 462 cl = bus_space_read_1(wdr->cmd_iot, 463 wdr->cmd_iohs[wd_cyl_lo], 0); 464 if (cl != 0x02) { 465 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 466 "got 0x%x != 0x02\n", 467 atac->atac_dev.dv_xname, 468 chp->ch_channel, cl), 469 DEBUG_PROBE); 470 ret_value &= ~0x01; 471 } 472 bus_space_write_1(wdr->cmd_iot, 473 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 474 cl = bus_space_read_1(wdr->cmd_iot, 475 wdr->cmd_iohs[wd_cyl_lo], 0); 476 if (cl != 0x01) { 477 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 478 "got 0x%x != 0x01\n", 479 atac->atac_dev.dv_xname, 480 chp->ch_channel, cl), 481 DEBUG_PROBE); 482 ret_value &= ~0x01; 483 } 484 bus_space_write_1(wdr->cmd_iot, 485 wdr->cmd_iohs[wd_sector], 0, 0x01); 486 cl = bus_space_read_1(wdr->cmd_iot, 487 wdr->cmd_iohs[wd_sector], 0); 488 if (cl != 0x01) { 489 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 490 "got 0x%x != 0x01\n", 491 atac->atac_dev.dv_xname, 492 chp->ch_channel, cl), 493 DEBUG_PROBE); 494 ret_value &= ~0x01; 495 } 496 bus_space_write_1(wdr->cmd_iot, 497 wdr->cmd_iohs[wd_sector], 0, 0x02); 498 cl = bus_space_read_1(wdr->cmd_iot, 499 wdr->cmd_iohs[wd_sector], 0); 500 if (cl != 0x02) { 501 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 502 "got 0x%x != 0x02\n", 503 atac->atac_dev.dv_xname, 504 chp->ch_channel, cl), 505 DEBUG_PROBE); 506 ret_value &= ~0x01; 507 } 508 cl = bus_space_read_1(wdr->cmd_iot, 509 wdr->cmd_iohs[wd_cyl_lo], 0); 510 if (cl != 0x01) { 511 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 512 "got 0x%x != 0x01\n", 513 atac->atac_dev.dv_xname, 514 chp->ch_channel, cl), 515 DEBUG_PROBE); 516 ret_value &= ~0x01; 517 } 518 } 519 /* Register writability test, drive 1. */ 520 if (ret_value & 0x02) { 521 if (wdc->select) 522 wdc->select(chp,1); 523 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 524 0, WDSD_IBM | 0x10); 525 bus_space_write_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 527 cl = bus_space_read_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_cyl_lo], 0); 529 if (cl != 0x02) { 530 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 531 "got 0x%x != 0x02\n", 532 atac->atac_dev.dv_xname, 533 chp->ch_channel, cl), 534 DEBUG_PROBE); 535 ret_value &= ~0x02; 536 } 537 bus_space_write_1(wdr->cmd_iot, 538 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 539 cl = bus_space_read_1(wdr->cmd_iot, 540 wdr->cmd_iohs[wd_cyl_lo], 0); 541 if (cl != 0x01) { 542 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 543 "got 0x%x != 0x01\n", 544 atac->atac_dev.dv_xname, 545 chp->ch_channel, cl), 546 DEBUG_PROBE); 547 ret_value &= ~0x02; 548 } 549 bus_space_write_1(wdr->cmd_iot, 550 wdr->cmd_iohs[wd_sector], 0, 0x01); 551 cl = bus_space_read_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_sector], 0); 553 if (cl != 0x01) { 554 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 555 "got 0x%x != 0x01\n", 556 atac->atac_dev.dv_xname, 557 chp->ch_channel, cl), 558 DEBUG_PROBE); 559 ret_value &= ~0x02; 560 } 561 bus_space_write_1(wdr->cmd_iot, 562 wdr->cmd_iohs[wd_sector], 0, 0x02); 563 cl = bus_space_read_1(wdr->cmd_iot, 564 wdr->cmd_iohs[wd_sector], 0); 565 if (cl != 0x02) { 566 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 567 "got 0x%x != 0x02\n", 568 atac->atac_dev.dv_xname, 569 chp->ch_channel, cl), 570 DEBUG_PROBE); 571 ret_value &= ~0x02; 572 } 573 cl = bus_space_read_1(wdr->cmd_iot, 574 wdr->cmd_iohs[wd_cyl_lo], 0); 575 if (cl != 0x01) { 576 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 577 "got 0x%x != 0x01\n", 578 atac->atac_dev.dv_xname, 579 chp->ch_channel, cl), 580 DEBUG_PROBE); 581 ret_value &= ~0x02; 582 } 583 } 584 585 if (ret_value == 0) { 586 splx(s); 587 return 0; 588 } 589 } 590 591 592 #if 0 /* XXX this break some ATA or ATAPI devices */ 593 /* 594 * reset bus. Also send an ATAPI_RESET to devices, in case there are 595 * ATAPI device out there which don't react to the bus reset 596 */ 597 if (ret_value & 0x01) { 598 if (wdc->select) 599 wdc->select(chp,0); 600 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 601 0, WDSD_IBM); 602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 603 ATAPI_SOFT_RESET); 604 } 605 if (ret_value & 0x02) { 606 if (wdc->select) 607 wdc->select(chp,0); 608 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 609 0, WDSD_IBM | 0x10); 610 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 611 ATAPI_SOFT_RESET); 612 } 613 614 delay(5000); 615 #endif 616 617 wdc->reset(chp, RESET_POLL); 618 DELAY(2000); 619 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 620 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 621 splx(s); 622 623 ret_value = __wdcwait_reset(chp, ret_value, poll); 624 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 625 atac->atac_dev.dv_xname, chp->ch_channel, 626 ret_value), DEBUG_PROBE); 627 628 /* if reset failed, there's nothing here */ 629 if (ret_value == 0) 630 return 0; 631 632 /* 633 * Test presence of drives. First test register signatures looking 634 * for ATAPI devices. If it's not an ATAPI and reset said there may 635 * be something here assume it's ATA or OLD. Ghost will be killed 636 * later in attach routine. 637 */ 638 for (drive = 0; drive < chp->ch_ndrive; drive++) { 639 if ((ret_value & (0x01 << drive)) == 0) 640 continue; 641 if (wdc->select) 642 wdc->select(chp,drive); 643 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 644 WDSD_IBM | (drive << 4)); 645 delay(10); /* 400ns delay */ 646 /* Save registers contents */ 647 sc = bus_space_read_1(wdr->cmd_iot, 648 wdr->cmd_iohs[wd_seccnt], 0); 649 sn = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0); 651 cl = bus_space_read_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_cyl_lo], 0); 653 ch = bus_space_read_1(wdr->cmd_iot, 654 wdr->cmd_iohs[wd_cyl_hi], 0); 655 656 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 657 "cl=0x%x ch=0x%x\n", 658 atac->atac_dev.dv_xname, 659 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 660 /* 661 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 662 * we get wrong values here, so ignore it. 663 */ 664 s = splbio(); 665 if (cl == 0x14 && ch == 0xeb) { 666 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 667 } else { 668 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 669 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 670 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 671 } 672 splx(s); 673 } 674 return (ret_value); 675 } 676 677 void 678 wdcattach(struct ata_channel *chp) 679 { 680 struct atac_softc *atac = chp->ch_atac; 681 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 682 683 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 684 685 /* default data transfer methods */ 686 if (wdc->datain_pio == NULL) 687 wdc->datain_pio = wdc_datain_pio; 688 if (wdc->dataout_pio == NULL) 689 wdc->dataout_pio = wdc_dataout_pio; 690 /* default reset method */ 691 if (wdc->reset == NULL) 692 wdc->reset = wdc_do_reset; 693 694 /* initialise global data */ 695 if (atac->atac_bustype_ata == NULL) 696 atac->atac_bustype_ata = &wdc_ata_bustype; 697 if (atac->atac_probe == NULL) 698 atac->atac_probe = wdc_drvprobe; 699 #if NATAPIBUS > 0 700 if (atac->atac_atapibus_attach == NULL) 701 atac->atac_atapibus_attach = wdc_atapibus_attach; 702 #endif 703 704 ata_channel_attach(chp); 705 } 706 707 int 708 wdcactivate(struct device *self, enum devact act) 709 { 710 struct atac_softc *atac = (struct atac_softc *) self; 711 int s, i, error = 0; 712 713 s = splbio(); 714 switch (act) { 715 case DVACT_ACTIVATE: 716 error = EOPNOTSUPP; 717 break; 718 719 case DVACT_DEACTIVATE: 720 for (i = 0; i < atac->atac_nchannels; i++) { 721 error = 722 config_deactivate(atac->atac_channels[i]->atabus); 723 if (error) 724 break; 725 } 726 break; 727 } 728 splx(s); 729 return (error); 730 } 731 732 int 733 wdcdetach(struct device *self, int flags) 734 { 735 struct atac_softc *atac = (struct atac_softc *) self; 736 struct ata_channel *chp; 737 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 738 int i, error = 0; 739 740 for (i = 0; i < atac->atac_nchannels; i++) { 741 chp = atac->atac_channels[i]; 742 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 743 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 744 DEBUG_DETACH); 745 error = config_detach(chp->atabus, flags); 746 if (error) 747 break; 748 } 749 if (adapt->adapt_refcnt != 0) { 750 #ifdef DIAGNOSTIC 751 printf("wdcdetach: refcnt should be 0 here??\n"); 752 #endif 753 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 754 } 755 return (error); 756 } 757 758 /* restart an interrupted I/O */ 759 void 760 wdcrestart(void *v) 761 { 762 struct ata_channel *chp = v; 763 int s; 764 765 s = splbio(); 766 atastart(chp); 767 splx(s); 768 } 769 770 771 /* 772 * Interrupt routine for the controller. Acknowledge the interrupt, check for 773 * errors on the current operation, mark it done if necessary, and start the 774 * next request. Also check for a partially done transfer, and continue with 775 * the next chunk if so. 776 */ 777 int 778 wdcintr(void *arg) 779 { 780 struct ata_channel *chp = arg; 781 struct atac_softc *atac = chp->ch_atac; 782 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 783 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 784 struct ata_xfer *xfer; 785 int ret; 786 787 if ((atac->atac_dev.dv_flags & DVF_ACTIVE) == 0) { 788 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 789 DEBUG_INTR); 790 return (0); 791 } 792 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 793 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 794 /* try to clear the pending interrupt anyway */ 795 (void)bus_space_read_1(wdr->cmd_iot, 796 wdr->cmd_iohs[wd_status], 0); 797 return (0); 798 } 799 800 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 801 xfer = chp->ch_queue->active_xfer; 802 #ifdef DIAGNOSTIC 803 if (xfer == NULL) 804 panic("wdcintr: no xfer"); 805 #endif 806 if (chp->ch_flags & ATACH_DMA_WAIT) { 807 wdc->dma_status = 808 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 809 xfer->c_drive, WDC_DMAEND_END); 810 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 811 /* IRQ not for us, not detected by DMA engine */ 812 return 0; 813 } 814 chp->ch_flags &= ~ATACH_DMA_WAIT; 815 } 816 chp->ch_flags &= ~ATACH_IRQ_WAIT; 817 ret = xfer->c_intr(chp, xfer, 1); 818 if (ret == 0) /* irq was not for us, still waiting for irq */ 819 chp->ch_flags |= ATACH_IRQ_WAIT; 820 return (ret); 821 } 822 823 /* Put all disk in RESET state */ 824 void 825 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 826 { 827 struct ata_channel *chp = drvp->chnl_softc; 828 struct atac_softc *atac = chp->ch_atac; 829 830 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 831 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 832 DEBUG_FUNCS); 833 834 ata_reset_channel(chp, flags); 835 } 836 837 void 838 wdc_reset_channel(struct ata_channel *chp, int flags) 839 { 840 TAILQ_HEAD(, ata_xfer) reset_xfer; 841 struct ata_xfer *xfer, *next_xfer; 842 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 843 844 TAILQ_INIT(&reset_xfer); 845 846 chp->ch_flags &= ~ATACH_IRQ_WAIT; 847 848 /* 849 * if the current command if on an ATAPI device, issue a 850 * ATAPI_SOFT_RESET 851 */ 852 xfer = chp->ch_queue->active_xfer; 853 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 854 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 855 if (flags & AT_WAIT) 856 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 857 else 858 delay(1000); 859 } 860 861 /* reset the channel */ 862 if (flags & AT_WAIT) 863 (void) wdcreset(chp, RESET_SLEEP); 864 else 865 (void) wdcreset(chp, RESET_POLL); 866 867 /* 868 * wait a bit after reset; in case the DMA engines needs some time 869 * to recover. 870 */ 871 if (flags & AT_WAIT) 872 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 873 else 874 delay(1000); 875 /* 876 * look for pending xfers. If we have a shared queue, we'll also reset 877 * the other channel if the current xfer is running on it. 878 * Then we'll dequeue only the xfers for this channel. 879 */ 880 if ((flags & AT_RST_NOCMD) == 0) { 881 /* 882 * move all xfers queued for this channel to the reset queue, 883 * and then process the current xfer and then the reset queue. 884 * We have to use a temporary queue because c_kill_xfer() 885 * may requeue commands. 886 */ 887 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 888 xfer != NULL; xfer = next_xfer) { 889 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 890 if (xfer->c_chp != chp) 891 continue; 892 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 893 xfer, c_xferchain); 894 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 895 } 896 xfer = chp->ch_queue->active_xfer; 897 if (xfer) { 898 if (xfer->c_chp != chp) 899 ata_reset_channel(xfer->c_chp, flags); 900 else { 901 callout_stop(&chp->ch_callout); 902 /* 903 * If we're waiting for DMA, stop the 904 * DMA engine 905 */ 906 if (chp->ch_flags & ATACH_DMA_WAIT) { 907 (*wdc->dma_finish)( 908 wdc->dma_arg, 909 chp->ch_channel, 910 xfer->c_drive, 911 WDC_DMAEND_ABRT_QUIET); 912 chp->ch_flags &= ~ATACH_DMA_WAIT; 913 } 914 chp->ch_queue->active_xfer = NULL; 915 if ((flags & AT_RST_EMERG) == 0) 916 xfer->c_kill_xfer( 917 chp, xfer, KILL_RESET); 918 } 919 } 920 921 for (xfer = TAILQ_FIRST(&reset_xfer); 922 xfer != NULL; xfer = next_xfer) { 923 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 924 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 925 if ((flags & AT_RST_EMERG) == 0) 926 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 927 } 928 } 929 } 930 931 static int 932 wdcreset(struct ata_channel *chp, int poll) 933 { 934 struct atac_softc *atac = chp->ch_atac; 935 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 936 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 937 int drv_mask1, drv_mask2; 938 939 wdc->reset(chp, poll); 940 941 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 942 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 943 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 944 (poll == RESET_SLEEP) ? 0 : 1); 945 if (drv_mask2 != drv_mask1) { 946 printf("%s channel %d: reset failed for", 947 atac->atac_dev.dv_xname, chp->ch_channel); 948 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 949 printf(" drive 0"); 950 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 951 printf(" drive 1"); 952 printf("\n"); 953 } 954 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 955 return (drv_mask1 != drv_mask2) ? 1 : 0; 956 } 957 958 void 959 wdc_do_reset(struct ata_channel *chp, int poll) 960 { 961 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 962 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 963 int s = 0; 964 965 if (poll != RESET_SLEEP) 966 s = splbio(); 967 if (wdc->select) 968 wdc->select(chp,0); 969 /* master */ 970 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 971 delay(10); /* 400ns delay */ 972 /* assert SRST, wait for reset to complete */ 973 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 974 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 975 delay(2000); 976 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 977 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 978 WDCTL_4BIT | WDCTL_IDS); 979 delay(10); /* 400ns delay */ 980 if (poll != RESET_SLEEP) { 981 if (wdc->irqack) 982 wdc->irqack(chp); 983 splx(s); 984 } 985 } 986 987 static int 988 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 989 { 990 struct atac_softc *atac = chp->ch_atac; 991 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 992 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 993 int timeout, nloop; 994 u_int8_t st0 = 0, st1 = 0; 995 #ifdef ATADEBUG 996 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 997 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 998 #endif 999 1000 if (poll) 1001 nloop = WDCNDELAY_RST; 1002 else 1003 nloop = WDC_RESET_WAIT * hz / 1000; 1004 /* wait for BSY to deassert */ 1005 for (timeout = 0; timeout < nloop; timeout++) { 1006 if ((drv_mask & 0x01) != 0) { 1007 if (wdc && wdc->select) 1008 wdc->select(chp,0); 1009 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1010 0, WDSD_IBM); /* master */ 1011 delay(10); 1012 st0 = bus_space_read_1(wdr->cmd_iot, 1013 wdr->cmd_iohs[wd_status], 0); 1014 #ifdef ATADEBUG 1015 sc0 = bus_space_read_1(wdr->cmd_iot, 1016 wdr->cmd_iohs[wd_seccnt], 0); 1017 sn0 = bus_space_read_1(wdr->cmd_iot, 1018 wdr->cmd_iohs[wd_sector], 0); 1019 cl0 = bus_space_read_1(wdr->cmd_iot, 1020 wdr->cmd_iohs[wd_cyl_lo], 0); 1021 ch0 = bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_cyl_hi], 0); 1023 #endif 1024 } 1025 if ((drv_mask & 0x02) != 0) { 1026 if (wdc && wdc->select) 1027 wdc->select(chp,1); 1028 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1029 0, WDSD_IBM | 0x10); /* slave */ 1030 delay(10); 1031 st1 = bus_space_read_1(wdr->cmd_iot, 1032 wdr->cmd_iohs[wd_status], 0); 1033 #ifdef ATADEBUG 1034 sc1 = bus_space_read_1(wdr->cmd_iot, 1035 wdr->cmd_iohs[wd_seccnt], 0); 1036 sn1 = bus_space_read_1(wdr->cmd_iot, 1037 wdr->cmd_iohs[wd_sector], 0); 1038 cl1 = bus_space_read_1(wdr->cmd_iot, 1039 wdr->cmd_iohs[wd_cyl_lo], 0); 1040 ch1 = bus_space_read_1(wdr->cmd_iot, 1041 wdr->cmd_iohs[wd_cyl_hi], 0); 1042 #endif 1043 } 1044 1045 if ((drv_mask & 0x01) == 0) { 1046 /* no master */ 1047 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1048 /* No master, slave is ready, it's done */ 1049 goto end; 1050 } 1051 if ((drv_mask & 0x02) == 0) { 1052 /* No master, no slave: it's done */ 1053 goto end; 1054 } 1055 } else if ((drv_mask & 0x02) == 0) { 1056 /* no slave */ 1057 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1058 /* No slave, master is ready, it's done */ 1059 goto end; 1060 } 1061 } else { 1062 /* Wait for both master and slave to be ready */ 1063 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1064 goto end; 1065 } 1066 } 1067 if (poll) 1068 delay(WDCDELAY); 1069 else 1070 tsleep(&nloop, PRIBIO, "atarst", 1); 1071 } 1072 /* Reset timed out. Maybe it's because drv_mask was not right */ 1073 if (st0 & WDCS_BSY) 1074 drv_mask &= ~0x01; 1075 if (st1 & WDCS_BSY) 1076 drv_mask &= ~0x02; 1077 end: 1078 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1079 "cl=0x%x ch=0x%x\n", 1080 atac->atac_dev.dv_xname, 1081 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1082 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1083 "cl=0x%x ch=0x%x\n", 1084 atac->atac_dev.dv_xname, 1085 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1086 1087 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1088 atac->atac_dev.dv_xname, chp->ch_channel, 1089 st0, st1), DEBUG_PROBE); 1090 1091 return drv_mask; 1092 } 1093 1094 /* 1095 * Wait for a drive to be !BSY, and have mask in its status register. 1096 * return -1 for a timeout after "timeout" ms. 1097 */ 1098 static int 1099 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1100 { 1101 struct atac_softc *atac = chp->ch_atac; 1102 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1103 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1104 u_char status; 1105 int xtime = 0; 1106 1107 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1108 atac->atac_dev.dv_xname, 1109 chp->ch_channel), DEBUG_STATUS); 1110 chp->ch_error = 0; 1111 1112 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1113 1114 for (;;) { 1115 chp->ch_status = status = 1116 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1117 if ((status & (WDCS_BSY | mask)) == bits) 1118 break; 1119 if (++xtime > timeout) { 1120 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1121 "status %x error %x (mask 0x%x bits 0x%x)\n", 1122 xtime, status, 1123 bus_space_read_1(wdr->cmd_iot, 1124 wdr->cmd_iohs[wd_error], 0), mask, bits), 1125 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1126 return(WDCWAIT_TOUT); 1127 } 1128 delay(WDCDELAY); 1129 } 1130 #ifdef ATADEBUG 1131 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1132 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1133 #endif 1134 if (status & WDCS_ERR) 1135 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1136 wdr->cmd_iohs[wd_error], 0); 1137 #ifdef WDCNDELAY_DEBUG 1138 /* After autoconfig, there should be no long delays. */ 1139 if (!cold && xtime > WDCNDELAY_DEBUG) { 1140 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1141 if (xfer == NULL) 1142 printf("%s channel %d: warning: busy-wait took %dus\n", 1143 atac->atac_dev.dv_xname, chp->ch_channel, 1144 WDCDELAY * xtime); 1145 else 1146 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1147 atac->atac_dev.dv_xname, chp->ch_channel, 1148 xfer->drive, 1149 WDCDELAY * xtime); 1150 } 1151 #endif 1152 return(WDCWAIT_OK); 1153 } 1154 1155 /* 1156 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1157 * thread if possible 1158 */ 1159 int 1160 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1161 { 1162 int error, i, timeout_hz = mstohz(timeout); 1163 1164 if (timeout_hz == 0 || 1165 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1166 error = __wdcwait(chp, mask, bits, timeout); 1167 else { 1168 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1169 if (error != 0) { 1170 if ((chp->ch_flags & ATACH_TH_RUN) || 1171 (flags & AT_WAIT)) { 1172 /* 1173 * we're running in the channel thread 1174 * or some userland thread context 1175 */ 1176 for (i = 0; i < timeout_hz; i++) { 1177 if (__wdcwait(chp, mask, bits, 1178 WDCDELAY_POLL) == 0) { 1179 error = 0; 1180 break; 1181 } 1182 tsleep(&chp, PRIBIO, "atapoll", 1); 1183 } 1184 } else { 1185 /* 1186 * we're probably in interrupt context, 1187 * ask the thread to come back here 1188 */ 1189 #ifdef DIAGNOSTIC 1190 if (chp->ch_queue->queue_freeze > 0) 1191 panic("wdcwait: queue_freeze"); 1192 #endif 1193 chp->ch_queue->queue_freeze++; 1194 wakeup(&chp->ch_thread); 1195 return(WDCWAIT_THR); 1196 } 1197 } 1198 } 1199 return (error); 1200 } 1201 1202 1203 /* 1204 * Busy-wait for DMA to complete 1205 */ 1206 int 1207 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1208 { 1209 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1210 int xtime; 1211 1212 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1213 wdc->dma_status = 1214 (*wdc->dma_finish)(wdc->dma_arg, 1215 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1216 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1217 return 0; 1218 delay(WDCDELAY); 1219 } 1220 /* timeout, force a DMA halt */ 1221 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1222 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1223 return 1; 1224 } 1225 1226 void 1227 wdctimeout(void *arg) 1228 { 1229 struct ata_channel *chp = (struct ata_channel *)arg; 1230 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1231 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1232 int s; 1233 1234 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1235 1236 s = splbio(); 1237 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1238 __wdcerror(chp, "lost interrupt"); 1239 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1240 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1241 xfer->c_bcount, 1242 xfer->c_skip); 1243 if (chp->ch_flags & ATACH_DMA_WAIT) { 1244 wdc->dma_status = 1245 (*wdc->dma_finish)(wdc->dma_arg, 1246 chp->ch_channel, xfer->c_drive, 1247 WDC_DMAEND_ABRT); 1248 chp->ch_flags &= ~ATACH_DMA_WAIT; 1249 } 1250 /* 1251 * Call the interrupt routine. If we just missed an interrupt, 1252 * it will do what's needed. Else, it will take the needed 1253 * action (reset the device). 1254 * Before that we need to reinstall the timeout callback, 1255 * in case it will miss another irq while in this transfer 1256 * We arbitray chose it to be 1s 1257 */ 1258 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1259 xfer->c_flags |= C_TIMEOU; 1260 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1261 xfer->c_intr(chp, xfer, 1); 1262 } else 1263 __wdcerror(chp, "missing untimeout"); 1264 splx(s); 1265 } 1266 1267 int 1268 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1269 { 1270 struct ata_channel *chp = drvp->chnl_softc; 1271 struct atac_softc *atac = chp->ch_atac; 1272 struct ata_xfer *xfer; 1273 int s, ret; 1274 1275 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1276 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1277 DEBUG_FUNCS); 1278 1279 /* set up an xfer and queue. Wait for completion */ 1280 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1281 ATAXF_NOSLEEP); 1282 if (xfer == NULL) { 1283 return ATACMD_TRY_AGAIN; 1284 } 1285 1286 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1287 ata_c->flags |= AT_POLL; 1288 if (ata_c->flags & AT_POLL) 1289 xfer->c_flags |= C_POLL; 1290 if (ata_c->flags & AT_WAIT) 1291 xfer->c_flags |= C_WAIT; 1292 xfer->c_drive = drvp->drive; 1293 xfer->c_databuf = ata_c->data; 1294 xfer->c_bcount = ata_c->bcount; 1295 xfer->c_cmd = ata_c; 1296 xfer->c_start = __wdccommand_start; 1297 xfer->c_intr = __wdccommand_intr; 1298 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1299 1300 s = splbio(); 1301 ata_exec_xfer(chp, xfer); 1302 #ifdef DIAGNOSTIC 1303 if ((ata_c->flags & AT_POLL) != 0 && 1304 (ata_c->flags & AT_DONE) == 0) 1305 panic("wdc_exec_command: polled command not done"); 1306 #endif 1307 if (ata_c->flags & AT_DONE) { 1308 ret = ATACMD_COMPLETE; 1309 } else { 1310 if (ata_c->flags & AT_WAIT) { 1311 while ((ata_c->flags & AT_DONE) == 0) { 1312 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1313 } 1314 ret = ATACMD_COMPLETE; 1315 } else { 1316 ret = ATACMD_QUEUED; 1317 } 1318 } 1319 splx(s); 1320 return ret; 1321 } 1322 1323 static void 1324 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1325 { 1326 struct atac_softc *atac = chp->ch_atac; 1327 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1328 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1329 int drive = xfer->c_drive; 1330 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1331 struct ata_command *ata_c = xfer->c_cmd; 1332 1333 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1334 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1335 DEBUG_FUNCS); 1336 1337 if (wdc->select) 1338 wdc->select(chp,drive); 1339 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1340 WDSD_IBM | (drive << 4)); 1341 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1342 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1343 case WDCWAIT_OK: 1344 break; 1345 case WDCWAIT_TOUT: 1346 ata_c->flags |= AT_TIMEOU; 1347 __wdccommand_done(chp, xfer); 1348 return; 1349 case WDCWAIT_THR: 1350 return; 1351 } 1352 if (ata_c->flags & AT_POLL) { 1353 /* polled command, disable interrupts */ 1354 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1355 WDCTL_4BIT | WDCTL_IDS); 1356 } 1357 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1358 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1359 1360 if ((ata_c->flags & AT_POLL) == 0) { 1361 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1362 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1363 wdctimeout, chp); 1364 return; 1365 } 1366 /* 1367 * Polled command. Wait for drive ready or drq. Done in intr(). 1368 * Wait for at last 400ns for status bit to be valid. 1369 */ 1370 delay(10); /* 400ns delay */ 1371 __wdccommand_intr(chp, xfer, 0); 1372 } 1373 1374 static int 1375 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1376 { 1377 struct atac_softc *atac = chp->ch_atac; 1378 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1379 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1380 struct ata_command *ata_c = xfer->c_cmd; 1381 int bcount = ata_c->bcount; 1382 char *data = ata_c->data; 1383 int wflags; 1384 int drive_flags; 1385 1386 if (ata_c->r_command == WDCC_IDENTIFY || 1387 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1388 /* 1389 * The IDENTIFY data has been designed as an array of 1390 * u_int16_t, so we can byteswap it on the fly. 1391 * Historically it's what we have always done so keeping it 1392 * here ensure binary backward compatibility. 1393 */ 1394 drive_flags = DRIVE_NOSTREAM | 1395 chp->ch_drive[xfer->c_drive].drive_flags; 1396 } else { 1397 /* 1398 * Other data structure are opaque and should be transfered 1399 * as is. 1400 */ 1401 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1402 } 1403 1404 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1405 /* both wait and poll, we can tsleep here */ 1406 wflags = AT_WAIT | AT_POLL; 1407 } else { 1408 wflags = AT_POLL; 1409 } 1410 1411 again: 1412 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1413 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1414 DEBUG_INTR); 1415 /* 1416 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1417 * Reselect again, it doesn't hurt for others commands, and the time 1418 * penalty for the extra regiter write is acceptable, 1419 * wdc_exec_command() isn't called often (mosly for autoconfig) 1420 */ 1421 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1422 WDSD_IBM | (xfer->c_drive << 4)); 1423 if ((ata_c->flags & AT_XFDONE) != 0) { 1424 /* 1425 * We have completed a data xfer. The drive should now be 1426 * in its initial state 1427 */ 1428 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1429 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1430 wflags) == WDCWAIT_TOUT) { 1431 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1432 return 0; /* IRQ was not for us */ 1433 ata_c->flags |= AT_TIMEOU; 1434 } 1435 goto out; 1436 } 1437 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1438 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1439 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1440 return 0; /* IRQ was not for us */ 1441 ata_c->flags |= AT_TIMEOU; 1442 goto out; 1443 } 1444 if (wdc->irqack) 1445 wdc->irqack(chp); 1446 if (ata_c->flags & AT_READ) { 1447 if ((chp->ch_status & WDCS_DRQ) == 0) { 1448 ata_c->flags |= AT_TIMEOU; 1449 goto out; 1450 } 1451 wdc->datain_pio(chp, drive_flags, data, bcount); 1452 /* at this point the drive should be in its initial state */ 1453 ata_c->flags |= AT_XFDONE; 1454 /* XXX should read status register here ? */ 1455 } else if (ata_c->flags & AT_WRITE) { 1456 if ((chp->ch_status & WDCS_DRQ) == 0) { 1457 ata_c->flags |= AT_TIMEOU; 1458 goto out; 1459 } 1460 wdc->dataout_pio(chp, drive_flags, data, bcount); 1461 ata_c->flags |= AT_XFDONE; 1462 if ((ata_c->flags & AT_POLL) == 0) { 1463 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1464 callout_reset(&chp->ch_callout, 1465 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1466 return 1; 1467 } else { 1468 goto again; 1469 } 1470 } 1471 out: 1472 __wdccommand_done(chp, xfer); 1473 return 1; 1474 } 1475 1476 static void 1477 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1478 { 1479 struct atac_softc *atac = chp->ch_atac; 1480 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1481 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1482 struct ata_command *ata_c = xfer->c_cmd; 1483 1484 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1485 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1486 DEBUG_FUNCS); 1487 1488 1489 if (chp->ch_status & WDCS_DWF) 1490 ata_c->flags |= AT_DF; 1491 if (chp->ch_status & WDCS_ERR) { 1492 ata_c->flags |= AT_ERROR; 1493 ata_c->r_error = chp->ch_error; 1494 } 1495 if ((ata_c->flags & AT_READREG) != 0 && 1496 (atac->atac_dev.dv_flags & DVF_ACTIVE) != 0 && 1497 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1498 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1499 wdr->cmd_iohs[wd_sdh], 0); 1500 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1501 wdr->cmd_iohs[wd_seccnt], 0); 1502 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1503 wdr->cmd_iohs[wd_sector], 0); 1504 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1505 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1506 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1507 wdr->cmd_iohs[wd_cyl_lo], 0); 1508 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1509 wdr->cmd_iohs[wd_error], 0); 1510 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1511 wdr->cmd_iohs[wd_features], 0); 1512 } 1513 callout_stop(&chp->ch_callout); 1514 chp->ch_queue->active_xfer = NULL; 1515 if (ata_c->flags & AT_POLL) { 1516 /* enable interrupts */ 1517 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1518 WDCTL_4BIT); 1519 delay(10); /* some drives need a little delay here */ 1520 } 1521 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1522 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1523 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1524 wakeup(&chp->ch_queue->active_xfer); 1525 } else 1526 __wdccommand_done_end(chp, xfer); 1527 } 1528 1529 static void 1530 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1531 { 1532 struct ata_command *ata_c = xfer->c_cmd; 1533 1534 ata_c->flags |= AT_DONE; 1535 ata_free_xfer(chp, xfer); 1536 if (ata_c->flags & AT_WAIT) 1537 wakeup(ata_c); 1538 else if (ata_c->callback) 1539 ata_c->callback(ata_c->callback_arg); 1540 atastart(chp); 1541 return; 1542 } 1543 1544 static void 1545 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1546 int reason) 1547 { 1548 struct ata_command *ata_c = xfer->c_cmd; 1549 1550 switch (reason) { 1551 case KILL_GONE: 1552 ata_c->flags |= AT_GONE; 1553 break; 1554 case KILL_RESET: 1555 ata_c->flags |= AT_RESET; 1556 break; 1557 default: 1558 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1559 reason); 1560 panic("__wdccommand_kill_xfer"); 1561 } 1562 __wdccommand_done_end(chp, xfer); 1563 } 1564 1565 /* 1566 * Send a command. The drive should be ready. 1567 * Assumes interrupts are blocked. 1568 */ 1569 void 1570 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1571 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1572 u_int8_t features) 1573 { 1574 struct atac_softc *atac = chp->ch_atac; 1575 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1576 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1577 1578 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1579 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1580 chp->ch_channel, drive, command, cylin, head, sector, count, 1581 features), DEBUG_FUNCS); 1582 1583 if (wdc->select) 1584 wdc->select(chp,drive); 1585 1586 /* Select drive, head, and addressing mode. */ 1587 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1588 WDSD_IBM | (drive << 4) | head); 1589 /* Load parameters into the wd_features register. */ 1590 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1591 features); 1592 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1593 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1594 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1596 0, cylin >> 8); 1597 1598 /* Send command. */ 1599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1600 return; 1601 } 1602 1603 /* 1604 * Send a 48-bit addressing command. The drive should be ready. 1605 * Assumes interrupts are blocked. 1606 */ 1607 void 1608 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1609 u_int64_t blkno, u_int16_t count) 1610 { 1611 struct atac_softc *atac = chp->ch_atac; 1612 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1613 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1614 1615 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1616 "count=%d\n", atac->atac_dev.dv_xname, 1617 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1618 DEBUG_FUNCS); 1619 1620 if (wdc->select) 1621 wdc->select(chp,drive); 1622 1623 /* Select drive, head, and addressing mode. */ 1624 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1625 (drive << 4) | WDSD_LBA); 1626 1627 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1628 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1629 0); 1630 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1631 0, count); 1632 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1633 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1634 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1635 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1636 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1637 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1638 } else { 1639 /* previous */ 1640 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1641 0); 1642 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1643 0, count >> 8); 1644 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1645 0, blkno >> 24); 1646 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1647 0, blkno >> 32); 1648 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1649 0, blkno >> 40); 1650 1651 /* current */ 1652 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1653 0); 1654 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1655 count); 1656 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1657 blkno); 1658 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1659 0, blkno >> 8); 1660 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1661 0, blkno >> 16); 1662 } 1663 1664 /* Send command. */ 1665 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1666 return; 1667 } 1668 1669 /* 1670 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1671 * tested by the caller. 1672 */ 1673 void 1674 wdccommandshort(struct ata_channel *chp, int drive, int command) 1675 { 1676 struct atac_softc *atac = chp->ch_atac; 1677 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1678 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1679 1680 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1681 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1682 DEBUG_FUNCS); 1683 1684 if (wdc->select) 1685 wdc->select(chp,drive); 1686 1687 /* Select drive. */ 1688 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1689 WDSD_IBM | (drive << 4)); 1690 1691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1692 } 1693 1694 static void 1695 __wdcerror(struct ata_channel *chp, const char *msg) 1696 { 1697 struct atac_softc *atac = chp->ch_atac; 1698 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1699 1700 if (xfer == NULL) 1701 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1702 msg); 1703 else 1704 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1705 chp->ch_channel, xfer->c_drive, msg); 1706 } 1707 1708 /* 1709 * the bit bucket 1710 */ 1711 void 1712 wdcbit_bucket(struct ata_channel *chp, int size) 1713 { 1714 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1715 1716 for (; size >= 2; size -= 2) 1717 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1718 if (size) 1719 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1720 } 1721 1722 static void 1723 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1724 { 1725 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1726 1727 if (flags & DRIVE_NOSTREAM) { 1728 if (flags & DRIVE_CAP32) { 1729 bus_space_read_multi_4(wdr->data32iot, 1730 wdr->data32ioh, 0, bf, len >> 2); 1731 bf = (char *)bf + (len & ~3); 1732 len &= 3; 1733 } 1734 if (len) { 1735 bus_space_read_multi_2(wdr->cmd_iot, 1736 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1737 } 1738 } else { 1739 if (flags & DRIVE_CAP32) { 1740 bus_space_read_multi_stream_4(wdr->data32iot, 1741 wdr->data32ioh, 0, bf, len >> 2); 1742 bf = (char *)bf + (len & ~3); 1743 len &= 3; 1744 } 1745 if (len) { 1746 bus_space_read_multi_stream_2(wdr->cmd_iot, 1747 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1748 } 1749 } 1750 } 1751 1752 static void 1753 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1754 { 1755 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1756 1757 if (flags & DRIVE_NOSTREAM) { 1758 if (flags & DRIVE_CAP32) { 1759 bus_space_write_multi_4(wdr->data32iot, 1760 wdr->data32ioh, 0, bf, len >> 2); 1761 bf = (char *)bf + (len & ~3); 1762 len &= 3; 1763 } 1764 if (len) { 1765 bus_space_write_multi_2(wdr->cmd_iot, 1766 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1767 } 1768 } else { 1769 if (flags & DRIVE_CAP32) { 1770 bus_space_write_multi_stream_4(wdr->data32iot, 1771 wdr->data32ioh, 0, bf, len >> 2); 1772 bf = (char *)bf + (len & ~3); 1773 len &= 3; 1774 } 1775 if (len) { 1776 bus_space_write_multi_stream_2(wdr->cmd_iot, 1777 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1778 } 1779 } 1780 } 1781
Indexes created Wed Sep 24 14:09:57 GMT 2025