wdc.c revision 1.238
1 /* $NetBSD: wdc.c,v 1.238 2006/09/30 15:56:17 itohy Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.238 2006/09/30 15:56:17 itohy Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "locators.h" 105 106 #include "atapibus.h" 107 #include "wd.h" 108 109 #define WDCDELAY 100 /* 100 microseconds */ 110 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 111 #if 0 112 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 113 #define WDCNDELAY_DEBUG 50 114 #endif 115 116 /* When polling wait that much and then tsleep for 1/hz seconds */ 117 #define WDCDELAY_POLL 1 /* ms */ 118 119 /* timeout for the control commands */ 120 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 121 122 /* 123 * timeout when waiting for BSY to deassert when probing. 124 * set to 5s. From the standards this could be up to 31, but we can't 125 * wait that much at boot time, and 5s seems to be enouth. 126 */ 127 #define WDC_PROBE_WAIT 5 128 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, /* wdc_ata_bio */ 137 NULL, /* wdc_reset_drive */ 138 wdc_reset_channel, 139 wdc_exec_command, 140 NULL, /* ata_get_params */ 141 NULL, /* wdc_ata_addref */ 142 NULL, /* wdc_ata_delref */ 143 NULL /* ata_kill_pending */ 144 }; 145 #endif 146 147 /* Flags to wdcreset(). */ 148 #define RESET_POLL 1 149 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 150 151 static int wdcprobe1(struct ata_channel *, int); 152 static int wdcreset(struct ata_channel *, int); 153 static void __wdcerror(struct ata_channel *, const char *); 154 static int __wdcwait_reset(struct ata_channel *, int, int); 155 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 156 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 157 static void __wdccommand_kill_xfer(struct ata_channel *, 158 struct ata_xfer *, int); 159 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 160 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 161 static int __wdcwait(struct ata_channel *, int, int, int); 162 163 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 164 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 165 166 #define DEBUG_INTR 0x01 167 #define DEBUG_XFERS 0x02 168 #define DEBUG_STATUS 0x04 169 #define DEBUG_FUNCS 0x08 170 #define DEBUG_PROBE 0x10 171 #define DEBUG_DETACH 0x20 172 #define DEBUG_DELAY 0x40 173 #ifdef ATADEBUG 174 extern int atadebug_mask; /* init'ed in ata.c */ 175 int wdc_nxfer = 0; 176 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 177 #else 178 #define ATADEBUG_PRINT(args, level) 179 #endif 180 181 /* 182 * Initialize the "shadow register" handles for a standard wdc controller. 183 */ 184 void 185 wdc_init_shadow_regs(struct ata_channel *chp) 186 { 187 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 188 189 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 190 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 191 } 192 193 /* 194 * Allocate a wdc_regs array, based on the number of channels. 195 */ 196 void 197 wdc_allocate_regs(struct wdc_softc *wdc) 198 { 199 200 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 201 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 202 } 203 204 /* Test to see controller with at last one attached drive is there. 205 * Returns a bit for each possible drive found (0x01 for drive 0, 206 * 0x02 for drive 1). 207 * Logic: 208 * - If a status register is at 0xff, assume there is no drive here 209 * (ISA has pull-up resistors). Similarly if the status register has 210 * the value we last wrote to the bus (for IDE interfaces without pullups). 211 * If no drive at all -> return. 212 * - reset the controller, wait for it to complete (may take up to 31s !). 213 * If timeout -> return. 214 * - test ATA/ATAPI signatures. If at last one drive found -> return. 215 * - try an ATA command on the master. 216 */ 217 218 static void 219 wdc_drvprobe(struct ata_channel *chp) 220 { 221 struct ataparams params; 222 struct atac_softc *atac = chp->ch_atac; 223 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 224 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 225 u_int8_t st0 = 0, st1 = 0; 226 int i, j, error, s; 227 228 if (wdcprobe1(chp, 0) == 0) { 229 /* No drives, abort the attach here. */ 230 return; 231 } 232 233 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 234 for (i = 0; i < mstohz(3000); i++) { 235 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 236 if (wdc->select) 237 wdc->select(chp,0); 238 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 239 0, WDSD_IBM); 240 delay(10); /* 400ns delay */ 241 st0 = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_status], 0); 243 } 244 245 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 246 if (wdc->select) 247 wdc->select(chp,1); 248 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 249 0, WDSD_IBM | 0x10); 250 delay(10); /* 400ns delay */ 251 st1 = bus_space_read_1(wdr->cmd_iot, 252 wdr->cmd_iohs[wd_status], 0); 253 } 254 255 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 256 == 0 || 257 (st0 & WDCS_DRDY)) && 258 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 259 == 0 || 260 (st1 & WDCS_DRDY))) 261 break; 262 tsleep(¶ms, PRIBIO, "atadrdy", 1); 263 } 264 s = splbio(); 265 if ((st0 & WDCS_DRDY) == 0) 266 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 267 if ((st1 & WDCS_DRDY) == 0) 268 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 269 splx(s); 270 271 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 272 atac->atac_dev.dv_xname, 273 chp->ch_channel, st0, st1), DEBUG_PROBE); 274 275 /* Wait a bit, some devices are weird just after a reset. */ 276 delay(5000); 277 278 for (i = 0; i < chp->ch_ndrive; i++) { 279 /* XXX This should be done by other code. */ 280 chp->ch_drive[i].chnl_softc = chp; 281 chp->ch_drive[i].drive = i; 282 283 #if NATA_DMA 284 /* 285 * Init error counter so that an error withing the first xfers 286 * will trigger a downgrade 287 */ 288 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 289 #endif 290 291 /* If controller can't do 16bit flag the drives as 32bit */ 292 if ((atac->atac_cap & 293 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 294 s = splbio(); 295 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 296 splx(s); 297 } 298 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 299 continue; 300 301 /* Shortcut in case we've been shutdown */ 302 if (chp->ch_flags & ATACH_SHUTDOWN) 303 return; 304 305 /* 306 * Issue an identify, to try to detect ghosts. 307 * Note that we can't use interrupts here, because if there 308 * is no devices, we will get a command aborted without 309 * interrupts. 310 */ 311 error = ata_get_params(&chp->ch_drive[i], 312 AT_WAIT | AT_POLL, ¶ms); 313 if (error != CMD_OK) { 314 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 315 316 /* Shortcut in case we've been shutdown */ 317 if (chp->ch_flags & ATACH_SHUTDOWN) 318 return; 319 320 error = ata_get_params(&chp->ch_drive[i], 321 AT_WAIT | AT_POLL, ¶ms); 322 } 323 if (error == CMD_OK) { 324 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 325 s = splbio(); 326 for (j = 0; j < chp->ch_ndrive; j++) 327 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 328 splx(s); 329 } else { 330 s = splbio(); 331 chp->ch_drive[i].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 splx(s); 334 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 335 atac->atac_dev.dv_xname, 336 chp->ch_channel, i, error), DEBUG_PROBE); 337 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 338 continue; 339 /* 340 * Pre-ATA drive ? 341 * Test registers writability (Error register not 342 * writable, but cyllo is), then try an ATA command. 343 */ 344 if (wdc->select) 345 wdc->select(chp,i); 346 bus_space_write_1(wdr->cmd_iot, 347 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 348 delay(10); /* 400ns delay */ 349 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 350 0, 0x58); 351 bus_space_write_1(wdr->cmd_iot, 352 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 353 if (bus_space_read_1(wdr->cmd_iot, 354 wdr->cmd_iohs[wd_error], 0) == 0x58 || 355 bus_space_read_1(wdr->cmd_iot, 356 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 357 ATADEBUG_PRINT(("%s:%d:%d: register " 358 "writability failed\n", 359 atac->atac_dev.dv_xname, 360 chp->ch_channel, i), DEBUG_PROBE); 361 s = splbio(); 362 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 363 splx(s); 364 continue; 365 } 366 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 367 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 368 atac->atac_dev.dv_xname, 369 chp->ch_channel, i), DEBUG_PROBE); 370 s = splbio(); 371 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 372 splx(s); 373 continue; 374 } 375 bus_space_write_1(wdr->cmd_iot, 376 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 377 delay(10); /* 400ns delay */ 378 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 379 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 380 atac->atac_dev.dv_xname, 381 chp->ch_channel, i), DEBUG_PROBE); 382 s = splbio(); 383 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 384 splx(s); 385 } else { 386 s = splbio(); 387 for (j = 0; j < chp->ch_ndrive; j++) 388 chp->ch_drive[j].drive_flags &= 389 ~(DRIVE_ATA | DRIVE_ATAPI); 390 splx(s); 391 } 392 } 393 } 394 } 395 396 int 397 wdcprobe(struct ata_channel *chp) 398 { 399 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 400 /* default reset method */ 401 if (wdc->reset == NULL) 402 wdc->reset = wdc_do_reset; 403 404 return (wdcprobe1(chp, 1)); 405 } 406 407 static int 408 wdcprobe1(struct ata_channel *chp, int poll) 409 { 410 struct atac_softc *atac = chp->ch_atac; 411 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 412 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 413 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 414 u_int8_t ret_value = 0x03; 415 u_int8_t drive; 416 int s; 417 int wdc_probe_count = 418 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 419 420 /* 421 * Sanity check to see if the wdc channel responds at all. 422 */ 423 424 s = splbio(); 425 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 426 while (wdc_probe_count-- > 0) { 427 if (wdc->select) 428 wdc->select(chp,0); 429 430 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 431 0, WDSD_IBM); 432 delay(10); /* 400ns delay */ 433 st0 = bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_status], 0); 435 436 if (wdc->select) 437 wdc->select(chp,1); 438 439 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 440 0, WDSD_IBM | 0x10); 441 delay(10); /* 400ns delay */ 442 st1 = bus_space_read_1(wdr->cmd_iot, 443 wdr->cmd_iohs[wd_status], 0); 444 if ((st0 & WDCS_BSY) == 0) 445 break; 446 } 447 448 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 449 atac->atac_dev.dv_xname, 450 chp->ch_channel, st0, st1), DEBUG_PROBE); 451 452 if (st0 == 0xff || st0 == WDSD_IBM) 453 ret_value &= ~0x01; 454 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 455 ret_value &= ~0x02; 456 /* Register writability test, drive 0. */ 457 if (ret_value & 0x01) { 458 if (wdc->select) 459 wdc->select(chp,0); 460 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 461 0, WDSD_IBM); 462 bus_space_write_1(wdr->cmd_iot, 463 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 464 cl = bus_space_read_1(wdr->cmd_iot, 465 wdr->cmd_iohs[wd_cyl_lo], 0); 466 if (cl != 0x02) { 467 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 468 "got 0x%x != 0x02\n", 469 atac->atac_dev.dv_xname, 470 chp->ch_channel, cl), 471 DEBUG_PROBE); 472 ret_value &= ~0x01; 473 } 474 bus_space_write_1(wdr->cmd_iot, 475 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 476 cl = bus_space_read_1(wdr->cmd_iot, 477 wdr->cmd_iohs[wd_cyl_lo], 0); 478 if (cl != 0x01) { 479 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 480 "got 0x%x != 0x01\n", 481 atac->atac_dev.dv_xname, 482 chp->ch_channel, cl), 483 DEBUG_PROBE); 484 ret_value &= ~0x01; 485 } 486 bus_space_write_1(wdr->cmd_iot, 487 wdr->cmd_iohs[wd_sector], 0, 0x01); 488 cl = bus_space_read_1(wdr->cmd_iot, 489 wdr->cmd_iohs[wd_sector], 0); 490 if (cl != 0x01) { 491 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 492 "got 0x%x != 0x01\n", 493 atac->atac_dev.dv_xname, 494 chp->ch_channel, cl), 495 DEBUG_PROBE); 496 ret_value &= ~0x01; 497 } 498 bus_space_write_1(wdr->cmd_iot, 499 wdr->cmd_iohs[wd_sector], 0, 0x02); 500 cl = bus_space_read_1(wdr->cmd_iot, 501 wdr->cmd_iohs[wd_sector], 0); 502 if (cl != 0x02) { 503 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 504 "got 0x%x != 0x02\n", 505 atac->atac_dev.dv_xname, 506 chp->ch_channel, cl), 507 DEBUG_PROBE); 508 ret_value &= ~0x01; 509 } 510 cl = bus_space_read_1(wdr->cmd_iot, 511 wdr->cmd_iohs[wd_cyl_lo], 0); 512 if (cl != 0x01) { 513 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 514 "got 0x%x != 0x01\n", 515 atac->atac_dev.dv_xname, 516 chp->ch_channel, cl), 517 DEBUG_PROBE); 518 ret_value &= ~0x01; 519 } 520 } 521 /* Register writability test, drive 1. */ 522 if (ret_value & 0x02) { 523 if (wdc->select) 524 wdc->select(chp,1); 525 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 526 0, WDSD_IBM | 0x10); 527 bus_space_write_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 529 cl = bus_space_read_1(wdr->cmd_iot, 530 wdr->cmd_iohs[wd_cyl_lo], 0); 531 if (cl != 0x02) { 532 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 533 "got 0x%x != 0x02\n", 534 atac->atac_dev.dv_xname, 535 chp->ch_channel, cl), 536 DEBUG_PROBE); 537 ret_value &= ~0x02; 538 } 539 bus_space_write_1(wdr->cmd_iot, 540 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 541 cl = bus_space_read_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_cyl_lo], 0); 543 if (cl != 0x01) { 544 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 545 "got 0x%x != 0x01\n", 546 atac->atac_dev.dv_xname, 547 chp->ch_channel, cl), 548 DEBUG_PROBE); 549 ret_value &= ~0x02; 550 } 551 bus_space_write_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_sector], 0, 0x01); 553 cl = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_sector], 0); 555 if (cl != 0x01) { 556 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 557 "got 0x%x != 0x01\n", 558 atac->atac_dev.dv_xname, 559 chp->ch_channel, cl), 560 DEBUG_PROBE); 561 ret_value &= ~0x02; 562 } 563 bus_space_write_1(wdr->cmd_iot, 564 wdr->cmd_iohs[wd_sector], 0, 0x02); 565 cl = bus_space_read_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_sector], 0); 567 if (cl != 0x02) { 568 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 569 "got 0x%x != 0x02\n", 570 atac->atac_dev.dv_xname, 571 chp->ch_channel, cl), 572 DEBUG_PROBE); 573 ret_value &= ~0x02; 574 } 575 cl = bus_space_read_1(wdr->cmd_iot, 576 wdr->cmd_iohs[wd_cyl_lo], 0); 577 if (cl != 0x01) { 578 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 579 "got 0x%x != 0x01\n", 580 atac->atac_dev.dv_xname, 581 chp->ch_channel, cl), 582 DEBUG_PROBE); 583 ret_value &= ~0x02; 584 } 585 } 586 587 if (ret_value == 0) { 588 splx(s); 589 return 0; 590 } 591 } 592 593 594 #if 0 /* XXX this break some ATA or ATAPI devices */ 595 /* 596 * reset bus. Also send an ATAPI_RESET to devices, in case there are 597 * ATAPI device out there which don't react to the bus reset 598 */ 599 if (ret_value & 0x01) { 600 if (wdc->select) 601 wdc->select(chp,0); 602 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 603 0, WDSD_IBM); 604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 605 ATAPI_SOFT_RESET); 606 } 607 if (ret_value & 0x02) { 608 if (wdc->select) 609 wdc->select(chp,0); 610 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 611 0, WDSD_IBM | 0x10); 612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 613 ATAPI_SOFT_RESET); 614 } 615 616 delay(5000); 617 #endif 618 619 wdc->reset(chp, RESET_POLL); 620 DELAY(2000); 621 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 622 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 623 splx(s); 624 625 ret_value = __wdcwait_reset(chp, ret_value, poll); 626 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 627 atac->atac_dev.dv_xname, chp->ch_channel, 628 ret_value), DEBUG_PROBE); 629 630 /* if reset failed, there's nothing here */ 631 if (ret_value == 0) 632 return 0; 633 634 /* 635 * Test presence of drives. First test register signatures looking 636 * for ATAPI devices. If it's not an ATAPI and reset said there may 637 * be something here assume it's ATA or OLD. Ghost will be killed 638 * later in attach routine. 639 */ 640 for (drive = 0; drive < chp->ch_ndrive; drive++) { 641 if ((ret_value & (0x01 << drive)) == 0) 642 continue; 643 if (wdc->select) 644 wdc->select(chp,drive); 645 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 646 WDSD_IBM | (drive << 4)); 647 delay(10); /* 400ns delay */ 648 /* Save registers contents */ 649 sc = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_seccnt], 0); 651 sn = bus_space_read_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_sector], 0); 653 cl = bus_space_read_1(wdr->cmd_iot, 654 wdr->cmd_iohs[wd_cyl_lo], 0); 655 ch = bus_space_read_1(wdr->cmd_iot, 656 wdr->cmd_iohs[wd_cyl_hi], 0); 657 658 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 659 "cl=0x%x ch=0x%x\n", 660 atac->atac_dev.dv_xname, 661 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 662 /* 663 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 664 * we get wrong values here, so ignore it. 665 */ 666 s = splbio(); 667 if (cl == 0x14 && ch == 0xeb) { 668 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 669 } else { 670 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 671 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 672 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 673 } 674 splx(s); 675 } 676 return (ret_value); 677 } 678 679 void 680 wdcattach(struct ata_channel *chp) 681 { 682 struct atac_softc *atac = chp->ch_atac; 683 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 684 685 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 686 687 /* default data transfer methods */ 688 if (wdc->datain_pio == NULL) 689 wdc->datain_pio = wdc_datain_pio; 690 if (wdc->dataout_pio == NULL) 691 wdc->dataout_pio = wdc_dataout_pio; 692 /* default reset method */ 693 if (wdc->reset == NULL) 694 wdc->reset = wdc_do_reset; 695 696 /* initialise global data */ 697 if (atac->atac_bustype_ata == NULL) 698 atac->atac_bustype_ata = &wdc_ata_bustype; 699 if (atac->atac_probe == NULL) 700 atac->atac_probe = wdc_drvprobe; 701 #if NATAPIBUS > 0 702 if (atac->atac_atapibus_attach == NULL) 703 atac->atac_atapibus_attach = wdc_atapibus_attach; 704 #endif 705 706 ata_channel_attach(chp); 707 } 708 709 int 710 wdcactivate(struct device *self, enum devact act) 711 { 712 struct atac_softc *atac = (struct atac_softc *) self; 713 int s, i, error = 0; 714 715 s = splbio(); 716 switch (act) { 717 case DVACT_ACTIVATE: 718 error = EOPNOTSUPP; 719 break; 720 721 case DVACT_DEACTIVATE: 722 for (i = 0; i < atac->atac_nchannels; i++) { 723 error = 724 config_deactivate(atac->atac_channels[i]->atabus); 725 if (error) 726 break; 727 } 728 break; 729 } 730 splx(s); 731 return (error); 732 } 733 734 int 735 wdcdetach(struct device *self, int flags) 736 { 737 struct atac_softc *atac = (struct atac_softc *) self; 738 struct ata_channel *chp; 739 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 740 int i, error = 0; 741 742 for (i = 0; i < atac->atac_nchannels; i++) { 743 chp = atac->atac_channels[i]; 744 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 745 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 746 DEBUG_DETACH); 747 error = config_detach(chp->atabus, flags); 748 if (error) 749 break; 750 } 751 if (adapt->adapt_refcnt != 0) { 752 #ifdef DIAGNOSTIC 753 printf("wdcdetach: refcnt should be 0 here??\n"); 754 #endif 755 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 756 } 757 return (error); 758 } 759 760 /* restart an interrupted I/O */ 761 void 762 wdcrestart(void *v) 763 { 764 struct ata_channel *chp = v; 765 int s; 766 767 s = splbio(); 768 atastart(chp); 769 splx(s); 770 } 771 772 773 /* 774 * Interrupt routine for the controller. Acknowledge the interrupt, check for 775 * errors on the current operation, mark it done if necessary, and start the 776 * next request. Also check for a partially done transfer, and continue with 777 * the next chunk if so. 778 */ 779 int 780 wdcintr(void *arg) 781 { 782 struct ata_channel *chp = arg; 783 struct atac_softc *atac = chp->ch_atac; 784 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 785 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 786 struct ata_xfer *xfer; 787 int ret; 788 789 if (!device_is_active(&atac->atac_dev)) { 790 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 791 DEBUG_INTR); 792 return (0); 793 } 794 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 795 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 796 /* try to clear the pending interrupt anyway */ 797 (void)bus_space_read_1(wdr->cmd_iot, 798 wdr->cmd_iohs[wd_status], 0); 799 return (0); 800 } 801 802 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 803 xfer = chp->ch_queue->active_xfer; 804 #ifdef DIAGNOSTIC 805 if (xfer == NULL) 806 panic("wdcintr: no xfer"); 807 if (xfer->c_chp != chp) { 808 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 809 chp->ch_channel); 810 panic("wdcintr: wrong channel"); 811 } 812 #endif 813 #if NATA_DMA || NATA_PIOBM 814 if (chp->ch_flags & ATACH_DMA_WAIT) { 815 wdc->dma_status = 816 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 817 xfer->c_drive, WDC_DMAEND_END); 818 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 819 /* IRQ not for us, not detected by DMA engine */ 820 return 0; 821 } 822 chp->ch_flags &= ~ATACH_DMA_WAIT; 823 } 824 #endif 825 chp->ch_flags &= ~ATACH_IRQ_WAIT; 826 ret = xfer->c_intr(chp, xfer, 1); 827 if (ret == 0) /* irq was not for us, still waiting for irq */ 828 chp->ch_flags |= ATACH_IRQ_WAIT; 829 return (ret); 830 } 831 832 /* Put all disk in RESET state */ 833 void 834 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 835 { 836 struct ata_channel *chp = drvp->chnl_softc; 837 struct atac_softc *atac = chp->ch_atac; 838 839 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 840 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 841 DEBUG_FUNCS); 842 843 ata_reset_channel(chp, flags); 844 } 845 846 void 847 wdc_reset_channel(struct ata_channel *chp, int flags) 848 { 849 TAILQ_HEAD(, ata_xfer) reset_xfer; 850 struct ata_xfer *xfer, *next_xfer; 851 #if NATA_DMA || NATA_PIOBM 852 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 853 #endif 854 855 TAILQ_INIT(&reset_xfer); 856 857 chp->ch_flags &= ~ATACH_IRQ_WAIT; 858 859 /* 860 * if the current command if on an ATAPI device, issue a 861 * ATAPI_SOFT_RESET 862 */ 863 xfer = chp->ch_queue->active_xfer; 864 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 865 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 866 if (flags & AT_WAIT) 867 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 868 else 869 delay(1000); 870 } 871 872 /* reset the channel */ 873 if (flags & AT_WAIT) 874 (void) wdcreset(chp, RESET_SLEEP); 875 else 876 (void) wdcreset(chp, RESET_POLL); 877 878 /* 879 * wait a bit after reset; in case the DMA engines needs some time 880 * to recover. 881 */ 882 if (flags & AT_WAIT) 883 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 884 else 885 delay(1000); 886 /* 887 * look for pending xfers. If we have a shared queue, we'll also reset 888 * the other channel if the current xfer is running on it. 889 * Then we'll dequeue only the xfers for this channel. 890 */ 891 if ((flags & AT_RST_NOCMD) == 0) { 892 /* 893 * move all xfers queued for this channel to the reset queue, 894 * and then process the current xfer and then the reset queue. 895 * We have to use a temporary queue because c_kill_xfer() 896 * may requeue commands. 897 */ 898 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 899 xfer != NULL; xfer = next_xfer) { 900 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 901 if (xfer->c_chp != chp) 902 continue; 903 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 904 xfer, c_xferchain); 905 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 906 } 907 xfer = chp->ch_queue->active_xfer; 908 if (xfer) { 909 if (xfer->c_chp != chp) 910 ata_reset_channel(xfer->c_chp, flags); 911 else { 912 callout_stop(&chp->ch_callout); 913 #if NATA_DMA || NATA_PIOBM 914 /* 915 * If we're waiting for DMA, stop the 916 * DMA engine 917 */ 918 if (chp->ch_flags & ATACH_DMA_WAIT) { 919 (*wdc->dma_finish)( 920 wdc->dma_arg, 921 chp->ch_channel, 922 xfer->c_drive, 923 WDC_DMAEND_ABRT_QUIET); 924 chp->ch_flags &= ~ATACH_DMA_WAIT; 925 } 926 #endif 927 chp->ch_queue->active_xfer = NULL; 928 if ((flags & AT_RST_EMERG) == 0) 929 xfer->c_kill_xfer( 930 chp, xfer, KILL_RESET); 931 } 932 } 933 934 for (xfer = TAILQ_FIRST(&reset_xfer); 935 xfer != NULL; xfer = next_xfer) { 936 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 937 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 938 if ((flags & AT_RST_EMERG) == 0) 939 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 940 } 941 } 942 } 943 944 static int 945 wdcreset(struct ata_channel *chp, int poll) 946 { 947 struct atac_softc *atac = chp->ch_atac; 948 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 949 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 950 int drv_mask1, drv_mask2; 951 952 wdc->reset(chp, poll); 953 954 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 955 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 956 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 957 (poll == RESET_SLEEP) ? 0 : 1); 958 if (drv_mask2 != drv_mask1) { 959 printf("%s channel %d: reset failed for", 960 atac->atac_dev.dv_xname, chp->ch_channel); 961 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 962 printf(" drive 0"); 963 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 964 printf(" drive 1"); 965 printf("\n"); 966 } 967 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 968 return (drv_mask1 != drv_mask2) ? 1 : 0; 969 } 970 971 void 972 wdc_do_reset(struct ata_channel *chp, int poll) 973 { 974 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 975 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 976 int s = 0; 977 978 if (poll != RESET_SLEEP) 979 s = splbio(); 980 if (wdc->select) 981 wdc->select(chp,0); 982 /* master */ 983 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 984 delay(10); /* 400ns delay */ 985 /* assert SRST, wait for reset to complete */ 986 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 987 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 988 delay(2000); 989 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 990 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 991 WDCTL_4BIT | WDCTL_IDS); 992 delay(10); /* 400ns delay */ 993 if (poll != RESET_SLEEP) { 994 /* ACK interrupt in case there is one pending left */ 995 if (wdc->irqack) 996 wdc->irqack(chp); 997 splx(s); 998 } 999 } 1000 1001 static int 1002 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1003 { 1004 struct atac_softc *atac = chp->ch_atac; 1005 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1006 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1007 int timeout, nloop; 1008 u_int8_t st0 = 0, st1 = 0; 1009 #ifdef ATADEBUG 1010 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1011 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1012 #endif 1013 1014 if (poll) 1015 nloop = WDCNDELAY_RST; 1016 else 1017 nloop = WDC_RESET_WAIT * hz / 1000; 1018 /* wait for BSY to deassert */ 1019 for (timeout = 0; timeout < nloop; timeout++) { 1020 if ((drv_mask & 0x01) != 0) { 1021 if (wdc->select) 1022 wdc->select(chp,0); 1023 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1024 0, WDSD_IBM); /* master */ 1025 delay(10); 1026 st0 = bus_space_read_1(wdr->cmd_iot, 1027 wdr->cmd_iohs[wd_status], 0); 1028 #ifdef ATADEBUG 1029 sc0 = bus_space_read_1(wdr->cmd_iot, 1030 wdr->cmd_iohs[wd_seccnt], 0); 1031 sn0 = bus_space_read_1(wdr->cmd_iot, 1032 wdr->cmd_iohs[wd_sector], 0); 1033 cl0 = bus_space_read_1(wdr->cmd_iot, 1034 wdr->cmd_iohs[wd_cyl_lo], 0); 1035 ch0 = bus_space_read_1(wdr->cmd_iot, 1036 wdr->cmd_iohs[wd_cyl_hi], 0); 1037 #endif 1038 } 1039 if ((drv_mask & 0x02) != 0) { 1040 if (wdc->select) 1041 wdc->select(chp,1); 1042 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1043 0, WDSD_IBM | 0x10); /* slave */ 1044 delay(10); 1045 st1 = bus_space_read_1(wdr->cmd_iot, 1046 wdr->cmd_iohs[wd_status], 0); 1047 #ifdef ATADEBUG 1048 sc1 = bus_space_read_1(wdr->cmd_iot, 1049 wdr->cmd_iohs[wd_seccnt], 0); 1050 sn1 = bus_space_read_1(wdr->cmd_iot, 1051 wdr->cmd_iohs[wd_sector], 0); 1052 cl1 = bus_space_read_1(wdr->cmd_iot, 1053 wdr->cmd_iohs[wd_cyl_lo], 0); 1054 ch1 = bus_space_read_1(wdr->cmd_iot, 1055 wdr->cmd_iohs[wd_cyl_hi], 0); 1056 #endif 1057 } 1058 1059 if ((drv_mask & 0x01) == 0) { 1060 /* no master */ 1061 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1062 /* No master, slave is ready, it's done */ 1063 goto end; 1064 } 1065 if ((drv_mask & 0x02) == 0) { 1066 /* No master, no slave: it's done */ 1067 goto end; 1068 } 1069 } else if ((drv_mask & 0x02) == 0) { 1070 /* no slave */ 1071 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1072 /* No slave, master is ready, it's done */ 1073 goto end; 1074 } 1075 } else { 1076 /* Wait for both master and slave to be ready */ 1077 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1078 goto end; 1079 } 1080 } 1081 if (poll) 1082 delay(WDCDELAY); 1083 else 1084 tsleep(&nloop, PRIBIO, "atarst", 1); 1085 } 1086 /* Reset timed out. Maybe it's because drv_mask was not right */ 1087 if (st0 & WDCS_BSY) 1088 drv_mask &= ~0x01; 1089 if (st1 & WDCS_BSY) 1090 drv_mask &= ~0x02; 1091 end: 1092 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1093 "cl=0x%x ch=0x%x\n", 1094 atac->atac_dev.dv_xname, 1095 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1096 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1097 "cl=0x%x ch=0x%x\n", 1098 atac->atac_dev.dv_xname, 1099 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1100 1101 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1102 atac->atac_dev.dv_xname, chp->ch_channel, 1103 st0, st1), DEBUG_PROBE); 1104 1105 return drv_mask; 1106 } 1107 1108 /* 1109 * Wait for a drive to be !BSY, and have mask in its status register. 1110 * return -1 for a timeout after "timeout" ms. 1111 */ 1112 static int 1113 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1114 { 1115 struct atac_softc *atac = chp->ch_atac; 1116 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1117 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1118 u_char status; 1119 int xtime = 0; 1120 1121 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1122 atac->atac_dev.dv_xname, 1123 chp->ch_channel), DEBUG_STATUS); 1124 chp->ch_error = 0; 1125 1126 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1127 1128 for (;;) { 1129 chp->ch_status = status = 1130 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1131 if ((status & (WDCS_BSY | mask)) == bits) 1132 break; 1133 if (++xtime > timeout) { 1134 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1135 "status %x error %x (mask 0x%x bits 0x%x)\n", 1136 xtime, status, 1137 bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_error], 0), mask, bits), 1139 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1140 return(WDCWAIT_TOUT); 1141 } 1142 delay(WDCDELAY); 1143 } 1144 #ifdef ATADEBUG 1145 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1146 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1147 #endif 1148 if (status & WDCS_ERR) 1149 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1150 wdr->cmd_iohs[wd_error], 0); 1151 #ifdef WDCNDELAY_DEBUG 1152 /* After autoconfig, there should be no long delays. */ 1153 if (!cold && xtime > WDCNDELAY_DEBUG) { 1154 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1155 if (xfer == NULL) 1156 printf("%s channel %d: warning: busy-wait took %dus\n", 1157 atac->atac_dev.dv_xname, chp->ch_channel, 1158 WDCDELAY * xtime); 1159 else 1160 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1161 atac->atac_dev.dv_xname, chp->ch_channel, 1162 xfer->c_drive, 1163 WDCDELAY * xtime); 1164 } 1165 #endif 1166 return(WDCWAIT_OK); 1167 } 1168 1169 /* 1170 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1171 * thread if possible 1172 */ 1173 int 1174 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1175 { 1176 int error, i, timeout_hz = mstohz(timeout); 1177 1178 if (timeout_hz == 0 || 1179 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1180 error = __wdcwait(chp, mask, bits, timeout); 1181 else { 1182 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1183 if (error != 0) { 1184 if ((chp->ch_flags & ATACH_TH_RUN) || 1185 (flags & AT_WAIT)) { 1186 /* 1187 * we're running in the channel thread 1188 * or some userland thread context 1189 */ 1190 for (i = 0; i < timeout_hz; i++) { 1191 if (__wdcwait(chp, mask, bits, 1192 WDCDELAY_POLL) == 0) { 1193 error = 0; 1194 break; 1195 } 1196 tsleep(&chp, PRIBIO, "atapoll", 1); 1197 } 1198 } else { 1199 /* 1200 * we're probably in interrupt context, 1201 * ask the thread to come back here 1202 */ 1203 #ifdef DIAGNOSTIC 1204 if (chp->ch_queue->queue_freeze > 0) 1205 panic("wdcwait: queue_freeze"); 1206 #endif 1207 chp->ch_queue->queue_freeze++; 1208 wakeup(&chp->ch_thread); 1209 return(WDCWAIT_THR); 1210 } 1211 } 1212 } 1213 return (error); 1214 } 1215 1216 1217 #if NATA_DMA 1218 /* 1219 * Busy-wait for DMA to complete 1220 */ 1221 int 1222 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1223 { 1224 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1225 int xtime; 1226 1227 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1228 wdc->dma_status = 1229 (*wdc->dma_finish)(wdc->dma_arg, 1230 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1231 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1232 return 0; 1233 delay(WDCDELAY); 1234 } 1235 /* timeout, force a DMA halt */ 1236 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1237 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1238 return 1; 1239 } 1240 #endif 1241 1242 void 1243 wdctimeout(void *arg) 1244 { 1245 struct ata_channel *chp = (struct ata_channel *)arg; 1246 #if NATA_DMA || NATA_PIOBM 1247 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1248 #endif 1249 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1250 int s; 1251 1252 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1253 1254 s = splbio(); 1255 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1256 __wdcerror(chp, "lost interrupt"); 1257 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1258 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1259 xfer->c_bcount, 1260 xfer->c_skip); 1261 #if NATA_DMA || NATA_PIOBM 1262 if (chp->ch_flags & ATACH_DMA_WAIT) { 1263 wdc->dma_status = 1264 (*wdc->dma_finish)(wdc->dma_arg, 1265 chp->ch_channel, xfer->c_drive, 1266 WDC_DMAEND_ABRT); 1267 chp->ch_flags &= ~ATACH_DMA_WAIT; 1268 } 1269 #endif 1270 /* 1271 * Call the interrupt routine. If we just missed an interrupt, 1272 * it will do what's needed. Else, it will take the needed 1273 * action (reset the device). 1274 * Before that we need to reinstall the timeout callback, 1275 * in case it will miss another irq while in this transfer 1276 * We arbitray chose it to be 1s 1277 */ 1278 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1279 xfer->c_flags |= C_TIMEOU; 1280 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1281 xfer->c_intr(chp, xfer, 1); 1282 } else 1283 __wdcerror(chp, "missing untimeout"); 1284 splx(s); 1285 } 1286 1287 int 1288 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1289 { 1290 struct ata_channel *chp = drvp->chnl_softc; 1291 struct atac_softc *atac = chp->ch_atac; 1292 struct ata_xfer *xfer; 1293 int s, ret; 1294 1295 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1296 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1297 DEBUG_FUNCS); 1298 1299 /* set up an xfer and queue. Wait for completion */ 1300 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1301 ATAXF_NOSLEEP); 1302 if (xfer == NULL) { 1303 return ATACMD_TRY_AGAIN; 1304 } 1305 1306 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1307 ata_c->flags |= AT_POLL; 1308 if (ata_c->flags & AT_POLL) 1309 xfer->c_flags |= C_POLL; 1310 if (ata_c->flags & AT_WAIT) 1311 xfer->c_flags |= C_WAIT; 1312 xfer->c_drive = drvp->drive; 1313 xfer->c_databuf = ata_c->data; 1314 xfer->c_bcount = ata_c->bcount; 1315 xfer->c_cmd = ata_c; 1316 xfer->c_start = __wdccommand_start; 1317 xfer->c_intr = __wdccommand_intr; 1318 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1319 1320 s = splbio(); 1321 ata_exec_xfer(chp, xfer); 1322 #ifdef DIAGNOSTIC 1323 if ((ata_c->flags & AT_POLL) != 0 && 1324 (ata_c->flags & AT_DONE) == 0) 1325 panic("wdc_exec_command: polled command not done"); 1326 #endif 1327 if (ata_c->flags & AT_DONE) { 1328 ret = ATACMD_COMPLETE; 1329 } else { 1330 if (ata_c->flags & AT_WAIT) { 1331 while ((ata_c->flags & AT_DONE) == 0) { 1332 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1333 } 1334 ret = ATACMD_COMPLETE; 1335 } else { 1336 ret = ATACMD_QUEUED; 1337 } 1338 } 1339 splx(s); 1340 return ret; 1341 } 1342 1343 static void 1344 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1345 { 1346 struct atac_softc *atac = chp->ch_atac; 1347 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1348 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1349 int drive = xfer->c_drive; 1350 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1351 struct ata_command *ata_c = xfer->c_cmd; 1352 1353 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1354 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1355 DEBUG_FUNCS); 1356 1357 if (wdc->select) 1358 wdc->select(chp,drive); 1359 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1360 WDSD_IBM | (drive << 4)); 1361 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1362 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1363 case WDCWAIT_OK: 1364 break; 1365 case WDCWAIT_TOUT: 1366 ata_c->flags |= AT_TIMEOU; 1367 __wdccommand_done(chp, xfer); 1368 return; 1369 case WDCWAIT_THR: 1370 return; 1371 } 1372 if (ata_c->flags & AT_POLL) { 1373 /* polled command, disable interrupts */ 1374 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1375 WDCTL_4BIT | WDCTL_IDS); 1376 } 1377 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1378 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1379 1380 if ((ata_c->flags & AT_POLL) == 0) { 1381 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1382 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1383 wdctimeout, chp); 1384 return; 1385 } 1386 /* 1387 * Polled command. Wait for drive ready or drq. Done in intr(). 1388 * Wait for at last 400ns for status bit to be valid. 1389 */ 1390 delay(10); /* 400ns delay */ 1391 __wdccommand_intr(chp, xfer, 0); 1392 } 1393 1394 static int 1395 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1396 { 1397 struct atac_softc *atac = chp->ch_atac; 1398 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1399 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1400 struct ata_command *ata_c = xfer->c_cmd; 1401 int bcount = ata_c->bcount; 1402 char *data = ata_c->data; 1403 int wflags; 1404 int drive_flags; 1405 1406 if (ata_c->r_command == WDCC_IDENTIFY || 1407 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1408 /* 1409 * The IDENTIFY data has been designed as an array of 1410 * u_int16_t, so we can byteswap it on the fly. 1411 * Historically it's what we have always done so keeping it 1412 * here ensure binary backward compatibility. 1413 */ 1414 drive_flags = DRIVE_NOSTREAM | 1415 chp->ch_drive[xfer->c_drive].drive_flags; 1416 } else { 1417 /* 1418 * Other data structure are opaque and should be transfered 1419 * as is. 1420 */ 1421 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1422 } 1423 1424 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1425 /* both wait and poll, we can tsleep here */ 1426 wflags = AT_WAIT | AT_POLL; 1427 } else { 1428 wflags = AT_POLL; 1429 } 1430 1431 again: 1432 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1433 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1434 DEBUG_INTR); 1435 /* 1436 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1437 * Reselect again, it doesn't hurt for others commands, and the time 1438 * penalty for the extra regiter write is acceptable, 1439 * wdc_exec_command() isn't called often (mosly for autoconfig) 1440 */ 1441 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1442 WDSD_IBM | (xfer->c_drive << 4)); 1443 if ((ata_c->flags & AT_XFDONE) != 0) { 1444 /* 1445 * We have completed a data xfer. The drive should now be 1446 * in its initial state 1447 */ 1448 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1449 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1450 wflags) == WDCWAIT_TOUT) { 1451 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1452 return 0; /* IRQ was not for us */ 1453 ata_c->flags |= AT_TIMEOU; 1454 } 1455 goto out; 1456 } 1457 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1458 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1459 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1460 return 0; /* IRQ was not for us */ 1461 ata_c->flags |= AT_TIMEOU; 1462 goto out; 1463 } 1464 if (wdc->irqack) 1465 wdc->irqack(chp); 1466 if (ata_c->flags & AT_READ) { 1467 if ((chp->ch_status & WDCS_DRQ) == 0) { 1468 ata_c->flags |= AT_TIMEOU; 1469 goto out; 1470 } 1471 wdc->datain_pio(chp, drive_flags, data, bcount); 1472 /* at this point the drive should be in its initial state */ 1473 ata_c->flags |= AT_XFDONE; 1474 /* 1475 * XXX checking the status register again here cause some 1476 * hardware to timeout. 1477 */ 1478 } else if (ata_c->flags & AT_WRITE) { 1479 if ((chp->ch_status & WDCS_DRQ) == 0) { 1480 ata_c->flags |= AT_TIMEOU; 1481 goto out; 1482 } 1483 wdc->dataout_pio(chp, drive_flags, data, bcount); 1484 ata_c->flags |= AT_XFDONE; 1485 if ((ata_c->flags & AT_POLL) == 0) { 1486 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1487 callout_reset(&chp->ch_callout, 1488 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1489 return 1; 1490 } else { 1491 goto again; 1492 } 1493 } 1494 out: 1495 __wdccommand_done(chp, xfer); 1496 return 1; 1497 } 1498 1499 static void 1500 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1501 { 1502 struct atac_softc *atac = chp->ch_atac; 1503 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1504 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1505 struct ata_command *ata_c = xfer->c_cmd; 1506 1507 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1508 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1509 ata_c->flags), DEBUG_FUNCS); 1510 1511 1512 if (chp->ch_status & WDCS_DWF) 1513 ata_c->flags |= AT_DF; 1514 if (chp->ch_status & WDCS_ERR) { 1515 ata_c->flags |= AT_ERROR; 1516 ata_c->r_error = chp->ch_error; 1517 } 1518 if ((ata_c->flags & AT_READREG) != 0 && 1519 device_is_active(&atac->atac_dev) && 1520 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1521 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1522 wdr->cmd_iohs[wd_sdh], 0); 1523 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1524 wdr->cmd_iohs[wd_seccnt], 0); 1525 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1526 wdr->cmd_iohs[wd_sector], 0); 1527 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1528 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1529 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1530 wdr->cmd_iohs[wd_cyl_lo], 0); 1531 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1532 wdr->cmd_iohs[wd_error], 0); 1533 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1534 wdr->cmd_iohs[wd_features], 0); 1535 } 1536 callout_stop(&chp->ch_callout); 1537 chp->ch_queue->active_xfer = NULL; 1538 if (ata_c->flags & AT_POLL) { 1539 /* enable interrupts */ 1540 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1541 WDCTL_4BIT); 1542 delay(10); /* some drives need a little delay here */ 1543 } 1544 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1545 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1546 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1547 wakeup(&chp->ch_queue->active_xfer); 1548 } else 1549 __wdccommand_done_end(chp, xfer); 1550 } 1551 1552 static void 1553 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1554 { 1555 struct ata_command *ata_c = xfer->c_cmd; 1556 1557 ata_c->flags |= AT_DONE; 1558 ata_free_xfer(chp, xfer); 1559 if (ata_c->flags & AT_WAIT) 1560 wakeup(ata_c); 1561 else if (ata_c->callback) 1562 ata_c->callback(ata_c->callback_arg); 1563 atastart(chp); 1564 return; 1565 } 1566 1567 static void 1568 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1569 int reason) 1570 { 1571 struct ata_command *ata_c = xfer->c_cmd; 1572 1573 switch (reason) { 1574 case KILL_GONE: 1575 ata_c->flags |= AT_GONE; 1576 break; 1577 case KILL_RESET: 1578 ata_c->flags |= AT_RESET; 1579 break; 1580 default: 1581 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1582 reason); 1583 panic("__wdccommand_kill_xfer"); 1584 } 1585 __wdccommand_done_end(chp, xfer); 1586 } 1587 1588 /* 1589 * Send a command. The drive should be ready. 1590 * Assumes interrupts are blocked. 1591 */ 1592 void 1593 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1594 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1595 u_int8_t features) 1596 { 1597 struct atac_softc *atac = chp->ch_atac; 1598 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1599 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1600 1601 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1602 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1603 chp->ch_channel, drive, command, cylin, head, sector, count, 1604 features), DEBUG_FUNCS); 1605 1606 if (wdc->select) 1607 wdc->select(chp,drive); 1608 1609 /* Select drive, head, and addressing mode. */ 1610 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1611 WDSD_IBM | (drive << 4) | head); 1612 /* Load parameters into the wd_features register. */ 1613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1614 features); 1615 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1616 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1617 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1618 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1619 0, cylin >> 8); 1620 1621 /* Send command. */ 1622 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1623 return; 1624 } 1625 1626 /* 1627 * Send a 48-bit addressing command. The drive should be ready. 1628 * Assumes interrupts are blocked. 1629 */ 1630 void 1631 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1632 u_int64_t blkno, u_int16_t count) 1633 { 1634 struct atac_softc *atac = chp->ch_atac; 1635 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1636 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1637 1638 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1639 "count=%d\n", atac->atac_dev.dv_xname, 1640 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1641 DEBUG_FUNCS); 1642 1643 if (wdc->select) 1644 wdc->select(chp,drive); 1645 1646 /* Select drive, head, and addressing mode. */ 1647 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1648 (drive << 4) | WDSD_LBA); 1649 1650 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1651 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1652 0); 1653 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1654 0, count); 1655 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1656 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1657 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1658 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1659 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1660 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1661 } else { 1662 /* previous */ 1663 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1664 0); 1665 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1666 0, count >> 8); 1667 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1668 0, blkno >> 24); 1669 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1670 0, blkno >> 32); 1671 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1672 0, blkno >> 40); 1673 1674 /* current */ 1675 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1676 0); 1677 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1678 count); 1679 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1680 blkno); 1681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1682 0, blkno >> 8); 1683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1684 0, blkno >> 16); 1685 } 1686 1687 /* Send command. */ 1688 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1689 return; 1690 } 1691 1692 /* 1693 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1694 * tested by the caller. 1695 */ 1696 void 1697 wdccommandshort(struct ata_channel *chp, int drive, int command) 1698 { 1699 struct atac_softc *atac = chp->ch_atac; 1700 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1701 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1702 1703 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1704 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1705 DEBUG_FUNCS); 1706 1707 if (wdc->select) 1708 wdc->select(chp,drive); 1709 1710 /* Select drive. */ 1711 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1712 WDSD_IBM | (drive << 4)); 1713 1714 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1715 } 1716 1717 static void 1718 __wdcerror(struct ata_channel *chp, const char *msg) 1719 { 1720 struct atac_softc *atac = chp->ch_atac; 1721 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1722 1723 if (xfer == NULL) 1724 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1725 msg); 1726 else 1727 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1728 chp->ch_channel, xfer->c_drive, msg); 1729 } 1730 1731 /* 1732 * the bit bucket 1733 */ 1734 void 1735 wdcbit_bucket(struct ata_channel *chp, int size) 1736 { 1737 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1738 1739 for (; size >= 2; size -= 2) 1740 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1741 if (size) 1742 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1743 } 1744 1745 static void 1746 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1747 { 1748 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1749 1750 if (flags & DRIVE_NOSTREAM) { 1751 if (flags & DRIVE_CAP32) { 1752 bus_space_read_multi_4(wdr->data32iot, 1753 wdr->data32ioh, 0, bf, len >> 2); 1754 bf = (char *)bf + (len & ~3); 1755 len &= 3; 1756 } 1757 if (len) { 1758 bus_space_read_multi_2(wdr->cmd_iot, 1759 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1760 } 1761 } else { 1762 if (flags & DRIVE_CAP32) { 1763 bus_space_read_multi_stream_4(wdr->data32iot, 1764 wdr->data32ioh, 0, bf, len >> 2); 1765 bf = (char *)bf + (len & ~3); 1766 len &= 3; 1767 } 1768 if (len) { 1769 bus_space_read_multi_stream_2(wdr->cmd_iot, 1770 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1771 } 1772 } 1773 } 1774 1775 static void 1776 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1777 { 1778 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1779 1780 if (flags & DRIVE_NOSTREAM) { 1781 if (flags & DRIVE_CAP32) { 1782 bus_space_write_multi_4(wdr->data32iot, 1783 wdr->data32ioh, 0, bf, len >> 2); 1784 bf = (char *)bf + (len & ~3); 1785 len &= 3; 1786 } 1787 if (len) { 1788 bus_space_write_multi_2(wdr->cmd_iot, 1789 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1790 } 1791 } else { 1792 if (flags & DRIVE_CAP32) { 1793 bus_space_write_multi_stream_4(wdr->data32iot, 1794 wdr->data32ioh, 0, bf, len >> 2); 1795 bf = (char *)bf + (len & ~3); 1796 len &= 3; 1797 } 1798 if (len) { 1799 bus_space_write_multi_stream_2(wdr->cmd_iot, 1800 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1801 } 1802 } 1803 } 1804
Indexes created Sat Sep 27 14:09:57 GMT 2025